WO2024060323A1 - 一种计数电路、半导体存储器以及计数方法 - Google Patents

一种计数电路、半导体存储器以及计数方法 Download PDF

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WO2024060323A1
WO2024060323A1 PCT/CN2022/124052 CN2022124052W WO2024060323A1 WO 2024060323 A1 WO2024060323 A1 WO 2024060323A1 CN 2022124052 W CN2022124052 W CN 2022124052W WO 2024060323 A1 WO2024060323 A1 WO 2024060323A1
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counting
signal
module
sub
mode
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PCT/CN2022/124052
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English (en)
French (fr)
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黄泽群
孙凯
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长鑫科技集团股份有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells

Definitions

  • the present disclosure relates to the field of integrated circuit technology, and in particular, to a counting circuit, a semiconductor memory and a counting method.
  • DDR Double Data Rate
  • DRAM Dynamic Random Access Memory
  • EC Error Counter
  • Embodiments of the present disclosure provide a counting circuit, a semiconductor memory, and a counting method.
  • an embodiment of the present disclosure provides a counting circuit, including a first decoding module and a first counting module, and the first decoding module is connected to the first counting module, wherein:
  • the first decoding module is configured to receive the first mode signal, decode the first mode signal, and generate a decoding signal
  • the first counting module includes at least one sub-counting module, configured to determine the selected target counting module from the at least one sub-counting module according to the decoding signal, and receive the counting signal, and count the counting signal through the target counting module. Whenever counting When the count value corresponding to the signal reaches an integer multiple of the counting threshold, the first counting pulse signal is output.
  • the first mode signal represents a count threshold.
  • the decoded signal includes N-bit sub-decoded signals, where N is an integer greater than 0; the first decoding module is further configured to, during the process of generating the decoded signal, if the voltage of the i-th sub-decoded signal is If the average value is the first value, then it is determined that the level values of the other bit decoding signals except the i-th bit sub-decoding signal are all the second value; where the first value is different from the second value, and the difference in i is The value corresponds to different decoding signals, and different decoding signals represent different counting thresholds.
  • i is an integer greater than 0 and less than or equal to N.
  • the number of at least one sub-counting module is N, and the at least one sub-counting module is in a cascade relationship, and there is a corresponding relationship between the i-th sub-counting module and the i-th sub-decoding signal; wherein, the first A counting module configured to determine the i-th sub-counting module to the N-th sub-counting module as the target counting module when the level value of the i-th sub-decoding signal is the first value; and through the i-th sub-counting module to the N-th sub-counting module The sub-counting module counts the counting signal and outputs the first counting pulse signal.
  • each sub-counting module includes a first input end, a second input end and an output end; wherein, the first input end of each sub-counting module is connected to the counting signal; the first input end of the first sub-counting module The second input terminal is connected to the first power supply signal, the second input terminal of the j-th sub-counting module is connected to the output terminal of the j-1th sub-counting module, and the output terminal of the N-th sub-counting module is used to output the first counting pulse signal, j is an integer greater than 1 and less than or equal to N.
  • the i-th sub-counting module includes an i-th selection unit and an i-th counting unit, and the first input end of the i-th selection unit serves as the first input end of the i-th sub-counting module for receiving counts.
  • the second input terminal of the i-th selection unit is used as the second input terminal of the i-th sub-counting module to receive the first input signal
  • the output terminal of the i-th selection unit is connected to the clock terminal of the i-th counting unit
  • the output end of the i-th counting unit is used as the output end of the i-th sub-counting module to output the i-th intermediate signal;
  • the i-th selection unit is configured to receive the i-th sub-decoding signal, and according to the i-th sub-decoding signal Select and output the i-th selection signal among the counting signal and the first input signal;
  • the i-th counting unit is configured to receive the i-th selection signal and count, and output the i-th intermediate signal; where, when i is equal to 1, the first input The signal is the first power signal; when i is greater than 1 and less than or equal to N, the first input signal is the i-1th intermediate signal output by the i-1th counting unit; and, when
  • the i-th counting unit is an asynchronous binary counter; wherein the asynchronous binary counter includes several first flip-flops connected in sequence, and the input terminal (D) of the first flip-flop of each stage is connected to its own th The two output terminals (Q NOT) are connected, and the second output terminal (Q NOT) of the first flip-flop of each stage is connected to the clock terminal (CLK) of the first flip-flop of the next stage.
  • the clock terminal is connected to the output terminal of the i-th selection unit, and the second output terminal (Q NOT) of the first flip-flop of the last stage is used as the output terminal of the i-th counting unit for outputting the i-th intermediate signal.
  • the counting circuit further includes a counting signal generation module configured to receive a second mode signal and generate a counting signal in response to the second mode signal, the second mode signal indicating a target counting mode of execution.
  • the target counting mode is the code word counting mode, and the counting signal is the first counting signal; or, if the level value of the second mode signal is the second value, Then it is determined that the target counting mode is the row counting mode, and the counting signal is the second counting signal.
  • the counting signal generation module includes an error detection module and a mode selection module; wherein the error detection module is configured to generate a first detection signal according to the detected codeword error, and send the first detection signal to the mode selection module. module; and generate a second detection signal according to the detected row with a code word error, and send the second detection signal to the mode selection module; the mode selection module is connected to the error detection module for receiving the second mode selection signal, The first detection signal and the second detection signal, and in response to the control of the second mode signal, the first counting signal is generated according to the first detection signal, or the second counting signal is generated according to the second detection signal.
  • the counting signal generation module includes an error detection module and a mode selection module; wherein the error detection module is configured to receive the second mode selection signal; in response to the second mode selection signal, the codeword count is Detect codeword errors in mode, generate a first detection signal based on the detected codeword error, and send the first detection signal to the mode selection module; or, detect rows with codeword errors in row counting mode, and generate a first detection signal based on the detected codeword error.
  • the rows with code word errors generate a second detection signal, and send the second detection signal to the mode selection module;
  • the mode selection module is connected to the error detection module, and is used to receive the first detection signal or the second detection signal, and based on The first detection signal generates a first counting signal, or a second counting signal is generated based on the second detection signal.
  • the number of bits of the decoded signal is 2 x ; where x represents the number of bits of the first mode signal.
  • an embodiment of the present disclosure provides a semiconductor memory, including a threshold counting circuit, a storage density counting circuit and a target counting circuit, and the threshold counting circuit is the counting circuit described in the first aspect; wherein:
  • a threshold counting circuit is used to receive a counting signal and count the counting signal through an internal target counting module, and output a first counting pulse signal whenever a counting value corresponding to the counting signal reaches an integer multiple of a counting threshold;
  • a storage density counting circuit used to count the first counting pulse signal, and output a second counting pulse signal whenever the count value corresponding to the first counting pulse signal reaches an integer multiple of the preset storage density
  • the target counting circuit is used to count the second counting pulse signal and output the target counting signal.
  • the storage density counting circuit is an asynchronous binary counter; wherein the asynchronous binary counter includes several second flip-flops connected in sequence, and the input terminal (D) of the second flip-flop of each stage is connected to its own second flip-flop.
  • the output terminal (Q NOT) is connected, and the second output terminal (Q NOT) of each stage's second flip-flop is connected to the clock terminal (CLK) of the next stage's second flip-flop.
  • the clock of the first stage's second flip-flop The terminal is connected to the output terminal of the threshold counting circuit, and the second output terminal (Q NOT) of the second flip-flop of the last stage is connected to the clock terminal (CLK) of the target counting circuit as the output terminal of the storage density counting circuit.
  • the preset storage density is 2 y
  • y represents the number of second flip-flops.
  • the target counting circuit is an asynchronous binary counter; wherein the asynchronous binary counter includes a plurality of third flip-flops connected in sequence, and the input terminal (D) of the third flip-flop of each stage is connected with its own second output terminal (Q NOT) is connected, and the second output terminal (Q NOT) of each stage of the third flip-flop is connected to the clock terminal (CLK) of the next stage of the third flip-flop, and the clock terminal of the first stage of the third flip-flop Connect to the output of the storage density counting circuit.
  • the asynchronous binary counter includes a plurality of third flip-flops connected in sequence, and the input terminal (D) of the third flip-flop of each stage is connected with its own second output terminal (Q NOT) is connected, and the second output terminal (Q NOT) of each stage of the third flip-flop is connected to the clock terminal (CLK) of the next stage of the third flip-flop, and the clock terminal of the first stage of the third flip-flop Connect to the output of the storage density counting circuit.
  • the number of third flip-flops is M
  • the target count signal is a binary number composed of the 0th bit to the M-1th bit target count sub-signal; wherein, the k+1th level third flip-flop
  • the first output terminal (Q) of the device is used to output the k-th target count sub-signal, where k is an integer greater than or equal to 0 and less than M.
  • the semiconductor memory further includes a second decoding module configured to decode the target count signal according to the received ECS end signal and store the decoded signal into a preset mode register.
  • the preset mode register includes at least M bits, and each bit corresponds to a preset counting range; wherein, the second decoding module is also configured to when the target counting result meets the kth preset counting range, The value stored in the k-th bit in the preset mode register is set to the first value, and the values stored in other bits except the k-th bit are set to the second value.
  • the target count result is the product of the count value represented by the target count signal and the preset value
  • the preset value is the product value of the count threshold and the preset storage density; wherein, the minimum value of the kth preset count range Set as the product of the preset value and 2 k ; the maximum value of the k-th preset count range is set as the difference between the product of the preset value and 2 k+1 and 1.
  • an embodiment of the present disclosure provides a counting method, applied to the semiconductor memory as described in the second aspect, the method includes:
  • the first counting pulse signal is counted through the density counting circuit, and whenever the count value corresponding to the first counting pulse signal reaches an integer multiple of the preset storage density, the second counting pulse signal is output;
  • the second counting pulse signal is counted through the target counting circuit, and the target counting signal is output.
  • Embodiments of the present disclosure provide a counting circuit, a semiconductor memory, and a counting method.
  • the counting circuit includes a first decoding module and a first counting module, and the first decoding module is connected to the first counting module; the first decoding module , configured to receive the first mode signal, decode the first mode signal, and generate a decoding signal; the first counting module includes at least one sub-counting module, and is configured to determine the target from the at least one sub-counting module according to the decoding signal.
  • the selected target counting module receives the counting signal, counts the counting signal through the target counting module, and outputs the first counting pulse signal whenever the counting value corresponding to the counting signal reaches an integer multiple of the counting threshold.
  • a decoding signal can be generated according to the first mode signal, and different decoding signals can represent different counting threshold levels, and different target counting modules can be selected according to different decoding signals, thereby meeting different counting threshold levels.
  • Counting statistics; in addition, adaptively selecting the target counting module according to the different decoding signals can also avoid the problem of too many connecting lines caused by the use of a large number of logic devices in related technologies, thereby also reducing the circuit area and the number of connecting lines. , while reducing circuit complexity, thereby improving memory performance.
  • Figure 1 is a schematic diagram of the structure of an error counter
  • Figure 2 is a schematic diagram of the logic circuit structure of an error counter
  • FIG3 is a schematic diagram of a structure of a counting circuit provided in an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram 2 of the composition of a counting circuit provided by an embodiment of the present disclosure
  • Figure 5 is a schematic diagram 3 of the composition of a counting circuit provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of a counting unit provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic diagram 4 of the composition of a counting circuit provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram 5 of a counting circuit provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram 6 of the composition of a counting circuit provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic structural diagram of a counting and statistics circuit provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic structural diagram of a storage density counting circuit provided by an embodiment of the present disclosure.
  • Figure 13 is a schematic structural diagram of a target counting circuit provided by an embodiment of the present disclosure.
  • Figure 14 is a schematic diagram 2 of the composition of a counting statistics circuit provided by an embodiment of the present disclosure.
  • Figure 15 is a detailed structural schematic diagram of a counting and statistics circuit provided by an embodiment of the present disclosure.
  • Figure 16 is a schematic flowchart of a counting method provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first ⁇ second ⁇ third” Where permitted, the specific order or sequence may be interchanged so that the disclosed embodiments described herein can be practiced in other sequences than illustrated or described herein.
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • the 5th generation DDR standard (DDR5Specification, DDR5SPEC);
  • Multi-Purpose Command (MPC)
  • MUX Multiplexer
  • MRS Mode Register Set
  • ECS Error Check and Scrub
  • the ECS mode can be divided into an automatic ECS operation mode and a manual ECS operation mode.
  • the MPC command sent by the memory controller (Controller) is used to generate the ECS command signal;
  • refresh (Refresh) or self-refresh (Self-Refresh) can be used to generate ECS Command signal; among them, the ECS command signal is used to perform ECS operations.
  • a complete ECS operation needs to be performed on the DRAM at least within 24 hours.
  • the threshold filter is used to cover up error counts that are less than the threshold filter set threshold.
  • mode register MR15 OP[2:0] can be set using the mode register MR15 OP[2:0].
  • the final recorded result of EC will be loaded into mode register MR20.
  • the error count result EC[7:0] corresponding to MR20 OP[7:0] indicates errors within a certain preset count range. count.
  • ETC Error Threshold Count
  • EC[7:1]min ETC*Density*2 ⁇ x
  • x 0,1,2,...,7.
  • Table 1 shows the error count threshold (ETC) corresponding to each memory unit (Gb) set by MR15.
  • ETC error count threshold
  • Gb memory unit set by MR15.
  • the error count threshold can be set to 256.
  • the error counter can be used to count the number of erroneous codewords.
  • Figure 1 shows a schematic diagram of the composition structure of an error counter.
  • the ECC_Error signal represents a pulse signal generated when erroneous codeword information is detected.
  • the error counter will increment.
  • the final error counting result will select the error counting threshold (ETC) and the preset storage density (nGb) based on the Code ⁇ N:0> decoded from MR15, and then load the value that meets the current counting standard into MR20.
  • ETC error counting threshold
  • nGb preset storage density
  • the current ETC can be determined based on the Code ⁇ N:0> decoded by MR15.
  • the error counter designed in this way will have a lot of connecting lines and logic circuits for EC* signals and ETCD* signals (here, "*" can mean 64, 128,..., 1024, 2048, etc.), as shown in Figure 2.
  • many logic devices such as MUX0, MUX1,..., MUX7, etc.
  • MUX0, MUX1,..., MUX7, etc. are needed, and there are many interfaces around each logic device, respectively with EC64, EC128,..., EC1024,..., ETCD64, ETCD128,..., ETCD1024 and many other signal connections.
  • This counting method requires many circuits and connecting lines, which not only increases the circuit area, but also increases the complexity. Therefore, how to better design a counting circuit is a problem to be solved by this disclosure.
  • FIG. 3 shows a schematic structural diagram of a counting circuit 30 provided by an embodiment of the present disclosure.
  • the counting circuit 30 may include a first decoding module 301 and a first counting module 302, and the first decoding module 301 is connected to the first counting module 302, where:
  • the first decoding module 301 is configured to receive the first mode signal, decode the first mode signal, and generate a decoding signal;
  • the first counting module 302 includes at least one sub-counting module, configured to determine the selected target counting module from the at least one sub-counting module according to the decoding signal, and receive the counting signal, and count the counting signal through the target counting module, each time When the count value corresponding to the counting signal reaches an integer multiple of the counting threshold, the first counting pulse signal is output.
  • the counting circuit 30 can be applied to a semiconductor memory, specifically a DRAM DDRR chip. More specifically, the counting circuit 30 can be applied to related circuits that perform error counting in ECS operations, but is not limited thereto. It can also be applied to other circuits that count and record results.
  • the first counting pulse signal represents the multiple relationship between the counting value corresponding to the counting signal and the counting threshold. For example, taking the counting threshold set to 4 as an example, when the counting signal accumulates 4 pulses, the output first counting pulse signal includes 1 pulse; when the counting signal accumulates 8 pulses, the output first counting pulse signal includes 2 pulses; that is to say, at the 4th, 8th, 12th, 16th, ... pulse of the counting signal, the first counting pulse signal output will correspond to a pulse. In short, the first counting pulse signal represents how many times the counting value corresponding to the counting signal is the counting threshold.
  • the first mode signal may represent the counting threshold.
  • the counting threshold here may also be called the error counting threshold.
  • the first mode signal can be represented by MR15 OP[2:0]. Wherein, if the first mode signal is 000, then the counting threshold may be 4; if the first mode signal is 001, then the counting threshold may be 16; if the first mode signal is 011, then the counting threshold may be 256 and so on. That is to say, different first mode signals may correspond to different counting thresholds.
  • the corresponding target counting module can be selected from the first counting module 302 according to the decoded signal.
  • different decoding signals can represent different counting threshold levels.
  • the decoded signal can also adaptively select the target counting module, so as to meet the counting statistics of different counting threshold levels.
  • the first decoding module 301 receives the first mode signal and decodes the first mode signal to generate a decoding signal.
  • the decoding signal may include an N-bit sub-decoding signal, As shown in Figure 3, sub-decoding signal 1, sub-decoding signal 2, ..., sub-decoding signal N.
  • the first counting module 302 includes at least one sub-counting module, and the number of the at least one sub-counting module is also N, such as sub-counting module 1, sub-counting module 2, ..., sub-counting module N as shown in Figure 3, and this At least one sub-counting module is in a cascade relationship. Among them, N is an integer greater than 0.
  • the decoded signal and the first mode signal are both multi-bit signals, and the number of bits of the decoded signal is There is a correlation relationship with the number of bits of the first mode signal. In some embodiments, the number of bits of the decoded signal is 2 x ; where x represents the number of bits of the first mode signal.
  • the decoded signal may be a multi-bit decoded signal.
  • the number of sub-decoding signals is equal to the number of bits of the decoding signal, and the number of sub-decoding signals is also equal to the number of sub-counting modules; each sub-decoding signal is connected to the corresponding sub-counting module.
  • the decoded signal may include eight bits, that is, the decoded signal may be composed of eight-bit sub-decoded signals. Therefore, in the embodiment of the present disclosure, the first decoding module 301 may also be called a three-eight decoder.
  • the decoded signal may include an N-bit sub-decoded signal, where N is an integer greater than 0;
  • the first decoding module 301 is also configured to, in the process of generating the decoding signal, if the level value of the i-th sub-decoding signal is the first value, determine the other bits except the i-th sub-decoding signal.
  • the level values of the code signals are all second values; wherein, the first value is different from the second value, and i is an integer greater than 0 and less than or equal to N.
  • the value of i has a correlation with the counting threshold.
  • the level value of only one of the N-bit sub-decoded signals is the first value.
  • the decoded signal changes. ;
  • Different decoding signals correspond to different counting thresholds.
  • different values of i correspond to different decoding signals, and different decoding signals represent different counting thresholds.
  • the first value may be a logic 1 indicating a high level
  • the second value may be a logic 0 indicating a low level; or, the first value may be a logic 0 indicating a low level.
  • the second value may be a logic 1 indicating a high level, without any limitation.
  • the decoding signal can be 0000 0001, 0000 0010, 0000 0100, 0000 1000, or 0001 0000, 0010 0000, 0100 0000, 1000 0000, etc.
  • the counting threshold at this time may be 4; if the first mode signal is 001, then the corresponding decoding signal is 0000 0010, and the counting threshold at this time may be 16; if the first mode signal is 010, then the corresponding decoding signal is 0000 0100, and the counting threshold at this time may be 64; if the first mode signal is 011, then the corresponding decoding signal is 0000 1000, and the counting threshold at this time may be 256, and so on.
  • different first mode signals may correspond to different decoding signals.
  • only one sub-decoding signal has a level value equal to 1; according to different positions where the level value is equal to 1, different decoding signals may correspond, and different decoding signals may represent different counting thresholds.
  • the number of at least one sub-counting module is N, and there is a corresponding relationship between the i-th sub-counting module and the i-th sub-decoding signal, where:
  • the first counting module 302 is configured to determine the i-th sub-counting module to the N-th sub-counting module as the target counting module when the level value of the i-th sub-decoding signal is the first value; and through the i-th sub-counting module The Nth sub-counting module counts the counting signal and outputs the first counting pulse signal.
  • these N sub-counting modules are in a cascade relationship, and each sub-counting module is connected to a corresponding sub-decoding signal.
  • the counting signal is used as the clock input of the i-th sub-counting module, and the i-th sub-counting module and its subsequent sub-counting modules (i.e., the i-th sub-counting module) are The i-th to N-th sub-counting modules) are used as target counting modules, that is, the counting signals are counted according to the i-th sub-counting module and its subsequent sub-counting modules.
  • sub-counting module i represents the i-th sub-counting module, and i is an integer greater than 0 and less than or equal to N.
  • each sub-counting module may include a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of each sub-counting module is connected to a counting signal. ; and the second input terminal of the first sub-counting module is connected to the first power signal, the second input terminal of the j-th sub-counting module is connected to the output terminal of the j-1th sub-counting module, and the output terminal of the N-th sub-counting module is connected Used to output the first counting pulse signal, j is an integer greater than 1 and less than or equal to N.
  • the first power signal may be a power signal provided by a first power source.
  • the first power supply can be a constant power supply.
  • the first power supply may be a VSS power supply, which is used to provide a constant low-level signal, so the first power supply signal may also be called a ground signal.
  • each sub-counting module may also include a control terminal for receiving the corresponding sub-decoding signal. In this way, according to the received sub-decoding signal, the required target counting module can be determined from the N sub-counting modules.
  • the first counting module 302 only includes one sub-counting module.
  • the decoding signal may also include only one sub-decoding signal, and the sub-counting module is the target counting module.
  • the first input end of the sub-counting module is connected to the counting signal
  • the second input end of the sub-counting module is connected to the first power signal
  • the control end of the sub-counting module is used to receive the unique sub-decoding signal.
  • the output terminal of the sub-counting module is used to output the first counting pulse signal.
  • N when N is equal to 1, there is actually only one implementation of the target counting module, which cannot meet the needs of multiple counting threshold levels. Therefore, in the embodiment of the present disclosure, N is usually greater than 1, that is to say, the counting circuit 30 can be applied to a variety of different counting threshold level scenarios.
  • the specific counting threshold can be determined according to the first mode signal decoding, and then selected.
  • a corresponding number of sub-counting modules serve as target counting modules, which can be applied to counting scenarios with different counting threshold levels (such as error counting scenarios, other counting scenarios, etc.), and have greater flexibility and adaptability.
  • the first input terminal of each sub-counting module is used to receive a counting signal
  • the control terminal of each sub-counting module is used to receive a corresponding sub-decoding signal
  • the second input terminal of the first sub-counting module i.e., sub-counting module 1
  • the output terminals of the first to N-1th sub-counting modules are connected to the second input terminal of the next sub-counting module
  • the output terminal of the last (Nth) sub-counting module i.e., sub-counting module N
  • the last (Nth) sub-counting module is used to output a first counting pulse signal.
  • the i-th sub-counting module may include an i-th selection unit and an i-th counting unit, and the i-th selection unit
  • the first input terminal of the i-th sub-counting module is used as the first input terminal for receiving the counting signal
  • the second input terminal of the i-th selection unit is used as the second input terminal of the i-th sub-counting module for receiving the first input signal.
  • the output terminal of the i-th selection unit is connected to the clock terminal of the i-th counting unit, and the output terminal of the i-th counting unit is used as the output terminal of the i-th sub-counting module to output the i-th intermediate signal, where:
  • the i-th selection unit is configured to receive the i-th sub-decoding signal, and select and output the i-th selection signal among the counting signal and the first input signal according to the i-th sub-decoding signal;
  • the i-th counting unit is configured to receive the i-th selection signal, perform counting, and output the i-th intermediate signal.
  • the first input signal is the first power signal; when i is greater than 1 and less than or equal to N, the first input signal is the i-1th intermediate signal output by the i-1th counting unit ; And, when i equals N, the Nth intermediate signal is the first counting pulse signal.
  • each sub-counting module is composed of a selection unit and a counting unit, that is: sub-counting module 1 (the first sub-counting module) is composed of It consists of selection unit 1 (the first selection unit) and counting unit 1 (the first counting unit).
  • Sub-counting module 2 (the second sub-counting module) is composed of selection unit 2 (the second selection unit) and counting unit 2. (the second counting unit),..., the sub-counting module N (the N-th sub-counting module) is composed of the selection unit N (the N-th selection unit) and the counting unit N (the N-th counting unit).
  • the selection unit is configured to receive the corresponding sub-decoding signal, that is: selection unit 1 is configured to receive sub-decoding signal 1 (the first sub-decoding signal), and selection unit 2 is configured to receive sub-decoding signal Code signal 2 (the 2nd sub-decoding signal), ..., the selection unit N is configured to receive the sub-decoding signal N (the N-th sub-decoding signal).
  • Each selection unit may include a first input terminal, a second input terminal, a control terminal and an output terminal.
  • the first input terminal of the i-th selection unit is the first input terminal of the i-th sub-counting module
  • the second input terminal of the i-th selection unit is the second input terminal of the i-th sub-counting module.
  • the control end of the selection unit is the control end of the i-th sub-counting module.
  • the output end of the i-th selection unit is connected to the clock end of the i-th counting unit.
  • the output end of the i-th counting unit is the i-th sub-counting module. The output of the module.
  • the output end of the selection unit 1 can select one of the counting signal and the first power signal to output as the first selection signal.
  • the clock of the counting unit 1 The terminal is used to receive the first selection signal, and the output terminal of the counting unit 1 is used to output the first intermediate signal; in the sub-counting module 2, the output terminal of the selection unit 2 can select one from the counting signal and the first intermediate signal.
  • the clock terminal of the counting unit 2 is used to receive the second selection signal, and the output terminal of the counting unit 2 is used to output the second intermediate signal; and so on, in the sub-counting module N, the selection unit N
  • the output terminal can select one of the counting signal and the N-1 intermediate signal to be output as the Nth selection signal.
  • the clock terminal of the counting unit N is used to receive the Nth selection signal, and the output terminal of the counting unit N is used to output The Nth intermediate signal (that is, the final first counting pulse signal).
  • the selection unit 1 if the level value of the first-bit sub-decoding signal (sub-decoding signal 1) is the first value, then the selection unit 1 will output the counting signal as the first selection signal.
  • the connected sub-counting module 1 to sub-counting module N is used as the target counting module; if the level value of the second sub-decoding signal (sub-decoding signal 2) is the first value, then the selection unit 2 will output the counting signal as the third 2 selects the signal.
  • the cascaded sub-counting module 2 to sub-counting module N serves as the target counting module; and by analogy, if the level value of the N-th sub-decoding signal (sub-decoding signal N) is the first value, Then the selection unit N will output the counting signal as the Nth selection signal. At this time, only the sub-counting module N serves as the target counting module. In this way, the target counting module can be adaptively selected according to the N-bit sub-decoding signal to meet different counting requirements. Count statistics for threshold levels.
  • the ith counting unit is an asynchronous binary counter, where:
  • the asynchronous binary counter may include several first flip-flops connected in sequence.
  • the input terminal (D) of the first flip-flop of each stage is connected to its own second output terminal (QN), and the first flip-flop of each stage
  • the second output terminal (Q NOT) is connected to the clock terminal (CLK) of the first flip-flop of the next stage.
  • the clock terminal of the first flip-flop of the first stage is connected to the output terminal of the i-th selection unit.
  • the last stage of the The second output terminal (Q NOT) of a flip-flop is used as the output terminal of the i-th counting unit for outputting the i-th intermediate signal.
  • the counting unit i may include two first flip-flops.
  • the first flip-flop can be a D-type flip-flop.
  • the D-type flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF) is an information storage device with memory function and two stable states. It is composed of The most basic logic unit of various sequential circuits, it is also an important unit circuit in digital logic circuits.
  • the D-type flip-flop has two stable states, namely "0" and "1". It can flip from one stable state to the other when triggered by the trigger edge of the signal received by the clock terminal of the flip-flop.
  • the first flip-flop includes an input terminal (D), a clock terminal (CLK), a first output terminal (Q), and a second output terminal (Q NOT, Indicated by /Q).
  • the input terminal (D) of the first flip-flop of each stage is connected to its second output terminal (/Q), and the second output terminal (/Q) of the first flip-flop of each stage is also connected to the next
  • the clock terminal (CLK) of the first flip-flop of the first stage is connected; in addition, the clock terminal (CLK) of the first flip-flop of the first stage (ie DFF11) is connected to the i-th selection signal, and the first flip-flop of the last stage (ie DFF12)
  • the second output terminal (/Q) is used to output the i-th intermediate signal.
  • the decoded signal includes an eight-bit sub-decoded signal
  • the first counting module 302 includes eight sub-counting modules, and the counting unit in each sub-counting module includes two cascaded first flip-flops; this At this time, if the level value of the first sub-decoding signal (sub-decoding signal 1) is the first value, the target counting module is obtained by cascading sub-counting module 1 to sub-counting module 8.
  • the target counting module includes 16 first flip-flops in cascade; or, if the level value of the 7th sub-decoding signal (sub-decoding signal 7) is the first value, the target counting module is from sub-counting module 7 to sub-counting module 8 At this time, the target counting module includes four cascaded first flip-flops; or, if the level value of the 8th bit sub-decoding signal (sub-decoding signal 8) is the first value, the target counting module only It includes sub-counting module 8. At this time, the target counting module includes two cascaded first flip-flops.
  • the first decoding module 301 decodes the first mode signal to obtain an eight-bit sub-decoding signal, it can not only determine the counting threshold level based on the eight-bit sub-decoding signal, but also select the counting signal as a certain counting unit ( Specifically, it refers to the clock input of a certain level of the first flip-flop), so that the level of the first counting module 302 can be controlled as a whole to achieve counting statistics that meet different counting threshold levels.
  • the counting circuit 30 may also include a counting signal generation module 303, wherein:
  • the counting signal generation module 303 is configured to receive a second mode signal and generate the counting signal in response to the second mode signal, where the second mode signal indicates an executed target counting mode.
  • the first mode signal and the second mode signal are different.
  • the first mode signal may be a mode signal in the mode register MR15 for setting the counting threshold
  • the second mode signal may be a mode signal in the mode register MR14 for setting the counting mode.
  • codeword counting mode is used to count the number of erroneous codewords
  • row counting mode is used to count the number of rows with at least one erroneous codeword. Therefore, in some embodiments, when counting circuit 30 performs ECS operations, wherein:
  • the level value of the second mode signal is the first value, it is determined that the target counting mode is the codeword counting mode, and the counting signal is the first counting signal; or,
  • the target counting mode is the row counting mode and the counting signal is the second counting signal.
  • the first counting signal may also be called a codeword error count signal
  • the second counting signal may also be called a codeword error row count signal
  • the first value may be a logic 1 indicating a high level
  • the second value may be a logic 0 indicating a low level
  • the first value may be a logic 0 indicating a low level
  • the second value may be a logic 0 indicating a low level.
  • the value can be, without limitation, a logic 1 indicating a high level.
  • the first value is logic 1 and the second value is logic 0, then when the second mode signal is equal to logic 1, it is a code word counting mode, and the corresponding counting signal is a first counting signal (i.e., a code word error counting signal); when the second mode signal is equal to logic 0, it is a row counting mode, and the corresponding counting signal is a second counting signal (i.e., a code word error row counting signal).
  • the second mode signal can be used to select whether to execute the row counting mode or the code word counting mode.
  • the counting signal generation module 303 may include an error detection module 3031 and a mode selection module 3032, wherein:
  • the error detection module 3031 is configured to generate a first detection signal according to the detected codeword error, and send the first detection signal to the mode selection module 3032; and generate a second detection signal according to the detected row with a codeword error, And send the second detection signal to the mode selection module 3032;
  • the mode selection module 3032 is connected to the error detection module 3031 and is used to receive the second mode selection signal, the first detection signal and the second detection signal, and in response to the control of the second mode signal, generate a first count according to the first detection signal signal, or generate a second counting signal according to the second detection signal.
  • the error detection module 3031 can not only detect codeword errors to generate a first detection signal, but also detect rows with codeword errors to generate a second detection signal; and then use the first detection signal to generate a second detection signal.
  • the signal and the second detection signal are sent to the mode selection module 3032 at the same time; at this time, in the mode selection module 3032, it is determined whether it is the code word counting mode or the line counting mode according to the received second mode selection signal; then if it is the code word counting mode mode, then the first counting signal can be generated according to the first detection signal; or, if it is the row counting mode, then the second counting signal can be generated according to the second detection signal.
  • the counting signal generation module 303 may include an error detection module 3033 and a mode selection module 3034, wherein:
  • the error detection module 3033 is configured to receive the second mode selection signal; in response to the second mode selection signal, detect codeword errors in the codeword counting mode, generate a first detection signal according to the detected codeword error, and generate the first detection signal.
  • the detection signal is sent to the mode selection module 3034; or, in the row counting mode, rows with codeword errors are detected, a second detection signal is generated based on the detected rows with codeword errors, and the second detection signal is sent to the mode selection module Module 3034;
  • the mode selection module 3034 is connected to the error detection module 3033, and is used to receive the first detection signal or the second detection signal, and generate a first counting signal according to the first detection signal, or generate a second counting signal according to the second detection signal.
  • the error detection module 3033 can be used to determine whether it is the code word counting mode or the line counting mode; then if it is the code word counting mode, then according to the detected code word
  • the first detection signal is generated by error, and the first detection signal is sent to the mode selection module 3034; or, if it is the row counting mode, a second detection signal is generated according to the detected row with a codeword error, and the second detection signal is The signal is sent to the mode selection module 3034; and then the first counting signal or the second counting signal is generated correspondingly according to the first detection signal or the second detection signal.
  • different counting modes correspond to different detection signals; different detection signals correspond to different counting signals (such as code word error counting signals or code word error row counting signals).
  • different counting signals can represent the number of rows with at least one code word error or the total number of code word errors, so that the counting circuit 30 can determine the multiple relationship between the counting value represented by the counting signal and the counting threshold, In other words, how many times the count threshold is included in the count value.
  • the first mode signal can represent a preset counting threshold, and at least one sub-decoding signal can be decoded according to the first mode signal. This at least one sub-decoding signal can determine the corresponding count threshold.
  • a target counting module in this way, the counting signal is counted through the target counting module, and a pulse can be output every time the count reaches the counting threshold, thereby generating a first counting pulse signal. That is to say, the first counting pulse signal represents the multiple relationship between the counting value corresponding to the counting signal and the counting threshold.
  • Embodiments of the present disclosure provide a counting circuit.
  • Different decoding signals can represent different counting threshold levels, and different target counting modules can be adaptively selected according to different decoding signals, thereby not only being able to meet different counting threshold levels.
  • Counting statistics and can also avoid the problem of too many connection lines caused by the use of a large number of logic devices in related technologies, reduce circuit complexity, and thereby improve memory performance.
  • FIG. 10 shows a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • the semiconductor memory 100 may include a counting statistics circuit 80 .
  • FIG. 11 shows a schematic structural diagram of a counting statistics circuit 80 .
  • the counting statistics circuit 80 may include a threshold counting circuit 801, a storage density counting circuit 802 and a target counting circuit 803, where:
  • the threshold counting circuit 801 is used to receive the counting signal and count the counting signal through the internal target counting module. Whenever the counting value corresponding to the counting signal reaches an integer multiple of the counting threshold, the first counting pulse signal is output;
  • the storage density counting circuit 802 is used to count the first counting pulse signal, and output a second counting pulse signal whenever the count value corresponding to the first counting pulse signal reaches an integer multiple of the preset storage density;
  • the target counting circuit 803 is used to count the second counting pulse signal and output the target counting signal.
  • the threshold counting circuit 801 may be the counting circuit 30 of any of the previous embodiments.
  • the first counting pulse signal can represent the multiple relationship between the counting value corresponding to the counting signal and the counting threshold
  • the second counting pulse signal can represent the counting corresponding to the first counting pulse signal.
  • the target count signal represents the count value corresponding to the second counting pulse signal
  • the target count result is the product of the count value represented by the target count signal, the counting threshold and the preset storage density, where
  • the target counting result of can represent the total number of errors counted by the counting and statistics circuit 80 for the current error data. In this way, after the target count result is obtained, its corresponding preset count range can be further determined according to the target count result, so that it can be loaded into the preset mode register.
  • the threshold counting circuit 801 can obtain the first count value
  • the storage density counting circuit 802 can obtain the second count value
  • the target counting circuit 803 can obtain the third count value.
  • the first count value indicates how many times the count threshold is included in the first count pulse signal
  • the second count value indicates how many times the preset storage density is included in the second count pulse signal
  • the third count value is the count represented by the target count signal. value.
  • the target count result may be determined based on the count threshold, the preset storage density and the third count value. More specifically, assuming that the preset value is the product value of the count threshold and the preset storage density, then the target count result is the third count value. The product of the count value and the preset value.
  • storage density counting circuit 802 may be an asynchronous binary counter, where:
  • the asynchronous binary counter includes a plurality of second flip-flops cascaded in sequence, the input terminal (D) of each stage of the second flip-flop is connected to its own second output terminal (/Q), and the second output terminal (/Q) of each stage of the second flip-flop is connected to the clock terminal (CLK) of the next stage of the second flip-flop, the clock terminal of the first stage of the second flip-flop is connected to the output terminal of the threshold counting circuit 801, and the second output terminal (/Q) of the last stage of the second flip-flop is connected to the clock terminal (CLK) of the target counting circuit 803 as the output terminal of the storage density counting circuit.
  • the preset storage density indicates that the DRAM memory is multiple Gb, such as 8Gb, 16Gb, 32Gb, etc.
  • the preset storage density can be specifically set according to the actual situation, and there is no limit here.
  • the asynchronous binary counter includes four second flip-flops.
  • the second flip-flop can be a D-type flip-flop.
  • the four second flip-flops are: DFF21, DFF22, DFF23 and DFF24 respectively, and DFF1, DFF22, DFF23 and DFF24 are in a cascade relationship.
  • the second flip-flop includes an input terminal (D), a clock terminal (CLK), a first output terminal (Q) and a second output terminal (/Q).
  • the input terminal (D) of the second flip-flop of each stage is connected to its own second output terminal (/Q), and the second output terminal (/Q) of the second flip-flop of each stage is also connected to the next
  • the clock terminal (CLK) of the second flip-flop of the first stage is connected; and the clock terminal (CLK) of the second flip-flop of the first stage (DFF21) is used to receive the first counting pulse signal, and the first flip-flop of the last stage (DFF24 )
  • the second output terminal (/Q) is used to output the second counting pulse signal.
  • the second counting pulse signal can represent the multiple relationship between the count value corresponding to the first counting pulse signal and the preset storage density, or it can also be the multiple relationship between the current error data and (counting threshold * preset storage density) .
  • the target counting circuit 803 may be an asynchronous binary counter, wherein:
  • the asynchronous binary counter includes several third flip-flops connected in sequence.
  • the input terminal (D) of each stage of the third flip-flop is connected to its own second output terminal (/Q), and the input terminal (D) of each stage of the third flip-flop is connected to its own second output terminal (/Q).
  • the second output terminal (/Q) is connected to the clock terminal (CLK) of the third flip-flop of the next stage, and the clock terminal of the third flip-flop of the first stage is connected to the output terminal of the storage density counting circuit 802.
  • the target count signal may be a binary number composed of the 0th bit to the M-1th bit target count sub-signal; correspondingly, the number of third flip-flops is M, where:
  • the first output terminal (Q) of the third trigger of the k+1th stage is used to output the kth target count sub-signal, where k is an integer greater than or equal to 0 and less than M, and M is an integer greater than zero.
  • the asynchronous binary counter includes eight third triggers.
  • the third trigger can be a D-type trigger
  • the eight third triggers are respectively: DFF31, DFF32, DFF33, DFF34, DFF35, DFF36, DFF37 and DFF38, and DFF31, DFF32, DFF33, DFF34, DFF35, DFF36, DFF37 and DFF38 are in a cascade relationship.
  • the third flip-flop includes an input terminal (D), a clock terminal (CLK), a first output terminal (Q) and a second output terminal (/Q).
  • the clock terminal (CLK) of the first-stage third flip-flop i.e., DFF31
  • the input terminal (D) of each stage of the third flip-flop is connected to its own second output terminal ( /Q) connection
  • the second output terminal (/Q) of the third flip-flop of each stage is also connected to the clock terminal (CLK) of the second flip-flop of the next stage
  • the first output of the third flip-flop of each stage Terminal (Q) is used to output a one-bit target count sub-signal.
  • eight-bit target count sub-signals are output here, namely: MR20 ⁇ 0>_PRE, MR20 ⁇ 1>_PRE, ..., MR20 ⁇ 7>_PRE; these eight-bit target count sub-signals can indicate the third count value , and the final target counting result can be determined according to the counting threshold, the preset storage density and the third counting value.
  • the counting and statistics circuit 80 may further include a second decoding module 804 and a preset mode register 805, wherein:
  • the second decoding module 804 is configured to decode the target count signal according to the received ECS end signal and store it in the preset mode register 805.
  • the preset mode register 805 may be MR20.
  • the preset mode register 805 includes at least M bits, and each bit corresponds to a preset count range, and the preset count ranges do not overlap, where:
  • the second decoding module 804 is also configured to set the value stored in the k-th bit in the preset mode register to the first value when the target count result meets the k-th preset counting range, and other bits except the k-th bit are set to the first value.
  • the stored value is set to the second value.
  • the first value may be a logic 1 indicating a high level
  • the second value may be a logic 0 indicating a low level
  • the first value may be a logic 0 indicating a low level
  • the second value may be a logic 0 indicating a low level.
  • a high-level logic 1 does not impose any restrictions on this.
  • the target counting result may be the product of the counting value represented by the target counting signal and the preset value
  • the preset value is the product of the counting threshold and the preset storage density.
  • the minimum value of the k-th preset counting range is set to the product of the preset value and 2 k
  • the maximum value of the k-th preset counting range is set to the difference between the product of the preset value and 2 k+1 and 1 .
  • the counting threshold is represented by ETC
  • the preset storage density is represented by Density (Gb)
  • the minimum value of the k-th preset counting range can be represented by EC[k]min
  • the minimum value of the k-th preset counting range can be represented by EC[k]min
  • the maximum value of the preset counting range of k is represented by EC[k]max.
  • k is an integer greater than or equal to 0 and less than M
  • M represents the number of bits included in the preset mode register 805
  • M is a positive integer
  • the error counting decoding signal can be obtained, represented by EC[7:0]; according to the error count decoding signal EC[7:0], the mode The value stored in the corresponding bit in register MR20 is set to the first value.
  • the error count decoding signal EC[7:0] can represent the error count within a certain counting range.
  • EC[7:0] can include: EC[0], EC[1], EC[2], EC[3], EC[4], EC[5], EC[6] and EC[7] ;
  • Table 3 shows schematic data ranges of eight preset count ranges.
  • the second decoding module 804 is also configured to set the value stored in the kth bit in the preset mode register to the first value when the count value represented by the target count signal meets the kth preset count range. value, the values stored in other bits except the k-th bit are set to the second value.
  • the minimum value of the k-th preset counting range can be represented by EC[k]min
  • the maximum value of the k-th preset counting range can be represented by EC[k]max.
  • k is an integer greater than or equal to 0 and less than M.
  • M is equal to 8
  • Table 4 shows schematic data ranges of eight preset count ranges.
  • the third count value is the count value represented by the target count signal, specifically the count value of the target count circuit 803 for the second count pulse signal; and the target count result is not
  • the count value of the second count pulse signal is the count value of the count signal (that is, the number of pulses included in the count signal).
  • the relationship between the target count result and the third count value is: the target count result is the third count The product of the value, the count threshold, and the preset storage density.
  • the target count result will be loaded into the mode register MR20.
  • MR20 OP[7:0] can represent the error count within a certain range.
  • the output EC[7:0] is the highest bit of 1
  • the corresponding bit of MR20 OP[7:0] will be set to 1. Since the final target count result is recorded in the mode register MR20, when the highest bit of the target count result is 1, the corresponding bit will be set to 1 and loaded into the mode register MR20.
  • other lower bits when other lower bits are 1, they will also be set to 1 at the previous moment. Once a bit higher than the previous moment becomes 1, the lower bit will become 0 and the higher bit will be set to 1.
  • Error Counter can choose to execute code word counting mode or line counting mode through mode register MR14OP[5]. After the DRAM completes the complete ECS operation, the EC count value will be loaded into the mode register MR20 according to the count threshold set by the mode register MR15[2:0]. Among them, how to better design the threshold counting circuit to meet the counting threshold set by MR15[2:0] is a problem that needs to be solved in this disclosure. In addition, EC[7:0] corresponding to mode register MR20 OP[7:0] can represent counting statistics within a certain range.
  • the corresponding bit of the mode register MR20OP[7:0] is set to 1, otherwise it is set to 0. Therefore, how to load the value of EC[7:0] into the mode register MR20 as required is also a problem that this disclosure needs to solve.
  • the counting statistics circuit can be applied to all operations of counting and loading the results into registers.
  • the preset counting range that the target counting result satisfies is determined, and the corresponding bit in the preset mode register can be set to the first value, which solves the problem of how to set the EC[7:0] in the related technology.
  • FIG15 shows a detailed structural diagram of a counting and statistics circuit 80.
  • the counting and statistics circuit 80 may include: an error detection module 121, a mode selection module 122, a first decoding module 123, a threshold counting module 124, a density counting module 125, an error counting module 126, and a second decoding module 127.
  • the first decoding module 123 and the threshold counting module 124 are the threshold counting circuits described in the above embodiment
  • the density counting module 125 is the storage density counting circuit described in the above embodiment
  • the error counting module 126 is the target counting circuit described in the above embodiment.
  • the error detection module 121 may be an error check when performing ECS operation on the storage array (DRAM Array), and generate an ECC_Error signal according to the detected error.
  • the first decoding module 123 can be a 38 decoder; here, after the first decoding module 123 receives the first mode signal MR15 OP[2:0], it decodes and outputs the decoding signal Code ⁇ 7 :0>, specifically including eight-bit sub-decoding signals, namely: Code ⁇ 0>,..., Code ⁇ 6>, Code ⁇ 7>.
  • the threshold counting module 124 it can include eight sub-counting modules. Each sub-counting module includes a selection unit and a counting unit. The selection unit (Multiplexer, MUX) here can convert any of them according to the signal from its own control end.
  • each counting unit is an asynchronous counter formed by a cascade of two first flip-flops, and the last stage of the first flip-flop
  • the second output terminal (QN) is connected to the clock terminal of the density counting module 125;
  • the density counting module 125 can be an asynchronous counter formed by a cascade of multiple second flip-flops, and the second output terminal of the last stage of the second flip-flop (Q is not) connected to the clock terminal of the error counting module 126;
  • the error counting module 126 can be an asynchronous counter formed by a cascade of eight third flip-flops, and the first output terminals (Q) of these eight third flip-flops are respectively Used to output MR20 ⁇ 0>_PRE, MR20 ⁇ 1>_PRE,..., MR20 ⁇ 7>_PRE, and MR20 ⁇ 0>_PRE, MR20 ⁇ 1>_PRE,..., MR20 ⁇ 7>_P
  • the second decoding module 127 can decode the received eight-bit target count sub-signal and store the final error count result. to mode register MR20 OP[7:0]. Specifically, when the error count result meets a certain preset count range, the corresponding bit in MR20 OP[7:0] is set to 1, otherwise it is 0.
  • the counting statistics circuit 80 can be applied to error counting in ECS operation, so an error counter (EC) is also proposed here, which is specifically composed of the first decoding module 123, The threshold counting module 124, the density counting module 125, the error counting module 126 and the second decoding module 127 are jointly composed.
  • ERR_CLK is selected as the clock input of which level of sub-counting module, thereby controlling the level of the overall counter to meet different Threshold levels. error count.
  • the eight-bit target count sub-signal finally output by this overall counter (loaded into MR20 and able to reflect the final error count result) will change as the number of flip-flops inserted into the overall counter changes, so that a large number of MUXes are no longer needed to change the It can be realized by using MR20 signals.
  • the wiring is also greatly reduced, and the circuit logic area can also be greatly reduced.
  • ERR_CLK is used as the input clock signal of the threshold counting module 124, and the signal Code ⁇ 7:0> decoded by MR15 determines the size of the counting threshold.
  • the counting module 126 includes 8 flip-flops, which are used to generate MR20 ⁇ 7:0>_PRE respectively.
  • the EC[7:0] corresponding to MR20 OP[7:0] can represent the error count within a certain range.
  • the corresponding bit of the mode register MR20OP[7:0] is set to 1, otherwise it is set to 0; thus, the error count result can be loaded into the mode register MR20.
  • the semiconductor memory 100 may include DRAM.
  • DRAM can not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, and DDR5, but also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, and LPDDR5. There are no restrictions here.
  • a counter is used to record the number of rows with at least one error or the number of code word errors, and after all ECS operations are performed, the recorded target count results (specifically, the error count results) need to be loaded into the pre-processor. Set in the mode register.
  • this technical solution can be applied to the related circuits of the Error Counter in error checking and clearing in DRAM DDR5 chips, but it is not limited to this scope.
  • FIG. 16 shows a schematic flowchart of a counting method provided by an embodiment of the present disclosure. As shown in Figure 16, the method may include:
  • S1401 Receive the counting signal, count the counting signal through the target counting module inside the threshold counting circuit, and output the first counting pulse signal whenever the counting value corresponding to the counting signal reaches an integer multiple of the counting threshold.
  • S1402 Count the first counting pulse signal through the density counting circuit, and output the second counting pulse signal whenever the count value corresponding to the first counting pulse signal reaches an integer multiple of the preset storage density.
  • the counting method in the embodiment of the present disclosure is applied to the counting and statistical circuit described in the previous embodiment or the semiconductor memory integrated with the counting and statistical circuit, and is specifically used in the circuit design of the DDR5 Error Counter.
  • this counting method specifically involves the circuit design of the Error Counter in error checking and clearing in DRAM DDR5 chips. It requires a complete ECS operation on the DRAM at least every 24 hours and records the number of errors.
  • the counting and statistical circuit may include a threshold counting circuit, a density counting circuit and a target counting circuit.
  • the threshold counting circuit may be the counting circuit 30 described in any one of the above embodiments.
  • the threshold counting circuit includes a first decoding module and a first counting module. Accordingly, the method may also include:
  • the selected target counting module is determined from at least one sub-counting module in the first counting module, and the counting signal is received, and the counting signal is counted by the target counting module. Whenever the counting value corresponding to the counting signal reaches When the counting threshold is an integer multiple, the first counting pulse signal is output.
  • the number of bits of the decoded signal is 2 x ; where x represents the number of bits of the first mode signal.
  • the first mode signal here represents the counting threshold.
  • the decoded signal includes N-bit sub-decoded signals, and N is an integer greater than 0.
  • the method may further include:
  • the level value of the i-th sub-decoded signal is the first value, it is determined that the level values of the other bit-decoded signals except the i-th sub-decoded signal are all the second value. value; wherein, the first value is different from the second value, and different values of i correspond to different decoding signals.
  • Different decoding signals represent different counting thresholds, and i is an integer greater than 0 and less than or equal to N.
  • the number of at least one sub-counting module is N, and the at least one sub-counting module is in a cascade relationship, and there is a corresponding relationship between the i-th sub-counting module and the i-th sub-decoding signal.
  • the method may also include:
  • the level value of the i-th sub-decoding signal is the first value
  • the signal is counted and the first counting pulse signal is output.
  • each sub-counting module includes a first input terminal, a second input terminal and an output terminal.
  • the first input terminal of each sub-counting module is connected to a counting signal;
  • the second input terminal of the first sub-counting module is connected to a first power supply signal;
  • the second input terminal of the jth sub-counting module is connected to an output terminal of the j-1th sub-counting module;
  • the output terminal of the Nth sub-counting module is used to output a first counting pulse signal, and j is an integer greater than 1 and less than or equal to N.
  • the i-th sub-counting module includes the i-th selection unit and the i-th counting unit, and the first input terminal of the i-th selection unit serves as the first input terminal of the i-th sub-counting module.
  • the second input terminal of the i-th selection unit serves as the second input terminal of the i-th sub-counting module for receiving the first input signal.
  • the output terminal of the i-th selection unit is connected to the clock of the i-th counting unit.
  • the output terminal of the i-th counting unit is used as the output terminal of the i-th sub-counting module for outputting the i-th intermediate signal.
  • the method may also include:
  • the i-th selection signal is received through the i-th counting unit and counted, and the i-th intermediate signal is output.
  • the first input signal is the first power signal; when i is greater than 1 and less than or equal to N, the first input signal is the i-1th intermediate signal output by the i-1th counting unit ; And, when i equals N, the Nth intermediate signal is the first counting pulse signal.
  • the i-th counting unit may be an asynchronous binary counter.
  • the asynchronous binary counter includes several first flip-flops connected in sequence, the input end of the first flip-flop of each level is connected to its own second output end, and the second output end of the first flip-flop of each level is connected to The clock terminal of the first flip-flop of the next stage is connected, the clock terminal of the first flip-flop of the first stage is connected to the output terminal of the i-th selection unit, and the second output terminal of the first flip-flop of the last stage is used as the i-th count The output terminal of the unit is used to output the i-th intermediate signal.
  • the method may further include: receiving a second mode signal through a counting signal generation module, and generating a counting signal in response to the second mode signal, where the second mode signal indicates a target counting mode of execution.
  • the method when the threshold counting circuit performs the ECS operation, the method may further include:
  • the target counting mode is the code word counting mode, and the counting signal is the first counting signal
  • the target counting mode is the row counting mode and the counting signal is the second counting signal.
  • the counting signal generation module may include an error detection module and a mode selection module.
  • the method may also include:
  • a first detection signal is generated based on the detected codeword error, and the first detection signal is sent to the mode selection module; and a second detection signal is generated based on the detected row with a codeword error, and the first detection signal is generated based on the detected codeword error.
  • the second detection signal is sent to the mode selection module;
  • the mode selection module receives the second mode selection signal, the first detection signal and the second detection signal, and in response to the control of the second mode signal, generates a first counting signal according to the first detection signal, or generates a first counting signal according to the second detection signal. second counting signal.
  • the method may further include:
  • the second mode selection signal is received through the error detection module; in response to the second mode selection signal, codeword errors are detected in the codeword counting mode, a first detection signal is generated according to the detected codeword error, and the first detection signal is sent to the mode selection module; or, in the row counting mode, detect rows with codeword errors, generate a second detection signal based on the detected rows with codeword errors, and send the second detection signal to the mode selection module;
  • the first detection signal or the second detection signal is received through the mode selection module, and a first counting signal is generated according to the first detection signal, or a second counting signal is generated according to the second detection signal.
  • the storage density counting circuit may be an asynchronous binary counter.
  • the asynchronous binary counter includes several second flip-flops connected in sequence, the input terminal of the second flip-flop of each stage is connected to its own second output terminal, and the second output terminal of the second flip-flop of each stage is connected to The clock terminal of the second flip-flop of the next stage is connected, the clock terminal of the second flip-flop of the first stage is connected to the output terminal of the threshold counting circuit, and the second output terminal of the second flip-flop of the last stage is used as the output of the storage density counting circuit.
  • the terminal is connected to the clock terminal of the target counting circuit.
  • the target counting circuit may be an asynchronous binary counter.
  • the asynchronous binary counter includes several third flip-flops connected in sequence, the input end of each level of the third flip-flop is connected to its own second output end, and the second output end of each level of the third flip-flop is connected to The clock terminal of the third flip-flop of the next stage is connected, and the clock terminal of the third flip-flop of the first stage is connected to the output terminal of the storage density counting circuit.
  • the number of third flip-flops is M
  • the target count signal is a binary number composed of the 0th bit to the M-1th bit target count sub-signal; wherein, the k+1th level third flip-flop The first output terminal of the flip-flop is used to output the k-th target count sub-signal, where k is an integer greater than or equal to 0 and less than M.
  • the method may further include: decoding the target count signal by a second decoding module according to the received ECS end signal and storing the decoded signal in a preset mode register.
  • the preset mode register includes at least M bits, and each bit corresponds to a preset counting range.
  • the method may also include: when the target count result meets the k-th preset count range, setting the value stored in the k-th bit in the preset mode register to the first value, except Values stored in bits other than the k-th bit are set to the second value; where the target count result is the product of the count value represented by the target count signal and the preset value, and the preset value is the product of the count threshold and the preset storage density. value.
  • the minimum value of the k-th preset counting range is set to the product of the preset value and 2 k ; the maximum value of the k-th preset counting range is set to the product of the preset value and 2 k+1 and 1 the difference between.
  • Embodiments of the present disclosure provide a counting method that is applied to the semiconductor memory described in the previous embodiments.
  • different decoding signals can represent different counting threshold levels, and different target counting modules can be selected according to different decoding signals, thereby meeting error counting statistics at different counting threshold levels; according to the decoding Adaptively selecting the target counting module based on different signals can also avoid the problem of excessive connection lines caused by the use of a large number of logic devices in related technologies, thus reducing the circuit area and number of connection lines, and at the same time reducing circuit complexity; in addition, According to the preset counting range that the final error counting result satisfies, the corresponding bit in the preset mode register can be set to 1, so that the error counting result can be loaded into the preset mode register as required, thereby improving memory performance.
  • Embodiments of the present disclosure provide a counting circuit, a semiconductor memory, and a counting method.
  • the counting circuit includes a first decoding module and a first counting module, and the first decoding module is connected to the first counting module; the first decoding module , configured to receive the first mode signal, decode the first mode signal, and generate a decoding signal; the first counting module includes at least one sub-counting module, and is configured to determine the target from the at least one sub-counting module according to the decoding signal.
  • the selected target counting module receives the counting signal, counts the counting signal through the target counting module, and outputs the first counting pulse signal whenever the counting value corresponding to the counting signal reaches an integer multiple of the counting threshold.
  • a decoding signal can be generated according to the first mode signal, and different decoding signals can represent different counting threshold levels, and different target counting modules can be selected according to different decoding signals, thereby meeting different counting threshold levels.
  • Counting statistics; in addition, adaptively selecting the target counting module according to the different decoding signals can also avoid the problem of too many connecting lines caused by the use of a large number of logic devices in related technologies, thereby also reducing the circuit area and the number of connecting lines. , while reducing circuit complexity, thereby improving memory performance.

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Abstract

本公开实施例提供了一种计数电路、半导体存储器以及计数方法，该计数电路包括第一译码模块和第一计数模块，且第一译码模块与第一计数模块连接，其中：第一译码模块，配置为接收第一模式信号，对第一模式信号进行译码处理，生成译码信号；第一计数模块包括至少一个子计数模块，配置为根据译码信号从至少一个子计数模块中确定被选择的目标计数模块，以及接收计数信号，通过目标计数模块对计数信号进行计数，每当计数信号对应的计数值达到计数阈值的整数倍时，输出第一计数脉冲信号。

Description

一种计数电路、半导体存储器以及计数方法
相关申请的交叉引用
本公开基于申请号为202211141024.X、申请日为2022年09月20日、发明名称为“一种计数电路、半导体存储器以及计数方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种计数电路、半导体存储器以及计数方法。
背景技术
随着半导体技术的不断发展，人们在制造和使用计算机等设备时，对数据的传输速度提出了越来越高的要求。为了获得更快的数据传输速度，应运而生了一系列数据可以双倍速率(Double Data Rate，DDR)传输的存储器等器件。
以动态随机存取存储器(Dynamic Random Access Memory，DRAM)为例，需要在至少每24小时对DRAM进行一次完整的错误检查与清除并且记录有多少错误数。然而，相关技术中的错误计数器(Error Counter，EC)存在较多的连接线和逻辑器件，导致电路面积大，而且实现的复杂度高。
发明内容
本公开实施例提供了一种计数电路、半导体存储器以及计数方法。
第一方面，本公开实施例提供了一种计数电路，包括第一译码模块和第一计数模块，且第一译码模块与第一计数模块连接，其中：
第一译码模块，配置为接收第一模式信号，对第一模式信号进行译码处理，生成译码信号；
第一计数模块包括至少一个子计数模块，配置为根据译码信号从至少一个子计数模块中确定被选择的目标计数模块，以及接收计数信号，通过目标计数模块对计数信号进行计数，每当计数信号对应的计数值达到计数阈值的整数倍时，输出第一计数脉冲信号。
在一些实施例中，第一模式信号表征计数阈值。
在一些实施例中，译码信号包括N位子译码信号，N为大于0的整数；第一译码模块，还配置为在生成译码信号的过程中，若第i位子译码信号的电平值为第一值，则确定除第i位子译码信号之外的其他位子译码信号的电平值均为第二值；其中，第一值与第二值不同，而且i的不同取值对应不同的译码信号，不同的译码信号表征不同的计数阈值，i为大于0且小于或等于N的整数。
在一些实施例中，至少一个子计数模块的数量为N个，且至少一个子计数模块为级联关系，第i个子计数模块与第i位子译码信号之间具有对应关系；其中，第一计数模块，配置为在第i位子译码信号的电平值为第一值时，将第i个子计数模块至第N个子计数模块确定为目标计数模块；以及通过第i个子计数模块至第N个子计数模块对计数信号进行计数，输出第一计数脉冲信号。
在一些实施例中，每一个子计数模块包括第一输入端、第二输入端和输出端；其中，每一个子计数模块的第一输入端均与计数信号连接；第1个子计数模块的第二输入端与第一电源信号连接，第j个子计数模块的第二输入端与第j-1个子计数模块的输出端连接，第N个子计数模块的输出端用于输出第一计数脉冲信号，j为大于1且小于或等于N的整数。
在一些实施例中，第i个子计数模块包括第i个选择单元和第i个计数单元，且第i个选择单元的第一输入端作为第i个子计数模块的第一输入端用于接收计数信号，第i个选择单元的第二输入端作为第i个子计数模块的第二输入端用于接收第一输入信号，第i个选择单元的输出端与第i个计数单元的时钟端连接，第i个计数单元的输出端作为第i个子计数模块的输出端用于输出第i中间信号；其中，第i个选择单元，配置为接收第i个子译码信号，根据第i个子译码信号在计数信号和第一输入信号中选择输出第i选择信号；第i个计数单元，配置为接收第i选择信号并进行计数，输出第i中间信号；其中，当i等于1时，第一输入信号为第一电源信号；当i大于1且小于或等于N时，第一输入信号为第i-1个计数单元输出的第i-1中间信号；以及，当i等于N时，第N中间信号为第一计数脉冲信号。
在一些实施例中，第i个计数单元为异步二进制计数器；其中，异步二进制计数器包括若干个 依次级联的第一触发器，每一级第一触发器的输入端(D)与其自身的第二输出端(Q非)连接，且每一级第一触发器的第二输出端(Q非)与下一级第一触发器的时钟端(CLK)连接，第一级第一触发器的时钟端与第i个选择单元的输出端连接，最后一级第一触发器的第二输出端(Q非)作为第i个计数单元的输出端用于输出第i中间信号。
在一些实施例中，计数电路还包括计数信号生成模块，配置为接收第二模式信号，响应于第二模式信号生成计数信号，第二模式信号指示执行的目标计数模式。
在一些实施例中，计数电路在执行错误检查与清除ECS操作时，其中：
若第二模式信号的电平值为第一值，则确定目标计数模式为码字计数模式，计数信号为第一计数信号；或者，若在第二模式信号的电平值为第二值，则确定目标计数模式为行计数模式，计数信号为第二计数信号。
在一些实施例中，计数信号生成模块包括错误检测模块和模式选择模块；其中，错误检测模块，配置为根据检测到的码字错误生成第一检测信号，并将第一检测信号发送给模式选择模块；以及根据检测到的存在码字错误的行生成第二检测信号，并将第二检测信号发送给模式选择模块；模式选择模块，与错误检测模块连接，用于接收第二模式选择信号、第一检测信号和第二检测信号，以及响应于第二模式信号的控制，根据第一检测信号生成第一计数信号，或者，根据第二检测信号生成第二计数信号。
在一些实施例中，计数信号生成模块包括错误检测模块和模式选择模块；其中，错误检测模块，配置为接收所述第二模式选择信号；响应于所述第二模式选择信号，在码字计数模式下检测码字错误，根据检测到的码字错误生成第一检测信号，并将第一检测信号发送给模式选择模块；或者，在行计数模式下检测存在码字错误的行，根据检测到的存在码字错误的行生成第二检测信号，并将第二检测信号发送给模式选择模块；模式选择模块，与错误检测模块连接，用于接收第一检测信号或第二检测信号，并根据第一检测信号生成第一计数信号，或者，根据第二检测信号生成第二计数信号。
在一些实施例中，译码信号的位数为2 x个；其中，x表示第一模式信号的位数。
第二方面，本公开实施例提供了一种半导体存储器，包括阈值计数电路、存储密度计数电路和目标计数电路，且阈值计数电路为第一方面所述的计数电路；其中：
阈值计数电路，用于接收计数信号，并通过内部的目标计数模块对计数信号进行计数，每当计数信号对应的计数值达到计数阈值的整数倍时，输出第一计数脉冲信号；
存储密度计数电路，用于对第一计数脉冲信号进行计数，每当第一计数脉冲信号对应的计数值达到预设存储密度的整数倍时，输出第二计数脉冲信号；
目标计数电路，用于对第二计数脉冲信号进行计数，输出目标计数信号。
在一些实施例中，存储密度计数电路为异步二进制计数器；其中，异步二进制计数器包括若干个依次级联的第二触发器，每一级第二触发器的输入端(D)与其自身的第二输出端(Q非)连接，且每一级第二触发器的第二输出端(Q非)与下一级第二触发器的时钟端(CLK)连接，第一级第二触发器的时钟端与阈值计数电路的输出端连接，最后一级第二触发器的第二输出端(Q非)作为存储密度计数电路的输出端与目标计数电路的时钟端(CLK)连接。
在一些实施例中，第二触发器的数量与预设存储密度之间具有关联关系；其中，预设存储密度为2 y，y表示第二触发器的数量。
在一些实施例中，目标计数电路为异步二进制计数器；其中，异步二进制计数器包括若干个依次级联的第三触发器，每一级第三触发器的输入端(D)与其自身的第二输出端(Q非)连接，且每一级第三触发器的第二输出端(Q非)与下一级第三触发器的时钟端(CLK)连接，第一级第三触发器的时钟端与存储密度计数电路的输出端连接。
在一些实施例中，第三触发器的数量为M个，且目标计数信号是由第0位至第M-1位目标计数子信号组成的二进制数；其中，第k+1级第三触发器的第一输出端(Q)用于输出第k位目标计数子信号，k为大于或等于0且小于M的整数。
在一些实施例中，半导体存储器还包括第二译码模块，配置为根据接收到的ECS结束信号，对目标计数信号进行译码并存储到预设模式寄存器中。
在一些实施例中，预设模式寄存器至少包括M位，且每一位对应一个预设计数范围；其中，第二译码模块，还配置为在目标计数结果满足第k预设计数范围时，将预设模式寄存器中第k位存储的数值设置为第一值，除第k位之外的其他位存储的数值设置为第二值。
在一些实施例中，目标计数结果为目标计数信号表征的计数值与预设值的乘积，预设值为计数阈值与预设存储密度的乘积值；其中，第k预设计数范围的最小值设置为预设值与2 k的乘积；第k预设计数范围的最大值设置为预设值与2 k+1的乘积和1之间的差值。
第三方面，本公开实施例提供了一种计数方法，应用于如第二方面所述的半导体存储器，该方法包括：
接收计数信号，通过阈值计数电路内部的目标计数模块对计数信号进行计数，每当计数信号对应的计数值达到计数阈值的整数倍时，输出第一计数脉冲信号；
通过密度计数电路对第一计数脉冲信号进行计数，每当第一计数脉冲信号对应的计数值达到预 设存储密度的整数倍时，输出第二计数脉冲信号；
通过目标计数电路对第二计数脉冲信号进行计数，输出目标计数信号。
本公开实施例提供了一种计数电路、半导体存储器以及计数方法，该计数电路包括第一译码模块和第一计数模块，且第一译码模块与第一计数模块连接；第一译码模块，配置为接收第一模式信号，对第一模式信号进行译码处理，生成译码信号；第一计数模块包括至少一个子计数模块，配置为根据译码信号从至少一个子计数模块中确定被选择的目标计数模块，以及接收计数信号，通过目标计数模块对计数信号进行计数，每当计数信号对应的计数值达到计数阈值的整数倍时，输出第一计数脉冲信号。这样，根据第一模式信号可以生成译码信号，而不同的译码信号可以表征不同的计数阈值等级，且根据不同的译码信号还能够选择不同的目标计数模块，从而能够满足不同计数阈值等级的计数统计；另外，根据译码信号的不同来自适应选择目标计数模块，还可以避免相关技术中使用大量的逻辑器件而导致连接线过多的问题，从而还能够减小电路面积和连接线数量，同时降低电路复杂度，进而改善存储器的性能。
附图说明
图1为一种错误计数器的组成结构示意图；
图2为一种错误计数器的逻辑电路结构示意图；
图3为本公开实施例提供的一种计数电路的组成结构示意图一；
图4为本公开实施例提供的一种计数电路的组成结构示意图二；
图5为本公开实施例提供的一种计数电路的组成结构示意图三；
图6为本公开实施例提供的一种计数单元的组成结构示意图；
图7为本公开实施例提供的一种计数电路的组成结构示意图四；
图8为本公开实施例提供的一种计数电路的组成结构示意图五；
图9为本公开实施例提供的一种计数电路的组成结构示意图六；
图10为本公开实施例提供的一种半导体存储器的组成结构示意图；
图11为本公开实施例提供的一种计数统计电路的组成结构示意图一；
图12为本公开实施例提供的一种存储密度计数电路的组成结构示意图；
图13为本公开实施例提供的一种目标计数电路的组成结构示意图；
图14为本公开实施例提供的一种计数统计电路的组成结构示意图二；
图15为本公开实施例提供的一种计数统计电路的详细结构示意图；
图16为本公开实施例提供的一种计数方法的流程示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅用于解释相关公开，而非对该公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关公开相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅仅是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
对本公开实施例进行进一步详细说明之前，先对本公开实施例中涉及的名词和术语进行说明，本公开实施例中涉及的名词和术语适用于如下的解释：
动态随机存取存储器(Dynamic Random Access Memory，DRAM)；
同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)；
双倍速率(Double Data Rate，DDR)；
第5代DDR标准(DDR5Specification，DDR5SPEC)；
保留供将来使用(Reserved for Future Usage，RFU)
多用途指令(Multi-Purpose Command，MPC)；
多路选择器(Multiplexer，MUX)；
模式寄存器(Mode Register，MR)；
模式寄存器设置(Mode Register Set，MRS)；
错误检查与清除(Error Check and Scrub，ECS)；
错误检查与纠正(Error Checking and Correcting，ECC)。
在本公开实施例中，ECS模式可以分为自动ECS操作模式和手动ECS操作模式。其中，在手动ECS操作模式下，利用内存控制器(Controller)发送的MPC命令来产生ECS命令信号；在自动ECS操作模式下，可以利用刷新(Refresh)或自刷新(Self-Refresh)来产生ECS命令信号；其中，ECS命令信号用于执行ECS操作。这里，需要至少在24小时内对DRAM进行一次完整的ECS操作。
可以理解地，以DDR5DRAM为例，错误计数器(Error Counter，EC)通过模式寄存器MR14OP[5]选择哪一种模式。其中，当OP[5]＝0时，表示选择行计数模式(默认情况)，该行计数模式用来计数有多少行至少有一个错误；当OP[5]＝1时，表示选择码字计数模式，该码字计数模式用来计数有多少码字错误。在所有ECS操作全部完成一次时，EC结果将根据阈值滤波器(Threshold Filter)加载到模式寄存器中，EC结果在被转移到模式寄存器后会被重置。在这里，阈值滤波器用于掩盖小于阈值滤波器设定阈值的错误计数，具体可以使用模式寄存器MR15 OP[2:0]来设置，默认的设置是256/内存单元，OP[2:0]＝011B。当执行完所有ECS操作后，EC最终记录的结果将会加载到模式寄存器MR20中，MR20 OP[7:0]对应的错误计数结果EC[7:0]表示在一定预设计数范围内的错误计数。例如，如果错误计数结果EC[0]的最小值大于阈值滤波器设定的错误计数阈值(Error Threshold Count，ETC)，且EC[0]的最大值小于或等于2*ETC*存储密度(Density，单位为Gb)-1，那么EC[0]的值为1。在这里，EC[7:1]的最小值被定义为EC[x]min＝ETC*Density*2^x，EC[7:1]的最大值被定义为EC[x]max＝2*(ETC*Density*2^x)-1，即若EC[7:0]的值满足对应的预设计数范围，则MR20 OP[7:0]对应的位会被设置为1，否则被设置为0。其中，x＝0,1,2,…，7。
示例性地，参见表1，其示出了MR15设定的每内存单元(Gb)对应的错误计数阈值(ETC)示意。在默认情况下，该错误计数阈值可以设定为256。
表1
Figure PCTCN2022124052-appb-000001
参见表2，其示出了MR20中每个颗粒(DRAM Die)对应的码字数值或者行数值的存储示意。
表2
  OP[7] OP[6] OP[5] OP[4] OP[3] OP[2] OP[1] OP[0]
MR20 EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0
以码字计数模式为例，错误计数器可以用来计数有多少错误的码字。图1示出了一种错误计数器的组成结构示意图。在图1中，ECC_Error信号表示检测到错误码字信息时产生的脉冲信号，当每一次读取有ECC错误时，错误计数器将会递增。在DRAM完成一次完整的ECS操作之后，最终的错误计数结果会根据MR15译码出来的Code<N:0>来选择错误计数阈值(ETC)和预设存储密度(nGb)，然后将符合当前计数标准的值加载到MR20中。
其中，根据MR15译码出来的Code<N:0>，可以决定当前的ETC，同时乘以芯片的预设存储密度(nGb)，能够得到需要设定的阈值ETCD。以ETCD＝64为例，这时候需要选择连接到MR20中最低位MR20[0]中的值应该时EC64；但如果ETCD＝128，那么需要选择连接到MR20中最低位MR20[0]中的值应该时EC128，其他MR20[1:7]同理倍增选取。如此所设计的错误计数器，就会出现EC*信号和ETCD*信号非常多的连接线和逻辑电路(这里，“*”可以表示64、128、…、1024、2048等)，具体如图2所示。在图2中，这里除了MR20译码模块之外，还需要很多个逻辑器件(例如MUX0、MUX1、...、MUX7等)，而且每一个逻辑器件周围还存在很多个接口，分别与EC64、EC128、…、EC1024、...、ETCD64、ETCD128、…、ETCD1024等等很多个信号连接。这种计数方法的实现电路和连接线较多，不仅增大电路面积，而且复杂度高。因此，如何更好的设计一种计数电路是本公开所需解决的问题。
下面将结合附图对本公开各实施例进行详细说明。
本公开的一实施例中，参见图3，其示出了本公开实施例提供的一种计数电路30的组成结构示意图。如图3所示，该计数电路30可以包括第一译码模块301和第一计数模块302，且第一译码模块301与第一计数模块302连接，其中：
第一译码模块301，配置为接收第一模式信号，对第一模式信号进行译码处理，生成译码信号；
第一计数模块302包括至少一个子计数模块，配置为根据译码信号从至少一个子计数模块中确定被选择的目标计数模块，以及接收计数信号，通过目标计数模块对计数信号进行计数，每当计数 信号对应的计数值达到计数阈值的整数倍时，输出第一计数脉冲信号。
需要说明的是，在本公开实施例中，该计数电路30可以应用于半导体存储器，具体可以是DRAM DDRR芯片中。更具体地，该计数电路30可以应用于执行ECS操作中错误计数的相关电路，但是并不局限于此，这里也可以适用于其他通过计数并且记录结果的电路。
还需要说明的是，在本公开实施例中，第一计数脉冲信号表征计数信号对应的计数值与计数阈值之间的倍数关系。示例性地，以计数阈值设置为4为例，当计数信号累计4个脉冲时，输出的第一计数脉冲信号包括1个脉冲；计数信号累计8个脉冲时，输出的第一计数脉冲信号包括2个脉冲；也就是说，在计数信号的第4、8、12、16、…个脉冲时，输出的第一计数脉冲信号会对应出现一个脉冲。简言之，第一计数脉冲信号表征的是计数信号对应的计数值为计数阈值的多少倍数。
还需要说明的是，在本公开实施例中，第一模式信号可以表征计数阈值。具体地，对于ECS操作过程中的错误计数，这里的计数阈值也可称为错误计数阈值。以前述的表1为例，第一模式信号可以用MR15 OP[2:0]表示。其中，如果第一模式信号为000，那么计数阈值可以为4；如果第一模式信号为001，那么计数阈值可以为16；如果第一模式信号为011，那么计数阈值可以为256等等。也就是说，不同的第一模式信号可以对应不同的计数阈值。
这样，通过第一译码模块301对第一模式信号进行译码处理之后，可以得到译码信号；根据译码信号能够从第一计数模块302中选择出对应的目标计数模块。如此，由于不同的第一模式信号对应不同的计数阈值，并且不同的第一模式信号经过译码得到的不同的译码信号，因而不同的译码信号可以表征不同的计数阈值等级，根据不同的译码信号还能够自适应选择目标计数模块，从而能够满足不同计数阈值等级的计数统计。
在本公开实施例中，具体参见图3，第一译码模块301接收第一模式信号，对第一模式信号进行译码以生成译码信号，该译码信号可以包括N位子译码信号，如图3中的子译码信号1、子译码信号2、…、子译码信号N。第一计数模块302包括至少一个子计数模块，这至少一个子计数模块的数量也为N个，如图3所示的子计数模块1、子计数模块2、…、子计数模块N，而且这至少一个子计数模块为级联关系。其中，N为大于0的整数。
进一步地，在本公开实施例中，无论是译码信号还是第一模式信号，其并非代表一个信号，这里的译码信号和第一模式信号均是多位信号，而且译码信号的位数与第一模式信号的位数之间具有关联关系。在一些实施例中，译码信号的位数为2 x个；其中，x表示第一模式信号的位数。
需要说明的是，译码信号可以是多位子译码信号。在这里，子译码信号的数量等于译码信号的位数，而且子译码信号的数量还等于子计数模块的数量；每一个子译码信号与对应的子计数模块连接。
示例性地，假定第一模式信号包括三位，那么译码信号可以包括八位，即译码信号可以是八位子译码信号组成。因此，在本公开实施例中，第一译码模块301也可以称为三八译码器。
在一些实施例中，译码信号可以包括N位子译码信号，N为大于0的整数；
第一译码模块301，还配置为在生成译码信号的过程中，若第i位子译码信号的电平值为第一值，则确定除第i位子译码信号之外的其他位子译码信号的电平值均为第二值；其中，第一值与第二值不同，i为大于0且小于或等于N的整数。
需要说明的是，在本公开实施例中，i的取值与计数阈值具有关联关系。其中，这N位子译码信号中仅其中一位子译码信号的电平值为第一值，根据这一位子译码信号的位置变化(即i的取值变化)，使得译码信号发生变化；而不同的译码信号对应不同的计数阈值，简言之，i的不同取值对应不同的译码信号，不同的译码信号表征不同的计数阈值。
还需要说明的是，在本公开实施例中，第一值可以为指示高电平的逻辑1，第二值可以为指示低电平的逻辑0；或者，第一值可以为指示低电平的逻辑0，第二值可以为指示高电平的逻辑1，对此并不作任何限定。
示例性地，假定第一值设置为逻辑1，第二值设置为逻辑0，以译码信号包括八位子译码信号为例，译码信号可以为0000 0001、0000 0010、0000 0100、0000 1000，也可以为0001 0000、0010 0000、0100 0000、1000 0000等。结合前述的表1，如果第一模式信号为000，那么对应的译码信号为0000 0001，此时的计数阈值可以为4；如果第一模式信号为001，那么对应的译码信号为0000 0010，此时的计数阈值可以为16；如果第一模式信号为010，那么对应的译码信号为0000 0100，此时的计数阈值可以为64；如果第一模式信号为011，那么对应的译码信号为0000 1000，此时的计数阈值可以为256等等。也就是说，不同的第一模式信号可以对应不同的译码信号。而且在这些不同的译码信号中，每一个译码信号中只有一位子译码信号的电平值等于1；根据电平值等于1的位置不同，可以对应不同的译码信号，不同的译码信号又可以表征不同的计数阈值。
在一些实施例中，在第一计数模块302中，这至少一个子计数模块的数量为N个，而且第i个子计数模块与第i位子译码信号之间具有对应关系，其中：
第一计数模块302，配置为在第i位子译码信号的电平值为第一值时，将第i个子计数模块至第N个子计数模块确定为目标计数模块；以及通过第i个子计数模块至第N个子计数模块对计数信号进行计数，输出第一计数脉冲信号。
需要说明的是，在本公开实施例中，这N个子计数模块为级联关系，而且每一个子计数模块分 别与对应的子译码信号连接。这样，在第i位子译码信号的电平值为第一值时，这时候计数信号作为第i个子计数模块的时钟输入，并且将第i个子计数模块及其之后的子计数模块(即第i个至第N个的子计数模块)作为目标计数模块，也即根据第i个子计数模块及其之后的子计数模块对计数信号进行计数。
对于第一计数模块302而言，参见图4，这里的N个子计数模块依次为：子计数模块1、子计数模块2、…、子计数模块N。其中，子计数模块i表示第i个子计数模块，i为大于0且小于或等于N的整数。
需要说明的是，在本公开实施例中，每一个子计数模块均可以包括第一输入端、第二输入端和输出端，其中，每一个子计数模块的第一输入端均与计数信号连接；以及第1个子计数模块的第二输入端与第一电源信号连接，第j个子计数模块的第二输入端与第j-1个子计数模块的输出端连接，第N个子计数模块的输出端用于输出第一计数脉冲信号，j为大于1且小于或等于N的整数。
在这里，第一电源信号可以是由第一电源提供的电源信号。其中，第一电源可以为一个恒定电源。例如，第一电源可以为VSS电源，用于提供恒定的低电平信号，故第一电源信号也可称为地信号。
还需要说明的是，在本公开实施例中，每一个子计数模块还可以包括控制端，用于接收对应的子译码信号。这样，根据接收到的子译码信号，可以从这N个子计数模块中确定出所需的目标计数模块。
具体来讲，当N等于1时，第一计数模块302只包括一个子计数模块，相应地，译码信号也可仅包括一个子译码信号，该子计数模块即为目标计数模块。这时候，该子计数模块的第一输入端与计数信号连接，该子计数模块的第二输入端与第一电源信号连接，同时该子计数模块的控制端用于接收唯一的子译码信号，该子计数模块的输出端用于输出第一计数脉冲信号。
在本公开实施例中，当N等于1时，实际上是只有一种目标计数模块的实现方式，无法满足多种计数阈值等级的需求。因此，在本公开实施例中，N通常大于1，也就是说，该计数电路30可以应用多种不同的计数阈值等级场景下，根据第一模式信号译码可以确定具体的计数阈值，然后选择相应数量的子计数模块作为目标计数模块，能够适用于不同计数阈值等级的计数场景(例如错误计数场景、其他计数场景等)，灵活性和适配性更强。
示例性地，如图4所示，在N大于1时，每一个子计数模块的第一输入端均用于接收计数信号，每一个子计数模块的控制端均用于接收对应的子译码信号；以及第1个子计数模块(即子计数模块1)的第二输入端与第一电源(VSS)连接，第1个至第N-1个子计数模块的输出端与下一个子计数模块的第二输入端连接，最后一个(第N个)子计数模块(即子计数模块N)的输出端用于输出第一计数脉冲信号。
进一步地，在一些实施例中，在图4所示计数电路30的基础上，参见图5，第i个子计数模块可以包括第i个选择单元和第i个计数单元，且第i个选择单元的第一输入端作为第i个子计数模块的第一输入端用于接收计数信号，第i个选择单元的第二输入端作为第i个子计数模块的第二输入端用于接收第一输入信号，第i个选择单元的输出端与第i个计数单元的时钟端连接，第i个计数单元的输出端作为第i个子计数模块的输出端用于输出第i中间信号，其中：
第i个选择单元，配置为接收第i个子译码信号，根据第i个子译码信号在计数信号和第一输入信号中选择输出第i选择信号；
第i个计数单元，配置为接收第i选择信号并进行计数，输出第i中间信号。
在这里，当i等于1时，第一输入信号为第一电源信号；当i大于1且小于或等于N时，第一输入信号为第i-1个计数单元输出的第i-1中间信号；以及，当i等于N时，第N中间信号为第一计数脉冲信号。
需要说明的是，在本公开实施例中，如图5所示，每一个子计数模块均是由一个选择单元和一个计数单元组成，即：子计数模块1(第1个子计数模块)是由选择单元1(第1个选择单元)和计数单元1(第1个计数单元)组成，子计数模块2(第2个子计数模块)是由选择单元2(第2个选择单元)和计数单元2(第2个计数单元)组成，…，子计数模块N(第N个子计数模块)是由选择单元N(第N个选择单元)和计数单元N(第N个计数单元)组成。
在每一个子计数模块中，选择单元配置为接收对应的子译码信号，即：选择单元1配置为接收子译码信号1(第1个子译码信号)，选择单元2配置为接收子译码信号2(第2个子译码信号)，…，选择单元N配置为接收子译码信号N(第N个子译码信号)。
每一个选择单元可以包括第一输入端、第二输入端、控制端和输出端。其中，第i个选择单元的第一输入端即为第i个子计数模块的第一输入端，第i个选择单元的第二输入端即为第i个子计数模块的第二输入端，第i个选择单元的控制端即为第i个子计数模块的控制端，第i个选择单元的输出端与第i个计数单元的时钟端连接，第i个计数单元的输出端即为第i个子计数模块的输出端。
具体来讲，如图5所示，在子计数模块1中，选择单元1的输出端可以是从计数信号和第一电源信号中选择一者作为第1选择信号进行输出，计数单元1的时钟端用于接收第1选择信号，计数单元1的输出端用于输出第1中间信号；在子计数模块2中，选择单元2的输出端可以是从计数信号和第1中间信号中选择一者作为第2选择信号进行输出，计数单元2的时钟端用于接收第2选择 信号，计数单元2的输出端用于输出第2中间信号；以此类推，在子计数模块N中，选择单元N的输出端可以是从计数信号和第N-1中间信号中选择一者作为第N选择信号进行输出，计数单元N的时钟端用于接收第N选择信号，计数单元N的输出端用于输出第N中间信号(即最终的第一计数脉冲信号)。
这样，根据N位子译码信号，如果第1位子译码信号(子译码信号1)的电平值为第一值，那么选择单元1将会输出计数信号作为第1选择信号，此时级联的子计数模块1至子计数模块N作为目标计数模块；如果第2位子译码信号(子译码信号2)的电平值为第一值，那么选择单元2将会输出计数信号作为第2选择信号，此时级联的子计数模块2至子计数模块N作为目标计数模块；以此类推，如果第N位子译码信号(子译码信号N)的电平值为第一值，那么选择单元N将会输出计数信号作为第N选择信号，此时仅有子计数模块N作为目标计数模块；如此，能够实现根据这N位子译码信号自适应选择目标计数模块，进而满足不同计数阈值等级的计数统计。
进一步地，对于第j个计数单元而言，在一些实施例中，第i个计数单元为异步二进制计数器，其中：
异步二进制计数器可以包括若干个依次级联的第一触发器，每一级第一触发器的输入端(D)与其自身的第二输出端(Q非)连接，且每一级第一触发器的第二输出端(Q非)与下一级第一触发器的时钟端(CLK)连接，第一级第一触发器的时钟端与第i个选择单元的输出端连接，最后一级第一触发器的第二输出端(Q非)作为第i个计数单元的输出端用于输出第i中间信号。
在本公开实施例中，对于计数单元i而言，以图6所示的异步二进制计数器为例，该计数单元i可以包括两个第一触发器。在这里，第一触发器可以为D型触发器，D型触发器(Data Flip-Flop或Delay Flip-Flop，DFF)是一个具有记忆功能的、具有两个稳定状态的信息存储器件，是构成多种时序电路的最基本逻辑单元，也是数字逻辑电路中一种重要的单元电路。D型触发器具有两个稳定状态，即“0”和“1”，在该触发器的时钟端所接收的信号触发沿触发下，可以从一个稳定状态翻转到另一个稳定状态。
对于图6中的第一触发器(DFF11或DFF12)而言，第一触发器包括输入端(D)、时钟端(CLK)、第一输出端(Q)和第二输出端(Q非，用/Q表示)。在这里，每一级第一触发器的输入端(D)与自身的第二输出端(/Q)连接，而且每一级第一触发器的第二输出端(/Q)还与下一级第一触发器的时钟端(CLK)连接；另外，第一级第一触发器(即DFF11)的时钟端(CLK)与第i选择信号连接，最后一级第一触发器(即DFF12)的第二输出端(/Q)用于输出第i中间信号。
还需要说明的是，假定译码信号包括八位子译码信号，第一计数模块302包括八个子计数模块，每一个子计数模块中的计数单元均包括两个级联的第一触发器；这时候，若第1位子译码信号(子译码信号1)的电平值为第一值，则目标计数模块是由子计数模块1至子计数模块8级联得到，此时目标计数模块中包括级联的16个第一触发器；或者，若第7位子译码信号(子译码信号7)的电平值为第一值，则目标计数模块是由子计数模块7至子计数模块8级联得到，此时目标计数模块中包括级联的4个第一触发器；或者，若第8位子译码信号(子译码信号8)的电平值为第一值，则目标计数模块仅包括子计数模块8，此时目标计数模块中包括级联的2个第一触发器。
这样，第一译码模块301对第一模式信号译码得到八位子译码信号之后，根据这八位子译码信号不仅可以确定计数阈值等级，而且还可以选择将计数信号作为某一个计数单元(具体是指某一级第一触发器)的时钟输入，从而能够整体控制第一计数模块302的等级，以实现满足不同计数阈值等级的计数统计。
在一些实施例中，在图3所示计数电路30的基础上，参见图7，该计数电路30还可以包括计数信号生成模块303，其中：
计数信号生成模块303，配置为接收第二模式信号，响应于所述第二模式信号生成所述计数信号，所述第二模式信号指示执行的目标计数模式。
需要说明的是，在本公开实施例中，第一模式信号和第二模式信号不同。其中，第一模式信号可以是模式寄存器MR15中的用于设定计数阈值的模式信号，第二模式信号可以是模式寄存器MR14中的用于设定计数模式的模式信号。
还需要说明的是，在本公开实施例中，这里的计数模式可以存在两种：码字计数模式和行计数模式。其中，码字计数模式用于计数有多少错误的码字数，行计数模式用于计数有多少至少有一个错误码字的行数。因此，在一些实施例中，计数电路30在执行ECS操作时，其中：
若第二模式信号的电平值为第一值，则确定目标计数模式为码字计数模式，计数信号为第一计数信号；或者，
若在第二模式信号的电平值为第二值，则确定目标计数模式为行计数模式，计数信号为第二计数信号。
在本公开实施例中，第一计数信号也可以称为码字错误计数信号，第二计数信号也可以称为码字错误行计数信号。
在本公开实施例中，第一值可以为指示高电平的逻辑1，第二值可以为指示低电平的逻辑0；或者，第一值可以为指示低电平的逻辑0，第二值可以为指示高电平的逻辑1，对此并不作任何限定。
示例性地，如果第一值为逻辑1，第二值为逻辑0，那么在第二模式信号等于逻辑1时，这时候 为码字计数模式，对应的计数信号为第一计数信号(即码字错误计数信号)；在第二模式信号等于逻辑0时，这时候为行计数模式，对应的计数信号为第二计数信号(即码字错误行计数信号)。这样，在计数电路30中，通过第二模式信号可以选择是执行行计数模式还是执行码字计数模式。
在一些实施例中，在图7所示计数电路30的基础上，参见图8，该计数信号生成模块303可以包括错误检测模块3031和模式选择模块3032，其中：
错误检测模块3031，配置为根据检测到的码字错误生成第一检测信号，并将第一检测信号发送给模式选择模块3032；以及根据检测到的存在码字错误的行生成第二检测信号，并将第二检测信号发送给模式选择模块3032；
模式选择模块3032，与错误检测模块3031连接，用于接收第二模式选择信号、第一检测信号和第二检测信号，以及响应于第二模式信号的控制，根据第一检测信号生成第一计数信号，或者，根据第二检测信号生成第二计数信号。
在本公开实施例中，错误检测模块3031既可以检测到码字错误，以生成第一检测信号，同时又可以检测到存在码字错误的行，以生成第二检测信号；然后将第一检测信号和第二检测信号同时发送给模式选择模块3032；此时在模式选择模块3032中，根据接收到的第二模式选择信号来确定是码字计数模式还是行计数模式；然后如果是码字计数模式，那么可以根据第一检测信号来生成第一计数信号；或者，如果是行计数模式，那么可以根据第二检测信号来生成第二计数信号。
在一些实施例中，在图7所示计数电路30的基础上，参见图9，该计数信号生成模块303可以包括错误检测模块3033和模式选择模块3034，其中：
错误检测模块3033，配置为接收第二模式选择信号；响应于第二模式选择信号，在码字计数模式下检测码字错误，根据检测到的码字错误生成第一检测信号，并将第一检测信号发送给模式选择模块3034；或者，在行计数模式下检测存在码字错误的行，根据检测到的存在码字错误的行生成第二检测信号，并将第二检测信号发送给模式选择模块3034；
模式选择模块3034，与错误检测模块3033连接，用于接收第一检测信号或第二检测信号，并根据第一检测信号生成第一计数信号，或者，根据第二检测信号生成第二计数信号。
在本公开实施例中，错误检测模块3033在接收到第二模式选择信号之后，可以用来确定是码字计数模式还是行计数模式；然后如果是码字计数模式，那么根据检测到的码字错误生成第一检测信号，并将第一检测信号发送给模式选择模块3034；或者，如果是行计数模式，那么根据检测到的存在码字错误的行生成第二检测信号，并将第二检测信号发送给模式选择模块3034；然后根据第一检测信号或第二检测信号来对应生成第一计数信号或第二计数信号。
还需要说明的是，在本公开实施例中，不同计数模式对应不同的检测信号；不同的检测信号对应不同的计数信号(如码字错误计数信号或者码字错误行计数信号)。在这里，不同的计数信号可以表征至少有一个码字错误的行数或者总共有多少码字错误数，从而根据计数电路30可以确定该计数信号表征的计数值与计数阈值之间的倍数关系，换言之，该计数值中包括多少倍的计数阈值。
示例性地，以码字计数模式为例，每检测到一个错误码字，就会对应产生一个脉冲，以此能够生成具有多个脉冲的计数信号。对于计数电路30而言，第一模式信号可以表征预设的计数阈值，而根据第一模式信号可以译码出至少一位子译码信号，这至少一位子译码信号可以确定出该计数阈值对应的目标计数模块；如此，通过该目标计数模块对计数信号进行计数，可以在每计数到计数阈值时会输出一个脉冲，以此生成第一计数脉冲信号。也就是说，第一计数脉冲信号表征计数信号对应的计数值与计数阈值之间的倍数关系。
本公开实施例提供了一种计数电路，不同的译码信号可以表征不同的计数阈值等级，且根据不同的译码信号还能够自适应选择不同的目标计数模块，从而不仅能够满足不同计数阈值等级的计数统计，而且还可以避免相关技术中使用大量的逻辑器件而导致连接线过多的问题，降低了电路复杂度，进而改善存储器的性能。
本公开的另一实施例中，参见图10，其示出了本公开实施例提供的一种半导体存储器的组成结构示意图。如图10所示，该半导体存储器100可以包括计数统计电路80。
在一些实施例中，图11示出了一种计数统计电路80的组成结构示意图。如图11所示，该计数统计电路80可以包括阈值计数电路801、存储密度计数电路802和目标计数电路803，其中：
阈值计数电路801，用于接收计数信号，并通过内部的目标计数模块对计数信号进行计数，每当计数信号对应的计数值达到计数阈值的整数倍时，输出第一计数脉冲信号；
存储密度计数电路802，用于对第一计数脉冲信号进行计数，每当第一计数脉冲信号对应的计数值达到预设存储密度的整数倍时，输出第二计数脉冲信号；
目标计数电路803，用于对第二计数脉冲信号进行计数，输出目标计数信号。
需要说明的是，在本公开实施例中，阈值计数电路801可以为前述实施例任一项的计数电路30。
还需要说明的是，在本公开实施例中，第一计数脉冲信号可以表征计数信号对应的计数值与计数阈值之间的倍数关系，第二计数脉冲信号可以表征第一计数脉冲信号对应的计数值与预设存储密度之间的倍数关系，目标计数信号表征第二计数脉冲信号对应的计数值，而目标计数结果为目标计数信号表征的计数值、计数阈值和预设存储密度的乘积，这里的目标计数结果能够表示计数统计电路80针对当前错误数据总共统计出多少个错误数。如此，在得到目标计数结果之后，根据该目标计 数结果可以进一步确定其对应的预设计数范围，以便将其加载到预设模式寄存器中。
还需要说明的是，在本公开实施例中，阈值计数电路801可以得到第一计数值，存储密度计数电路802可以得到第二计数值，目标计数电路803可以得到第三计数值。其中，第一计数值指示第一计数脉冲信号包括多少倍的计数阈值，第二计数值指示第二计数脉冲信号包括多少倍的预设存储密度，第三计数值即为目标计数信号表征的计数值。如此，目标计数结果可以是根据计数阈值、预设存储密度和第三计数值确定的，更具体地，假定预设值为计数阈值与预设存储密度的乘积值，那么目标计数结果为第三计数值与预设值的乘积。
在一些实施例中，对于存储密度计数电路802而言，存储密度计数电路802可以为异步二进制计数器，其中：
异步二进制计数器包括若干个依次级联的第二触发器，每一级第二触发器的输入端(D)与其自身的第二输出端(/Q)连接，且每一级第二触发器的第二输出端(/Q)与下一级第二触发器的时钟端(CLK)连接，第一级第二触发器的时钟端与阈值计数电路801的输出端连接，最后一级第二触发器的第二输出端(/Q)作为存储密度计数电路的输出端与目标计数电路803的时钟端(CLK)连接。
需要说明的是，在本公开实施例中，预设存储密度表征DRAM的内存为多个Gb，例如8Gb、16Gb、32Gb等。在实际应用中，预设存储密度可以根据实际情况进行具体设定，这里不作任何限定。
还需要说明的是，在本公开实施例中，第二触发器的数量与预设存储密度之间具有关联关系；其中，预设存储密度为d，第二触发器的数量为y，且d＝2 y。
对于存储密度计数电路802而言，以图12所示的异步二进制计数器为例，假定预设存储密度为16Gb，那么该异步二进制计数器包括四个第二触发器。在这里，第二触发器可以为D型触发器，这四个第二触发器分别为：DFF21、DFF22、DFF23和DFF24，而且DFF1、DFF22、DFF23和DFF24为级联关系。
对于图12中的每一级第二触发器而言，第二触发器包括输入端(D)、时钟端(CLK)、第一输出端(Q)和第二输出端(/Q)。在这里，每一级第二触发器的输入端(D)与自身的第二输出端(/Q)连接，而且每一级第二触发器的第二输出端(/Q)还与下一级第二触发器的时钟端(CLK)连接；而且第一级第二触发器(即DFF21)的时钟端(CLK)用于接收第一计数脉冲信号，最后一级第一触发器(即DFF24)的第二输出端(/Q)用于输出第二计数脉冲信号。其中，第二计数脉冲信号可以表征第一计数脉冲信号对应的计数值与预设存储密度之间的倍数关系，也可以是当前错误数据与(计数阈值*预设存储密度)之间的倍数关系。
在一些实施例中，对于目标计数电路803而言，目标计数电路803可以为异步二进制计数器，其中：
异步二进制计数器包括若干个依次级联的第三触发器，每一级第三触发器的输入端(D)与其自身的第二输出端(/Q)连接，且每一级第三触发器的第二输出端(/Q)与下一级第三触发器的时钟端(CLK)连接，第一级第三触发器的时钟端与存储密度计数电路802的输出端连接。
在一些实施例中，目标计数信号可以是由第0位至第M-1位目标计数子信号组成的二进制数；相应地，第三触发器的数量为M个，其中：
第k+1级第三触发器的第一输出端(Q)用于输出第k位目标计数子信号，k为大于或等于0且小于M的整数，且M为大于零的整数。
需要说明的是，对于目标计数电路803而言，以图13所示的异步二进制计数器为例，假定M等于8，那么该异步二进制计数器包括八个第三触发器。在这里，第三触发器可以为D型触发器，这八个第三触发器分别为：DFF31、DFF32、DFF33、DFF34、DFF35、DFF36、DFF37和DFF38，而且DFF31、DFF32、DFF33、DFF34、DFF35、DFF36、DFF37和DFF38为级联关系。
对于图13中的每一级第三触发器而言，第三触发器包括输入端(D)、时钟端(CLK)、第一输出端(Q)和第二输出端(/Q)。在这里，第一级第三触发器(即DFF31)的时钟端(CLK)用于接收第二计数脉冲信号，每一级第三触发器的输入端(D)与自身的第二输出端(/Q)连接，而且每一级第三触发器的第二输出端(/Q)还与下一级第二触发器的时钟端(CLK)连接，每一级第三触发器的第一输出端(Q)用于输出一位目标计数子信号。在图13中，这里会输出八位目标计数子信号，即：MR20<0>_PRE、MR20<1>_PRE、…、MR20<7>_PRE；这八位目标计数子信号可以指示第三计数值，而根据计数阈值、预设存储密度和第三计数值能够确定最终的目标计数结果。
进一步地，在一些实施例中，在图11所示计数统计电路80的基础上，参见图14，计数统计电路80还可以包括第二译码模块804和预设模式寄存器805，其中：
第二译码模块804，配置为根据接收到的ECS结束信号，对目标计数信号进行译码并存储到预设模式寄存器805中。
需要说明的是，在本公开实施例中，预设模式寄存器805可以是MR20。在一些实施例中，该预设模式寄存器805至少包括M位，且每一位对应一个预设计数范围，且预设计数范围之间不重叠，其中：
第二译码模块804，还配置为在目标计数结果满足第k预设计数范围时，将预设模式寄存器中第k位存储的数值设置为第一值，除第k位之外的其他位存储的数值设置为第二值。
在这里，第一值可以为指示高电平的逻辑1，第二值可以为指示低电平的逻辑0；或者，第一值可以为指示低电平的逻辑0，第二值可以为指示高电平的逻辑1，对此并不作任何限定。
在这里，目标计数结果可以为目标计数信号表征的计数值与预设值的乘积，该预设值则为计数阈值与预设存储密度的乘积值。如此，第k预设计数范围的最小值设置为预设值与2 k的乘积；第k预设计数范围的最大值设置为预设值与2 k+1的乘积和1之间的差值。
还需要说明的是，在本公开实施例中，假定计数阈值用ETC表示，预设存储密度用Density(Gb)表示，第k预设计数范围的最小值可以用EC[k]min表示，第k预设计数范围的最大值用EC[k]max表示，具体计算公式如下：
EC[k]min＝ETC*Density(Gb)*2 k                   (1)；
EC[k]max＝2*(ETC*Density(Gb)*2 k)-1＝ETC*Density(Gb)*2 k+1-1     (2)。
其中，k为大于或等于0且小于M的整数，M表示预设模式寄存器805所包括的位数，且M为正整数。
可以理解地，以错误计数为例，在接收到ECS结束信号之后，意味着本次ECS操作的错误计数完成。在M等于8的情况下，通过对目标计数信号进行译码处理，可以得到错误计数译码信号，用EC[7:0]表示；根据错误计数译码信号EC[7:0]来将模式寄存器MR20中对应位存储的数值设置为第一值。
具体来讲，错误计数译码信号EC[7:0]可以表示在一定计数范围内的错误计数。其中，EC[7:0]可以包括：EC[0]、EC[1]、EC[2]、EC[3]、EC[4]、EC[5]、EC[6]和EC[7]；这里，在第一值为逻辑1，第二值为逻辑0时，EC[0]＝1对应第0预设计数范围，EC[1]＝1对应第1预设计数范围，EC[2]＝1对应第2预设计数范围，…，EC[7]＝1对应第7预设计数范围。示例性地，表3示出了八种预设计数范围的示意数据范围。
表3
EC[] 预设计数范围
EC[0]＝1 64～127
EC[1]＝1 128～255
EC[2]＝1 256～511
EC[3]＝1 512～1023
EC[4]＝1 1024～2047
EC[5]＝1 2048～4095
EC[6]＝1 4096～8191
EC[7]＝1 8192～16383
在这里，在得到最终的目标计数结果之后，如果目标计数结果为125，该目标计数结果处于第0预设计数范围，此时EC[0]＝1，那么模式寄存器MR20中第0位(即MR20 OP[0])被设置为1；如果目标计数结果为456，该目标计数结果处于第2预设计数范围，此时EC[2]＝1，那么模式寄存器MR20中第2位(即MR20 OP[2])被设置为1；如果目标计数结果为3000，该目标计数结果处于第5预设计数范围，此时EC[5]＝1，那么模式寄存器MR20中第5位(即MR20 OP[5])被设置为1等等。也就是说，在目标计数结果满足对应的预设计数范围时，模式寄存器MR20中对应的位被设置为1。
在另一些实施例中，第二译码模块804，还配置为在目标计数信号表征的计数值满足第k预设计数范围时，将预设模式寄存器中第k位存储的数值设置为第一值，除第k位之外的其他位存储的数值设置为第二值。
在这里，第k预设计数范围的最小值可以用EC[k]min表示，第k预设计数范围的最大值用EC[k]max表示，具体计算公式如下：
EC[k]min＝2 k              (3)；
EC[k]max＝2 k+1-1               (4)。
其中，k为大于或等于0且小于M的整数。示例性地，在M等于8时，表4示出了八种预设计数范围的示意数据范围。
表4
EC[] 预设计数范围
EC[0]＝1 1～1
EC[1]＝1 2～3
EC[2]＝1 4～7
EC[3]＝1 8～15
EC[4]＝1 16～31
EC[5]＝1 32～63
EC[6]＝1 64～127
EC[7]＝1 128～255
在这里，在确定出目标计数信号表征的计数值(即为第三计数值)之后，如果第三计数值为1，即第三计数值处于第0预设计数范围，此时EC[0]＝1，那么模式寄存器MR20中第0位(即MR20 OP[0])被设置为1；如果第三计数值为3，即第三计数值处于第1预设计数范围，此时EC[1]＝1，那么模式寄存器MR20中第1位(即MR20 OP[1])被设置为1；如果第三计数值为45，第三计数值处于第5预设计数范围，此时EC[5]＝1，那么模式寄存器MR20中第5位(即MR20 OP[5])被设置为1等等。也就是说，在第三计数值满足对应的预设计数范围时，模式寄存器MR20中对应的位被设置为1。需要注意的是，第三计数值与目标计数结果不同，第三计数值是目标计数信号表征的计数值，具体是目标计数电路803针对第二计数脉冲信号的计数值；而目标计数结果并非是第二计数脉冲信号的计数值，其是针对计数信号的计数值(即计数信号所包括的脉冲个数)，目标计数结果与第三计数值之间的关系是：目标计数结果是第三计数值、计数阈值与预设存储密度的三者乘积。
简单来说，在完成一次完整的ECS操作后，目标计数结果将会加载到模式寄存器MR20中。其中，MR20 OP[7:0]能够表示在一定范围内的错误计数，当输出EC[7:0]为1的最高位时，MR20 OP[7:0]对应的位会被设置为1。由于模式寄存器MR20中记录最终的目标计数结果，所以当目标计数结果的最高位为1时，对应的位才会被设置为1，同时加载到模式寄存器MR20中。另外，需要注意的是，当其他较低位为1时，也会在前一时刻设置为1，一旦出现比前一时刻高的位变为1，此时较低位就会变为0，同时较高位会被设置为1。
综上可知，Error Counter可以通过模式寄存器MR14OP[5]进行选择执行码字计数模式或者行计数模式。在DRAM完成完整的ECS操作后，EC计数的值会根据模式寄存器MR15[2:0]设定的计数阈值，将目标计数结果加载到模式寄存器MR20中。其中，如何更好地设计阈值计数电路来满足MR15[2:0]设定的计数阈值是本公开需要解决的问题。另外，模式寄存器MR20 OP[7:0]对应的EC[7:0]可以表示在一定范围内的计数统计。当目标计数结果满足对应的预设计数范围时，模式寄存器MR20OP[7:0]对应的位被设置为1，否则被设置为0。因此，如何将EC[7:0]的值按照要求加载到模式寄存器MR20中也是本公开需要解决的问题。
在本公开实施例中，该计数统计电路可以适用于所有计数并将结果加载到寄存器的操作。根据所得到的目标计数结果，确定出目标计数结果满足的预设计数范围，可以将预设模式寄存器中对应的位设置为第一值，解决了相关技术中如何将EC[7:0]的值按照要求加载到模式寄存器中的技术问题，从而能够准确地将错误计数结果按照需求加载到模式寄存器中。
在一种具体的实施例中，图15示出了一种计数统计电路80的详细结构示意图。如图15所示，该计数统计电路80可以包括：错误检测模块121、模式选择模块122、第一译码模块123、阈值计数模块124、密度计数模块125、错误计数模块126和第二译码模块127。其中，第一译码模块123和阈值计数模块124即为前述实施例所述的阈值计数电路，密度计数模块125即为前述实施例所述的存储密度计数电路，错误计数模块126即为前述实施例所述的目标计数电路。
在图15中，错误检测模块121可以是对存储阵列(DRAM Array)进行ECS操作时的错误检查，根据检查到的错误来生成ECC_Error信号。模式选择模块122在接收到第二模式信号MR14OP[5]之后，若MR14OP[5]＝1，则为码字计数模式；若MR14OP[5]＝0，则为行计数模式；无论是码字计数模式还是行计数模式，根据ECC_Error信号可以生成计数信号ERR_CLK，ERR_CLK信号作为阈值计数模块124的时钟输入。对于第一译码模块123而言，可以是三八译码器；在这里，第一译码模块123接收第一模式信号MR15 OP[2:0]后，译码输出译码信号Code<7:0>，具体包括八位子译码信号，即：Code<0>、…、Code<6>、Code<7>。而对于阈值计数模块124而言，这里可以包括八个子计数模块，每一个子计数模块均包括一个选择单元和一个计数单元，这里的选择单元(Multiplexer，MUX)可以根据自身控制端的信号将其中任意一路输入信号选择输出，而每一个选择单元的控制端与对应的子译码信号连接；每一个计数单元是由2个第一触发器级联形成的异步计数器，最后一级第一触发器的第二输出端(Q非)与密度计数模块125的时钟端连接；密度计数模块125可以是由多个第二触发器级联形成的异步计数器，最后一级第二触发器的第二输出端(Q非)与错误计数模块126的时钟端连接；错误计数模块126可以是由八个第三触发器级联形成的异步计数器，这八个第三触发器的第一输出端(Q)分别用于输出MR20<0>_PRE、MR20<1>_PRE、…、MR20<7>_PRE，而MR20<0>_PRE、MR20<1>_PRE、…、MR20<7>_PRE这八位目标计数子信号可以表征最终的目标计数结果(具体为错误计数结果)。这样，在接收到ECS结束信号ECS_END之后，表示本次ECS操作完成，这时候第二译码模块127可以对接收到的这八位目标计数子信号进行译码，并且将最终的错误计数结果存储到模式寄存器MR20 OP[7:0]中。具体地，在错误计数结果满足某预设计数范围时，将MR20 OP[7:0]中对应的位设置为1，否则为0。
需要说明的是，在本公开实施例中，计数统计电路80可以应用于ECS操作中的错误计数，故这里还提出了一种错误计数器(EC)，其具体是由第一译码模块123、阈值计数模块124、密度计数模块125、错误计数模块126和第二译码模块127共同组成的。对于该错误计数器而言，通过采用选择ERR_CLK的方式，根据MR15译码出来的ETC值，选择将ERR_CLK作为第几级子计数模块的时钟输入，从而控制整体计数器的等级，来实现满足不同Threshold等级的错误计数。此整体计数 器最终输出的八位目标计数子信号(加载到MR20，且能够反映最终的错误计数结果)会随着插入整体的触发器数量变化而变化，如此不再需要大量的MUX来改变加载到MR20的信号来实现，同时由于信号数量的减少，绕线也大大减少，同时还能够使得电路逻辑面积大大减小。
在图15中，ERR_CLK作为阈值计数模块124的输入时钟信号，MR15译码出信号Code<7:0>决定计数阈值的大小，可以选择ERR_CLK接入子计数模块的级数。示例性地，当选择第一级MUX的1输入时代表计数阈值设置为最大值，有最多的触发器接入的错误计数；当选择第二级MUX时，则第一级MUX输入VSS信号，计数阈值就相对较少，当Code<0>为1时，这时候的计数阈值等于4，因此只有两个触发器接入。由于技术规格定义：EC[k]min＝ETC*Density(Gb)*2 k，所以之后再加入密度计数模块125的部分，以16Gb容量为例，这里会再插入4个触发器；最后的错误计数模块126包括有8个触发器，分别用来产生MR20<7:0>_PRE。这样，MR20 OP[7:0]对应的EC[7:0]可以表示在一定范围内的错误计数。当错误计数结果满足对应的预设计数范围时，模式寄存器MR20OP[7:0]对应的位被设置为1，否则被设置为0；从而能够实现将错误计数结果加载到模式寄存器MR20中。
需要说明的是，在本公开实施例中，半导体存储器100可以包括DRAM。其中，对于DRAM来说，不仅可以符合DDR、DDR2、DDR3、DDR4、DDR5等内存规格，还可以符合LPDDR、LPDDR2、LPDDR3、LPDDR4、LPDDR5等内存规格，这里不作任何限定。
还需要说明的是，在本公开实施例中，这里主要涉及集成电路设计中错误检查与清除中的Error Counter的相关电路设计，尤其涉及DRAM DDR5芯片中，它需要在至少每24小时对DRAM进行一次完整的ECS操作并且记录有多少错误数。具体地，这里是采用计数器记录至少有一个错误的行数或者记录有多少码字错误数，并且在执行完所有ECS操作之后，需要将记录的目标计数结果(具体为错误计数结果)加载到预设模式寄存器中。换句话说，本技术方案可以应用于DRAM DDR5芯片中错误检查与清除中的Error Counter的相关电路，但不局限于此范围，其他通过计数并且记录结果的相关电路也适用于本技术方案。本公开的再一实施例中，参见图16，其示出了本公开实施例提供的一种计数方法的流程示意图。如图16所示，该方法可以包括：
S1401：接收计数信号，通过阈值计数电路内部的目标计数模块对计数信号进行计数，每当计数信号对应的计数值达到计数阈值的整数倍时，输出第一计数脉冲信号。
S1402：通过密度计数电路对第一计数脉冲信号进行计数，每当第一计数脉冲信号对应的计数值达到预设存储密度的整数倍时，输出第二计数脉冲信号。
S1403：通过目标计数电路对第二计数脉冲信号进行计数，输出目标计数信号。
需要说明的是，本公开实施例的计数方法应用于前述实施例所述的计数统计电路或者集成有该计数统计电路的半导体存储器，具体应用于DDR5 Error Counter的电路设计中。也就是说，该计数方法具体涉及DRAM DDR5芯片中错误检查与清除中的Error Counter的相关电路设计，它需要在至少每24小时对DRAM进行一次完整的ECS操作并且记录有多少错误数。
还需要说明的是，在本公开实施例中，计数统计电路可以包括阈值计数电路、密度计数电路和目标计数电路。其中，阈值计数电路可以为前述实施例中任一项所述的计数电路30。
可以理解地，在一些实施例中，阈值计数电路包括第一译码模块和第一计数模块。相应地，该方法还可以包括：
通过第一译码模块接收第一模式信号，对第一模式信号进行译码处理，生成译码信号；
根据译码信号，从第一计数模块中的至少一个子计数模块中确定被选择的目标计数模块，以及接收计数信号，通过目标计数模块对计数信号进行计数，每当计数信号对应的计数值达到计数阈值的整数倍时，输出第一计数脉冲信号。
在本公开实施例中，译码信号的位数为2 x个；其中，x表示第一模式信号的位数。另外，这里的第一模式信号表征计数阈值。
在本公开实施例中，译码信号包括N位子译码信号，N为大于0的整数。相应地，对于第一译码模块而言，在一些实施例中，该方法还可以包括：
在生成译码信号的过程中，若第i位子译码信号的电平值为第一值，则确定除第i位子译码信号之外的其他位子译码信号的电平值均为第二值；其中，第一值与第二值不同，而且i的不同取值对应不同的译码信号，不同的译码信号表征不同的计数阈值，i为大于0且小于或等于N的整数。
在本公开实施例中，至少一个子计数模块的数量为N个，且至少一个子计数模块为级联关系，第i个子计数模块与第i位子译码信号之间具有对应关系。相应地，对于第一计数模块而言，在一些实施例中，该方法还可以包括：
在第i位子译码信号的电平值为第一值时，将第i个子计数模块至第N个子计数模块确定为目标计数模块；以及通过第i个子计数模块至第N个子计数模块对计数信号进行计数，输出第一计数脉冲信号。
在一些实施例中，每一个子计数模块包括第一输入端、第二输入端和输出端。其中，每一个子计数模块的第一输入端均与计数信号连接；第1个子计数模块的第二输入端与第一电源信号连接，第j个子计数模块的第二输入端与第j-1个子计数模块的输出端连接，第N个子计数模块的输出端用于输出第一计数脉冲信号，j为大于1且小于或等于N的整数。
进一步地，在一些实施例中，第i个子计数模块包括第i个选择单元和第i个计数单元，且第i个选择单元的第一输入端作为第i个子计数模块的第一输入端用于接收计数信号，第i个选择单元的第二输入端作为第i个子计数模块的第二输入端用于接收第一输入信号，第i个选择单元的输出端与第i个计数单元的时钟端连接，第i个计数单元的输出端作为第i个子计数模块的输出端用于输出第i中间信号。相应地，该方法还可以包括：
通过第i个选择单元接收第i个子译码信号，根据第i个子译码信号在计数信号和第一输入信号中选择输出第i选择信号；
通过第i个计数单元接收第i选择信号并进行计数，输出第i中间信号。
在这里，当i等于1时，第一输入信号为第一电源信号；当i大于1且小于或等于N时，第一输入信号为第i-1个计数单元输出的第i-1中间信号；以及，当i等于N时，第N中间信号为第一计数脉冲信号。
进一步地，在一些实施例中，第i个计数单元可以为异步二进制计数器。其中，异步二进制计数器包括若干个依次级联的第一触发器，每一级第一触发器的输入端与其自身的第二输出端连接，且每一级第一触发器的第二输出端与下一级第一触发器的时钟端连接，第一级第一触发器的时钟端与第i个选择单元的输出端连接，最后一级第一触发器的第二输出端作为第i个计数单元的输出端用于输出第i中间信号。
进一步地，在一些实施例中，该方法还可以包括：通过计数信号生成模块接收第二模式信号，响应于第二模式信号生成计数信号，第二模式信号指示执行的目标计数模式。
在本公开实施例中，阈值计数电路在执行ECS操作时，该方法还可以包括：
若第二模式信号的电平值为第一值，则确定目标计数模式为码字计数模式，计数信号为第一计数信号；或者，
若在第二模式信号的电平值为第二值，则确定目标计数模式为行计数模式，计数信号为第二计数信号。
进一步地，在本公开实施例中，计数信号生成模块可以包括错误检测模块和模式选择模块。相应地，在一些实施例中，该方法还可以包括：
基于错误检测模块，根据检测到的码字错误生成第一检测信号，并将第一检测信号发送给模式选择模块；以及根据检测到的存在码字错误的行生成第二检测信号，并将第二检测信号发送给模式选择模块；
通过模式选择模块接收第二模式选择信号、第一检测信号和第二检测信号，以及响应于第二模式信号的控制，根据第一检测信号生成第一计数信号，或者，根据第二检测信号生成第二计数信号。
在另一些实施例中，该方法还可以包括：
通过错误检测模块接收第二模式选择信号；响应于第二模式选择信号，在码字计数模式下检测码字错误，根据检测到的码字错误生成第一检测信号，并将第一检测信号发送给模式选择模块；或者，在行计数模式下检测存在码字错误的行，根据检测到的存在码字错误的行生成第二检测信号，并将第二检测信号发送给模式选择模块；
通过模式选择模块接收第一检测信号或第二检测信号，并根据第一检测信号生成第一计数信号，或者，根据第二检测信号生成第二计数信号。
还可以理解地，在一些实施例中，存储密度计数电路可以为异步二进制计数器。其中，异步二进制计数器包括若干个依次级联的第二触发器，每一级第二触发器的输入端与其自身的第二输出端连接，且每一级第二触发器的第二输出端与下一级第二触发器的时钟端连接，第一级第二触发器的时钟端与阈值计数电路的输出端连接，最后一级第二触发器的第二输出端作为存储密度计数电路的输出端与目标计数电路的时钟端连接。
在本公开实施例中，第二触发器的数量与预设存储密度之间具有关联关系；其中，预设存储密度为d，第二触发器的数量为y，且d＝2 y。
还可以理解地，在一些实施例中，目标计数电路可以为异步二进制计数器。其中，异步二进制计数器包括若干个依次级联的第三触发器，每一级第三触发器的输入端与其自身的第二输出端连接，且每一级第三触发器的第二输出端与下一级第三触发器的时钟端连接，第一级第三触发器的时钟端与存储密度计数电路的输出端连接。
在本公开实施例中，第三触发器的数量为M个，且目标计数信号是由第0位至第M-1位目标计数子信号组成的二进制数；其中，第k+1级第三触发器的第一输出端用于输出第k位目标计数子信号，k为大于或等于0且小于M的整数。
进一步地，在一些实施例中，该方法还可以包括：根据接收到的ECS结束信号，通过第二译码模块对目标计数信号进行译码并存储到预设模式寄存器中。
进一步地，在一些实施例中，预设模式寄存器至少包括M位，且每一位对应一个预设计数范围。相应地，对于第二译码模块而言，该方法还可以包括：在目标计数结果满足第k预设计数范围时，将预设模式寄存器中第k位存储的数值设置为第一值，除第k位之外的其他位存储的数值设置为第二值；其中，目标计数结果为目标计数信号表征的计数值与预设值的乘积，预设值为计数阈值与预设存储密度的乘积值。
在本公开实施例中，第k预设计数范围的最小值设置为预设值与2 k的乘积；第k预设计数范围的最大值设置为预设值与2 k+1的乘积和1之间的差值。
本公开实施例提供了一种计数方法，应用于前述实施例所述的半导体存储器。在该半导体存储器中，不同的译码信号可以表征不同的计数阈值等级，而且根据不同的译码信号还能够选择不同的目标计数模块，从而能够满足不同计数阈值等级的错误计数统计；根据译码信号的不同来自适应选择目标计数模块，还可以避免相关技术中使用大量的逻辑器件而导致连接线过多的问题，从而还能够减小电路面积和连接线数量，同时降低电路复杂度；另外，根据最终的错误计数结果满足的预设计数范围，可以将预设模式寄存器中对应的位设置为1，从而能够将错误计数结果按照需求加载到预设模式寄存器中，进而改善存储器的性能。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或电路实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种计数电路、半导体存储器以及计数方法，该计数电路包括第一译码模块和第一计数模块，且第一译码模块与第一计数模块连接；第一译码模块，配置为接收第一模式信号，对第一模式信号进行译码处理，生成译码信号；第一计数模块包括至少一个子计数模块，配置为根据译码信号从至少一个子计数模块中确定被选择的目标计数模块，以及接收计数信号，通过目标计数模块对计数信号进行计数，每当计数信号对应的计数值达到计数阈值的整数倍时，输出第一计数脉冲信号。这样，根据第一模式信号可以生成译码信号，而不同的译码信号可以表征不同的计数阈值等级，且根据不同的译码信号还能够选择不同的目标计数模块，从而能够满足不同计数阈值等级的计数统计；另外，根据译码信号的不同来自适应选择目标计数模块，还可以避免相关技术中使用大量的逻辑器件而导致连接线过多的问题，从而还能够减小电路面积和连接线数量，同时降低电路复杂度，进而改善存储器的性能。

Claims (21)

  1. 一种计数电路，包括第一译码模块和第一计数模块，且所述第一译码模块与所述第一计数模块连接，其中：
    所述第一译码模块，配置为接收第一模式信号，对所述第一模式信号进行译码处理，生成译码信号；
    所述第一计数模块包括至少一个子计数模块，配置为根据所述译码信号从所述至少一个子计数模块中确定被选择的目标计数模块，以及接收计数信号，通过所述目标计数模块对所述计数信号进行计数，每当所述计数信号对应的计数值达到计数阈值的整数倍时，输出第一计数脉冲信号。
  2. 根据权利要求1所述的计数电路，其中，所述第一模式信号表征所述计数阈值。
  3. 根据权利要求1所述的计数电路，其中，所述译码信号包括N位子译码信号，N为大于0的整数；
    所述第一译码模块，还配置为在生成所述译码信号的过程中，若第i位子译码信号的电平值为第一值，则确定除所述第i位子译码信号之外的其他位子译码信号的电平值均为第二值；其中，所述第一值与所述第二值不同，而且i的不同取值对应不同的所述译码信号，不同的所述译码信号表征不同的所述计数阈值，i为大于0且小于或等于N的整数。
  4. 根据权利要求3所述的计数电路，其中，所述至少一个子计数模块的数量为N个，且所述至少一个子计数模块为级联关系，第i个子计数模块与第i位子译码信号之间具有对应关系，其中：
    所述第一计数模块，配置为在所述第i位子译码信号的电平值为第一值时，将所述第i个子计数模块至第N个子计数模块确定为所述目标计数模块；以及通过所述第i个子计数模块至第N个子计数模块对所述计数信号进行计数，输出所述第一计数脉冲信号。
  5. 根据权利要求4所述的计数电路，其中，每一个所述子计数模块包括第一输入端、第二输入端和输出端，其中：
    每一个所述子计数模块的第一输入端均与所述计数信号连接；
    第1个子计数模块的第二输入端与第一电源信号连接，第j个子计数模块的第二输入端与第j-1个子计数模块的输出端连接，第N个子计数模块的输出端用于输出所述第一计数脉冲信号，j为大于1且小于或等于N的整数。
  6. 根据权利要求5所述的计数电路，其中，所述第i个子计数模块包括第i个选择单元和第i个计数单元，且所述第i个选择单元的第一输入端作为所述第i个子计数模块的第一输入端用于接收所述计数信号，所述第i个选择单元的第二输入端作为所述第i个子计数模块的第二输入端用于接收第一输入信号，所述第i个选择单元的输出端与所述第i个计数单元的时钟端连接，所述第i个计数单元的输出端作为所述第i个子计数模块的输出端用于输出第i中间信号，其中：
    所述第i个选择单元，配置为接收第i个子译码信号，根据所述第i个子译码信号在所述计数信号和所述第一输入信号中选择输出第i选择信号；
    所述第i个计数单元，配置为接收所述第i选择信号并进行计数，输出所述第i中间信号；
    其中，当i等于1时，所述第一输入信号为所述第一电源信号；当i大于1且小于或等于N时，所述第一输入信号为第i-1个计数单元输出的第i-1中间信号；以及，当i等于N时，第N中间信号为所述第一计数脉冲信号。
  7. 根据权利要求6所述的计数电路，其中，所述第i个计数单元为异步二进制计数器，其中：
    所述异步二进制计数器包括若干个依次级联的第一触发器，每一级所述第一触发器的输入端与其自身的第二输出端连接，且每一级所述第一触发器的第二输出端与下一级所述第一触发器的时钟端连接，第一级所述第一触发器的时钟端与所述第i个选择单元的输出端连接，最后一级所述第一触发器的第二输出端作为所述第i个计数单元的输出端用于输出所述第i中间信号。
  8. 根据权利要求1至7任一项所述的计数电路，其中，所述计数电路还包括计数信号生成模块，其中：
    所述计数信号生成模块，配置为接收第二模式信号，响应于所述第二模式信号生成所述计数信号，所述第二模式信号指示执行的目标计数模式。
  9. 根据权利要求8所述的计数电路，其中，所述计数电路在执行错误检查与清除ECS操作时，其中：
    若所述第二模式信号的电平值为第一值，则确定所述目标计数模式为码字计数模式，所述计数信号为第一计数信号；或者，
    若在所述第二模式信号的电平值为第二值，则确定所述目标计数模式为行计数模式，所述计数信号为第二计数信号。
  10. 根据权利要求9所述的计数电路，其中，所述计数信号生成模块包括错误检测模块和模式选择模块，其中：
    所述错误检测模块，配置为根据检测到的码字错误生成第一检测信号，并将所述第一检测信号 发送给所述模式选择模块；以及根据检测到的存在码字错误的行生成第二检测信号，并将所述第二检测信号发送给所述模式选择模块；
    所述模式选择模块，与所述错误检测模块连接，用于接收所述第二模式选择信号、所述第一检测信号和所述第二检测信号，以及响应于所述第二模式信号的控制，根据所述第一检测信号生成所述第一计数信号，或者，根据所述第二检测信号生成所述第二计数信号。
  11. 根据权利要求9所述的计数电路，其中，所述计数信号生成模块包括错误检测模块和模式选择模块，其中：
    所述错误检测模块，配置为接收所述第二模式选择信号；响应于所述第二模式选择信号，在所述码字计数模式下检测码字错误，根据检测到的码字错误生成第一检测信号，并将所述第一检测信号发送给所述模式选择模块；或者，在行计数模式下检测存在码字错误的行，根据检测到的存在码字错误的行生成第二检测信号，并将所述第二检测信号发送给所述模式选择模块；
    所述模式选择模块，与所述错误检测模块连接，用于接收所述第一检测信号或所述第二检测信号，并根据所述第一检测信号生成所述第一计数信号，或者，根据所述第二检测信号生成所述第二计数信号。
  12. 根据权利要求1所述的计数电路，其中，所述译码信号的位数为2 x个；其中，x表示所述第一模式信号的位数。
  13. 一种半导体存储器，包括阈值计数电路、存储密度计数电路和目标计数电路，且所述阈值计数电路为如权利要求1至12任一项所述的计数电路；其中：
    所述阈值计数电路，用于接收计数信号，并通过内部的目标计数模块对所述计数信号进行计数，每当所述计数信号对应的计数值达到计数阈值的整数倍时，输出第一计数脉冲信号；
    所述存储密度计数电路，用于对所述第一计数脉冲信号进行计数，每当所述第一计数脉冲信号对应的计数值达到预设存储密度的整数倍时，输出第二计数脉冲信号；
    所述目标计数电路，用于对所述第二计数脉冲信号进行计数，输出目标计数信号。
  14. 根据权利要求13所述的半导体存储器，其中，所述存储密度计数电路为异步二进制计数器，其中：
    所述异步二进制计数器包括若干个依次级联的第二触发器，每一级所述第二触发器的输入端与其自身的第二输出端连接，且每一级所述第二触发器的第二输出端与下一级所述第二触发器的时钟端连接，第一级所述第二触发器的时钟端与所述阈值计数电路的输出端连接，最后一级所述第二触发器的第二输出端作为所述存储密度计数电路的输出端与所述目标计数电路的时钟端连接。
  15. 根据权利要求14所述的半导体存储器，其中，所述第二触发器的数量与所述预设存储密度之间具有关联关系；其中，所述预设存储密度为d，所述第二触发器的数量为y，且d＝2 y。
  16. 根据权利要求13所述的半导体存储器，其中，所述目标计数电路为异步二进制计数器，其中：
    所述异步二进制计数器包括若干个依次级联的第三触发器，每一级所述第三触发器的输入端与其自身的第二输出端连接，且每一级所述第三触发器的第二输出端与下一级所述第三触发器的时钟端连接，第一级所述第三触发器的时钟端与所述存储密度计数电路的输出端连接。
  17. 根据权利要求16所述的半导体存储器，其中，所述第三触发器的数量为M个，且所述目标计数信号是由第0位至第M-1位目标计数子信号组成的二进制数；
    其中，第k+1级所述第三触发器的第一输出端用于输出第k位目标计数子信号，k为大于或等于0且小于M的整数。
  18. 根据权利要求13所述的半导体存储器，其中，所述半导体存储器还包括第二译码模块，其中：
    所述第二译码模块，配置为根据接收到的ECS结束信号，对所述目标计数信号进行译码并存储到预设模式寄存器中。
  19. 根据权利要求18所述的半导体存储器，其中，所述预设模式寄存器至少包括M位，且每一位对应一个预设计数范围，其中：
    所述第二译码模块，还配置为在目标计数结果满足第k预设计数范围时，将所述预设模式寄存器中第k位存储的数值设置为第一值，除所述第k位之外的其他位存储的数值设置为第二值。
  20. 根据权利要求19所述的半导体存储器，其中，所述目标计数结果为所述目标计数信号表征的计数值与预设值的乘积，所述预设值为所述计数阈值与所述预设存储密度的乘积值；其中：
    所述第k预设计数范围的最小值设置为所述预设值与2 k的乘积；
    所述第k预设计数范围的最大值设置为所述预设值与2 k+1的乘积和1之间的差值。
  21. 一种计数方法，应用于如权利要求13至20任一项所述的半导体存储器，所述方法包括：
    接收计数信号，通过所述阈值计数电路内部的目标计数模块对所述计数信号进行计数，每当所述计数信号对应的计数值达到计数阈值的整数倍时，输出第一计数脉冲信号；
    通过所述密度计数电路对所述第一计数脉冲信号进行计数，每当所述第一计数脉冲信号对应的计数值达到预设存储密度的整数倍时，输出第二计数脉冲信号；
    通过所述目标计数电路对所述第二计数脉冲信号进行计数，输出目标计数信号。
PCT/CN2022/124052 2022-09-20 2022-10-09 一种计数电路、半导体存储器以及计数方法 WO2024060323A1 (zh)

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