WO2024052952A1 - 半導体装置、半導体装置の制御方法、および半導体装置の製造方法 - Google Patents

半導体装置、半導体装置の制御方法、および半導体装置の製造方法 Download PDF

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Publication number
WO2024052952A1
WO2024052952A1 PCT/JP2022/033226 JP2022033226W WO2024052952A1 WO 2024052952 A1 WO2024052952 A1 WO 2024052952A1 JP 2022033226 W JP2022033226 W JP 2022033226W WO 2024052952 A1 WO2024052952 A1 WO 2024052952A1
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Prior art keywords
region
main surface
pillar region
semiconductor device
type
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English (en)
French (fr)
Japanese (ja)
Inventor
朋宏 玉城
誠 橋本
陽平 須藤
忠義 出口
光久 河瀬
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Mitsubishi Electric Corp
Nisshinbo Micro Devices Inc
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Mitsubishi Electric Corp
Nisshinbo Micro Devices Inc
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Priority to CN202280099412.8A priority Critical patent/CN119769194A/zh
Priority to JP2024545282A priority patent/JP7793067B2/ja
Priority to DE112022007742.5T priority patent/DE112022007742T5/de
Priority to PCT/JP2022/033226 priority patent/WO2024052952A1/ja
Publication of WO2024052952A1 publication Critical patent/WO2024052952A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/418—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/058—Forming charge compensation regions, e.g. superjunctions by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/417—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the collector side relative to other parts of the drift region

Definitions

  • the present disclosure relates to a semiconductor device, a method of controlling a semiconductor device, and a method of manufacturing a semiconductor device.
  • a superjunction structure in which n-type pillar regions and p-type pillar regions are arranged alternately in a plan view is a structure mainly used for the drift layer of power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). By narrowing the pitch at which the p-type pillar regions are arranged, it is possible to increase the concentration (lower resistance) of the n-type pillar regions.
  • a power MOSFET that employs a superjunction structure can obtain a lower on-voltage with the same withstand voltage compared to a conventional power MOSFET (a power MOSFET that does not employ a superjunction structure).
  • a superjunction IGBT that applies a superjunction structure to an IGBT (Insulated Gate Bipolar Transistor) uses holes injected from the p-type collector layer on the back side to create an It is expected that the on-voltage will be lowered even further by exerting the Injection Enhanced (Injection Enhanced) effect and strengthening the conductivity modulation.
  • IGBT Insulated Gate Bipolar Transistor
  • Non-Patent Document 1 a superjunction structure in which an n-type pillar region and a p-type pillar region are formed perpendicularly to the depth direction has been disclosed (for example, see Non-Patent Document 1).
  • Patent Documents 1 and 2 and Non-Patent Document 1 do not disclose a superjunction structure that can achieve both reduction in on-voltage and robustness of withstand voltage.
  • Patent Document 2 a p-type pillar region and a p-type base region are electrically connected, and holes injected from the back surface in an on state pass through the p-type pillar region and the p-type base region to the emitter terminal. It will be discharged. Therefore, in order to reduce the on-voltage, it is necessary to increase the concentration of the n-type pillar region by narrowing the pitch at which the n-type pillar region and the p-type pillar region are arranged.
  • narrowing the pitch has limitations in manufacturing technology, and by increasing the concentration of the n-type pillar region, electrons are biased in the n-type pillar region and holes are biased in the p-type pillar region. There is a limit to the reduction of the on-voltage because the current is in a conductive state.
  • Non-Patent Document 1 in a structure in which the n-type pillar region and the p-type pillar region are formed perpendicularly to the depth direction as in Non-Patent Document 1, the sensitivity of the element withstand voltage to the concentration of the pillar region becomes strong, so that the withstand voltage robustness against manufacturing variations increases. There is an inconvenience in that it is significantly impaired.
  • the present disclosure has been made to solve such problems, and provides a semiconductor device having a superjunction structure that can achieve both reduction in on-voltage and robustness of withstand voltage, a method for controlling a semiconductor device,
  • the present invention also aims to provide a method for manufacturing a semiconductor device.
  • a semiconductor device has a first main surface and a second main surface opposite to the first main surface, and has a first main surface and a second main surface.
  • a drift layer including first pillar regions of a first conductivity type and second pillar regions of a second conductivity type alternately arranged in parallel directions; a base region of a second conductivity type; a gate insulating film disposed in contact with the base region; a gate electrode disposed facing the base region with the gate insulating film interposed therebetween; the base region and a second pillar region; a first conductivity type charge retention region disposed between the first conductivity type charge retention region and a first conductivity type emitter region selectively disposed in the surface layer on the first main surface side of the base region;
  • the lower end that is the end on the second main surface side is located closer to the second main surface than the lower end that is the end on the second main surface side in the first pillar region, and the lower end is the end on the first main surface side in the second
  • wp1 be the width of the upper end that is the end
  • wp2 be the width of the second pillar region at the same position as the lower end of the first pillar region
  • wp3 be the width of the lower end of the second pillar region
  • FIG. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to Embodiment 1.
  • FIG. FIG. 3 is a diagram for explaining the relationship between the ratio of the amount of impurity in the p-type pillar region to the amount of impurity in the n-type pillar region and the breakdown voltage of the semiconductor device.
  • FIG. 3 is a diagram for explaining the relationship between the ratio of the amount of impurity in the p-type pillar region to the amount of impurity in the n-type pillar region and the breakdown voltage of the semiconductor device.
  • FIG. 3 is a diagram for explaining the relationship between the ratio of the amount of impurity in the p-type pillar region to the amount of impurity in the n-type pillar region and the breakdown voltage of the semiconductor device.
  • FIG. 3 is a diagram for explaining the relationship between the ratio of the amount of impurity in the p-type pillar region to the amount of impurity in the n-type pillar region and the four voltages of the semiconductor device.
  • FIG. 3 is a diagram for explaining the relationship between the ratio of the amount of impurity in the p-type pillar region to the amount of impurity in the n-type pillar region and the breakdown voltage of the semiconductor device. It is a graph which shows an example of the electric field intensity along the direction from the 1st main surface to the 2nd main surface in a semiconductor device.
  • 1 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a first embodiment; FIG.
  • FIG. 1 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a first embodiment
  • FIG. 1 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a first embodiment
  • FIG. 1 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a first embodiment
  • FIG. 1 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a first embodiment
  • FIG. 1 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a first embodiment
  • FIG. 1 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a first embodiment
  • FIG. 1 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a first embodiment
  • FIG. 1 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a first embodiment
  • FIG. 1 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a first embodiment
  • FIG. 1 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a first embodiment
  • FIG. 1 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a first embodiment
  • FIG. 1 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a first embodiment
  • FIG. 3 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a modification of the first embodiment.
  • FIG. 3 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing an example of the configuration of a semiconductor device according to Modification 1 of Embodiment 2; 7 is a cross-sectional view showing an example of the configuration of a semiconductor device according to Modification 2 of Embodiment 2.
  • FIG. FIG. 3 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a third embodiment.
  • 7 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a third embodiment.
  • FIG. 7 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a third embodiment.
  • FIG. 7 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a third embodiment.
  • FIG. 7 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a third embodiment.
  • FIG. 7 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a third embodiment.
  • FIG. 12 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a modification of Embodiment 3.
  • FIG. 7 is a plan view showing an example of a top layout of a semiconductor device according to a fourth embodiment. 29 is a sectional view taken along line A1-A2 in FIG. 28.
  • FIG. 12 is a graph showing an example of a timing chart of a first gate voltage and a second gate voltage for driving the semiconductor device according to the fourth embodiment.
  • 12 is a graph showing an example of the dependence of the second gate voltage on the delay time with respect to the surge voltage and turn-off loss in the semiconductor device according to the fourth embodiment.
  • 12 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a modification of Embodiment 4.
  • FIG. 4 is a cross-sectional view showing an example of the configuration of a
  • the first conductivity type is n-type
  • the second conductivity type is p-type. Identical parts in the drawings are designated by the same numbers.
  • the termination structure in the peripheral region of the device is not shown, but the cross-sectional structure of the unit cell is shown.
  • Semiconductor substrates used in devices include wafers manufactured by the MCZ (Magnetic field applied Czochralski) method, wafers manufactured by the FZ (Floating Zone) method, or epitaxial substrates manufactured by the CZ (Czochralski) method. Regardless of the manufacturing method, it may be manufactured using any suitable substrate manufacturing technology necessary for manufacturing the device.
  • the device may also be a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that uses an n-type drain layer instead of the p-type collector layer on the back side, and has an n-type collector layer in addition to the p-type collector layer. It may be partially patterned. Alternatively, both a MOSFET region and a diode region are provided on the front surface, a p-type collector region is arranged on the back surface of the semiconductor substrate directly under the MOSFET region, and an n-type cathode region is arranged on the back surface of the semiconductor substrate directly under the diode region. It may be an RC (Reverse-Conducting) type IGBT.
  • RC Reverse-Conducting
  • FIG. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the first embodiment.
  • the semiconductor device shown in FIG. 1 is a planar gate type superjunction IGBT element manufactured using a silicon-based semiconductor substrate.
  • the following will specifically explain a semiconductor device with an emitter-collector breakdown voltage of about 1200 volts as an example, but it can also be applied to superjunction IGBT elements with other breakdown voltages or semiconductor devices with other superjunction structures. It is.
  • the semiconductor device shown in FIG. 1 has a first main surface and a second main surface opposite to the first main surface.
  • the first principal surface is the upper surface of the paper in FIG. 1, and corresponds to the surface of the semiconductor device.
  • the second principal surface is a surface on the lower side of the paper in FIG. 1, and corresponds to the back surface of the semiconductor device.
  • the drift layer 10 includes n-type pillar regions 107 (first conductivity type first pillar regions) and p-type pillar regions 108 (first conductivity type first pillar regions) which are alternately arranged in a direction parallel to the first main surface and the second main surface. 2 conductivity type second pillar region).
  • P-type base region 105 is selectively placed on the first main surface side of drift layer 10 .
  • N-type emitter region 103 and p-type body contact region 104 are selectively arranged in the surface layer of p-type base region 105 on the first main surface side.
  • An n-type charge storage region (carrier stored region: CS region) 106 is arranged between the p-type base region 105 and the p-type pillar region 108.
  • Gate insulating film 101 is placed in contact with p-type base region 105 .
  • Gate electrode 102 is placed facing p-type base region 105 with gate insulating film 101 in between.
  • the lower end of the p-type pillar region 108 which is the end on the second main surface side, is located closer to the second main surface than the lower end, which is the end of the n-type pillar region 107 on the second main surface side.
  • the width of the upper end of the region 108 on the first main surface side is wp1, the width of the p-type pillar region 108 at the same position (same depth position) as the lower end of the n-type pillar region 107 is wp2, and the width of the p-type pillar region 108 is wp2.
  • the width of the lower end of the region 108 is wp3, wp3>wp2 and wp1>wp2.
  • the n-type bottom layer 109 is arranged on the second main surface side of the drift layer 10.
  • the n-type buffer layer 110 is arranged on the second main surface side of the n-type bottom layer 109.
  • the p-type collector layer 111 is arranged on the second main surface side of the n-type buffer layer 110.
  • Collector electrode 112 is arranged on the second main surface side of p-type collector layer 111.
  • a plurality of striped gate electrodes 102 are arranged above the n-type pillar region 107, and like the p-type pillar region 108, the gate electrodes 102 also extend in the depth direction of the paper in FIG. 1 (in the direction perpendicular to the paper). By arranging them in stripes, a MOSFET with a planar gate structure is formed.
  • one gate electrode 102 is provided above one n-type pillar region 107, and the pitch in the width direction of the n-type pillar region 107 and the gate electrode 102 are the same. Pillar region 107 and gate electrode 102 may have different widths in the width direction.
  • FIGS. 2 to 5 are diagrams for explaining the relationship between the ratio of the amount of impurity in the p-type pillar region to the amount of impurity in the n-type pillar region and the breakdown voltage of the semiconductor device.
  • the horizontal axis represents the ratio (Qp/Qn) of the impurity amount (Qp) in the p-type pillar region to the impurity amount (Qn) in the n-type pillar region
  • the vertical axis represents the breakdown voltage of the semiconductor device.
  • Structures A to C shown in FIGS. 2 to 4 are superjunction structures.
  • Structures A and B are superjunction structures possessed by the semiconductor device according to the comparative example, and structure C is a superjunction structure possessed by the semiconductor device according to the first embodiment.
  • FIG. 5 shows simulation results regarding the influence of impurity ratios on breakdown voltage in structures A to C shown in FIGS. 2 to 4.
  • FIG. 6 is a graph showing an example of the electric field strength along the direction (depth direction) from the first main surface to the second main surface in the semiconductor device. Structures A to C shown in FIG. 6 correspond to structures A to C shown in FIGS. 2 to 5.
  • the semiconductor device according to the comparative example is a semiconductor device including a drift layer including an n-type pillar region and a p-type pillar region forming a superjunction structure (structure A or structure B).
  • the breakdown voltage can be ensured by setting the pitch interval or impurity concentration of the p-type pillar region and the n-type pillar region so that depletion layers expanding from adjacent pillar regions can punch through each other.
  • the breakdown voltage of a semiconductor device depends on the impurity amount ratio in the drift layer.
  • the expansion of the depletion layer according to the voltage becomes maximum, and the breakdown voltage increases. Maximum.
  • the amount of one of the impurities increases due to, for example, variations in the manufacturing process, that is, if "Qn>Qp" or "Qn ⁇ Qp"
  • the depletion layer does not expand sufficiently and the breakdown voltage decreases.
  • the sensitivity of the impurity amount ratio of the drift layer to the breakdown voltage of the semiconductor device changes depending on the shape of the pillar region. For example, if the upper end width and lower end width (bottom width) of the p-type pillar region are equal and the p-type pillar region is formed in the vertical direction, the sensitivity of the impact on the breakdown voltage to changes in the amount of impurities in the pillar region is It gets expensive.
  • the space charge density in the drift layer becomes almost zero, the electric field strength distribution in the depth direction becomes flat, and the breakdown voltage is maximized.
  • a state in which the amount of impurities in the n-type pillar region (Qn) is equal to the amount of impurities in the p-type pillar region (Qp) and the balance of charge amounts is maintained is called a charge balance state.
  • a charge imbalance state in which either the amount of impurity in the n-type pillar region (Qn) or the amount of impurity in the p-type pillar region (Qp) increases is called a charge imbalance state.
  • Qn>Qp the drift layer with positive space charge density holds the applied voltage
  • Qn ⁇ Qp the drift layer with negative space charge density holds the applied voltage. The voltage is maintained.
  • the lower end width of the p-type pillar region is made smaller than the upper end width to suppress the decrease in breakdown voltage due to the amount of excess charge in the drift layer.
  • This can be achieved by forming a p-type pillar region that has a forward tapered shape over two principal surfaces. According to this method, the amount of surplus charge is not uniform in the drift layer, but the amount of surplus charge in the drift layer becomes smaller along the direction from the first principal surface to the second principal surface.
  • the effects of reducing the sensitivity of the impurity amount ratio of the drift layer to the breakdown voltage of the semiconductor device and improving the breakdown voltage of the semiconductor device described above can also be applied to superjunction MOSFET elements.
  • the JFET resistance generated between the p-type base regions can be reduced by the charge retention region serving as a current diffusion layer.
  • the resistance component of the bottom layer cannot be reduced, so it is difficult to sufficiently lower the on-resistance as it is. Therefore, by providing an n-type buffer region and a p-type collector region on the second main surface side, bipolar operation is possible, and by further providing a charge retention region, it is possible to further reduce the on-resistance.
  • an inversion layer is formed on the surface of the p-type base region directly under the gate electrode, and from the emitter electrode to the n-type emitter region and the inversion layer. Electrons are injected into the drift layer via. Electrons injected into the drift layer are drifted toward the second principal surface by the electric field and move to the collector electrode through the n-type buffer layer and the p-type collector layer. Since the potential of the n-type buffer layer is lowered by the electrons moving from the first main surface, the built-in potential of the pn junction on the second main surface side is lowered, and holes are injected from the p-type collector layer. At this time, if the concentration of holes injected from the p-type collector layer is higher than the impurity concentration of the n-type bottom layer and the drift layer, conductivity modulation can be caused and the on-resistance can be reduced.
  • the breakdown voltage value is lowered. This is because, as shown in FIG.
  • a semiconductor device using a vertically shaped p-type pillar region has a nearly flat electric field intensity distribution in the depth direction, whereas a p-type pillar region having a forwardly tapered shape This is because, in a semiconductor device using the p-type pillar region, the electric field intensity distribution in the depth direction has one peak in the drift layer, and the electric field intensity decreases near the top and bottom of the p-type pillar region.
  • the upper end width (wp1) of the p-type pillar region 108 is set at the same depth as the lower end of the n-type pillar region 107.
  • an n-type bottom layer 109 is disposed below the drift layer 10, the lower end of the p-type pillar region 108 is disposed closer to the second main surface than the n-type pillar region 107, and the p-type
  • the maximum width (wp3) at the bottom of the pillar region 108 larger than wp2 (wp3>wp2), the electric field strength near the bottom of the p-type pillar region 108 can be increased, and the breakdown voltage can also be improved.
  • the n-type charge retention region 106 serves as a potential barrier for holes injected from the p-type collector layer 111.
  • hole accumulation or IE effect
  • the n-type charge retention region 106 is separated directly below the center of the gate electrode 102 (at a position corresponding to the center of the gate electrode 102).
  • the n-type charge retention region 106 is separated directly under the center of the gate electrode 102, it is possible to suppress an increase in the electric field at the junction interface between the p-type base region 105 and the n-type charge retention region 106, and achieve the desired breakdown voltage. can be obtained.
  • the n-type charge retention region 106 is formed at a deeper position than the p-type base region 105 so as to surround the p-type base region 105.
  • the planar dimension of the n-type charge retention region 106 is calculated as the planar dimension of the p-type base region 105 (the first principal surface).
  • the width of the p-type base region 105 in the direction parallel to the surface and the second principal surface is larger than the width of the p-type base region 105 in the direction parallel to the plane and the second principal surface. It becomes possible to hold the
  • the n-type charge retention region 106 and the p-type base region 105 are formed by ion implantation and diffusion processing, and the impurity concentration of the n-type charge retention region 106 is made higher than that of the p-type pillar region 108.
  • Type base region 105 and p-type pillar region 108 are separated by n-type charge retention region 106.
  • the p-type pillar region 108 separated from the p-type base region 105 by the n-type charge retention region 106 becomes floating (in an electrically floating state).
  • the n-type charge retention region 106 sandwiched between the p-type pillar region 108 and the p-type base region 105 can serve as a charge storage layer.
  • the p-type pillar region 108 and the p-type base region 105 it is not necessary to separate the p-type pillar region 108 and the p-type base region 105, for example, outside the active region that is the main part of the device.
  • the p-type pillar region 108 by connecting the p-type pillar region 108 to the p-type base region 105 in a region other than the main part of the device, unnecessary carriers generated during device operation can be discharged through the contact of the emitter electrode 100. It becomes possible to improve long-term reliability and breakdown resistance of devices.
  • n-type bottom epitaxial layer 409 n-type bottom layer 109
  • drift layer 10 n-type top epitaxial layer 407
  • processes not directly related to the present disclosure such as a cleaning process before a gate oxide film, a sintering process for interlayer films and metal wiring, or a passivation film forming process, and manufacturing of a device termination structure. Necessary processing steps and assembly steps for dividing devices into individual pieces and assembling them into modules and the like can be added as appropriate.
  • an n-type bottom epitaxial layer 409 doped with phosphorus on the order of 10 13 cm -3 is formed to a thickness of about 30 to 50 ⁇ m. form it.
  • an n-type top epitaxial layer 407 doped with, for example, phosphorus on the order of 10 15 cm ⁇ 3 is formed to a thickness of about 50 to 70 ⁇ m.
  • a semiconductor wafer is prepared in which an n-type bottom epitaxial layer 409 and an n-type top epitaxial layer 407 are formed on an n-type silicon single crystal substrate 400.
  • an n-type substrate is exemplified as the silicon single crystal substrate, but as will be described later, since the n-type silicon single crystal substrate 400 is ultimately removed by grinding, a p-type substrate may be used instead of the n-type substrate. Good too.
  • the impurity concentration of the semiconductor wafer is not limited, it is preferable that the impurity concentration of the n-type bottom epitaxial layer 409 is lower than the impurity concentration of the n-type top epitaxial layer 407 in order to obtain a desired breakdown voltage.
  • the surface of the n-type top epitaxial layer 407 of the semiconductor wafer is defined as a first main surface, and the surface opposite to the first main surface is defined as a second main surface.
  • a hard mask film 410 for forming trenches made of, for example, P-TEOS (Plasma-Tetraethylorthosilicate) is patterned on the first main surface.
  • the hard mask film for forming the trench groove 401 for the p-type pillar region as a mask, the n-type top epitaxial layer 407 is dry-etched to the extent that the n-type bottom epitaxial layer 409 is reached.
  • a trench groove 401 (trench groove for second pillar region) is formed. The mesa portion sandwiched between the p-type pillar region trench grooves 401 becomes the n-type pillar region 107.
  • the n-type bottom epitaxial layer 409 corresponds to the n-type bottom layer 109.
  • the bottom of the p-type pillar region trench groove 401 reaches the n-type bottom epitaxial layer 409, but impurities at the bottom of the p-type pillar region 108 are removed from the n-type bottom epitaxial layer by a thermal diffusion process described later.
  • the bottom of the p-type pillar region trench groove 401 does not necessarily have to reach the n-type bottom epitaxial layer 409 at this point.
  • boron ions may be implanted into the bottom of the trench groove 401 for the p-type pillar region. Thereafter, the hard mask film 410 that is no longer needed is removed.
  • an overgrowth region 411 is also epitaxially grown on the n-type pillar region 107 so that the p-type pillar region trench groove 401 is completely filled.
  • the overgrowth region 411 other than the trench groove 401 for the p-type pillar region is removed, and the first main region of the semiconductor wafer is removed. Flatten the surface.
  • CMP Chemical Mechanical Polishing
  • a gate oxide film is formed on almost the entire first main surface of the semiconductor wafer by thermal oxidation, and a polysilicon film (corresponding to the gate electrode 102) is formed thereon by, for example, low-pressure CVD. (Chemical Vapor Deposition). Then, the polysilicon film and the gate oxide film are dry etched by lithography using the resist film as a mask to pattern the gate electrode 102 and the gate insulating film 101.
  • a Si oxide film with a thickness of approximately 100 nm is exemplified as the gate insulating film 101
  • a polysilicon film is exemplified as the material of the gate electrode 102.
  • amorphous silicon may be used as the material of the gate electrode 102, and molybdenum or other materials may be used. Metal materials may also be used.
  • an n-type charge retention region 106 is formed by ion-implanting phosphorus at a dose of, for example, about 10 14 cm -2 .
  • thermal diffusion treatment is performed at, for example, 1100° C. for about 140 minutes to diffuse the n-type charge retention region 106 to just below the gate electrode 102, and to diffuse the boron at the bottom of the p-type pillar region 108.
  • the width of the bottom of the p-type pillar region 108 is widened by diffusing the p-type into the n-type bottom layer 109.
  • a p-type base region 105 is formed by ion-implanting boron at a dose of, for example, about 3 ⁇ 10 14 cm ⁇ 2 , and then subjected to thermal diffusion treatment at, for example, 1100° C. for about 30 minutes. is performed to diffuse the p-type base region 105.
  • thermal diffusion treatment at, for example, 1100° C. for about 30 minutes.
  • ions of antimony, arsenic, etc. are implanted at a dose of about 4 ⁇ 10 15 cm ⁇ 2 to form the n-type emitter region 103 .
  • the resist film for the n-type emitter region that is no longer needed is removed.
  • ions of, for example, boron are implanted at a dose of about 4 ⁇ 10 15 cm ⁇ 2 to form the p-type body contact region 104 .
  • annealing is performed at, for example, about 1000° C. using lamp heating or a diffusion furnace.
  • a PSG (Phospho-Silicate-Glass) film is formed on almost the entire first main surface of the semiconductor wafer by the CVD method.
  • a BPSG (Boro-Phospho-Silicate Glass) film or an SOG (Spin on Glass) film may be stacked and flattened.
  • a resist film for opening an emitter contact hole is formed, and the emitter contact hole is opened by dry etching using the resist film for opening an emitter contact hole as a mask. Then, the resist film that is no longer needed is removed. Thereafter, an aluminum-based metal layer is formed by sputtering or the like via a barrier metal film such as TiW, and patterned to form the emitter electrode 100.
  • the n-type silicon single crystal substrate 400 located on the second main surface of the semiconductor wafer is removed and ground so that the n-type bottom epitaxial layer 109 is exposed on the surface layer of the second main surface.
  • the grinding damage layer may be removed by chemical etching treatment.
  • the first main surface can be It is desirable to protect the device structure formed during the process.
  • an n-type buffer layer 110 is formed by ion-implanting phosphorus at a dose of, for example, about 5 ⁇ 10 12 cm ⁇ 2 onto the second main surface of the semiconductor wafer. Thereafter, boron ions are implanted at a dose of, for example, about 1 ⁇ 10 13 cm ⁇ 2 to form a p-type collector layer 111 at a position shallower than the n-type buffer layer 110 (on the second principal surface side). Thereafter, the n-type buffer layer 110 and the p-type collector layer 111 are activated using, for example, a laser annealing device.
  • FIG. 18 is a cross-sectional view schematically showing the structure of a semiconductor device according to a modification of the first embodiment.
  • the same parts as those in FIG. 1 are given the same reference numerals, and the description thereof will be omitted.
  • the difference between the semiconductor device according to this modification and the semiconductor device according to the first embodiment is that an n-type pillar is provided between the striped n-type charge retention regions 106 extending perpendicularly to the paper surface of FIG.
  • the point is that an n-type JFET region 121 having a higher impurity concentration than the region 107 is newly arranged.
  • the n-type JFET region 121 It becomes possible to suppress the width of the depletion layer extending from the type base region 105.
  • n-type charge retention regions 106 formed in stripes are separated by an n-type pillar region 107 as in a conventional semiconductor device
  • the depletion layer extending from the p-type base region 105
  • the on-resistance of the semiconductor device increases. According to this modification, by providing the n-type JFET region 121, it is possible to solve this problem and reduce the on-resistance.
  • FIG. 19 is a cross-sectional view schematically showing the structure of a semiconductor device according to the second embodiment.
  • the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that the p-type pillar bottom region exists at a position deeper than the bottom end of the n-type pillar region 107 (position on the second main surface side).
  • a point 122 contains impurities at a higher concentration than the p-type pillar region 108 which is located closer to the first main surface than the p-type pillar bottom region 122 .
  • the p-type pillar bottom region 122 exists at a position deeper than the lower end of the n-type pillar region 107 and below the p-type pillar region 108. Further, the impurity concentration of the p-type pillar bottom region 122 is higher than the impurity concentration of the p-type pillar region 108.
  • the impurity concentration of the p-type pillar bottom region 122 is higher than the impurity concentration of the p-type pillar region 108.
  • FIG. 20 is a cross-sectional view schematically showing the structure of a semiconductor device according to Modification 1 of Embodiment 2.
  • FIG. 21 is a cross-sectional view schematically showing the structure of a semiconductor device according to a second modification of the second embodiment.
  • FIGS. 20 and 21 the same parts as those in FIG. 19 are given the same reference numerals, and explanations thereof will be omitted.
  • the semiconductor device according to Modification 1 shown in FIG. 20 differs from the semiconductor device according to Embodiment 2 in that p-type pillar bottom regions 122 and 123 are composed of a plurality of regions having different widths and impurity concentrations in the depth direction.
  • the point is that The p-type pillar bottom region 122 in the semiconductor device according to the first modification shown in FIG. 20 is formed as an extension of the p-type pillar region 108, and is different from the semiconductor device according to the first modification in this point.
  • the semiconductor device according to the second modification shown in FIG. 21 differs from the semiconductor device according to the second embodiment in that the impurity concentration between the adjacent p-type pillar bottom regions 122 is higher than that in the n-type pillar region 107.
  • the point is that an n-type JFET region 124 is provided.
  • the n-type JFET region 124 is in contact with the lower end of the n-type pillar region 107.
  • the semiconductor device according to the second modification is the same as the second embodiment or the first modification in that the impurity concentration of the p-type pillar bottom region 122 is different from the impurity concentration of the p-type pillar region 108.
  • one p-type pillar bottom region 122 is arranged which has a higher impurity concentration than the p-type pillar region 108 which is located at a shallower position than the bottom end of the n-type pillar region 107.
  • the semiconductor device according to Modification Example 1 shown in FIG. 20 has a plurality of p-type pillar bottom regions 123 arranged in the depth direction, allowing more fine control of electric field distribution.
  • an n-type JFET region 124 having a higher impurity concentration than the n-type pillar region 107 is arranged between the p-type pillar bottom regions 122. Therefore, it is possible to both improve breakdown voltage and reduce on-resistance.
  • FIG. 22 is a cross-sectional view showing the structure of a semiconductor device according to the third embodiment.
  • the semiconductor device according to the third embodiment is a trench gate type superjunction IGBT element manufactured using a silicon-based semiconductor substrate.
  • the following will specifically explain a semiconductor device with an emitter-collector breakdown voltage of about 1200 volts as an example, but it can also be applied to superjunction IGBT elements with other breakdown voltages or semiconductor devices with other superjunction structures. It is.
  • the semiconductor device according to the third embodiment is different from the semiconductor device according to the first embodiment in that the semiconductor device according to the first embodiment is a planar gate type MOS semiconductor device, whereas the semiconductor device according to the third embodiment is a planar gate type MOS semiconductor device.
  • the semiconductor device according to the above is a trench gate type MOS type semiconductor device.
  • the upper end of the p-type pillar region 108 and the p-type base region 105 selectively provided on the first main surface side above the p-type pillar region 108 are connected to the n-type charge retention region 106. separated by.
  • the trench groove 201 is formed from a low resistance n-type emitter region 103 provided on the surface layer of the p-type base region 105 so as to penetrate through the p-type base region 105 and reach a part of the n-type charge retention region 106. They are formed so as to be selectively arranged above the pillar region 107.
  • a gate electrode 102 is provided in the trench groove 201 with a gate insulating film 101 interposed therebetween.
  • the depth position of the bottom (lower end) of the trench groove 201 is shallower than the depth position of the upper end of the p-type pillar region 108. Therefore, it is possible to prevent the breakdown voltage from decreasing due to an increase in the electric field between the upper part of the p-type pillar region 108 and the trench groove 201.
  • FIGS. 23 to 26 ⁇ Method for manufacturing semiconductor device according to third embodiment>
  • FIGS. 7 to 10 the steps up to manufacturing the superjunction structure on the first main surface side will be explained in FIGS. 7 to 10. Since this method is the same as the method for manufacturing a planar gate type superjunction IGBT element as shown in FIG. Furthermore, since the steps on the second main surface side are basically the same as those shown after FIG. 16, only the different parts will be explained here.
  • a holding area 106 is formed.
  • a p-type base region 105 is formed by implanting boron ions at a dose of, for example, about 3 ⁇ 10 14 cm ⁇ 2 .
  • thermal diffusion treatment is performed at, for example, 1100° C. for about 140 minutes to diffuse the n-type charge retention region 106 and the p-type base region 105, and at the same time, to diffuse the bottom of the p-type pillar region 108.
  • thermal diffusion treatment is performed at, for example, 1100° C. for about 140 minutes to diffuse the n-type charge retention region 106 and the p-type base region 105, and at the same time, to diffuse the bottom of the p-type pillar region 108.
  • the width of the bottom of the p-type pillar region 108 is increased.
  • a trench gate type MOSFET is formed in which a gate electrode 102 is embedded in a trench groove 201 (gate trench groove) with a gate insulating film 101 interposed therebetween.
  • the trench gate structure is formed after forming the p-type base region 105, but conversely, it is also possible to form the p-type base region 105 after forming the trench gate structure first. good.
  • FIG. 27 is a cross-sectional view schematically showing the structure of a semiconductor device according to a modification of the third embodiment. Components that are the same as those in FIG. 22 are given the same reference numerals, and their explanation will be omitted.
  • the difference between the semiconductor device according to this modification and the semiconductor device according to the third embodiment is that in the semiconductor device according to the third embodiment, only the gate electrode 102 is formed in the trench groove 201. In this modification, some of the trench grooves are not provided with the n-type emitter region 103 on the first main surface side of the p-type base region 105 in contact with the side wall of the trench groove 201.
  • a dummy gate electrode 202 is formed with the gate insulating film 101 interposed in the trench groove 201 in contact with the p-type base region 105 on which the n-type emitter region 103 is not provided on the first main surface side.
  • the dummy gate electrode 202 embedded in the trench groove 201 of the trench dummy gate may be connected to the gate electrode 102 or the emitter electrode 100.
  • the n-type emitter region 103 is not provided on the first main surface side of the p-type base region 105 that is in contact with the sidewall of the trench groove 201 of the trench dummy gate, so that electrons are not injected through the sidewall of the trench groove 201 of the trench dummy gate. Therefore, it is called a "trench dummy gate" to distinguish it from the original gate (trench gate).
  • this trench dummy gate for example, above the p-type pillar region 108, it is possible to enhance the hole accumulation effect and reduce the on-state voltage.
  • the trench groove 201 of the trench dummy gate is disposed above the p-type pillar region 108, and the trench groove 201 of the trench gate is desirably disposed above the n-type pillar region 107.
  • the n-type charge retention region 106 and the n-type pillar region 107 below it are transferred from the n-type emitter region 103 through the inversion layer formed in the p-type base region 105 near the sidewall of the trench groove 201 of the trench gate. electrons are efficiently injected into the
  • a dynamic avalanche occurs due to the high charge generated during the switching operation, and hot carriers generated by the avalanche may be trapped at the MOS interface of the trench dummy gate provided above the p-type pillar region 108. Then, when the p-type pillar region 108 is floating, charges trapped at the bottom of the trench groove 201 above the p-type pillar region 108 are accumulated by long-term operation, and the p-type pillar region 108 The charge balance near the upper end of the battery gradually collapses, impairing long-term reliability.
  • the p-type pillar region 108 is connected to the p-type base region 105 in, for example, a termination structure region or a gate lead-out wiring region outside the active region, and the p-type pillar region 108 and the p-type base region 105 are separated in the active region.
  • FIG. 28 is a plan view schematically showing the top layout of the semiconductor device according to the fourth embodiment.
  • first gate electrodes 203 and second gate electrodes 204 are alternately arranged in the active region.
  • the plurality of first gate electrodes 203 arranged in the active region are bundled near the center of the top layout (connected to the first gate wiring 304) and electrically connected to the first gate electrode pad 302.
  • the plurality of second gate electrodes 204 arranged in the active region are bundled around the active region (connected to the second gate wiring 305) and electrically connected to the second gate electrode pad 303. .
  • each gate can be driven individually by disposing the first gate electrode 203 above the n-type pillar region 107 and disposing the second gate electrode 204 above the p-type pillar region 108. This makes it possible to perform fine-grained control suitable for reducing switching loss.
  • FIG. 29 is a cross-sectional view schematically showing the structure of the semiconductor device according to the fourth embodiment at A1-A2 in FIG. 28.
  • the semiconductor device according to the fourth embodiment is a trench gate type superjunction IGBT element manufactured using a silicon-based semiconductor substrate.
  • the semiconductor device according to the fourth embodiment differs from the semiconductor devices according to the first to third embodiments in that it includes two types of gates to which different voltages can be applied.
  • the upper end of the p-type pillar region 108 is formed by a p-type base region 105 selectively provided on the first main surface side above the p-type pillar region 108 and an n-type charge retention region 106.
  • the trench groove 201 is formed from a low resistance n-type emitter region 103 provided on the surface layer of the p-type base region 105 so as to penetrate through the p-type base region 105 and reach a part of the n-type charge retention region 106. They are formed so as to be selectively arranged above the pillar region 107.
  • a first gate electrode 203 is provided in the trench groove 201 so as to face the n-type pillar region 107 with the gate insulating film 101 interposed therebetween.
  • a trench groove 201 is formed from a low-resistance n-type emitter region 103 provided on the surface layer of the p-type base region 105 so as to penetrate through the p-type base region 105 and reach a part of the n-type charge retention region 106. They are formed so as to be selectively arranged above the p-type pillar region 108.
  • a second gate electrode 204 is disposed in this trench groove 201 so as to face the p-type pillar region 108 with the gate insulating film 101 interposed therebetween.
  • the first gate electrode 203 is arranged to divide the active region of the semiconductor device, and the second gate electrode 204 is arranged inward from the outer periphery of the active region.
  • the first gate electrode 203 is installed over a first gate wiring 304
  • the second gate electrode 204 is installed over a second gate wiring 305.
  • the first gate wiring 304 and the second gate wiring 305 are routed and arranged on the upper surface of the semiconductor device, the first gate wiring 304 is electrically connected to the first gate electrode pad 302, and the second gate wiring 304 is electrically connected to the first gate electrode pad 302. 305 is electrically connected to the second gate electrode pad 303.
  • the first gate wiring 304 and the second gate wiring 305 may be formed of polysilicon or amorphous silicon, but are preferably formed of a metal wiring material such as aluminum in order to further reduce the delay of gate signals.
  • a first gate electrode 203 is installed over a first gate wiring 304 in the active region so as to divide the active area of the semiconductor device, and a second gate electrode 204 is connected to a second gate wiring 305 in the periphery of the semiconductor device.
  • the layout is illustrated in which the first gate electrode 203 is installed over the first gate wiring 304 in the periphery of the semiconductor device, and the second gate electrode 204 is installed over the second gate wiring 305 in the active region. You can leave it there.
  • a layout in which the first gate electrode 203 and the second gate electrode 204 are connected alternately from the left and right or top and bottom of the active region into the active region instead of a gate wiring layout that divides the active region, a layout in which the first gate electrode 203 and the second gate electrode 204 are connected alternately from the left and right or top and bottom of the active region into the active region.
  • similar effects can be expected.
  • FIG. 30 is a graph illustrating a timing chart of the first gate voltage and the second gate voltage for driving the semiconductor device according to the fourth embodiment.
  • a first gate voltage is applied to the first gate electrode pad 302, and a second gate voltage is applied to the second gate electrode pad 303.
  • the semiconductor device includes a drift layer 10 including an n-type pillar region 107 and a p-type pillar region 108 forming a superjunction structure.
  • the emitter electrode 100 When the emitter electrode 100 is grounded and the power supply voltage is applied to the collector electrode 112, if the first gate voltage is equal to or lower than the gate threshold voltage of the MOSFET formed on the first main surface, the p-type base region 105 and drift A reverse bias is applied between the collector electrode 112 and the emitter electrode 100, and a current is cut off between the collector electrode 112 and the emitter electrode 100, resulting in an off state.
  • n-type inversion layer is formed in a portion of the mold base region 105 that is in contact with the first gate electrode 203 and the second gate electrode 204 via the gate insulating film 101. Then, a current is conducted from the collector electrode 112 to the emitter electrode 100 via this inversion layer, thereby turning the off state into an on state.
  • zero bias or negative bias is applied as a second gate voltage to the second gate electrode 204.
  • zero bias or negative bias is applied to the first gate electrode 203 as the first gate voltage.
  • the accumulated carriers in the drift layer 10 and the n-type bottom layer 109 are attenuated, and the depletion layer between the p-type pillar region 108 and the n-type pillar region 107 in the drift layer 10 is punched through, and the collector electrode 112 and the emitter electrode 100 are punched through.
  • ⁇ t is preferably between 0.1 microseconds and 10 microseconds.
  • an off signal is first applied as a second gate voltage to the second gate electrode 204 provided above the p-type pillar region 108. Then, the n-type inversion layer generated at the MOS interface of the p-type base region 105 in contact with the second gate electrode 204 disappears, and the n-type emitter region adjacent to the second gate electrode 204 through the gate insulating film 101 disappears. The supply of electrons from 103 stops. At this time, a p-type inversion layer is formed in a portion of the n-type charge retention region 106 that is in contact with the second gate electrode 204 via the gate insulating film 101.
  • holes are discharged from the upper part of the p-type pillar region 108 to the p-type base region 105 via the n-type charge retention region 106 and the p-type inversion layer.
  • the carriers accumulated in the drift layer 10 are discharged, and a depletion layer is formed between the pn junction between the p-type pillar region 108 and the n-type pillar region 107 in the drift layer 10 and a part of the n-type bottom layer. is growing. However, at this point, the superjunction region is not completely depleted.
  • the turn-off loss Eoff is reduced and becomes saturated at a certain point.
  • a depletion layer enters the n-type bottom layer 109 when either the first gate electrode 203 or the second gate electrode 204 is turned off, and the collector - Since the emitter-to-emitter voltage reaches its peak, the surge voltage Vcep has almost no effect on ⁇ t. Therefore, by setting ⁇ t>0, it is possible to reduce the turn-off loss Eoff without causing an increase in the surge voltage Vcep at turn-off.
  • FIG. 32 is a cross-sectional view schematically showing the structure of a semiconductor device according to a modification of the fourth embodiment. Components that are the same as those in FIG. 29 and the like are given the same reference numerals and explanations will be omitted.
  • the semiconductor device according to this modification differs from the semiconductor device according to the fourth embodiment in that the semiconductor device according to this modification has a planar gate structure.
  • the off signal is applied as the second gate voltage to the second gate electrode 204 by a time of ⁇ t earlier than the off signal is applied as the first gate voltage to the first gate electrode 203.
  • the n-type inversion layer generated at the MOS interface of the p-type base region 105 in contact with the second gate electrode 204 disappears, and the n-type emitter adjacent to the second gate electrode 204 through the gate insulating film 101 disappears.
  • the supply of electrons from region 103 is stopped.
  • a p-type inversion layer is formed in a portion of the n-type charge retention region 106 that is in contact with the second gate electrode 204 via the gate insulating film 101.
  • the p-type inversion layer is connected to both the p-type base region 105 and the p-type pillar region 108, the accumulated carriers in the drift layer 10 are transferred to the p-type via the p-type pillar region 108 and the p-type inversion layer. It is discharged to an emitter electrode 100 connected to a base region 105. Therefore, when an off signal is applied to the first gate electrode 203 as the first gate voltage, the time required for the drift layer 10 to be completely depleted is shortened. Therefore, it is possible to reduce turn-off loss without causing an increase in surge voltage.
  • 10 drift layer 100 emitter electrode, 101 gate insulating film, 102 gate electrode, 103 n-type emitter region, 104 p-type body contact region, 105 p-type base region, 106 n-type charge retention region, 107 n-type pillar region, 108 p-type pillar region, 109 n-type bottom layer, 110 n-type buffer layer, 111 p-type collector layer, 112 collector electrode, 121 n-type JFET region, 122 p-type pillar bottom region, 123 p-type pillar bottom region, 124 n-type JFET region, 201 trench groove, 202 dummy gate electrode, 203 first gate electrode, 204 second gate electrode, 302 first gate electrode pad, 303 second gate electrode pad, 304 first gate wiring, 305 second gate wiring, 400 n-type silicon single crystal substrate, 401 trench groove for p-type pillar region, 407 n-type top epitaxial layer, 409 n-type bottom epitaxial layer, 410

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JP2019054169A (ja) * 2017-09-15 2019-04-04 株式会社東芝 半導体装置
JP2021057552A (ja) * 2019-10-02 2021-04-08 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN112864219A (zh) * 2019-11-12 2021-05-28 南通尚阳通集成电路有限公司 超结器件及其制造方法

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