DE112022007742T5 - Halbleitereinrichtung, Verfahren zum Steuern einer Halbleitereinrichtung, sowie Verfahren zum Herstellen einer Halbleitereinrichtung - Google Patents

Halbleitereinrichtung, Verfahren zum Steuern einer Halbleitereinrichtung, sowie Verfahren zum Herstellen einer Halbleitereinrichtung Download PDF

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Publication number
DE112022007742T5
DE112022007742T5 DE112022007742.5T DE112022007742T DE112022007742T5 DE 112022007742 T5 DE112022007742 T5 DE 112022007742T5 DE 112022007742 T DE112022007742 T DE 112022007742T DE 112022007742 T5 DE112022007742 T5 DE 112022007742T5
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DE
Germany
Prior art keywords
region
main surface
layer
type
pillar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE112022007742.5T
Other languages
German (de)
English (en)
Inventor
Tomohiro Tamaki
Makoto Hashimoto
Yohei Sudo
Tadayoshi Deguchi
Mitsuhisa Kawase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Nisshinbo Micro Devices Inc
Original Assignee
Mitsubishi Electric Corp
Nisshinbo Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp, Nisshinbo Micro Devices Inc filed Critical Mitsubishi Electric Corp
Publication of DE112022007742T5 publication Critical patent/DE112022007742T5/de
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/418—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/058—Forming charge compensation regions, e.g. superjunctions by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/417—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the collector side relative to other parts of the drift region

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
DE112022007742.5T 2022-09-05 2022-09-05 Halbleitereinrichtung, Verfahren zum Steuern einer Halbleitereinrichtung, sowie Verfahren zum Herstellen einer Halbleitereinrichtung Pending DE112022007742T5 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/033226 WO2024052952A1 (ja) 2022-09-05 2022-09-05 半導体装置、半導体装置の制御方法、および半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE112022007742T5 true DE112022007742T5 (de) 2025-06-18

Family

ID=90192347

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112022007742.5T Pending DE112022007742T5 (de) 2022-09-05 2022-09-05 Halbleitereinrichtung, Verfahren zum Steuern einer Halbleitereinrichtung, sowie Verfahren zum Herstellen einer Halbleitereinrichtung

Country Status (4)

Country Link
JP (1) JP7793067B2 (https=)
CN (1) CN119769194A (https=)
DE (1) DE112022007742T5 (https=)
WO (1) WO2024052952A1 (https=)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4447065B2 (ja) 1999-01-11 2010-04-07 富士電機システムズ株式会社 超接合半導体素子の製造方法
JP2007012858A (ja) * 2005-06-30 2007-01-18 Toshiba Corp 半導体素子及びその製造方法
JP2007300034A (ja) 2006-05-02 2007-11-15 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP2008294109A (ja) 2007-05-23 2008-12-04 Toshiba Corp 半導体装置及び半導体装置の製造方法
US9685506B2 (en) 2015-03-05 2017-06-20 Infineon Technologies Americas Corp. IGBT having an inter-trench superjunction structure
JP2017050423A (ja) * 2015-09-02 2017-03-09 株式会社東芝 半導体装置の製造方法
JP6713885B2 (ja) * 2016-09-09 2020-06-24 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP2019054169A (ja) * 2017-09-15 2019-04-04 株式会社東芝 半導体装置
CN111200010B (zh) 2018-11-20 2023-09-29 深圳尚阳通科技股份有限公司 超结器件及其制造方法
CN110212018B (zh) 2019-05-20 2022-08-16 上海华虹宏力半导体制造有限公司 超结结构及超结器件
JP2021057552A (ja) * 2019-10-02 2021-04-08 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN112864219B (zh) 2019-11-12 2024-08-27 南通尚阳通集成电路有限公司 超结器件及其制造方法

Also Published As

Publication number Publication date
JP7793067B2 (ja) 2025-12-26
WO2024052952A1 (ja) 2024-03-14
CN119769194A (zh) 2025-04-04
JPWO2024052952A1 (https=) 2024-03-14

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