CN107112356B - 具有薄底部射极层并在屏蔽区域和终止环中的渠沟中植入掺杂物的垂直功率电晶体 - Google Patents

具有薄底部射极层并在屏蔽区域和终止环中的渠沟中植入掺杂物的垂直功率电晶体 Download PDF

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CN107112356B
CN107112356B CN201680003915.5A CN201680003915A CN107112356B CN 107112356 B CN107112356 B CN 107112356B CN 201680003915 A CN201680003915 A CN 201680003915A CN 107112356 B CN107112356 B CN 107112356B
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substrate
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CN107112356A (zh
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哈姆扎·耶勒马兹
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Miracle Power Semiconductor Co ltd
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MaxPower Semiconductor Inc
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Abstract

本发明公开了在垂直电晶体(例如IGBT)中的各种改进。该等改进包括在生长基板的顶端表面区中形成周期性高度掺杂p型射极熔接点，接着是生长该等各种电晶体层，接着是磨光该基板的底面，接着是该底面的湿式蚀刻以暴露该高浓度掺杂p+层。金属接点随后在该p+层上面形成。在另一改进中，边缘终止结构利用植入渠沟中的p‑掺杂物以产生用于塑形该电场的深p‑区，以及在该等渠沟之间用于在截止之后快速地去除电洞的浅p‑区。在另一改进中，使用n‑层和分布式n+区的双缓冲层改进崩溃电压和饱和电压。在另一改进中，在终止结构中不同浓度的p‑分区借由变化渠沟的间距而形成。在另一改进中，斜切锯道提高崩溃电压。

Description

具有薄底部射极层并在屏蔽区域和终止环中的渠沟中植入掺 杂物的垂直功率电晶体
本申请案是由Hamza Yilmaz于2016年9月8日所申请的美国专利申请案序号 15/259,877的国际申请案，其对2015年10月20日所申请的美国临时申请案序号62/244,120主张优先权。15/259,877和62/244,120两者皆转让给本发明受让人，且并入文中作为参考。
技术领域
本发明涉及隔离闸极装置，例如垂直绝缘闸极双极性电晶体(Insulated gatebipolar transistors，IGBTs)，尤其是关于改进效率并提高崩溃电压的装置结构和制造技术。
背景技术
尽管本发明可应用于多种垂直隔离闸极装置，但是IGBT将用作范例。
常见垂直IGBT的一种类型含有借由开始载子的注入的MOSFET而驱动的垂直pnp双极性电晶体(由并行的许多单元形成)，其随后完全接通该pnp电晶体。在高电流准位下，在垂直IGBT中的正向电压降(Vce-sat)通常低于垂直 MOSFET。在处理高电流和高电压(例如用于工业马达控制、感应加热等)的高功率IGBT中，该n型基极需要相对较轻掺杂以产生宽空乏层，以在该截止状态下耐受该高电压。这种厚且轻掺杂n型基极层系降低该Vcs-sat的瓶颈。当该电晶体从接通切换为截止时，重要的是从该n型基极迅速地去除电洞，以快速地停止该电流流动。
更薄、更高浓度掺杂p型射极(其可能是该IGBT的底部半导体层)欲提高电洞注入效率并减少该IGBT的Vce-sat。不过，在提高注入效率与该IGBT的截止速度之间有权衡利弊。薄p型射极层通常在完成该等前端制程之后(即在形成该等电晶体层之后)形成，其中该晶圆(硅基板)的底面机械地磨光，接着是植入该底面中的该等p型射极掺杂物，接着是退火步骤。雷射退火是所需的，因为该所得到的热不会导致任何该等正面掺杂物进一步扩散。此退火步骤添加该制造过程复杂度并需要专门设备。
所需该装置具有高崩溃电压但是低Vce-sat。在该等主动单元的区域中的崩溃(在该截止状态下)可导致永久性装置故障，因此所需该装置提供远离该精细主动单元数组的崩溃路径。高电压的有效处理而无损害一般指称为坚固性。
接近该晶粒的该等边缘的区域特别容易由于电场拥挤而崩溃，且不应为该装置的整体崩溃电压的瓶颈。终止结构通常在该晶粒的该等边缘周围用于高功率装置。
在所有该等以上所提及区域中的改进皆是所需，以产生更坚固又有效的 IGBT。
发明内容
本发明所公开的内容说明减少正向电压降(Vce-sat)、改进截止时间以及改进该主动单元数组的坚固性的IGBT结构和制造方法。该等教示可应用于各种其他类型的功率装置。
在一个具体实施例中，相对较浅且窄的渠沟式闸极在主动单元数组区域中形成以形成MOSFET或IGBT，且用闸极材料填充的较宽深渠沟在围绕主动区域的屏蔽区中形成。深浮接p-区在深渠沟下方形成(借由植入渠沟中)，从而在主动区域周围产生等电位环以改进装置的崩溃电压。在屏蔽区中的深渠沟之间的较浅p-区至顶部源极金属短路，以在IGBT闸极已截止之后，从n型基极迅速地去除电洞，以加速电流流动的截止。深浮接p-区区域专为在正常截止和 IGBT截止模式期间屏蔽浅p-区以免崩溃所设计。
若有多段的单元数组，则在每个单元数组周围可能有屏蔽区。在晶粒的边缘周围的终止结构可能围绕单元数组和屏蔽区。
屏蔽区专为具有低于主动区域和IGBT装置的边缘终止结构的崩溃电压的崩溃电压所设计。屏蔽区非常坚固，因此在崩溃时对该装置通常无永久性损害，其中屏蔽区分流电流远离主动区域。
此外，紧邻深渠沟(在屏蔽区中)的「电洞旁路p+区」安全地提供给在n型漂移区中的汲极电洞，远离浅渠沟MOSFET或IGBT的寄生npn双极性电晶体以防止触发此类装置结构内在的4层npnp寄生闸流体。由于在屏蔽区中的深渠沟下面形成「电洞旁路p+区」和深p-区结果，依据本发明所形成的MOSFET 或IGBT装置将具有强化安全操作区域(Safe OperationArea，SOA)，其定义为可预期装置操作而没有损害的电压和电流条件。
在另一个具体实施例中，在将p型掺杂物植入在屏蔽区中的深渠沟中之后，渠沟用介电体填充。金属环在介电体上方的顶端表面上形成并用作浮接场板。介电体填充渠沟在金属环与深p-区之间用作垂直间隙层，其用于控制空乏区的形状(其控制崩溃电压)。介于深p-区接面处与其相关联浮接金属场板之间的垂直深度差设定在相关联金属环中的电压。
在IGBT结构的另一个具体实施例中，分段高度掺杂n+缓冲层(形成条带或点)在惯用n缓冲层上方形成。n+分段缓冲层部分提高穿透电压以提高崩溃电压，但是由于在n+分段缓冲层中的间隙而未显着减少底部p型射极的电洞注入效率。n+分段缓冲层也降低Vce-sat。这也允许上覆n型漂移区更薄。因而，双缓冲层导致Vce-sat减少而崩溃电压提高。
在另一个具体实施例中，IGBT结构与分段高度掺杂且薄的p型射极一起形成，从而无需雷射退火。较薄的p型射极(IGBT的底部半导体层)提高电洞注入效率并减少IGBT的Vce-sat。形成薄高度掺杂p型射极的方法包括使用屏蔽将p型掺杂物的单元(例如点)或条带区植入p型硅基板的顶端表面中，以形成许多p+区。然后，各种磊晶层在该顶端表面上面生长，且掺杂区形成，以实际上完成IGBT的正面处理。用于正面处理的各种加热步骤提供p型点/条带的一些驱入和启动，这可能在某种程度上合并点/条带，但是仍然在生长基板的顶端表面区中导致高低p-掺杂物浓度。在正面处理之后，硅晶圆的后表面机械地磨光至约其最终厚度的80-90％，接着湿式蚀刻以暴露在底面上的p型点。高度掺杂p+区域用作湿式蚀刻的蚀刻停止层(借由色彩而光学地侦测到)。底面不必借由雷射进一步加热以扩散p型点，从而减轻处理要求。由于湿式蚀刻速率在某种程度上依掺杂物浓度而定，因此所得到的减薄基板具有对底部电极提供极好电接触的粗化底面。金属电极层随后在直接接触暴露p型点的后表面上沉积。该金属层可能进行退火以改进接触电阻。所得到的p型射极层高度掺杂(指称为p+)且极薄，这导致更高效率的IGBT。
说明在晶粒的边缘周围的终止结构，其包括渠沟和在渠沟下方的深p- 区，其借由通过渠沟的植入而形成。在一些具体实施例中，渠沟用导电材料填充以提供等电位环。在其他具体实施例中，渠沟用介电体填充。在渠沟用介电体填充的具体实施例中，深p-区连接至用作用于延展电场的浮接场板的顶部金属环。各种深p-区的掺杂物浓度可借由变化该等渠沟的间距而变化，以使掺杂物浓度朝向晶粒的边缘变低以优化崩溃电压。
说明其他具体实施例。
附图说明
图1A是具有沿着该中心单元数组(该主动区域)的周边的屏蔽区和沿着形成IGBT的晶粒的边缘的高电压终止区域的晶粒的俯视图。
图1B是IGBT晶粒的俯视图，其中每组主动单元皆被深浮接p-屏蔽区围绕，且高电压终止区域沿着该晶粒的边缘。
图2是主动单元数组和围绕该主动单元数组的深浮接p-屏蔽区的一个范例的剖面图。所示主动单元数组可能在晶粒中心的较大单元数组的简写版(如图 1A所示)或单元的条带(如图1B所示)。用于在该屏蔽区中的该等深p-区的该等 p型掺杂物，通过该等深且宽的渠沟植入。沿着该晶粒的边缘的高电压终止区域在图2中未显示，但是在其他图标中显示。
图3-图10是例示在图2的IGBT的形成中的制造步骤。
图11是例示图2的IGBT的变化例，其中在用于在截止之后从该n-基极层去除电洞的屏蔽区中的该等深渠沟之间没有浅p-区。
图12-图14例示用于形成该高度掺杂且极薄底部p型射极层的步骤。
图15和图16例示用于形成该高度掺杂且极薄底部p+射极层的另一个具体实施例的步骤，其中附加n+区形成以在该等电压极性反转时通过该IGBT提供反向传导。
图17-图19例示沿着该晶粒的边缘的高电压终止区域的替代性具体实施例，其中该闸极材料填充围绕单元数组的宽且深渠沟，且其中深p-区在每个渠沟下方。该等各种替代例使用不同数量的屏蔽，这会影响制造成本。
图20-图26例示终止区域的替代性具体实施例，其中介电体材料填充围绕单元数组的宽且深渠沟，且其中深p-区在每个渠沟下方。该等各种替代例使用不同数量的屏蔽，这会影响制造成本。
图27-图29例示变化在该终止区域中的该等深渠沟之间隔以达成该等深 p-区的锥形嵌埋p-掺杂物浓度，以进一步改进该崩溃电压。该等p-掺杂物透过该等渠沟植入。
图30例示斜切该晶粒的边缘以改进用于非常高电压IGBT(例如>1700V) 的崩溃电压。
在该等各种图示中的等同或类似组件用相同编号识别。
具体实施方式
尽管垂直pnp IGBT装置在图标中显示，但是npn IGBT可能借由反转各种区域/层的极性而制造。此公开内容的教示可以很容易地借由用n型基板取代p 型基板而应用于垂直MOSFET。
图1A依据本发明的一个具体实施例的IGBT 10的俯视图。硅晶粒具有外缘12。IGBT10具有中心部分，包含单元14的数组，其并行连接。作为概述，每个垂直单元区域皆包含pnp电晶体的顶部p型集极；p-主体，其用于由 MOSFET部分反转以引发接通；顶部n+源极区；厚n-基极层(包括n型缓冲层)；底部p型射极层；以及渠沟式闸极，其紧邻n+源极区和p-主体。足够高的闸极电压在p-主体中产生n-通道，以开始电子从n+源极流入垂直pnp电晶体的p型射极中。结果，来自p型射极的电洞注入n-基极层中。注入来自p型射极的电洞和来自MOSFET的n+源极区的电子将导致电子和电洞储存于厚n-基极区内部，这称为基极导电调变效应。由于基极导电调变效应，因此IGBT的Vce-sat 将减小。然而，若过多电子和电洞对储存于n-基极层内部，则IGBT截止速度变得非常慢，且IGBT耗散过多功率以致无法有用于许多应用，即使Vce-sat 较低。
当IGBT截止时，在顶部源极金属与底部射极金属之间通常将有高电压。大型空乏区在厚n-基极层(漂移区)中形成以耐受该电压。借由设计，围绕主动单元的屏蔽单元(屏蔽区域16)具有最低崩溃电压，因此其箝制IGBT的整体崩溃电压。在高电压终止区域15内部周围(沿着晶粒边缘12)的屏蔽区域16，为在n-基极层中的电洞提供安全路径以在截止期间放电，以加速停止电流流动。使屏蔽区域16的崩溃电压略少于主动区域的崩溃电压以避免损害主动区域。因此，IGBT更坚固。以下参照图2提供更多细节。
图1B是IGBT 17的另一个具体实施例的俯视图，其中单元在条带18 中形成，且屏蔽区域16围绕每个条带18。沿着晶粒的边缘的高电压终止区域 15与在条带18之间的屏蔽区域16不同。设想其他配置。
在围绕主动单元的屏蔽区域中的深且浅P-区
图2是IGBT 10或17的剖面图，其显示单元14的简写数组(在图1A的情况下)或单元的窄条带18(在图1B的情况下)。屏蔽区域16围绕单元14的数组并在单元14的数组周围连续。在单元组周围的屏蔽区域16依单元14的数组形状而定，可能形成正方形环(如图1A所示)、矩形环(如图1B所示)或其他形状，例如六边形、圆形等。
在一般应用中，负载19(例如马达)具有耦接接地的一个端子和连接至 IGBT 10的顶部源极金属20的另一个端子。正电压(例如500V)连接至底部射极金属22。当IGBT 10接通时，大约500V跨负载19两端连接。IGBT 10通常系封装晶粒。
为接通IGBT 10，假设足够电位跨源极金属20和射极金属22两端、足够正值闸极-源极电压施加于在单元14中的渠沟式闸极24。闸极24可能掺杂多晶硅。闸极24由薄介电体26隔离。p-主体28和较高n+源极区29在相邻闸极 24之间。源极金属20由延伸穿越介电层34的Ti/W金属连接件32连接至n+ 源极区29和p+主体接触区30。
偏压闸极24反转相邻p-主体区28，以在n+源极区29与轻掺杂n-基极层 36之间产生垂直n-通道。电流随后在n+源极区29与底部p型射极层42之间垂直地流动(形成由n-通道MOSFET驱动的正向偏压pnp双极性电晶体)。射极层42的高掺杂导致掺杂程度较佳为p+。
由于MOSFET动作的初始电流导致电洞注入n-基极层36中，这接通由p+ 接触区30、p-主体区28、n型基极层36和p型射极层42形成的垂直pnp双极性电晶体，以进一步减少正向电压降Vce-sat。
为截止IGBT，正值闸极-源极电压去除，且n-基极层36由p-主体区28、 p+接触区30和源极金属20放电。闸极24可能至源极金属20短路或连接至略负值电压。
在单元14的数组中的渠沟式闸极24相对较浅并仅需要比p-主体区28略深。
屏蔽区域16含有用闸极材料46(例如掺杂多晶硅)填充的较深且较宽渠沟 44。介电体47使深渠沟44有线条。闸极材料46经由金属接点48和闸极金属 50电连接至各种浅闸极24。在一个范例中，闸极24的数量级可能是1.5μm 深，而在深渠沟44中的闸极材料46可能约2-2.5μm深并比闸极24更宽。如稍后所说明，深渠沟44的较大宽度(在屏蔽步骤中所定义)导致其在相同蚀刻步骤期间蚀刻得比窄渠沟更深，因此形成深渠沟44没有额外步骤。
在深渠沟44之间和在深渠沟44下方轻掺杂p-区，包含深p-区56，其在深渠沟44下方；以及较浅p-区57，其在深渠沟44之间。深p-区56可能向下延伸举例来说至深渠沟44下方2μm。深p-区56也指称为p-屏蔽。深p-区56 由于低掺杂浓度而具有高电阻率，并由连接至源极金属20、分布在屏蔽区域 16周围的p+接触区58微弱地偏压。
在截止状态下，较浅p-区57和n-基极层36反向偏压。深p-区56降低在渠沟44下方的电场，因为p-区56在崩溃之前完全空乏，这导致较高的崩溃电压(给定n-基极层36的特定掺杂物浓度)。p-区56也用于横向地空乏n-基极层 36，以进一步提高崩溃电压。p-区56区可完全地浮接，但是为将装置从截止状态切换为接通，起因于空乏层的寄生电容必须放电。因此，优选为经由在晶粒的某些位置上的p+接触区58将p-区56「微弱地」连接至源极金属20，以在装置从截止切换为接通状态期间放电电容并减少切换延迟。
当IGBT10截止时，n-基极层36和p-区56/57依电位差的量值而定变得空乏，且掺杂导致屏蔽区域16在略少于在单元14的数组区域中的崩溃电压的电压下崩溃。这防止在崩溃之后损害主动单元。重要的是单元14不会受到崩溃影响，因为受损单元可能在单元区域中汲取更多电流并导致热失控。由于优选掺杂程度受到许多因素影响，因此可借由模拟决定。
介于深渠沟44之间较浅p型区57。当IGBT 10截止时，剩余在n型基极层36中的电洞由p-区56/57且主要由分布在屏蔽区域16周围、紧邻p+接触区 58的较浅p-区57抽出，以更迅速快地截止IGBT 10(即n型基极层36放电)。电洞也通过在单元14的数组中的p-主体区28抽出。
此外，屏蔽区域16的另一部分在最内层深渠沟44与单元14的数组之间形成。此区域包含浅p-区60，其具有与p-主体区28相同的掺杂物浓度，且比在深渠沟44周围的p-区56/57更高浓度掺杂。电洞也被浅p-区60经由p+接触区62和源极金属20扫除。由于这不是MOSFET区域，因此在p-区60上方没有n+源极区。
图2借由箭头66例示在屏蔽区域16中的一些任意电洞收集轨迹(用于改进截止速度)，其指称为电洞旁路区，因为一些电洞扫除旁路被单元14扫除的电洞。
此外，箭头68标识当IGBT接通时来自n+源极区29区的电子注入的向下方向。在接通时间期间由p型射极层42注入的一些电洞的向上方向由箭头 70指出。
由于轻掺杂p-区56/57在截止状态下伴随n-基极层36空乏，因此n-基极层36可以比惯用n-基极层更高度掺杂，以减少Vce-sat而不减少崩溃电压。
屏蔽区域16可位于单元的整个数组周围或单元组(例如形成为条带的单元组)周围。在图2的范例中，单元可能进出所附图式的各种区域和闸极的并行条带。屏蔽区域16可围绕任何数量的单元。其他形状的单元可能是正方形、六边形等。在单元形成为长条带组的一个具体实施例中，屏蔽区域16围绕多达二十个单元条带。依IGBT的电流要求而定，可能有任何数量的并行连接的条带组。
双n和n+缓冲层
n型缓冲层74和在缓冲层74上面形成的n+点76(或者n+条带)也新颖。缓冲层74和n+点/条带76减少跨IGBT两端的接通电阻和饱和电压Vce-sat降，同时借由防止在n-基极层36中的空乏区到达p型射极层42(停止穿透)而最大化崩溃电压(当IGBT截止时)。缓冲层74可能约5μm厚。砷或锑n型掺杂物由于较慢的扩散而较磷佳。来自p型射极层42的电洞仅注入在n+点/条带76 之间的n-基极层36中，如箭头70所示。借由延展开n+点/条带76，电洞可通过在n+点/条带76之间的n-缓冲层74从p型射极层42注入，而n+点/条带76 用于减少饱和电压降Vce-sat。n+点/条带76也迅速地扫除在n-基极层36中的储存电荷以加快截止时间，并允许n-缓冲层74为了减少的Vce-sat而较薄。此外，n-缓冲层74和n+点/条带76的组合可用于借由调整缓冲层74的掺杂密度和介于n+点/条带76之间的间隔，而自定义介于Vce-sat与截止时间切换速度之间的权衡利弊。
以下说明图2的装置的制造，包括新颖制造过程，其用于形成晶圆的底部部分和其他特征。稍后也说明终止区域和处理选项的各种其他具体实施例。
参照图3，起始基板80是p型。n型缓冲层74随后以磊晶方式生长。屏蔽和植入步骤形成n+点/条带76。高电阻率n-基极层36随后生长。厚度和掺杂依所需崩溃电压而定。更高度掺杂n-层82随后在n-基极层36上面生长，接着是又更高度掺杂n-层84。在一个范例中，层82和84形成IGBT的半导体层的顶部6-9μm以形成锥形掺杂物浓度，以优化Vce-sat和崩溃电压。
表面随后选择性地屏蔽，且p-掺杂物植入在驱入步骤之后形成p-阱86。
在形成p-阱86之后，SiO2/Si3N4/SiO2硬屏蔽层88沉积。
参照图4，屏蔽层88布局图样以形成渠沟，且渠沟使用活性离子蚀刻(RIE) 进行蚀刻。在屏蔽层88中的宽开口将内在地形成较深渠沟90，同时在屏蔽层 88中的窄开口将形成较浅渠沟92。蚀刻在较浅渠沟92到达其目标深度之后停止，这大约是n-层84的深度。较浅渠沟92的深度可能约1.5-2.5μm。
参照图5，较浅渠沟92使用现有技术的制造过程技术用屏蔽材料94(例如氧化物或光阻)填充。
参照图6，尽管浅渠沟92仍用屏蔽材料94(图5)填充，但是p型掺杂物透过深渠沟90植入并驱入以形成深p-区56。出自图3的p-阱86现在形成较浅 p-区57。硬屏蔽层88随后去除。n-层82和84(图5)在后续图标中不会显示为分开层，因为现在有从顶部向下至n-基极层36的平滑n型掺杂物浓度变化。所有氧化物随后皆去除以暴露较浅渠沟92。
参照图7，晶圆氧化以在深渠沟44侧壁上形成闸极介电体26(500-1200埃) 和介电体47。掺杂多晶硅随后沉积以填充入所有渠沟，以在深渠沟44中形成闸极24和闸极材料46。晶圆随后平坦化以从顶端表面去除多晶硅。
参照图8，p-主体屏蔽(未显示)形成以暴露邻接浅渠沟92的区域，且p型掺杂物植入并驱入以使p-主体28不会在闸极24下方延伸。
参照图9，屏蔽(未显示)暴露介于较浅渠沟92之间的区域，且n型掺杂物植入并驱入以形成浅顶部n+源极层。硼磷硅玻璃(BPSG)屏蔽93随后沉积，以暴露该n+源极层的中心区域。RIE蚀刻去除n+源极层的中心部分，以形成紧邻浅闸极24的n+源极区29。
参照图10，p-掺杂物植入(硼)使用相同的屏蔽93进行，以形成p+接触区 62。该硼剂量少于源极掺杂物植入剂量。
返回参照图2，Ti/W金属连接件32随后在屏蔽93(图10)开口中沉积，且表面平坦化。在图2中的介电层34是在图10中的BPSG屏蔽93。铝源极金属 20随后沉积并布局图样，以与各种n+源极区29和p+接触区62电接触。闸极金属50电接触各种闸极24(在较浅渠沟中)和填充较深渠沟44的闸极材料46。形成闸极的导电多晶硅可能用于在图2的平面外部，将所有闸极材料电连接在一起。闸极金属50与源极金属20隔离，且闸极/源极金属层50/20用氧化物/ 氮化物钝化层94覆盖，除了用于将封装端子引线接合至源极金属20和闸极金属50的焊垫开口区域。
图2-图11例示在屏蔽区域16之间具有窄主动区域(单元14的数组)的屏蔽区域16，且其中每个屏蔽区域16皆具有两个深渠沟44，其在每个渠沟44下方皆具有用于改进崩溃电压的深p-区56，以及在渠沟44的间用于在IGBT切换为截止之后快速地扫除电洞的较浅p-区57，以缩减截止时间。如先前所提及，坚固终止区域在略少于主动区域(单元14的数组)的崩溃电压的电压下崩溃，以保护单元14。
图11显示具有屏蔽区域100所围绕的重复主动区域98的IGBT的另一个具体实施例，其中每个屏蔽区域100皆仅有一个用于改进IGBT的崩溃电压的深渠沟102。所有其他实施方式如在图2中皆相同。
在p型射极中形成包括高度掺杂p型点或条带的背面特征
现在将说明晶圆的背面的新颖形成。所需具有用于最有效电洞注入的极薄高度掺杂底部p型射极层。所公开的制造过程形成此类薄高度掺杂底部p型射极层，而实质上未在正面中扩散掺杂物，且所得到的底面借由湿式蚀刻制造过程粗化以改进与底部金属电极的电接触。
参照图12，使用p型起始基板106(晶圆)。在硅晶圆中仅显示单一晶粒的区域。在基板106的顶端表面上面沉积屏蔽(未显示)，以在预期晶粒区域的中心部分上面产生小型开口，以及在晶粒区域的边缘处产生较宽开口。高能量p 型掺杂物植入(硼)以5E14-1E16cm-2的剂量进行。这在p-基板106中产生更高浓度掺杂p型材料的小型条带或点108。点108具有高浓度掺杂p+中心110和较少掺杂p壳层112。由于在每个晶粒区域的边缘处的该等较宽开口，植入导致较深p+中心114和p壳层116。掺杂物此时未驱入。
参照图13，可以惯用或如图2所示任一者的IGBT结构的各种层在基板 106的顶端表面上面以磊晶方式生长，且各种区域和闸极形成以完成正面处理。正面层在图13中未详细显示，且在n-缓冲层74(其可能包含先前所说明的双缓冲层)上面标示118。用于正面处理的各种热步骤进行植入基板106的顶端表面区中的p-掺杂物的初始驱入，且p-掺杂物延展由层119显示，因此点108可在某种程度上合并。基板106的底面随后机械地磨光120以刚好在p型植入点 108的底部下方，这约是基板106的最终厚度的80-90％。
参照图14，氢氧化钾(KOH)、氢氧化四甲胺(Tetramethyl ammonium hydroxide，TMAH)、乙二胺邻苯二酚(Ethylene diamine pyrochatechol，EDP)或混合液等慢速各向异性蚀刻剂122施加于后表面以去除硅，直到点108的p+ 中心110(具有>1E19cm-3的掺杂物浓度)经光学侦测(改变颜色)。因此，p+硅用作蚀刻停止层，并导致IGBT的p型射极的最小厚度。湿式蚀刻剂以其具有依硅的晶体方向而定的不同蚀刻速率而优选地选择性。底面由于p和p+区域的不同蚀刻速率而在湿式蚀刻之后相对较粗糙，这可改进金属对硅电接触。附加硼植入可能执行以改进奥姆接触。
在制造各种步骤期间加热晶圆的过程中，点108可能合并或可能延展以形成紧密间隔p+区。在任何情况下，IGBT表面的底部基本上皆将系p+型层。背面金属22(Al/Ti/Ni/Ag)随后沉积，并在450℃或低于450℃的温度下烧结，这进一步扩散p-掺杂物。该所得到的p型射极层42(图2)可能少于2μm，且在一个具体实施例中少于1μm。
晶圆随后沿着对应于较宽p+中心114和p-壳层116的位置的线切割，以分割IGBT晶粒。
参照图15，显示对底面结构的修改以形成反向传导IGBT，其中n+点124 借由使用5E15-1E16cm-2磷植入物屏蔽基板106的表面(在顶层形成之前)接近每个晶粒区域的边缘而形成。使用上述相同制造过程减薄/蚀刻基板106并驱入掺杂物。n+点124的密度也可提高，举例来说，以完全地填充介于p+点108 之间的空间。
参照图16，底面随后金属化以形成金属层22，其接触底部半导体层的p+ 和n+部分。n+点124直接接触n-缓冲层74和金属层22，以在有反转极性事件时允许反向电流流过IGBT，因为正向偏压二极管现在当底部金属层22相对于顶部源极金属层足够负值时形成。
高电压边缘终止选项
以下说明在单元的晶粒或数组的边缘周围的各种终止结构，其对于极高电压IGBT(例如超过500V)特别有用。用于高功率电晶体的晶粒的边缘由于在晶粒边缘处的不对称而特别容易崩溃。图17-图19显示渠沟用掺杂多晶硅填充的终止选项，而其余图标显示渠沟用介电体(例如氧化物(SiO2))填充的终止选项。
图17显示在用闸极材料46填充的深渠沟44下方的深p-区130所形成的嵌埋场环的一个具体实施例。深p-区130借由通过渠沟植入，以与先前所说明的深p-区相同的方式形成。深p-区130也可指称为浮接防护环。介于渠沟之间与IGBT的p-主体区28(图2)同时形成的p型区134。闸极材料46和p型区 134使用金属接点132电连接至也指称为场板的相关联浮接金属环136A-136D。浮接金属场板彼此隔离并在每个环136A-136D下方皆等化电压，以限制电场并最大化崩溃电压。含有单元数组和屏蔽区域(未显示)的主动区域系在终止结构的左侧。接近该晶粒区域的外缘的通道停止区域138防止寄生通道的形成，并防止空乏区延伸至该晶粒的最边缘。浮接深p-区130能使n-基极层36更高度掺杂(以减少Vce-sat)，而不会降低该装置的崩溃电压。
随着n-基极层36空乏，空乏穿透各种浮接深p-区130(从最内层浮接p- 区130起始)并箝住深p-区130的电位。p-区130注入少量的电洞，且损失电荷被来自p-区130的外缘的n-基极层36的空乏取代。此类动作从内部深p-区130 至外部深p-区130连续地发生。如此，有朝向晶粒的边缘的平滑空乏区。
下述各种附加具体实施例可能简单地借由排除一个或多个屏蔽而与其他具体实施例不同，从而导致类似性能，但是较少制造步骤。
图18类似于图17，但是其中p-主体植入以使p-区134延伸至通道停止区域140。因此，屏蔽步骤借由不遮蔽晶粒区域的右侧边缘的p-主体植入而省下。
图19类似于图18，除了用于形成n+源极区29(图2)的n-掺杂物植入也在渠沟之间形成n+区142，因而排除另一屏蔽步骤。
深渠沟用介电体填充以垂直地间隔浮接金属环和深P-区
图20类似于图17，但是用介电体146而非导电多晶硅填充渠沟44。渠沟 44(在用介电体146填充之前)用p型掺杂物植入以形成深p-区130。该上覆的金属形成用作浮接场板的浮接金属环，例如环136B。介电体填充渠沟在深p- 区130与相关联金属环136之间用作垂直间隙层，其可用于控制空乏区的形状。在此结构中，介于深p-区130接合处深度与介电体填充渠沟的深度之间的垂直深度差设定在每个浮接场环中的电压。
图21类似于图20，除了在p-主体植入期间没有p-区134(图20)形成，且有较少金属场板。
图22类似于图21，除了没有中间金属场板。
图23类似于图21，除了在用介电体146填充的渠沟之间有p-区134在p- 主体植入期间形成，因而排除一个屏蔽步骤。
图24类似于图23，但是使用渠沟式通道停止区148。
图25类似于图24，但是包括n+层142，其在用于形成图2中n+源极区的n型掺杂物的植入期间形成，因而排除p-主体和n+源极两者植入屏蔽步骤。
图26未形成深p-区，而是依赖借由金属接点132连接至其相关联金属浮接场板150的p-区134，以为晶粒的边缘提供平滑过渡。
图27例示使用嵌埋接面处终止延伸(Junction Termination Extension，JTE) 的终止区域。在渠沟154蚀刻的后，p型硼以用于深植入的高能量植入1-4E12 cm-2的范围内。在扩散的后，p-区156的那些植入凹穴合并在一起，以形成具有不同平均p掺杂浓度的分区(分区1-4)。渠沟154朝向晶粒的边缘间隔更宽，且介于渠沟154之间的硅台面尺寸决定在每个分区中的p-电荷。分区和p-掺杂物浓度的相对百分比重迭在p-区156上面，其中掺杂物浓度朝向晶粒的边缘减少。在分区1中有较小型台面，而在分区4中有较大型台面。更多分区可添加以最大化崩溃电压并用制造过程改变最小化崩溃变异数(variance)，以及用氧化物电荷的不同极性和量最小化崩溃变异数。锥形掺杂物浓度更均等地延展电场。合并的p-区156经由p-区159和金属接点132电耦接至金属场板150。金属场板150可能连接至参考电压或浮接。在该表面与p-区156的间的n-区158 (n-基极层36的一部分)由介电体填充渠沟154分段。这些浮接n-区158将假设相邻分区的局部电位。这将使终止区域对氧化物电荷变化和在顶部区域/表面中的n-掺杂物浓度变化不敏感。
图28类似于图27，除了有经由p-区162和金属接点132电耦接至合并p- 区156的附加外部场板160。
图29类似于图28，除了有省下屏蔽步骤、形成p-区168的p-主体植入。
晶粒的斜切边缘提高崩溃电压
图30例示该晶粒区域的最边缘，其中屏蔽用于蚀刻在晶圆上的晶粒区域的边缘，以沿着用于分割的锯道(saw streets)形成斜切边缘170。屏蔽湿式蚀刻将形成此类斜切边缘。表面随后用氧化物/氮化物层172钝化。晶粒随后在邻接晶粒区域的斜切边缘170之间进行分割。斜切边缘由于起因于斜切边缘更好的电场分布，因此允许IGBT支持超过1700V的电压。
结论
文中揭示各种发明，从而针对IGBT或其他功率电晶体提供改进，包括但不限于：
1.周期性高度掺杂p型射极熔接点或条带(图12-图14)在生长基板的顶端表面区中形成，接着生长各种电晶体层。点/条带可能由于各种加热步骤而在某种程度上合并。基板的底面随后磨光，接着湿式蚀刻以暴露高度掺杂p型硅。高度掺杂p型射极熔接点或条带(或合并层)在湿式蚀刻期间标识蚀刻停止层，从而导致极薄p型射极。薄p型射极实现具有低Vce-sat的高效IGBT。点/条带也在为了改进金属对基板接触的湿式蚀刻之后产生粗化底面。
2.终止结构(图20-图25)形成以围绕单元数组，其中介电体填充深渠沟，其中深p-区在每个渠沟下方(借由植入渠沟中)，其中浮接金属环(场环)在每个渠沟上面以提供高度可控制的终止特性，且其中介于深p-区接面处与其相关联金属环之间的垂直深度差设定每个浮接环的电压，以改进崩溃电压。
3.在p型基板(射极)上面的双缓冲层(图2)形成，包含第一n层，其在基板上面；以及薄第二n+层，其在第一n层上面，用于减少Vce-sat，同时借由停止穿透而最大化崩溃电压。n+层可能由点或条带形成，且来自p型基板的电洞注入在点/条带的间。因而，电洞注入效率不会受到n+层不利地影响。
4.深且宽的渠沟(图2)形成，其中深p-区在围绕单元数组的渠沟下方，用于控制崩溃电压，伴随较浅p-区在深p-区的间，用于迅速地去除电洞，以快速截止装置并防止发生闸流体动作。导电材料填充渠沟。
5.在终止区域(图27-图29)中，渠沟的数组以变化间距形成，然后p型掺杂物植入渠沟中。渠沟朝向晶粒的边缘间隔更宽。在扩散之后，p-区合并并形成具有不同平均p掺杂浓度的横向p型分区。介于渠沟之间的硅台面宽度与在每个分区中的p-电荷成反比，因此p掺杂浓度朝向晶粒的边缘减少。p-区连接至顶部金属场板。p掺杂浓度的梯度提供更均匀的电场分布以增加崩溃电压。
6.在晶粒之间的斜切锯道170(图30)借由湿式蚀刻而形成，以用于极高电压装置。钝化层(氧化物172)在斜切边缘和锯道上面形成。
以上六点发明如下进一步分别加以总结：
1.一种形成垂直功率装置(图12-图14)的方法包含：
提供基板106，基板具有顶端表面和底面；
用第一导电类型(例如p型)的掺杂物掺杂基板的顶端表面区，以使基板的顶端表面区比基板的底面区更高度掺杂的第一导电类型；
在基板的顶端表面上面生长第二导电类型的磊晶层118，并形成该第一导电类型28和第二导电类型29的区域，以形成垂直电晶体结构；
磨光基板的底面；
使用顶端表面区作为蚀刻停止层湿式蚀刻基板的磨光底面，以暴露顶端表面区；
在湿式蚀刻之后在暴露顶端表面区上形成第一金属电极22；以及
在磊晶层上面形成第二金属电极20。
2.一种用于电晶体的终止结构(图20-图25)包含：
单元数组14，其在第一导电类型(例如n型)的第一半导体材料36中形成；
同心渠沟44，其在围绕单元数组的第一半导体材料中形成；
第二导电类型的深区130，其在渠沟下方形成，其中每个深区皆与渠沟之一相关联；
介电体材料146，其至少部分地填充渠沟；以及
导电环136，其上覆每个渠沟，每个导电环都是浮接场环，其中在每个渠沟内的介电体材料皆在深区与导电环之间用作垂直间隙层，其中介于深区接面处与其相关联金属环之间的垂直深度差设定每个环的电压。
3.一种垂直电晶体结构(图2)包含：
第一导电类型(例如p型)的第一半导体材料36；
第二导电类型的第一缓冲层74，其在第一半导体材料上面，第一缓冲层具有第一掺杂物浓度；
第二导电类型的第二缓冲层76，其在第一缓冲层上面形成，第二缓冲层具有高于第一掺杂物浓度的第二掺杂物浓度，第二缓冲层形成由第一缓冲层的第二区隔开的横向第一区；
第二导电类型的第二半导体材料42，其在第二缓冲层上面形成，并具有低于第一掺杂物浓度的第三掺杂物浓度；以及
单元数组14，其在第二半导体材料中形成。
4.一种垂直电晶体(图2)包含：
单元数组14，其在第一导电类型(例如n型)的第一半导体材料36中形成；
同心渠沟44，其在围绕单元数组的第一半导体材料中形成；
第二导电类型的深区56，其在渠沟下方形成，其中每个深区皆与渠沟之一相关联；
第二导电类型的较浅区57，其在渠沟之间；
导电材料46，其填充渠沟；
第二导电类型的基板42，其至少借由第一半导体材料而由深区和较浅区垂直地隔开；
第一电极22，其在基板的底面上形成；以及
第二电极20，其上覆单元数组和渠沟的至少部分而形成，其中深区和较浅区将32/58电耦接至第二电极。
5.一种形成垂直电晶体的方法(图27-图29)包含：
在一第一导电类型(例如n型)的第一半导体材料36中形成单元数组14；
在围绕单元数组的第一半导体材料中形成同心渠沟154，其中介于渠沟之间的空间随着远离单元数组的距离而增加；
将第二导电类型的第一掺杂物植入渠沟中，以在每个渠沟下方皆形成第二导电类型的第一区；
扩散第一掺杂物以合并第一区并形成第一掺杂物的分区(分区1-4)，其中第一掺杂物的掺杂物浓度由于介于渠沟之间的变化空间而随着与单元数组的距离横向地降低；
将合并第一区耦接至金属场板；
在电晶体的底面上形成第一电极22；以及
上覆单元数组的至少部分形成第二电极20。
6.一种垂直电晶体晶粒(图30)包含：
单元数组14，其在第一导电类型(例如n型)的第一半导体材料36中；
蚀刻斜切边缘170，其沿着晶粒的外缘；以及
钝化层172，其在斜切边缘上面形成。
尽管本发明的特定具体实施例已显示及说明，但是本领域技术人员应可显而易见，改变和修饰可能做出而不悖离本发明更广泛的实施方式，因此，所附诸权利要求书欲在其范围内涵盖如落于本发明的真实精神与范围内的所有此类改变和修饰。

Claims (16)

1.一种形成垂直功率装置的方法，其特征在于，包含：
提供基板，所述基板具有顶端表面和底面；
用第一导电类型的掺杂物掺杂所述基板的顶端表面区，以使所述基板的顶端表面区是比所述基板的底面区更高度掺杂的第一导电类型，其中用所述第一导电类型的掺杂物掺杂所述基板的顶端表面区的步骤包含：屏蔽所述基板的顶端表面，以暴露所述顶端表面的多个区域；以及将所述第一导电类型的掺杂物植入所述所暴露的多个区域中，以在所述基板的顶端表面区中产生所述第一导电类型的多个分段高度掺杂区；
在所述基板的顶端表面上面生长第二导电类型的磊晶层，并形成所述第一导电类型和所述第二导电类型的区域，以形成垂直功率装置；
在所述垂直功率装置上方形成第一金属电极；
磨光所述基板的底面；
使用硅蚀刻剂湿式蚀刻所述基板的磨光底面，使用所述基板的包含所述第一导电类型的所述多个分段高度掺杂区的更高度掺杂的第一导电类型顶端表面区作为蚀刻停止层，以暴露在所述垂直功率装置的底面上的所述顶端表面区，其中所述湿式蚀刻的步骤导致所述基板的所暴露的顶端表面区具有粗化表面，其中所述粗化表面是由于具有所述第一导电类型的所述多个分段高度掺杂区的所述顶端表面区的不同蚀刻速率所导致的；以及
在所述垂直功率装置的粗化的底面上形成第二金属电极。
2.如权利要求1所述的方法，其特征在于，在所述基板的顶端表面上面生长所述磊晶层，并形成所述第一导电类型和所述第二导电类型的区域的步骤，包含：
在所述磊晶层中形成所述第一导电类型的主体区；以及
在所述磊晶层中形成所述第二导电类型的源极区，其中所述源极区连接至所述第一金属电极，
其中偏压闸极在所述主体区中产生导电通道，以在所述第一金属电极与所述第二金属电极之间传导电流。
3.如权利要求2所述的方法，其特征在于，所述垂直功率装置是隔离闸极双极性电晶体(IGBT)。
4.如权利要求2所述的方法，其特征在于，所述垂直功率装置是金氧半导体场效电晶体(MOSFET)。
5.如权利要求1所述的方法，其特征在于，使用所述基板的包含所述第一导电类型的所述多个分段高度掺杂区的更高度掺杂的第一导电类型顶端表面区作为所述蚀刻停止层湿式蚀刻所述基板的底面的步骤，包含光学侦测表示所述第一导电类型的高度掺杂顶端表面区的颜色变化。
6.如权利要求1所述的方法，其特征在于，还包含加热所述基板，以在所述顶端表面区中扩散所述第一导电类型的所述掺杂物。
7.如权利要求1所述的方法，其特征在于，磨光所述基板的步骤包含在所述湿式蚀刻之前，将所述基板磨光至大于其最后厚度的80％。
8.如权利要求1所述的方法，其特征在于，所述第一导电类型的所述掺杂物包含硼，且其中在所述基板的顶端表面区中的硼浓度在掺杂所述基板的顶端表面的步骤之后大于1E19 cm-3。
9.如权利要求1所述的方法，其特征在于，所述基板是所述第一导电类型。
10.如权利要求1所述的方法，其特征在于，还包含也用所述第二导电类型的掺杂物掺杂所述基板的顶端表面区的区域，以在电压极性反转时通过所述装置提供反向传导。
11.一种垂直电晶体，其特征在于，包含：
基板，其具有顶端表面和底面；
所述基板的顶端表面区，包含第一区域，其含有第一导电类型的掺杂物，以使所述第一区域是比所述基板的底面区更高度掺杂的第一导电类型，其中所述顶端表面区也包含所述第一导电类型的第二区域，其具有比所述第一区域更低的掺杂浓度，其中所述第一区域包含多个分段高度掺杂区，且所述第二区域包含在所述多个分段高度掺杂区之间的区域；
第二导电类型的磊晶层，其在所述基板的顶端表面上面生长；
在所述磊晶层中的第一导电类型的主体区；
在所述磊晶层中的第二导电类型的源极区；
闸极，其与所述主体区隔离，其中偏压闸极在所述主体区中产生导电通道；
其中所述基板的顶端表面磨光并随后湿式蚀刻以暴露所述顶端表面区，其中所述顶端表面区由于针对包含多个分段高度掺杂区的所述第一区域和包含在所述多个分段高度掺杂区之间的区域的所述第二区域具有不同蚀刻速率的湿式蚀刻而粗化，从而导致所述基板的所暴露的顶端表面区具有粗化表面；
第一金属电极，其在所述垂直电晶体上方，其中所述源极区连接至所述第一金属电极；以及
第二金属电极，其在所述垂直电晶体的底部上的粗化顶端表面区上。
12.如权利要求11所述的电晶体，其特征在于，所述垂直电晶体是IGBT。
13.如权利要求11所述的电晶体，其特征在于，所述垂直电晶体是MOSFET。
14.如权利要求11所述的电晶体，其特征在于，在所述基板的顶端表面区的所述第一区域中的第一导电类型掺杂物浓度大于1E19 cm-3。
15.如权利要求11所述的电晶体，其特征在于，所述第一区域包含的多个分段高度掺杂区为点或条带，且所述第二区域包含在所述点或条带之间的区域。
16.如权利要求11所述的电晶体，其特征在于，还包含所述顶端表面区的第三区域，其含有所述第二导电类型的掺杂物，以在电压极性反转时通过所述电晶体提供反向传导。
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US10396150B2 (en) 2019-08-27
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US20170243746A1 (en) 2017-08-24
US20170110535A1 (en) 2017-04-20
US9852910B2 (en) 2017-12-26
US9978831B2 (en) 2018-05-22
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