GB2596296A - Edge termination design for a vertical bipolar transistor and corresponding fabrication method - Google Patents

Edge termination design for a vertical bipolar transistor and corresponding fabrication method Download PDF

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Publication number
GB2596296A
GB2596296A GB2009514.7A GB202009514A GB2596296A GB 2596296 A GB2596296 A GB 2596296A GB 202009514 A GB202009514 A GB 202009514A GB 2596296 A GB2596296 A GB 2596296A
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semiconductor
region
power device
semiconductor layer
layer
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GB202009514D0 (en
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Udrea Florin
Pathirana Vasantha
Wa Chan Chun
Trajkovic Tanya
Udugampola Nishad
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Electric Power Research Institute of State Grid Shandong Electric Power Co Ltd
Global Energy Interconnection Research Institute
Global Energy Interconnection Res Institute Europe GmbH
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Electric Power Research Institute of State Grid Shandong Electric Power Co Ltd
Global Energy Interconnection Research Institute
Global Energy Interconnection Res Institute Europe GmbH
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Priority to GB2009514.7A priority Critical patent/GB2596296A/en
Publication of GB202009514D0 publication Critical patent/GB202009514D0/en
Publication of GB2596296A publication Critical patent/GB2596296A/en
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Abstract

A termination region of an Insulated Gate Bipolar Transistor has at least one floating n+ layer or region 100 formed in the n-buffer field stop layer 5 arranged above the p+ collector 4 and within the termination area. This layer can be continuous or segmented into islands. The layer has a doping concentration of a few orders of magnitude higher than that of the n-buffer region. The floating n+ layer or regions weaken the hole injection from the collector p+ around the termination area and improve the breakdown voltage and reduce current crowding effects.

Description

EDGE TERMINATION DESIGN FOR A VERTICAL BIPOLAR TRANSISTOR AND
CORRESPONDING FABRICATION METHOD
Field of the Disclosure
The present invention relates to a termination design of an IGBT which can improve dynamic ruggedness and reduce leakage current.
Background of the Disclosure
Insulated Gate Bipolar Transistors (IGBTs) are key components in high-voltage applications such as inverters and converters for railway, electric vehicles and power transmission systems. One essential part of a functional IGBT chip is its termination region which surrounds an inner active region designed to perform electrical operations. The purpose of a termination region is to relax the electric field near the edge of the active region, preventing premature breakdown of the chip. In an IGBT, hole injection is used to create high level plasma of electrons and holes in equilibrium within the drift region as to minimize the on-state resistance. However, hole injection also occurs in the termination area and at the boundary between the active region and the termination region. This is undesirable as it will lower the termination region breakdown, cause current crowding and eventually initiate premature breakdown. Moreover, the leakage current can be reduced if the hole injection in the termination area can be significantly lowered. Very high voltage IGBTs (>6.5kV), will suffer even more from these effects as its termination region is very large to sustain the required blocking voltage. At high temperatures, these undesired effects will be enhanced (parasitic hole injection) and therefore IGBTs are more prone to thermal destruction.
Fig. 1 shows an example of a cross-sectional view of an n-channel IGBT as in the prior art. The IGBT substrate includes a n-drift layer 6, a n-buffer layer 5 and a p+ layer 4 stacked from top to bottom. In the bottom surface of the substrate, the p+ layer is in contact with the collector electrode 13. Present on the top surface of the substrate, from left to right, is an active region 1, a transition region 2 and a termination region 3. The active region includes an array of IGBT cells each having a p-body layer 7 surrounding n+ 8 and p+ regions 10 which are connected to the emitter electrode or contact 12. An inherent pnp transistor is formed by the p+ collector, the n-drift and p-body. The gate electrode 9 together with the oxide layer 14 form a metal-oxide-semiconductor structure and it controls the base current to the pnp transistor. The transitional region usually includes a deeper p layer 15 and it is connected to the emitter contact. The termination region has a lowly doped p-type JTE implant 11 to spread the potential towards the die edge to prevent premature breakdown.
It is worth noting that the structures on top surface are for demonstration purpose only and can take any form based upon different techniques. For example, active region can use a planar cell design instead of trench cell. Also, for the termination region it can be field ring termination instead of JTE termination.
When a sufficiently high potential is applied to the collector with respect to the emitter and gate is turned on, holes will be injected from the p+ layer in the active region as well as the termination region. Holes injected from the termination region will not significantly contribute to lowering the on-state resistance. Such hole injection will worsen current crowding in the termination region during high current and high voltage turn-off. This leads to local heating and impairs dynamic avalanche ruggedness. Furthermore, p+ in the termination region will increase the bipolar gain and negatively affects the leakage current and breakdown voltage, especially at high temperatures.
One prior-art solution to this is to lower the doping of the p+ layer in the termination region, as illustrated in Fig. 2. In this solution leakage current and current crowding can be improved with a p collector layer 20 having low doping in the termination region due to reduced bipolar gain. However, this arrangement has some drawbacks. The doping of the p+ injector layer in the active area is adjusted to give a good trade-off between on-state and switching speed. For fast devices the doping needs to be quite low and the collector contact becomes non-ohmic. Since the p-region in the active area has even lower doping, this means that the contact is highly non-ohmic towards Schottky. The control of the hole injection in this region is limited. Additionally, it is difficult to control the charge dose of a lowly doped region. Moreover, this design may increase the leakage if a Schottky contact is formed on the p collector layer.
Another prior-art solution is shown in Fig. 3, which has been proposed for a reverse conducting IGBT. In this solution the hole injection is alleviated in the termination region by having collector shorted segmented n+ regions 30 and p+ regions 4 in the termination area. In this case both the n+ and p+ regions are connected to the collector electrode 13. This however leads to potential snapback in the on-state characteristics of the IGBT. This is because before the pnp transistor is turned on the electron current flows in a unipolar manner through the n+ collector regions. Once the junctions between the p+ collector regions 4 and the n-buffer region 5 are forward-biased the current can flow in a bipolar conduction through the pnp transistor. The snapback occurs at the transition between the unipolar and bipolar conduction. The snapback could be more enhanced at very low ambient temperatures. The snapback is undesirable as it features a negative resistance which could introduce oscillations and undesirable harmonics during switching. The IGBT shown in this figure has snapback problems and additionally introduces a diode in the reverse conduction mode, which is not desirable for a non-reverse conducting IGBT design.
Fig. 4 shows a IGBT design with floating n+ islands 40 around the n-buffer region 5. In this solution n+ islands 40 are used to get a better trade-off between Von and turn-off, and hence the design was targeted for the active region. There is no differentiation between the injection efficiency of the collector junction in the active area and the termination region.
Fig. 5 shows that a better trade-off between Von and turn-off losses can be achieved in an IGBT structure where alternating p+/n regions 50, 51 are inserted between the n-buffer 5 and transparent p+ collector 4. The alternating p+ regions 51 are designed to provide high carrier injection efficiency under forward on-state conduction while the alternating n-regions 50 provide effective hole extraction during turn-off transient. As in the previous case, there is no differentiation between the injection efficiency of the collector junction in the active area and the termination region.
Summary
The present invention is defined by the independent claims. Preferred embodiments are defined in the dependent claims.
We herein describe a semiconductor power device comprising a semiconductor body having an active cell area, transition area and an edge termination area, wherein the semiconductor body has a top surface where an emitter electrode is formed and a bottom surface where a collector electrode is formed and wherein the semiconductor body further comprises a first semiconductor layer of first conductivity type, with low doping concentration; a second semiconductor layer of first conductivity type with higher doping than first semiconductor layer; at least one semiconductor region of first conductivity type with higher doping than the second semiconductor layer, formed within the second semiconductor layer in the termination area and/or transition area; a third semiconductor layer of second conductivity type below the second semiconductor region; an electrode in contact with the third semiconductor layer; wherein the first semiconductor layer supports the largest fraction of the voltage during the blocking mode of the said semiconductor power device and wherein, the at least one semiconductor region is used to limit, block or partially block the carrier injection from the collector electrode into the first semiconductor layer within the termination area and/or the transition area, but leave substantially unaffected the carrier injection in the active area.
It will be understood that the active area (also called the active region) of the semiconductor device generally acts as an area where the transistor operation takes place between the emitter and collector electrodes. For example the current control, the switching of the current on and off occur in this region. In contrast, the termination area (also called the termination region) generally helps to relax the electric field near the edge of the active region and thereby improve the breakdown voltage of the device. The transition area (also called the transition region) provides a lateral separation between the active and termination areas.
It will also be appreciated that the term 'substantially unaffected' means the carrier injection does not noticeably change, reduce or improve from the collector to the emitter electrode in the active area.
Optionally the power device is an Insulated Gate Bipolar Transistor and further comprises a gate terminal, an insulated gate attached to a surface of a p-body region, a p+ contact region to the body region, an n+ emitter region in physical contact to the said insulated gate and wherein the emitter electrode contacts both the n+ emitter region and the p+ contact region and wherein the gate terminal controls the current flowing from the emitter region, through the inversion channel formed in the p-body region and the first semiconductor region.
In one embodiment the termination area comprises any combination of: junction termination extensions with one or multiple zones of second conductivity type, highly doped floating rings of second conductivity type, field plates and floating channel stopper of first conductivity type at the die edge.
The at least one semiconductor region configured to limit, block or partially block the carrier injection from the collector electrode into the first semiconductor layer may reside inside the first semiconductor layer, second semiconductor layer or third semiconductor layer.
The implant dose and energy for the at least one semiconductor region may be high enough to form a floating n+ layer that acts as a strong barrier hindering hole injection in the termination region, without being contacted to the collector electrode. That is to say that the at least one semiconductor region may be vertically spaced from the collector electrode such that they are not in direct contact.
In another embodiment, the at least one semiconductor region may be uninterrupted. This may lead to reduction of the bipolar gain at the termination region thereby reducing the leakage, increasing the breakdown voltage and relaxing the current crowding.
Alternatively the at least one semiconductor region may be segmented into equal segments. The width and gap between the segments are configured to control the bipolar gain in the termination area In a further alternative embodiment, the at least one semiconductor region may be partitioned into segments with their widths increased from the perimeter of the active region to the edge of the termination region. The spacing between the segments is set to achieve a smoother plasma transition (given by carrier injection) from the active region to the end of termination region.
According to this disclosure there is provided a manufacturing method for the termination region of the semiconductor device described above, the method comprising: implantation of impurities of the first conductivity type higher than the first semiconductor layer into the back surface of the first semiconductor layer; a second implantation of impurities of the first conductivity type into the second semiconductor layer via a photoresist mask defining the layout of the at least one semiconductor region; the dose and energy of the second implantation are higher than those of the first implantation; a third implantation of the second conductivity type into the surface of the second semiconductor layer.
Also described herein is a manufacturing method for the termination region of the semiconductor device described above, the method comprising. forming the third semiconductor layer from the substrate, the substrate having a second conductivity type; implantation of impurities of first conductivity type into the third semiconductor layer via a photoresist mask defining the layout of the at least one semiconductor region; epitaxial growth of a second semiconductor layer of a first conductivity type; and epitaxial growth of a first semiconductor layer of the first conductivity type.
Optionally the at least one semiconductor region may be formed during or after the formation of the first and/or second semiconductor layers.
Brief Description of the Drawings
Some preferred embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings, in which: FIG.1 shows schematically a cross-sectional view of an IGBT according to prior art, including an active region, a transition region and a termination region.
FIG.2 shows schematically a cross-sectional view of an IGBT according to prior art, where the collector p layer has a low doping in the termination region and high doping in the active region.
FIG.3 shows schematically a cross-sectional view of a RC-IGBT according to prior art, having shorted N+ and P+ at the collector.
FIG.4 shows schematically a cross-sectional view of an IGBT according to prior art, having buried n+ islands to improve the Von vs. Eoff trade-off in the active region.
FIG.5 shows schematically a cross-sectional view of an IGBT according to prior art, having alternating p+/n regions on top of a very thin transparent P+ collector.
FIG.6 shows schematically a cross-sectional view of an IGBT according to the first embodiment of the current invention, having a floating n+ layer uninterrupted in the termination and transition regions.
FIG.7 shows off-state characteristics according to the prior art and current invention. The leakage current is reduced, and breakdown voltage is increased in the proposed structure.
FIG.8 compares current crowding effects between the prior art IGBT and the IGBT according to the current invention. It shows how current crowding can be reduced using floating a n+ layer in the n-buffer.
FIG.9 shows schematically a cross-sectional view of an IGBT according to the second embodiment of the current invention, having a floating n+ layer segmented into portions of equal width. Depending on the width and the spacing of the floating n+ islands hole injection at the termination can be controlled.
FIG.10 shows schematically a cross-sectional view of an IGBT according to the current invention, having a floating n+ layer partitioned into portions with their widths increasing from the active region to the edge of the termination region. This design will give a gradual charge distribution from active region to the termination. This structure shows a single p-type JTE in the termination region.
FIG.11 shows schematically a cross-sectional view of an IGBT according to the current invention, having a floating n+ layer partitioned into portions with their widths increasing from the active region to the edge of the termination region. This design will give a gradual charge distribution from active region to the termination. This structure shows floating p-rings in the termination region.
FIG.12 depicts possible fabrication processes for the current invention.
Detailed Description of the Preferred Embodiments
Fig. 6 shows a semiconductor power device in which the termination region 3 features a highly doped floating n+ layer 100 in the n-buffer layer 5. Several features of Fig. 6 correspond to features shown in Figs. 1-5, and the same reference numerals are used for these features. The floating n+ layer 100 has a doping value several orders of magnitude higher than that of the n-buffer layer 5, thereby acting as a strong barrier impeding hole injection in the termination area 3.
This may lower bipolar gain around the termination region 3 and improve the breakdown voltage and lower the leakage current.
The injection efficiency in the active area may be governed by the doping and/or the thickness of the p+ collector layer 4. The injection efficiency in the termination layer may be significantly smaller and may be governed by one or both of the doping of the floating n+ layer 100 and the distance between n+ regions Of more than one n+ region 100 is provided).
The n+ floating barrier layer 100 is uninterrupted and can extend laterally up to the end of the transition region 2 as shown in Fig 6, or within the transition region 2 or stay only in the termination region 3. The skilled person will understand that the floating n+ layer 100 may reside anywhere in the n-buffer 5, n-drift 6 or the collector p+ layers 4, and that the position of the floating n+ layer 100 in Fig. 6 is merely an example.
Fig. 7 shows a graph of the leakage current I at the collector as the collector voltage V is varied. The semiconductor power device shown in Fig. 6 may have a lower collector leakage current and a higher breakdown voltage than prior art designs (for example, Fig. 1).
Fig. 8 shows a comparison of the effects of current crowding in an embodiment of the present invention and the prior art. Fig. 8(a) corresponds to the prior art shown in Fig. 1, while Fig. 8(b) corresponds to the embodiment shown in Fig. 6. In Fig. 8(b), due to the lower bipolar gain around the termination region, fewer carriers are injected from the p+ collector and current crowding at the emitter p+ contact at the top surface is reduced. Each of the effects of improved breakdown voltage, reduced leakage current and lower current crowding may improve the devices ruggedness and/or robustness to high voltage and high current switching events. This improvement may be particularly pronounced at high temperatures, up to the junction temperature, which is typically between about 125°C and about 200 °C.
In Fig. 9 the n+ floating layer is segmented uniformly, or otherwise segmented approximately or substantially uniformly to form n+ floating layer segments 100. By segmenting the n+ floating layer it is possible to control the collector p+ injection efficiency in the termination region 3 by varying the width and/or spacing between the n+ floating layer segments 100.
Fig. 10 shows an embodiment in which the n+ floating layer is segmented in a non-uniform manner. In this example, the width of the n+ layer segments 100 increases as the position of the segments move from the active region 1 towards the termination 3. By segmenting the n+ floating layer non-uniformly, the collector p+ injection efficiency in the termination region may be controlled by varying the width of the n+ floating layer segments 100 and/or by varying the spacing between the n+ floating layer segments 100. This structure allows a smoother transition of plasma from the active region 1 to the edge of termination region 3 and may improve the optimisation of the device. Thus in one or both of the transition region 2 and parts of the termination region 3 the distances between the n+ islands 100 may be larger to allow on-state current still to flow, while the distances between the n+ regions 100 may become smaller (gradually or otherwise) thereby obstructing the on-state current flow towards the die edge. This may also reduce or minimise the off-state leakage without impacting the on-state performance of the device.
It is important to note that the termination area 3 could be made of field rings, filed plates, junction termination extensions or any combination of these. A floating n+ channel stopper may be present at the edge of the termination. Figs. 1-10 described above generally show a simple junction termination extension (p JTE) with one zone. However, different zones with different doping levels could also be added.
Fig. 11 depicts a device that uses p-field rings 200 in the termination region 3. The p-ring fields may be formed with or from a Deep-p implant.
For completeness, we note that several features of Figs. 9-11 utilise the same reference numerals as Figs. 1-6.
Fig 12 shows examples of fabrication steps for producing a device with a floating n+ layer as described above.
Fig. 12(a) depicts an example of steps for forming the proposed structure with the wafer back side processing. The steps in this process may form one or more extra implant steps in the normal soft punch through (SAT) IGBT fabrication process. Prior to the back p+ collector implant, the backside of the wafer may be masked for the desired pattern and n+ dopants like Phosphorus or Arsenic can be implanted. Optionally, this step may implanting of the n+ dopants may occur immediately prior to the implanting of the back p+ collector. To form a buried n+ layer the implant energy and dose of the n+ dopants should be reasonably high. Typical doses (charge) are above about 1 10'2 cm-2 and more common doses are above about 1 1013 cm-2.
Fig. 12(b) shows an alternative fabrication process for a punch through (PT) or non-punch through (NPT) IGBT designs would be to do it at the epi growth stage that is a suitable fabrication process for a PT IGBT. The floating n+ implant can be introduced prior to the n-buffer growth step or prior to the n-drift growth step. Optionally this floating n+ implant may occur immediately prior to either of these steps. The floating n+ implant may be done through a mask. A single mask and a single n+ implant may be used for segmenting the n+ islands into different regions (i.e. floating islands or floating n+ segments as described above) with different shapes or distances between them. Alternatively, multiple masks and/or n+ implants may be used. The n+ implant may be made of Phosphorus or Arsenic, however the skilled person will understand that other materials may be used.
The skilled person will understand that the embodiments described above are not exhaustive and that the features of one embodiment may be combined with those of other embodiments.
References 1. Z. Chen et al., "A Balanced High Voltage IGBT Design with Ultra Dynamic Ruggedness and Area-efficient Edge Termination", Proceeding of the 25th ISPSD 2013, pp. 37-40 2. W. Zhang et al., "Increase of the Reliability of the Junction Terminations of Reverse-Conducting Insulated Gate Bipolar Transistor by Appropriate Backside Layout Design", IEEE electron device letters 2014, Vol. 35, No. 12, pp. 1281-1283 3. F. Udrea et al., "Semiconductor Device and Method for Forming the Same", Patent No. US7994569 B2, 2011 4. H. Yilmaz et al., "Vertical Power Transistor with Thin Bottom Emitter Layer and Dopants Implanted in Trenches in Shield Area and Termination Rings", Patent No. U59825128 B2, 2017 5. K. MA et al., "Novel Low Turn-Off Loss Trench-Gate FS-IGBT With a Hybrid p+/n Collector Structure", Journal of the Electron Devices Society 2019, Vol. 7, pp. 677-681

Claims (17)

  1. CLAIMS: 1 A vertical bipolar semiconductor power device comprising an active area, a transition area and a termination area, wherein the active area, the transition area and the termination area are laterally adjacent to one another, and wherein the transition area is located between the active area and the termination area, and further comprising a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type below the first semiconductor layer, wherein a doping concentration of the second semiconductor layer is greater than a doping concentration of the first semiconductor layer; a third semiconductor layer of a second conductivity type below the second semiconductor layer; a first electrode located on a first surface; a second electrode located on a second surface vertically opposed to the first electrode, the second electrode being operatively connected to the third semiconductor layer; and at least one semiconductor region of the first conductivity type, wherein a doping concentration of the at least one semiconductor region is greater than the doping concentration of the second semiconductor layer, and wherein the at least one semiconductor region is configured to reduce carrier injection from the second electrode to the first electrode within the termination area, and wherein the at least one semiconductor region is configured to keep the carrier injection substantially unaffected from the second electrode to the first electrode in the active area.
  2. 2. The semiconductor power device according to claim 1, wherein the at least one semiconductor region is located in at least one of the first, second and third semiconductor layers.
  3. 3 The semiconductor power device according to claim 1, wherein the at least one semiconductor region is located in at least one of the termination area and the transition area.
  4. 4 The semiconductor power device according to claim 3, wherein the at least one semiconductor region is a floating layer, wherein the floating layer is configured to reduce hole injection from the second electrode in the termination area, wherein the floating layer is vertically spaced from the second electrode.
  5. The semiconductor power device according to any preceding claim, wherein the vertical bipolar semiconductor power device is an Insulated Gate Bipolar Transistor (IGBT), the vertical bipolar semiconductor power device further comprising: a gate terminal; a second semiconductor region of the second conductivity type located in the first semiconductor layer; an insulated gate electrode operatively connected to the gate terminal; a contact region of the second conductivity type operatively connected to the second semiconductor region; and an emitter region of the first conductivity type adjacent to said insulated gate electrode; wherein the first electrode is operatively connected to both the emitter region and the contact region, and wherein the gate terminal is configured to control a current flowing from the emitter region through an inversion channel formed in the second semiconductor region and the first semiconductor layer.
  6. 6 The semiconductor power device according to any preceding claim, further comprising one or more junction termination extensions of the second conductivity type located in the termination area.
  7. 7. The semiconductor power device according to any preceding claim, further comprising one or more highly doped floating rings of the second conductivity type located in the termination area.
  8. 8. The semiconductor power device according to any preceding claim, further comprising one or more field plates located in the termination area.
  9. 9 The semiconductor power device according to any preceding claim, further comprising a floating channel stopper of the first conductivity type at a die edge of the semiconductor power device located in the termination area.
  10. The semiconductor power device according to any preceding claim, wherein the at least one semiconductor region is a single continuous semiconductor layer.
  11. 11. The semiconductor power device according to any one of claims 1 to 9, wherein the at least one semiconductor region comprises a plurality of discrete semiconductor regions that are laterally separated.
  12. 12. The semiconductor power device according to claim 11, wherein the plurality of discrete semiconductor regions have approximately equal dimensions.
  13. 13. The semiconductor power device according to claim 12, wherein the plurality of discrete semiconductor regions have non-uniform dimensions.
  14. 14. The semiconductor power device according to claim 13, wherein a width of the plurality of discrete semiconductor regions increases as the discrete semiconductor regions move from the transition area to the termination area.
  15. 15. A method of manufacturing a semiconductor power device according to any preceding claim, the method comprising: forming the second semiconductor layer over the first semiconductor layer; implanting the at least one semiconductor region into the second semiconductor region via a photoresist mask; and forming the third semiconductor layer over the second semiconductor layer.
  16. 16. A method of manufacturing a semiconductor power device according to any one of claims 1 to 14, the method comprising: implanting the at least one semiconductor region into a surface of the third semiconductor layer via a photoresist mask; forming the second semiconductor layer over the surface of the third semiconductor layer via epitaxial growth; and forming the first semiconductor layer over the second semiconductor layer via epitaxial growth.
  17. 17. The method according to claim 16, further comprising implanting the at least one semiconductor region after forming the second semiconductor layer and before forming the first semiconductor layer.
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US20230104778A1 (en) * 2020-11-17 2023-04-06 Hamza Yilmaz High voltage edge termination structure for power semiconductor devices

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US20170110535A1 (en) * 2015-10-20 2017-04-20 Maxpower Semiconductor, Inc. Vertical power transistor with thin bottom emitter layer and dopants implanted in trenches in shield area and termination rings
US20170317075A1 (en) * 2016-05-02 2017-11-02 Hitachi Power Semiconductor Device, Ltd. Diode and power convertor using the same
EP3640996A1 (en) * 2018-10-15 2020-04-22 Infineon Technologies Austria AG Semiconductor device

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US20170110535A1 (en) * 2015-10-20 2017-04-20 Maxpower Semiconductor, Inc. Vertical power transistor with thin bottom emitter layer and dopants implanted in trenches in shield area and termination rings
US20170317075A1 (en) * 2016-05-02 2017-11-02 Hitachi Power Semiconductor Device, Ltd. Diode and power convertor using the same
EP3640996A1 (en) * 2018-10-15 2020-04-22 Infineon Technologies Austria AG Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230104778A1 (en) * 2020-11-17 2023-04-06 Hamza Yilmaz High voltage edge termination structure for power semiconductor devices
US12087831B2 (en) 2020-11-17 2024-09-10 Taiwan Semiconductor Co., Ltd. High voltage edge termination structure for power semiconductor devices and manufacturing method thereof

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