WO2024020720A1 - 拼接显示面板和显示装置 - Google Patents

拼接显示面板和显示装置 Download PDF

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Publication number
WO2024020720A1
WO2024020720A1 PCT/CN2022/107605 CN2022107605W WO2024020720A1 WO 2024020720 A1 WO2024020720 A1 WO 2024020720A1 CN 2022107605 W CN2022107605 W CN 2022107605W WO 2024020720 A1 WO2024020720 A1 WO 2024020720A1
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WIPO (PCT)
Prior art keywords
metal
chip
along
display
connections
Prior art date
Application number
PCT/CN2022/107605
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English (en)
French (fr)
Inventor
徐宸科
谢相伟
叶岩溪
Original Assignee
厦门市芯颖显示科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 厦门市芯颖显示科技有限公司 filed Critical 厦门市芯颖显示科技有限公司
Priority to CN202280002334.5A priority Critical patent/CN117769733A/zh
Priority to PCT/CN2022/107605 priority patent/WO2024020720A1/zh
Publication of WO2024020720A1 publication Critical patent/WO2024020720A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes

Definitions

  • the present application relates to the field of display technology, and in particular, to a spliced display panel and a display device.
  • splicing screens require that the gap between two adjacent screens after splicing is small.
  • splicing screens narrow the borders of the screens to form a modular single screen, and then pass the single screen through the mechanical components in a matrix style. They are arranged and spliced into a splicing screen, and the signal control of the splicing screen is achieved by controlling each single screen and then performing signal coordination between the single screens.
  • the present application provides a spliced display panel and a display device, aiming to solve at least one of the above problems.
  • the present application provides a spliced display panel, which includes a display area and a non-display area surrounding the display area.
  • the spliced display panel further includes: a cover plate with metal lines provided on the cover plate; A display substrate, a plurality of the display substrates are arranged on one side of the cover plate; a plurality of chip-on-chip films located in the non-display area, each of the chip-on-chip films is provided correspondingly to a plurality of the display substrates, A plurality of the chip-on-chip films and a plurality of the display substrates are arranged on the same side of the cover plate; the metal wires are electrically connected to the chip-on-chip films in the non-display area, and the metal wires are on the The display area is electrically connected to the display substrate.
  • a plurality of the display substrates are arranged in an array along a first direction and a second direction, and the first direction is perpendicular to the second direction;
  • the display substrate includes a plurality of pixel units, A plurality of the pixel units are arranged corresponding to the metal lines, wherein each of the pixel units includes a plurality of sub-pixels;
  • the cover plate has a first center extending in the first direction and the second direction respectively. axis and the second central axis.
  • a plurality of the chip-on-chip films are disposed on opposite sides of the second central axis.
  • the metal lines include a plurality of metal connections, and the plurality of metal connections are arranged corresponding to a plurality of pixel units along the first direction; wherein, in the display area Each metal connection line is connected to two adjacent display substrates along the first direction, and one end of each metal connection line in the non-display area is connected to one display substrate along the first direction. , the other end is bound to one of the flip-chip films.
  • the metal wires include multiple groups of metal wires, and the multiple groups of metal wires are arranged along the first direction and arranged at intervals along the second direction; wherein, each group of the metal wires Metal connections are arranged corresponding to a plurality of pixel units along the first direction; each group of metal connections includes a plurality of sub-connections spaced apart from each other along the second direction, and the metal connections in the same group include One end of each sub-connection line along the first direction is connected to a different display substrate, and the other end is bound to the same chip-on-chip film.
  • a plurality of the chip-on-chip films are arranged around the cover plate.
  • the metal lines include a plurality of first metal connections and a plurality of second metal connections, and the plurality of first metal connections connect with a plurality of the pixels along the first direction. Units are arranged correspondingly, and a plurality of second metal connections are arranged correspondingly to a plurality of sub-pixels along the second direction; wherein each of the first metal connections in the display area is arranged along the first metal connection along the second direction.
  • each first metal connection in the non-display area is connected to one of the display substrates along the first direction, and the other end is connected to one of the On-chip film binding; each second metal connection in the display area connects two adjacent display substrates along the second direction, and each second metal connection in the non-display area One end of the two metal connections is connected to one of the display substrates along the second direction, and the other end is bound to one of the chip-on-chip films along the second direction.
  • the metal wires include multiple groups of first metal wires and multiple groups of second metal wires, and the multiple groups of first metal wires are arranged along the first direction and along the first direction. Arranged at intervals in two directions, multiple groups of the second metal connections are arranged along the second direction and arranged at intervals along the first direction; wherein, each group of the first metal connections is arranged along the first direction.
  • Each group of the second metal wires is arranged corresponding to a plurality of the pixel units, and each group of the second metal wires is arranged corresponding to a plurality of the sub-pixels along the second direction; each group of the first metal wires includes a group of the first metal wires along the second direction.
  • One end is bound to the same chip-on-chip film;
  • each group of second metal connections includes a plurality of second sub-connections spaced apart from each other along the first direction, and the second metal connections in the same group include One end of each second sub-connection along the second direction is connected to a different display substrate, and the other end is bound to the same chip-on-chip film.
  • an insulating layer is provided between multiple groups of the first metal connections and multiple groups of the second metal connections.
  • the display substrate further includes a driving substrate and an encapsulating glue layer disposed on the driving substrate.
  • Conductive balls are provided in the encapsulating glue layer, and both ends of the conductive balls are respectively connected to each other. the metal lines and the driving substrate.
  • the spliced display panel further includes a plurality of light-emitting devices, and the plurality of light-emitting devices are bound to the driving substrate through metal or anisotropic conductive adhesive films.
  • This application also provides a display device, including the above-mentioned splicing display panel.
  • multiple display substrates are provided in the display area and multiple flip-chip films are disposed in the non-display area, thereby avoiding the binding space required for the flip-chip films from causing splicing gaps in the display area;
  • Each chip-on-chip film is set correspondingly to multiple display substrates to avoid setting an independent chip-on-chip film for each display substrate, thereby reducing the number of chip-on-chip films required to control all display substrates on the spliced display panel.
  • the cost effect of the splicing screen thirdly, by setting metal lines on the cover plate to bridge the display substrate and the chip-on-chip film, the cost of collaborative devices can be eliminated, further reducing the cost of the splicing display panel.
  • Figure 1 is a schematic structural diagram of a splicing display panel provided by an embodiment of the present application.
  • Figure 2A is a schematic diagram of the wiring structure of a metal wire provided by an embodiment of the present application.
  • Figure 2B is a schematic diagram of the routing structure of another metal line provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of another splicing display panel provided by an embodiment of the present application.
  • Figure 4A is a schematic diagram of the wiring structure of a metal wire provided by an embodiment of the present application.
  • Figure 4B is a schematic diagram of the wiring structure of another metal line provided by an embodiment of the present application.
  • Figure 5A is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 5B is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • Figure 6 is a schematic cross-sectional structural diagram at D-D' in Figure 2A;
  • Figure 7A is a schematic cross-sectional structural diagram at A-A’ in Figure 2B;
  • Figure 7B is a schematic cross-sectional structural diagram at B-B' in Figure 2B;
  • Figure 7C is a schematic cross-sectional structural diagram at C-C' in Figure 2B.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • plurality means two or more than two, unless otherwise explicitly and specifically limited.
  • connection should be understood in a broad sense.
  • connection or integral connection; it can be mechanical connection, electrical connection or mutual communication; it can be direct connection, or indirect connection through an intermediary, it can be internal connection of two elements or interaction of two elements relation.
  • the term “above” or “below” a first feature on a second feature may include direct contact between the first and second features, or may also include the first and second features. Not in direct contact but through additional characteristic contact between them.
  • the terms “above”, “above” and “above” a first feature on a second feature include the first feature being directly above and diagonally above the second feature, or simply mean that the first feature is higher in level than the second feature.
  • “Below”, “under” and “under” the first feature is the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature is less horizontally than the second feature.
  • FIG. 1 is a schematic structural diagram of a splicing display panel provided by this application.
  • the spliced display panel 10 includes a display area AA and a non-display area NA.
  • the non-display area NA is arranged around the display area AA.
  • the spliced display panel 10 also includes a cover plate 11 , a plurality of display substrates 12 and a plurality of chip-on-chip films 13 .
  • a plurality of display substrates 12 are located in the display area AA, and a plurality of display substrates 12 are arranged on one side of the cover plate 11; a plurality of chip-on-chip films 13 are located in the non-display area NA, and each chip-on-chip film 13 corresponds to a plurality of display substrates 12 A plurality of chip-on-chip films 13 and a plurality of display substrates 12 are disposed on the same side of the cover plate 11 .
  • a plurality of chip-on-chip films 13 are arranged in the non-display area NA.
  • the binding space required for the chip-on-chip films 13 is avoided in the display area.
  • the splicing gap caused by AA; in the embodiment of the present application, each chip-on-chip film 13 is also provided correspondingly with multiple display substrates 12 to avoid that each display substrate 12 is provided with an independent chip-on-chip film 13, so that in the The number of chip-on-chip films 13 required to control all display substrates 12 on the splicing display panel 10 is reduced, thereby achieving the effect of reducing the cost of the splicing screen.
  • Figures 2A, 2B, 4A and 4B are schematic diagrams of routing structures of four metal lines provided by embodiments of the present application.
  • the metal wires 14/24/34/44 are electrically connected to the chip-on-chip film 13 in the non-display area NA.
  • the metal wires 14/24/ 34/44 are electrically connected to the display substrate 12 in the display area AA.
  • the display substrate 12 and the chip-on-chip film 13 are bridged by the metal wires 14/24/34/44 on the cover plate 11, and the metal wires 14/24/34/44 can be used to transmit signals, there is no need to set up additional Cooperative devices transmit signals between display substrates, thus eliminating the cost of cooperating devices and further reducing the cost of splicing display panels.
  • a plurality of display substrates 12 can be arranged in an array along a first direction and a second direction.
  • the first direction is perpendicular to the second direction.
  • the first direction corresponds to the x direction
  • the first direction corresponds to the x direction.
  • the two directions correspond to the y direction.
  • the display substrate 12 includes a plurality of pixel units 123 arranged corresponding to the metal lines 14 , where each pixel unit 123 includes a plurality of sub-pixels 1231 ; the cover plate 11 has extension directions respectively. are the first central axis L1 and the second central axis L2 in the x direction and y direction.
  • the sub-pixel 1231 may be any one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and a plurality of pixel units 123 are arranged in an array along the x direction and the y direction.
  • a plurality of chip-on-chip films 13 are disposed on opposite sides of the second central axis pair L2 .
  • the metal lines 14 include a plurality of metal connections for transmitting the first signal. 141.
  • a plurality of metal connections 141 are arranged corresponding to the plurality of pixel units 123 along the x direction.
  • Figure 6 is a schematic cross-sectional structural diagram of multiple metal connections 141 at D-D' in Figure 2A.
  • Each metal connection 141 in the display area AA connects adjacent ones along the x direction.
  • each metal connection 141 in the non-display area NA is connected to a display substrate 12 along the x direction, and the other end is bound to a flip-chip film 13 .
  • multiple display substrates 12 are connected in series using metal wires 14 to achieve signal bridging between the display substrates 12 .
  • the first signal may be a Data signal/Gate signal/other public signal.
  • the metal lines 24 include multiple sets of metal connections for transmitting the first signal. 241.
  • Multiple sets of metal connections 241 are arranged along the x direction and arranged at intervals along the y direction.
  • the multiple sets of metal connections 241 can be further configured as Distributed symmetrically about the second central axis L2.
  • Each group of metal connections 241 is arranged corresponding to a plurality of pixel units 123 along the x direction.
  • Each group of metal connections 241 includes a plurality of sub-connections 2411 spaced apart from each other along the y direction.
  • Figures 7A to 7C are A-A' and B-B in Figure 2B respectively.
  • One end of each sub-connection 2411 in the same group of metal connections 241 along the x direction is connected to a different display substrate 12 respectively, and the other end is connected to the same Flip chip 13 binding.
  • the first signal may be a Data signal/Gate signal/other public signal.
  • FIG. 3 is a schematic structural diagram of another spliced display panel provided by an embodiment of the present application, in which a plurality of chip-on-chip films are disposed around the cover 11 .
  • the metal lines 34 include a plurality of first metal connections 341 for transmitting first signals and a plurality of first metal connections 341 for transmitting first signals.
  • a plurality of first metal connections 341 are arranged corresponding to the plurality of pixel units 123 along the x direction.
  • a plurality of second metal connections 342 are connected to the plurality of sub-pixels along the y direction. 1231 corresponding settings.
  • each first metal connection 341 in the display area AA connects two adjacent display substrates 12 along the x direction, and one end of each first metal connection 341 in the non-display area NA connects to a display along the x direction.
  • the other end of the substrate 12 is bound to a chip-on-chip film 13;
  • each second metal connection 342 in the display area NA connects two adjacent display substrates 12 along the y direction, and each second metal connection 342 in the non-display area NA
  • One end of the metal connection 342 is connected to a display substrate 12 along the y direction, and the other end is bound to a chip-on-chip film 13 along the y direction.
  • the first signal may be a Data signal/Gate signal/other public signal
  • the second signal may be a Gate signal/Data signal/other public signal that is different from the first signal.
  • the metal lines 44 include multiple sets of first metal connections 441 for transmitting first signals and multiple sets of first metal connections 441 for transmitting first signals.
  • a set of second metal connections 442 for transmitting the second signal a plurality of sets of first metal connections 441 arranged along the x direction and spaced apart along the y direction, a plurality of sets of second metal connections 442 arranged along the y direction and arranged along the x direction.
  • an insulating layer is provided between the plurality of first metal connections 441 and the plurality of second metal connections 442 to prevent short circuits between the first metal connections 441 and the second metal connections 442, resulting in signal Crosstalk occurs in transmission.
  • the plurality of sets of first metal connections 441 can be further Disposed to be symmetrically distributed about the second central axis L2, the plurality of sets of second metal wires 442 may be further configured to be symmetrically distributed about the first central axis L1.
  • Each group of first metal connections 441 is arranged corresponding to the plurality of pixel units 123 along the x direction, and each group of second metal connections 442 is arranged corresponding to the plurality of sub-pixels 1231 along the y direction.
  • Each group of first metal connections 441 includes a plurality of first sub-connections 4411 spaced apart from each other along the y direction. One end of each first sub-connection 4411 in the same group of first metal connections 441 along the x direction is connected to a different The other end of the display substrate 12 is bound to the same chip-on-chip film 13 .
  • Each group of second metal connections 442 includes a plurality of second sub-connections 4421 spaced apart from each other along the x-direction. One end of each second sub-connection 4421 in the same group of second metal connections 442 along the y-direction is respectively connected to a different The other end of the display substrate 12 is bound to the same chip-on-chip film 13 .
  • first metal connections 441 in the same group can be used to connect multiple display substrates 12 in parallel along the x direction
  • multiple second metal connections 442 in the same group can be used to connect multiple display substrates 12 in parallel.
  • the display substrates 12 are connected in parallel along the y direction to achieve signal bridging between all display substrates 12 and the chip-on-chip film 13 . Since the first metal connection 441 and the second metal connection 442 intersect when multiple display substrates 12 are connected in parallel, in the embodiment of the present application, the first metal connection 441 and the second metal connection 442 are respectively provided.
  • the first signal may be a Data signal/Gate signal/other public signals
  • the second signal may be a Gate signal/Data signal/other public signals.
  • each chip can be further utilized.
  • the pixel units 123 are wired in the space distributed in the x direction and the y direction. When the wiring space is increased, the splicing space is also increased, which is conducive to splicing more display substrates 12 and achieving a larger display area.
  • FIG. 5A and FIG. 5B are respectively schematic cross-sectional structural diagrams of two display substrates.
  • the display substrate 12 includes a driving substrate and an encapsulant layer 124 provided on the driving substrate.
  • a plurality of light-emitting devices 20 are provided.
  • conductive balls 125 are provided in the encapsulation glue layer 124 .
  • the plurality of light-emitting devices 20 correspond to the plurality of sub-pixels 1231 on a one-to-one basis.
  • two ends of the conductive ball 125 are respectively connected to the metal wire 14 and the driving substrate.
  • the driving substrate includes a substrate 121, a thin film transistor layer 122, and the thin film transistor layer 122 and a plurality of light emitting devices 20 are sequentially arranged on the substrate 121.
  • the encapsulant layer 124 is located between the cover plate 11 and the thin film transistor layer 122 , and is distributed around the display substrate 12 .
  • a plurality of light-emitting devices 20 can be bound to the driving substrate through the anisotropic conductive adhesive film 126 and be electrically connected to the thin film transistor layer 122 .
  • a plurality of light-emitting devices 20 may be bonded to a plurality of pixel electrodes 127 of the driving substrate through metal.
  • the light-emitting device 20 can be any one of a red light-emitting device, a green light-emitting device, and a blue light-emitting device.
  • the conductive ball 125 can be a gold ball (Au Ball) or other connecting block with conductive function.
  • the encapsulating glue 124 is made of It is one of silicone, ethylene-vinyl acetate copolymer, polymethylmethacrylate, epoxy resin or fluororesin. The encapsulating glue 124 is specifically used to adhere and fix the display substrate 12 and the cover plate 11 .
  • the conductive balls 125 are distributed on each corresponding display substrate 12.
  • the positions can be exactly the same.
  • the conductive ball 125 is in each sub-connection 2411/first sub-connection 4411/ The positions distributed on the second sub-connections 4421 connecting different display substrates 12 are shifted from each other to avoid disorder in signal transmission between the display substrates 12 .
  • An embodiment of the present application also provides a display device (not shown in the figure), including the spliced display panel 10 as described above.

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请提供一种拼接显示面板和显示装置，拼接显示面板包括显示区和非显示区，其还包括盖板、多个显示基板以及多个覆晶薄膜。通过在显示区设置多个显示基板，将多个覆晶薄膜设置在非显示区，避免在显示区带来拼接缝隙；将每个覆晶薄膜与多个显示基板对应设置，在盖板上设置金属线桥接显示基板和覆晶薄膜，以降低制造成本。

Description

拼接显示面板和显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种拼接显示面板和显示装置。
 背景技术
在相关技术中，拼接屏要求拼接后的相邻两块屏幕的缝隙较小，目前拼接屏都是把屏幕的边框做窄形成模块化的单屏，再将单屏通过机构件以矩阵式的排列拼接成拼接屏，而拼接屏的信号控制是通过控制每一个单屏，然后在单屏间再进行信号协同来实现。
然而，控制每一个单屏需要利用绑定在单屏的COF（Chip On Film），在多个单屏拼接后形成的大屏后，拼接屏中的COF的数量过多，单屏与单屏之间的协同器件也增多，这导致拼接屏的成本过高。另外，COF的存在需要每个单屏上具有一定的绑定空间，这使得消除相邻两块单屏之间的缝隙的技术存在瓶颈。
 技术问题
本申请提供一种拼接显示面板和显示装置，旨在解决上述问题中的至少之一。
 技术解决方案
本申请提供一种拼接显示面板，包括显示区和围绕所述显示区的非显示区，所述拼接显示面板还包括：盖板，所述盖板上设置金属线；位于所述显示区的多个显示基板，多个所述显示基板设置在所述盖板的一侧；位于所述非显示区的多个覆晶薄膜，每个所述覆晶薄膜与多个所述显示基板对应设置，多个所述覆晶薄膜和多个所述显示基板设置在所述盖板的同侧；所述金属线在所述非显示区与所述覆晶薄膜电连接，所述金属线在所述显示区与所述显示基板电连接。
在本申请一些实施例中，多个所述显示基板沿第一方向和第二方向阵列拼接排布，所述第一方向与所述第二方向垂直；所述显示基板包括多个像素单元，多个所述像素单元与所述金属线对应设置，其中每个所述像素单元包括多个子像素；所述盖板具有延伸方向分别为所述第一方向和所述第二方向的第一中轴线和第二中轴线。
在本申请一些实施例中，多个所述覆晶薄膜设置在所述第二中轴线的相对两侧。
在本申请一些实施例中，所述金属线包括多条金属连线，多条所述金属连线沿所述第一方向与多个所述像素单元对应设置；其中，在所述显示区的每条所述金属连线沿所述第一方向连接相邻的两个显示基板，在所述非显示区的每条所述金属连线沿所述第一方向的一端连接一个所述显示基板，另一端与一个所述覆晶薄膜绑定。
在本申请一些实施例中，所述金属线包括多组金属连线，多组所述金属连线沿所述第一方向设置且沿所述第二方向间隔排布；其中，每组所述金属连线沿所述第一方向与多个所述像素单元对应设置；每组所述金属连线包括沿所述第二方向相互间隔的多条子连线，同组所述金属连线中的每条所述子连线沿所述第一方向的一端分别连接不同的所述显示基板，另一端与同一个所述覆晶薄膜绑定。
在本申请一些实施例中，多个所述覆晶薄膜设置在所述盖板的四周。
在本申请一些实施例中，所述金属线包括多条第一金属连线和多条第二金属连线，多条所述第一金属连线沿所述第一方向与多个所述像素单元对应设置，多条所述第二金属连线沿所述第二方向与多个所述子像素对应设置；其中，在所述显示区的每条所述第一金属连线沿所述第一方向连接相邻的两个所述显示基板，在所述非显示区的每条所述第一金属连线的一端沿所述第一方向连接一个所述显示基板，另一端与一个所述覆晶薄膜绑定；在所述显示区的每条所述第二金属连线沿所述第二方向连接相邻的两个所述显示基板，在所述非显示区的每条所述第二金属连线的一端沿所述第二方向连接一个所述显示基板，另一端沿所述第二方向与一个所述覆晶薄膜绑定。
在本申请一些实施例中，所述金属线包括多组第一金属连线和多组第二金属连线，多组所述第一金属连线沿所述第一方向设置且沿所述第二方向间隔排布，多组所述第二金属连线沿所述第二方向设置且沿所述第一方向间隔排布；其中，每组所述第一金属连线沿所述第一方向与多个所述像素单元对应设置，每组所述第二金属连线沿所述第二方向与多个所述子像素对应设置；每组所述第一金属连线包括沿所述第二方向相互间隔的多条第一子连线，同组所述第一金属连线中的每条所述第一子连线沿所述第一方向的一端分别连接不同的所述显示基板，另一端与同一个所述覆晶薄膜绑定；每组所述第二金属连线包括沿所述第一方向相互间隔的多条第二子连线，同组所述第二金属连线中的每条所述第二子连线沿所述第二方向的一端分别连接不同的所述显示基板，另一端与同一个所述覆晶薄膜绑定。
在本申请一些实施例中，多组所述第一金属连线和多组所述第二金属连线之间设置有绝缘层。
在本申请一些实施例中，所述显示基板还包括驱动基板和设置在所述驱动基板上的封装胶层，所述封装胶层中设置有导电球，所述导电球的两端分别连接所述金属线和所述驱动基板。
在本申请一些实施例中，所述拼接显示面板还包括多个发光器件，多个所述发光器件通过金属或者异方性导电胶膜绑定在所述驱动基板上。
本申请还提供一种显示装置，包括如上述所述的拼接显示面板。
 有益效果
本申请第一方面通过在显示区设置多个显示基板，将多个覆晶薄膜设置在非显示区，从而避免覆晶薄膜所需的绑定空间在显示区带来拼接缝隙；第二方面通过将每个覆晶薄膜与多个显示基板对应设置，以避免对每个显示基板均设置独立的覆晶薄膜，从而在降低控制拼接显示面板上所有显示基板所需覆晶薄膜的数量，达到降低拼接屏成本的效果；第三方面通过在盖板上设置金属线实现显示基板和覆晶薄膜的桥接，因此可以省去协同器件所带来的成本，进一步降低拼接显示面板的成本。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种拼接显示面板的结构示意图；
图2A是本申请实施例提供的一种金属线的走线结构示意图；
图2B是本申请实施例提供的另一种金属线的走线结构示意图；
图3是本申请实施例提供的另一种拼接显示面板的结构示意图；
图4A是本申请实施例提供的一种金属线的走线结构示意图；
图4B是本申请实施例提供的另一种金属线的走线结构示意图；
图5A是本申请实施例提供的一种显示面板的结构示意图；
图5B是本申请实施例提供的另一种显示面板的结构示意图；
图6是图2A中D-D’处的剖面结构示意图；
图7A是图2B中A-A’处的剖面结构示意图；
图7B是图2B中B-B’处的剖面结构示意图；
图7C是图2B中C-C’处的剖面结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参阅图1，图1是本申请提供的一种拼接显示面板的结构示意图。如图1所示，该拼接显示面板10包括显示区AA和非显示区NA，非显示区NA围绕于显示区AA设置。拼接显示面板10还包括盖板11、多个显示基板12以及多个覆晶薄膜13。其中，多个显示基板12位于显示区AA，多个显示基板12设置在盖板11一侧；多个覆晶薄膜13位于非显示区NA，每个覆晶薄膜13与多个显示基板12对应设置，多个覆晶薄膜13和多个显示基板12设置在盖板11的同侧。
在本申请实施例中，将多个覆晶薄膜13设置在非显示区NA，通过将多个覆晶薄膜13设置在非显示区NA，从而避免覆晶薄膜13所需绑定空间在显示区AA所带来的拼接缝隙；在本申请实施例中，还将每个覆晶薄膜13与多个显示基板12对应设置，以避免每个显示基板12均设置独立的覆晶薄膜13，从而在降低控制拼接显示面板10上所有显示基板12所需覆晶薄膜13的数量，达到降低拼接屏成本的效果。
请参阅图2A、图2B、图4A和图4B，图2A、图2B、图4A和图4B是本申请实施例提供的四种金属线的走线结构示意图，如图2A、图2B、图4A和图4B所示，盖板11上设置金属线14/24/34/44，金属线14/24/34/44在非显示区NA与覆晶薄膜13电连接，金属线14/24/34/44在显示区AA与显示基板12电连接。由于在盖板11上通过金属线14/24/34/44实现显示基板12和覆晶薄膜13的桥接，而金属线14/24/34/44可以用于传输信号，从而不需要设置额外的协同器件在显示基板间传输信号，因此可以省去协同器件所带来的成本，进一步降低拼接显示面板的成本。
请继续参阅图1，其中，多个显示基板12可以沿第一方向和第二方向阵列拼接排布，第一方向与第二方向垂直，在图1中该第一方向对应x方向，该第二方向对应y方向。如图2A和图2B所示，显示基板12包括多个像素单元123，多个像素单元123与金属线14对应设置，其中每个像素单元123包括多个子像素1231；盖板11具有延伸方向分别为x方向和y方向的第一中轴线L1和第二中轴线L2。可选地，子像素1231可以是红色子像素、绿色子像素以及蓝色子像素中任意一种，多个像素单元123沿x方向和y方向阵列排布。
在图1对应的一种实施例中，多个覆晶薄膜13设置在第二中轴线对L2的相对两侧。
在一种实施例中，当多个覆晶薄膜13设置在第二中轴线对L2的相对两侧时，如图2A所示，金属线14包括多条用于传输第一信号的金属连线141，多条金属连线141沿x方向与多个像素单元123对应设置。其中，请结合图2A参阅图6，图6是图2A中D-D’处的多条金属连线141的剖面结构示意图，在显示区AA的每条金属连线141沿x方向连接相邻的两个显示基板12，在非显示区NA的每条金属连线141沿x方向的一端连接一个显示基板12，另一端与一个覆晶薄膜13绑定。在图2A对应的实施例中，利用金属线14将多个显示基板12进行串联，以实现显示基板12之间信号的桥接。可选地，该第一信号可以是Data信号/Gate信号/其他公共信号。
在另一种实施例中，当多个覆晶薄膜13设置在第二中轴线L2的相对两侧时，如图2B所示，金属线24包括多组用于传输第一信号的金属连线241，多组金属连线241沿x方向设置且沿y方向间隔排布。可选地，根据显示基板12的拼接方式，当沿x方向和y方向拼接的显示基板12的数量均为偶数时，如4*6的拼接方式时，多组金属连线241可以进一步设置为关于第二中轴线L2对称分布。
其中，每组金属连线241沿x方向与多个像素单元123对应设置。每组金属连线241包括沿y方向相互间隔的多条子连线2411，请结合图2B参阅图7A至7C，图7A、图7B和图7C分别是图2B中A-A’、B-B’和C-C’处的多条金属连线141的剖面结构示意图，同组金属连线241中的每条子连线2411沿x方向的一端分别连接不同的显示基板12，另一端与同一个覆晶薄膜13绑定。
在图2B对应的实施例中，由于同组金属连线241中的每条子连线2411沿x方向的一端分别连接不同的显示基板12，另一端与同一个覆晶薄膜13绑定，以实现显示基板12与覆晶薄膜13之间信号的桥接。可选地，该第一信号可以是Data信号/Gate信号/其他公共信号。
请参阅图3，图3是本申请实施例提供的另一种拼接显示面板的结构示意图，其中，多个覆晶薄膜设置在盖板11的四周。
在一种实施例中，当多个覆晶薄膜13设置在盖板11的四周时，如图4A所示，金属线34包括多条用于传输第一信号的第一金属连线341和多条用于传输第二信号的第二金属连线342，多条第一金属连线341沿x方向与多个像素单元123对应设置，多条第二金属连线342沿y方向与多个子像素1231对应设置。其中，在显示区AA的每条第一金属连线341沿x方向连接相邻的两个显示基板12，在非显示区NA的每条第一金属连线341的一端沿x方向连接一个显示基板12，另一端与一个覆晶薄膜13绑定；在显示区NA的每条第二金属连线342沿y方向连接相邻的两个显示基板12，在非显示区NA的每条第二金属连线342的一端沿y方向连接一个显示基板12，另一端沿y方向与一个覆晶薄膜13绑定。
在图4A对应的实施例中，利用金属线34将多个显示基板12进行串联，以实现显示基板12之间信号的桥接，并且由于第一金属连线341和第二金属连线342分别沿不同的方向串联相邻的两个显示基板12，因此在显示区AA，第一金属连线341和第二金属连线342不存在交叉，从而第一金属连线341和第二金属连线342可以设置在位于金属线的同一层中，从而减少第一金属连线341和第二金属连线342之间的电容电阻负载效应。可选地，该第一信号可以是Data信号/Gate信号/其他公共信号，该第二信号可以是Gate信号/Data信号/其他公共信号中不同于第一信号的一种。
在另一种实施例中，当多个覆晶薄膜设置在盖板11的四周时，如图4B所示，金属线44包括多组用于传输第一信号的第一金属连线441和多组用于传输第二信号的第二金属连线442，多组第一金属连线441沿x方向设置且沿y方向间隔排布，多组第二金属连线442沿y方向设置且沿x方向间隔排布。具体地，多组第一金属连线441与多组第二金属连线442之间设置有绝缘层，以避免第一金属连线441与第二金属连线442之间出现短接，导致信号传输出现串扰。可选地，根据显示基板12的拼接方式，当沿x方向和y方向拼接的显示基板12的数量均为偶数时，如4*6的拼接方式时，多组第一金属连线441可进一步设置为关于第二中轴线L2对称分布，多组第二金属连线442可进一步设置为关于第一中轴线L1对称分布。
其中，每组第一金属连线441沿x方向与多个像素单元123对应设置，每组第二金属连线442沿y方向与多个子像素1231对应设置。每组第一金属连线441包括沿y方向相互间隔的多条第一子连线4411，同组第一金属连线441中的每条第一子连线4411沿x方向的一端分别连接不同的显示基板12，另一端与同一个覆晶薄膜13绑定。每组第二金属连线442包括沿x方向相互间隔的多条第二子连线4421，同组第二金属连线442中的每条第二子连线4421沿y方向的一端分别连接不同的显示基板12，另一端与同一个覆晶薄膜13绑定。
在图4B对应的实施例中，利用同组的多条第一金属连线441可以将多个显示基板12沿x方向进行并联，利用同组的多条第二金属连线442可以将多个显示基板12沿y方向进行并联，以实现所有显示基板12与覆晶薄膜13之间信号的桥接。由于第一金属连线441和第二金属连线442在并联多个显示基板12时，存在交叉，在本申请实施例中，通过将第一金属连线441和第二金属连线442分别设置在不同层，并利用绝缘层将不同层之间进行隔开，从而避免第一金属连线441和第二金属连线442之间出现短接的现象。可选地，该第一信号可以是Data信号/Gate信号/其他公共信号，该第二信号可以是Gate信号/Data信号/其他公共信号。
在图3、图4A和图4B对应的实施例中，通过多个覆晶薄膜13布置在盖板11的四周，相较于图1、图2A和图2B对应的实施例，可以进一步利用每个像素单元123在x方向和y方向分布的空间进行布线，在布线空间得到提升时，拼接空间也得到增大，有利于拼接更多的显示基板12，实现更大的显示面积。
请参阅图5A和图5B，图5A和图5B分别是两种显示基板的剖面结构示意图，其中，显示基板12包括驱动基板和设置在驱动基板上的封装胶层124，多个发光器件20设置在驱动基板上，封装胶层124中设置有导电球125。在显示基板12中，多个发光器件20与多个子像素1231一一对应。在拼接显示面板10中，导电球125的两端分别连接金属线14和驱动基板。驱动基板包括衬底121、薄膜晶体管层122，薄膜晶体管层122和多个发光器件20依次设置在衬底121上。在拼接显示面板10中，封装胶层124位于盖板11和薄膜晶体管层122之间，且分布于显示基板12的四周。
在一种实施例中，如图5A所示，多个发光器件20可通过异方性导电胶膜126绑定在驱动基板上且与薄膜晶体管层122电性连接。在另一种实施例中，如图5B所示，多个发光器件20可通过金属绑定在驱动基板的多个像素电极127上。
可选地，发光器件20可以是红色发光器件、绿色发光器件以及蓝色发光器件中任意一种，导电球125可以是金球（Au Ball）或者其他具有导电功能的连接块，封装胶124材质为硅胶、乙烯-醋酸乙烯共聚物、聚甲基丙烯酸甲酯、环氧树脂或氟树脂中的一种。封装胶124具体用于将显示基板12与盖板11粘接固定。
在图2A或图4A对应的实施例中，由于通过金属线14/34串联多个显示基板12以及串联显示基板12与覆晶薄膜13，因此，对应的每个显示基板12上导电球125分布的位置可以完全相同。在图2B或图4B对应的实施例中，由于通过金属线24/44并联多个显示基板12与覆晶薄膜13，因此，导电球125在每条子连线2411/第一子连线4411/第二子连线4421连接不同的显示基板12上所分布的位置相互错位，以避免信号的在显示基板12之间的传输发生紊乱。
本申请实施例还提供一种显示装置（图中未示出），包括如上述的拼接显示面板10。
除上述实施例外，本申请还可以有其他实施方式。凡采用等同替换或等效替换形成的技术方案，均落在本申请要求的保护范围。
综上所述，虽然本申请已将优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (12)

  1. 一种拼接显示面板，其包括显示区和围绕所述显示区的非显示区，所述拼接显示面板还包括：
    盖板，所述盖板上设置金属线；
    位于所述显示区的多个显示基板，多个所述显示基板设置在所述盖板的一侧；
    位于所述非显示区的多个覆晶薄膜，每个所述覆晶薄膜与多个所述显示基板对应设置，多个所述覆晶薄膜和多个所述显示基板设置在所述盖板的同侧；
    所述金属线在所述非显示区与所述覆晶薄膜电连接，所述金属线在所述显示区与所述显示基板电连接。
  2. 根据权利要求1所述的拼接显示面板，其中，多个所述显示基板沿第一方向和第二方向阵列拼接排布，所述第一方向与所述第二方向垂直；所述显示基板包括多个像素单元，多个所述像素单元与所述金属线对应设置，其中每个所述像素单元包括多个子像素；所述盖板具有延伸方向分别为所述第一方向和所述第二方向的第一中轴线和第二中轴线。
  3. 根据权利要求2所述的拼接显示面板，其中，多个所述覆晶薄膜设置在所述第二中轴线的相对两侧。
  4. 根据权利要求3所述的拼接显示面板，其中，所述金属线包括多条金属连线，多条所述金属连线沿所述第一方向与多个所述像素单元对应设置；
    其中，在所述显示区的每条所述金属连线沿所述第一方向连接相邻的两个显示基板，在所述非显示区的每条所述金属连线沿所述第一方向的一端连接一个所述显示基板，另一端与一个所述覆晶薄膜绑定。
  5. 根据权利要求3所述的拼接显示面板，其中，所述金属线包括多组金属连线，多组所述金属连线沿所述第一方向设置且沿所述第二方向间隔排布；
    其中，每组所述金属连线沿所述第一方向与多个所述像素单元对应设置；每组所述金属连线包括沿所述第二方向相互间隔的多条子连线，同组所述金属连线中的每条所述子连线沿所述第一方向的一端分别连接不同的所述显示基板，另一端与同一个所述覆晶薄膜绑定。
  6. 根据权利要求2所述的拼接显示面板，其中，多个所述覆晶薄膜设置在所述盖板的四周。
  7. 根据权利要求6所述的拼接显示面板，其中，所述金属线包括多条第一金属连线和多条第二金属连线，多条所述第一金属连线沿所述第一方向与多个所述像素单元对应设置，多条所述第二金属连线沿所述第二方向与多个所述子像素对应设置；
    其中，在所述显示区的每条所述第一金属连线沿所述第一方向连接相邻的两个所述显示基板，在所述非显示区的每条所述第一金属连线的一端沿所述第一方向连接一个所述显示基板，另一端与一个所述覆晶薄膜绑定；在所述显示区的每条所述第二金属连线沿所述第二方向连接相邻的两个所述显示基板，在所述非显示区的每条所述第二金属连线的一端沿所述第二方向连接一个所述显示基板，另一端沿所述第二方向与一个所述覆晶薄膜绑定。
  8. 根据权利要求6所述的拼接显示面板，其中，所述金属线包括多组第一金属连线和多组第二金属连线，多组所述第一金属连线沿所述第一方向设置且沿所述第二方向间隔排布，多组所述第二金属连线沿所述第二方向设置且沿所述第一方向间隔排布；
    其中，每组所述第一金属连线沿所述第一方向与多个所述像素单元对应设置，每组所述第二金属连线沿所述第二方向与多个所述子像素对应设置；每组所述第一金属连线包括沿所述第二方向相互间隔的多条第一子连线，同组所述第一金属连线中的每条所述第一子连线沿所述第一方向的一端分别连接不同的所述显示基板，另一端与同一个所述覆晶薄膜绑定；
    每组所述第二金属连线包括沿所述第一方向相互间隔的多条第二子连线，同组所述第二金属连线中的每条所述第二子连线沿所述第二方向的一端分别连接不同的所述显示基板，另一端与同一个所述覆晶薄膜绑定。
  9. 根据权利要求8所述的拼接显示面板，其中，多组所述第一金属连线和多组所述第二金属连线之间设置有绝缘层。
  10. 根据权利要求1所述的拼接显示面板，其中，所述显示基板还包括驱动基板和设置在所述驱动基板上的封装胶层，所述封装胶层中设置有导电球，所述导电球的两端分别连接所述金属线和所述驱动基板。
  11. 根据权利要求10中所述的拼接显示面板，其中，所述拼接显示面板还包括多个发光器件，多个所述发光器件通过金属或者异方性导电胶膜绑定在所述驱动基板上。
  12. 一种显示装置，其包括如权利要求1中所述的拼接显示面板。
PCT/CN2022/107605 2022-07-25 2022-07-25 拼接显示面板和显示装置 WO2024020720A1 (zh)

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CN111681610A (zh) * 2020-07-07 2020-09-18 京东方科技集团股份有限公司 一种显示装置及其制作方法
CN111951697A (zh) * 2020-08-10 2020-11-17 Tcl华星光电技术有限公司 拼接显示屏
CN112071192A (zh) * 2020-09-03 2020-12-11 Tcl华星光电技术有限公司 显示面板及拼接显示面板
CN113075808A (zh) * 2021-03-17 2021-07-06 Tcl华星光电技术有限公司 拼接显示面板及显示装置
CN113593424A (zh) * 2021-07-30 2021-11-02 Tcl华星光电技术有限公司 拼接显示面板及显示装置
CN114361039A (zh) * 2020-10-13 2022-04-15 浙江清华柔性电子技术研究院 拼接显示面板的制备方法、拼接显示面板及面板单元

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