WO2024007385A1 - 半导体器件和电子装置 - Google Patents

半导体器件和电子装置 Download PDF

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Publication number
WO2024007385A1
WO2024007385A1 PCT/CN2022/108652 CN2022108652W WO2024007385A1 WO 2024007385 A1 WO2024007385 A1 WO 2024007385A1 CN 2022108652 W CN2022108652 W CN 2022108652W WO 2024007385 A1 WO2024007385 A1 WO 2024007385A1
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Prior art keywords
semiconductor device
layer
metal
doped
active layer
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English (en)
French (fr)
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罗成志
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US17/759,866 priority Critical patent/US12148839B2/en
Publication of WO2024007385A1 publication Critical patent/WO2024007385A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present application relates to the field of display technology, and in particular, to a semiconductor device and an electronic device.
  • the buffer layer is provided with a groove in a region in contact with the active layer, and the metal block is disposed in the groove.
  • the material of the metal layer has a melting point less than 1410 degrees Celsius.
  • the semiconductor device includes a plurality of thin film transistors, and the active layer of at least one of the thin film transistors has no grain boundaries.
  • the active layer of the thin film transistor includes first crystal grains, the first crystal grains are arranged corresponding to the metal blocks, and the number of the first crystal grains is equal to the number of the metal blocks. .
  • the active layer includes a channel portion and first doping portions and second doping portions located on both sides of the channel portion, the first doping portion and the second doping portion
  • the shape of the doped portion along the connection line between the channel portions is the same as the shape of the metal block corresponding to the first doped portion and the second doped portion of the thin film transistor along the connection line between the channel portions.
  • the shape of the connection between the first doped part and the second doped part along the channel part is a straight line, and the metal blocks are arranged along the straight line array.
  • the first doped portion and the second doped portion are located on the same horizontal line, and the first doped portion and the second doped portion are along the channel portion.
  • the shape of the connecting lines is a polyline, and the metal blocks are arranged along the polyline array.
  • the channel portion includes a first portion disposed in a perpendicular direction of the first doped portion, a second portion disposed in a perpendicular direction of the second doped portion, and a second portion disposed in the perpendicular direction of the second doped portion.
  • the first part and the third part are vertically connected to the second part, and the first doped part and the second doped part are along the connection line between the channel part and the first part and the third part.
  • the third part and the second part are arranged, and the metal blocks are arranged in an array along the first part, the third part and the second part.
  • the channel part includes a fourth part and a fifth part connecting the first doped part and the second doped part, and the fourth part and the fifth part are arranged vertically , the metal blocks are arranged in an array along the direction of the fourth part and the fifth part.
  • the diameter of the first grain is equal to the distance between center points of adjacent metal blocks.
  • the thickness of the metal block ranges from 0.05 microns to 0.5 microns.
  • the spacing between the metal blocks is 1 micron to 5 microns.
  • the width of the metal block ranges from 0.5 microns to 2 microns.
  • embodiments of the present application provide an electronic device, which includes the semiconductor device described in any of the above embodiments.
  • the electronic device includes a liquid crystal display panel.
  • the electronic device includes an organic light emitting diode display panel.
  • the present application provides a semiconductor device and an electronic device; the semiconductor device includes a thin film transistor.
  • the thin film transistor includes a substrate, a buffer layer and an active layer.
  • the buffer layer is arranged on one side of the substrate, and the active layer is arranged on the buffer layer away from the substrate. on one side, wherein the semiconductor device further includes a metal layer, the metal layer is disposed on a side of the active layer facing the buffer layer, the metal layer includes at least one metal block, and the metal block is in direct contact with at least part of the active layer.
  • a metal layer is provided on the side of the active layer facing the buffer layer.
  • the metal layer includes at least one metal block, so that the metal block is in direct contact with at least part of the active layer.
  • the active layer is converted from amorphous silicon to In the case of polycrystalline silicon, due to the catalytic effect of the metal block, the size of the crystal grains in the polycrystalline silicon is increased, which reduces the grain boundaries in the polycrystalline silicon and improves the mobility of the semiconductor device.
  • FIG. 1 is a first schematic diagram of a semiconductor device provided by an embodiment of the present application.
  • FIG. 2 is a second schematic diagram of a semiconductor device provided by an embodiment of the present application.
  • FIG. 3 is a first schematic diagram of an active layer provided by an embodiment of the present application.
  • FIG. 4 is a second schematic diagram of an active layer provided by an embodiment of the present application.
  • FIG. 5 is a third schematic diagram of an active layer provided by an embodiment of the present application.
  • FIG. 6 is a first structural diagram of a semiconductor device corresponding to each step of the semiconductor device preparation method provided by the embodiment of the present application.
  • FIG. 7 is a second structural diagram of a semiconductor device corresponding to each step of the semiconductor device preparation method provided by the embodiment of the present application.
  • Embodiments of the present application address the technical problem of low mobility of the semiconductor device caused by the small grain size of the polysilicon formed due to process limitations of existing semiconductor devices, and provide a semiconductor device and electronic device to alleviate the above technical problem. .
  • the semiconductor device 1 includes a thin film transistor 10.
  • the thin film transistor 10 includes:
  • Buffer layer 13 is provided on one side of the substrate 11;
  • the active layer 15 is provided on the side of the buffer layer 13 away from the substrate 11;
  • the semiconductor device 1 further includes a metal layer 14, the metal layer 14 is provided on a side of the active layer 15 facing the buffer layer 13, the metal layer 14 includes at least one metal block, and the The metal block is in direct contact with at least part of said active layer 15 .
  • Embodiments of the present application provide a semiconductor device.
  • the semiconductor device disposes a metal layer on the side of the active layer facing the buffer layer.
  • the metal layer includes at least one metal block, so that the metal block is in direct contact with at least part of the active layer. Then
  • the active layer is converted from amorphous silicon to polycrystalline silicon, due to the catalytic effect of the metal block, the size of the crystal grains in the polycrystalline silicon is increased, reducing the grain boundaries in the polycrystalline silicon and improving the mobility of the semiconductor device.
  • the metal block is disposed between the buffer layer and the active layer.
  • the metal block can catalyze the reaction process of amorphous silicon when polysilicon is formed.
  • the metal block acts as a crystal nucleus, making the width of the formed grains larger. Thereby reducing the number of grain boundaries and improving the mobility of semiconductor devices.
  • the buffer layer is provided with a groove in a region in contact with the active layer, and the metal block is disposed in the groove.
  • the material of the buffer layer includes silicon nitride, silicon oxide, or a stack of silicon nitride and silicon oxide.
  • the thickness of the buffer layer ranges from 0.3 microns to 1 micron.
  • the depth of the groove ranges from 0.05 micron to 0.5 micron
  • the width of the groove ranges from 0.5 micron to 2 micron
  • the spacing between adjacent edges of adjacent grooves ranges from 0.5 micron to 3 micron
  • the center of the adjacent grooves ranges from 1 micron to 5 microns.
  • the depth of the groove ranges from 0.05 to 0.5 microns, it is avoided that the depth of the groove is too large, resulting in a smaller thickness of the part of the buffer layer where the groove is formed, so that the buffer layer has a better ability to block water and oxygen; and the width of the groove ranges is 0.5 microns to 2 microns, so that the metal block can be placed in the groove to catalyze the active layer and reduce grain boundaries; the spacing between adjacent edges of adjacent grooves is 0.5 microns to 3 microns, and the distance between adjacent grooves is 0.5 microns to 3 microns. The distance between the midpoints is 1 micron to 5 microns, which can make the metal block have a certain period, the grains can be larger, and the grain boundaries can be reduced.
  • the melting point of the material of the metal layer is less than 1410 degrees Celsius.
  • the melting point of the metal layer is lower than the melting point of silicon.
  • the metal layer easily forms a solid solution with silicon, so that in the process of converting amorphous silicon into polycrystalline silicon, the metal layer reacts The process is catalyzed to increase the size of polysilicon grains and reduce grain boundaries.
  • the material of the metal layer includes one of aluminum, nickel, gallium, and indium.
  • the metal layer can easily form a solid solution with silicon, thereby catalyzing the reaction process through the metal layer during the conversion of amorphous silicon into polycrystalline silicon and improving the grain size of polycrystalline silicon. size, reducing grain boundaries.
  • the semiconductor device includes a plurality of thin film transistors, and the active layer of at least one of the thin film transistors has no grain boundaries. By making the active layer of the thin film transistor without grain boundaries, the particles will not be blocked by grain boundaries during their migration, thereby improving the mobility of the semiconductor device.
  • the metal layer 14 includes a metal block
  • the active layer 15 includes single crystal silicon
  • the diameter of the single crystal silicon is less than 5 microns.
  • a metal block can be placed under the active layer, so that under the catalysis of this metal block, amorphous silicon is converted into single crystal silicon, and only one crystal grain exists, so that there is There are no grain boundaries in the source layer, which improves the mobility of semiconductor devices.
  • the active layer 15 of the thin film transistor 10 includes a first crystal grain 151, and the first crystal grain 151 is arranged corresponding to the metal block 141, so The number of the first crystal grains 151 is equal to the number of the metal blocks 141 .
  • the first crystal grains are formed under the catalysis of the metal blocks, and the diameter of the first crystal grains is larger, which reduces the number of crystal grains.
  • the number of boundaries increases the mobility of semiconductor devices.
  • the first crystal grains are formed through the catalysis of the metal block, even if there is still a diameter smaller than the first crystal grain between the first crystal grains due to process limitations. grains, but due to the larger diameter of the first grains, the number of grain boundaries in the active layer can still be reduced and the mobility of the semiconductor device can be improved.
  • the first crystal grain is round or nearly round, and the diameter of the first crystal grain is 1 micron to 5 micron.
  • the diameter of the first crystal grains is 1 micron to 5 microns.
  • the metal layer 14 includes metal blocks 141 arranged in an array
  • the active layer 15 includes a plurality of first grains 151
  • the number of the metal blocks 141 is the same as the number of the metal blocks 141 .
  • the number of first crystal grains 151 is equal, and the grain boundaries 152 of the first crystal grains are located between two adjacent metal blocks 141 .
  • each first crystal grain is formed through the catalysis of the metal block, and the width of each first crystal grain is larger, thereby reducing the number of grain boundaries and improving The mobility of the semiconductor device, and the first grain will grow around the position of the metal block, so that the grain boundary of the first grain is located between two adjacent metal blocks.
  • the spacing of the metal blocks the The width of the first crystal grain is adjusted to reduce the number of grain boundaries and improve the mobility of the semiconductor device.
  • the thickness of the metal layer ranges from 0.05 microns to 0.5 microns.
  • the thickness of the metal layer is too large, resulting in a smaller thickness of the buffer layer, and the occurrence of water and oxygen from the thickness of the buffer layer. Minor location intrusions.
  • the spacing between the metal blocks is 1 micron to 5 microns
  • the array period of the metal blocks is 1 micron to 5 microns, so that the width of the crystal grains is 1 micron to 5 microns, increasing the width of the crystal grains and reducing the grain size.
  • the number of boundaries increases the mobility of semiconductor devices.
  • the width of the metal block ranges from 0.5 microns to 2 microns.
  • the width of the metal block is too small, which will lead to a smaller width of the grains, resulting in a larger number of grain boundaries and lower mobility of the semiconductor device.
  • the width of the metal block is too large, the aperture ratio of the display panel will be low, which will affect the transmittance of the display panel.
  • the width of the metal block is large, there may be multiple nucleations on the metal block. position, causing a metal block to form multiple grains, making the width of the grains smaller and more grain boundaries.
  • the width of the metal block to 0.5 microns to 2 microns, and control the period of the adjacent metal array to 1 micron to 5 micron, prepare crystal grains with a grain width of 1 micron to 5 micron, so that the width of the formed grains is larger, the number of grain boundaries is smaller, and the mobility of the semiconductor device is improved.
  • the active layer 15 includes a channel portion 251 and a first doping portion 252 and a second doping portion 253 located on both sides of the channel portion 251 , so The shape of the first doped portion 252 and the second doped portion 253 along the connection line between the channel portion 251 is consistent with the first doped portion 252 and the second doped portion 253 of the thin film transistor.
  • the shapes of the connecting lines of the corresponding metal blocks 141 along the channel portion are the same.
  • the shapes of the connections are the same, so that for active layers with different arrangements, the crystal grains of the active layer located in the channel part, the first doped part and the second doped part can be changed by changing the arrangement of the metal array.
  • the width is larger, which can reduce the number of grain boundaries and improve the mobility of semiconductor devices.
  • the metal blocks can be arranged in an array, and the spacing and width of the metal blocks can be set according to the required shape of the active layer, so that The width of the crystal grains of the active layer is large and the number of grain boundaries is small.
  • single crystal silicon can also be formed to improve the mobility of the semiconductor device.
  • the shape of the first doped part 252 and the second doped part 253 along the connection line between the channel part 251 is a straight line, and the The metal blocks 141 are arranged along the linear array.
  • the crystal grains located in the area where the metal blocks are located can grow along the direction of the metal blocks, making the width of the crystal grains larger and the number of grain boundaries smaller, thereby improving the mobility of the semiconductor device.
  • first doped portions and second doped portions along the shape of the connection line between the channel portions and metal blocks corresponding to the first doped portions and the second doped portions.
  • the shapes of the connecting lines to the channel part are the same, and the channel part, the first doped part and the second doped part are arranged along the arrangement direction of the metal block to obtain an active layer of "in-line channel", and the The width of the crystal grains of the active layer is larger, the number of grain boundaries is smaller, and the mobility of the semiconductor device is higher.
  • the channel portion 251 includes a first portion disposed in the vertical direction of the first doped portion 252 , and a vertical portion disposed in the second doped portion 253 .
  • the second part in the line direction and the third part perpendicularly connected to the first part and the second part, the first doped part 252 and the second doped part 253 are along the channel part 251
  • the connection lines are arranged along the first part, the third part and the second part, and the metal blocks 141 are arranged in an array along the first part, the third part and the second part. .
  • the channel part, the first doped part and the second doped part of the active layer are arranged along the arrangement direction of the metal block, and an active layer with a "digital channel" is obtained.
  • the width of the crystal grains of the active layer is larger, the number of grain boundaries is smaller, and the mobility of the semiconductor device is higher.
  • the channel part 251 includes a fourth part and a fifth part connecting the first doped part 252 and the second doped part 253 , and the third part
  • the four parts and the fifth part are arranged vertically, and the metal blocks 141 are arranged in an array along the direction of the fourth part and the fifth part.
  • the metal block include mutually perpendicular portions, when forming the active layer, the active layer can be formed along the metal block, and due to the catalytic effect of the metal block, the channel portion, the first doping portion and the second doping portion
  • the width of the grains at the bottom is larger and the number of grain boundaries is smaller, thereby improving the mobility of the semiconductor device.
  • the amorphous silicon layer when forming the active layer, is processed to obtain the polysilicon layer 25.
  • the amorphous silicon layer can be processed by laser annealing. Since there are A metal block 141 is provided in the area of the active layer 15, so that the crystal grains of the active layer 15 grow faster under the catalysis of the metal block 141, and the width of the crystal grains is larger. However, the area outside the active layer 15 has no metal block. , so that the width of the grains in the ineffective portion 26 is smaller and the number of grain boundaries is larger; then the polysilicon layer is etched, as shown in (b) in Figure 5, to remove the ineffective portion 26 and form the pattern of the active layer , the active layer 15 is obtained.
  • the channel part, the first doped part and the second doped part of the active layer are arranged along the arrangement direction of the metal block, and an "L-shaped channel" active layer is obtained.
  • the width of the crystal grains of the active layer is larger, the number of grain boundaries is smaller, and the mobility of the semiconductor device is higher.
  • the diameter L1 of the first crystal grain is equal to the distance L2 between the center points of adjacent metal blocks.
  • the metal blocks are arranged at equal intervals.
  • the diameter of the first crystal grain refers to the width at the center line of the trapezoid.
  • the above embodiments are described in detail by taking the metal blocks to be arranged at equal intervals as an example, but the embodiments of the present application are not limited thereto.
  • the metal blocks can be If the spacing is unequal and the sizes of the metal blocks are unequal, the grain widths of the channel portion and the doped portion can be different.
  • arranging amorphous silicon in the buffer layer in current semiconductor devices will result in amorphous silicon.
  • the thickness increases, and the amorphous silicon located in the buffer layer during laser annealing will increase nucleation sites, which can easily lead to an increase in the number of crystal grains, and the effect of increasing the grain size is not obvious; and the embodiment of the present application uses a metal block as a catalyst, Since the metal block is made of different materials than amorphous silicon, it will not combine with amorphous silicon to increase the thickness of amorphous silicon and change its performance.
  • the semiconductor device 1 further includes a light-shielding layer 12 , and the light-shielding layer 12 is provided corresponding to the active layer 15 .
  • the semiconductor device 1 further includes a gate insulating layer 16, a gate layer 17, an interlayer insulating layer 18, a source and drain layer 19, a planarization layer 20, a first The electrode layer 21, the passivation layer 22 and the second electrode layer 23, the gate insulating layer 16 is disposed on the side of the active layer 15 away from the buffer layer 13, and the gate layer 17 is disposed on the gate insulating layer 16 away from the active layer 15
  • the interlayer insulating layer 18 is disposed on the side of the gate layer 17 away from the gate insulating layer 16
  • the source and drain layer 19 is disposed on the side of the interlayer insulating layer 18 away from the gate layer 17
  • the planarization layer 20 The first electrode layer 21 is disposed on the side of the source and drain layer 19 away from the interlayer insulating layer 18
  • the first electrode layer 21 is disposed on the side of the planarization layer 20 away from the source and drain layer 19
  • inventions of the present application provide a method for manufacturing a semiconductor device.
  • the method for manufacturing a semiconductor device includes:
  • the semiconductor device can be leveled to facilitate subsequent processes.
  • polysilicon can be formed through the amorphous silicon layer.
  • the amorphous silicon layer is then laser annealed to transform the amorphous silicon layer into a polycrystalline silicon layer; the structure of the semiconductor device corresponding to this step is shown in (b) in Figure 7;
  • the width of the polysilicon grains is different between the area where the metal block exists and the area where the metal block does not exist.
  • the number of grain boundaries is different, and the width of the polysilicon grains in the area where the metal block is present is larger and the number of grain boundaries is smaller. Therefore, when the active layer is formed, the width of the grains of the active layer is larger and the number of grain boundaries is smaller. Less, improve the mobility of semiconductor devices.
  • this step is described by taking the amorphous silicon layer into a polycrystalline silicon layer as an example.
  • the embodiments of the present application are not limited thereto.
  • the amorphous silicon layer can be transformed into a single crystal silicon layer.
  • the polysilicon layer is then exposed, developed and etched to form an active layer; the structure of the semiconductor device corresponding to this step is shown in (c) in Figure 7;
  • a gate insulating layer, a gate layer, an interlayer insulating layer, a source and drain layer, a planarization layer, a first electrode layer, a passivation layer and a second electrode layer are formed on the active layer to obtain a semiconductor device.
  • embodiments of the present application provide an electronic device, which includes the semiconductor device described in any of the above embodiments.
  • the electronic device may be a liquid crystal display panel or an organic light-emitting diode display panel.
  • Embodiments of the present application provide a semiconductor device and an electronic device; the semiconductor device includes a thin film transistor.
  • the thin film transistor includes a substrate, a buffer layer and an active layer.
  • the buffer layer is disposed on one side of the substrate, and the active layer is disposed away from the buffer layer.
  • a metal layer is provided on the side of the active layer facing the buffer layer.
  • the metal layer includes at least one metal block, so that the metal block is in direct contact with at least part of the active layer.
  • the active layer is converted from amorphous silicon to In the case of polycrystalline silicon, due to the catalytic effect of the metal block, the size of the crystal grains in the polycrystalline silicon is increased, which reduces the grain boundaries in the polycrystalline silicon and improves the mobility of the semiconductor device.

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Abstract

本申请提供一种半导体器件和电子装置；该半导体器件通过在有源层朝向缓冲层的一侧设置金属层，金属层包括至少一个金属块，使金属块与有源层的至少部分直接接触，则在将有源层由非晶硅转化为多晶硅时，由于金属块的催化作用，使得多晶硅中的晶粒的尺寸交大，减少了多晶硅中的晶界，提高了半导体器件的迁移率。

Description

半导体器件和电子装置 技术领域
本申请涉及显示技术领域，尤其是涉及一种半导体器件和电子装置。
 背景技术
随着显示技术的发展，现有显示器件对窄边框、高开口率、高亮度、高分辨率提出了越来越高的要求，因此，需要在减小薄膜晶体管的尺寸的同时，保持良好的开态电流。现有半导体器件会采用多晶硅作为有源层以提高载流子迁移率，提高开态电流。但在多晶硅的制备过程中，由于工艺的限制，导致激光退火后形成的多晶硅的晶粒尺寸较小，导致载流子迁移率较低，从而导致半导体器件的开态电流较低，无法满足需求。
所以，现有半导体器件存在工艺限制形成的多晶硅的晶粒尺寸较小所导致的半导体器件的迁移率较低的技术问题。
 技术问题
本申请实施例提供一种半导体器件和电子装置，用以缓解现有半导体器件存在工艺限制形成的多晶硅的晶粒尺寸较小所导致的半导体器件的迁移率较低的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种半导体器件，该半导体器件
薄膜晶体管，所述薄膜晶体管包括：
衬底；
缓冲层，设置于所述衬底一侧；
有源层，设置于所述缓冲层远离所述衬底的一侧；
其中，所述半导体器件还包括金属层，所述金属层设置于所述有源层朝向所述缓冲层的一侧，所述金属层包括至少一个金属块，且所述金属块与所述有源层的至少部分直接接触。
在一些实施例中，所述缓冲层在与所述有源层接触的区域设置有凹槽，所述金属块设置于所述凹槽内。
在一些实施例中，所述金属层的材料的熔点小于1410摄氏度。
在一些实施例中，所述金属层的材料包括铝、镍、镓、铟中的至少一个。
在一些实施例中，所述半导体器件包括多个薄膜晶体管，至少一个所述薄膜晶体管的有源层无晶界。
在一些实施例中，所述薄膜晶体管的有源层包括第一晶粒，所述第一晶粒与所述金属块对应设置，所述第一晶粒的数量与所述金属块的数量相等。
在一些实施例中，述第一晶粒为圆形或者类圆形，所述第一晶粒的直径为1微米至5微米。
在一些实施例中，所述薄膜晶体管包括多个第一晶粒，所述金属层包括阵列设置的金属块，所述第一晶粒的晶界位于相邻两个金属块之间。
在一些实施例中，所述有源层包括沟道部和位于所述沟道部两侧的第一掺杂部和第二掺杂部，所述第一掺杂部及所述第二掺杂部沿着所述沟道部之间的连线的形状与所述薄膜晶体管的第一掺杂部和第二掺杂部对应的金属块沿所述沟道部的连线的形状相同。
在一些实施例中，所述第一掺杂部与所述第二掺杂部沿着所述沟道部之间的连线的形状为直线，所述金属块沿着所述直线阵列设置。
在一些实施例中，所述第一掺杂部与所述第二掺杂部位于同一水平线上，所述第一掺杂部及所述第二掺杂部沿着所述沟道部之间的连线的形状为折线，所述金属块沿着所述折线阵列设置。
在一些实施例中，所述沟道部包括设置于所述第一掺杂部的垂线方向的第一部分、设置于所述第二掺杂部的垂线方向的第二部分和与所述第一部分和所述第二部分垂直连接的第三部分，所述第一掺杂部及所述第二掺杂部沿着所述沟道部之间的连线沿着所述第一部分、所述第三部分和所述第二部分设置，所述金属块沿着所述第一部分、所述第三部分和所述第二部分阵列设置。
在一些实施例中，所述沟道部包括连接所述第一掺杂部和所述第二掺杂部的第四部分和第五部分，所述第四部分和所述第五部分垂直设置，所述金属块沿所述第四部分和所述第五部分的方向阵列设置。
在一些实施例中，所述第一晶粒的直径与相邻所述金属块的中心点之间的间距相等。
在一些实施例中，所述金属块的厚度范围为0.05微米至0.5微米。
在一些实施例中，所述金属块之间的间距为1微米至5微米。
在一些实施例中，所述金属块的宽度范围为0.5微米至2微米。
同时，本申请实施例提供一种电子装置，该电子装置包括如上述实施例任一所述的半导体器件。
在一些实施例中，所述电子装置包括液晶显示面板。
在一些实施例中，所述电子装置包括有机发光二极管显示面板。
 有益效果
本申请提供一种半导体器件和电子装置；该半导体器件包括薄膜晶体管，薄膜晶体管包括衬底、缓冲层和有源层，缓冲层设置于衬底一侧，有源层设置于缓冲层远离衬底的一侧，其中，半导体器件还包括金属层，金属层设置于有源层朝向缓冲层的一侧，金属层包括至少一个金属块，且金属块与有源层的至少部分直接接触。本申请通过在有源层朝向缓冲层的一侧设置金属层，金属层包括至少一个金属块，使金属块与有源层的至少部分直接接触，则在将有源层由非晶硅转化为多晶硅时，由于金属块的催化作用，使得多晶硅中的晶粒的尺寸交大，减少了多晶硅中的晶界，提高了半导体器件的迁移率。
 附图说明
图1为本申请实施例提供的半导体器件的第一种示意图。
图2为本申请实施例提供的半导体器件的第二种示意图。
图3为本申请实施例提供的有源层的第一种示意图。
图4为本申请实施例提供的有源层的第二种示意图。
图5为本申请实施例提供的有源层的第三种示意图。
图6为本申请实施例提供的半导体器件制备方法的各个步骤对应的半导体器件的第一种结构图。
图7为本申请实施例提供的半导体器件制备方法的各个步骤对应的半导体器件的第二种结构图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例针对现有半导体器件存在工艺限制形成的多晶硅的晶粒尺寸较小所导致的半导体器件的迁移率较低的技术问题，提供一种半导体器件和电子装置，用以缓解上述技术问题。
如图1所示，本申请实施例提供一种半导体器件，该半导体器件1包括薄膜晶体管10，所述薄膜晶体管10包括：
衬底11；
缓冲层13，设置于所述衬底11一侧；
有源层15，设置于所述缓冲层13远离所述衬底11的一侧；
其中，所述半导体器件1还包括金属层14，所述金属层14设置于所述有源层15朝向所述缓冲层13的一侧，所述金属层14包括至少一个金属块，且所述金属块与所述有源层15的至少部分直接接触。
本申请实施例提供一种半导体器件，该半导体器件通过在有源层朝向缓冲层的一侧设置金属层，金属层包括至少一个金属块，使金属块与有源层的至少部分直接接触，则在将有源层由非晶硅转化为多晶硅时，由于金属块的催化作用，使得多晶硅中的晶粒的尺寸交大，减少了多晶硅中的晶界，提高了半导体器件的迁移率。
需要说明的是，在本申请中的附图中，由于晶界能在微观上看到，因此，本申请中的附图以实线示出晶界的位置以及示意的形状。
在一种实施例中，所述金属块设置于所述缓冲层与所述有源层之间。通过将金属块设置在缓冲层与有源层之间，使得在形成多晶硅时，金属块能够对非晶硅的反应过程进行催化，金属块作为晶核，使得形成的晶粒的宽度变大，从而减少晶界的数量，提高半导体器件的迁移率。
针对金属块设置于缓冲层与有源层之间会导致有源层的厚度变小，影响有源层的电性的问题。在一种实施例中，所述缓冲层在与所述有源层接触的区域设置凹槽，所述金属块设置于所述凹槽内。通过在缓冲层上设置凹槽，使金属块设置在凹槽内，则有源层与缓冲层和金属块接触的表面保持平整，使有源层的电性较好，且金属块作为催化剂使得有源层的晶粒的宽度变大，减小晶界的数量，提高半导体器件的迁移率。
具体的，缓冲层的材料包括氮化硅、氧化硅或者氮化硅和氧化硅的叠层。
具体的，缓冲层的厚度范围为0.3微米至1微米。
具体的，凹槽的深度范围为0.05微米至0.5微米，凹槽的宽度范围为0.5微米至2微米，相邻凹槽的相邻边缘的间距为0.5微米至3微米，相邻凹槽的中点的间距为1微米至5微米。通过使凹槽的深度范围为0.05至0.5微米，避免凹槽的深度过大导致缓冲层形成有凹槽的部分厚度较小，使缓冲层阻隔水氧的能力较好；而凹槽的宽度范围为0.5微米至2微米，使得金属块能够设置在凹槽内，对有源层进行催化，减少晶界；使相邻凹槽的相邻边缘的间距为0.5微米至3微米，相邻凹槽的中点的间距为1微米至5微米，则可以使得金属块具有一定的周期，晶粒能够较大，减少晶界。
在一种实施例中，所述金属层的材料的熔点小于1410摄氏度。通过采用熔点小于1410摄氏度的材料作为金属层的材料，使得金属层的熔点低于硅的熔点，金属层容易与硅形成固溶体，从而在非晶硅转换为多晶硅的过程中，通过金属层对反应过程进行催化，提高多晶硅的晶粒的尺寸，减少晶界。
在一种实施例中，金属层的材料包括铝、镍、镓、铟中的一种。通过采用铝、镍、镓、铟作为金属层的材料，使金属层容易与硅形成固溶体，从而在非晶硅转换为多晶硅的过程中，通过金属层对反应过程进行催化，提高多晶硅的晶粒的尺寸，减少晶界。
针对多晶硅的晶界较多会导致半导体器件的迁移率较低的问题。在一种实施例中，所述半导体器件包括多个薄膜晶体管，至少一个所述薄膜晶体管的有源层无晶界。通过使薄膜晶体管的有源层无晶界，则在粒子的迁移过程中不会受到晶界的阻挡，提高了半导体器件的迁移率。
具体的，如图2所示，所述金属层14包括一个金属块，所述有源层15包括单晶硅，所述单晶硅的直径小于5微米。在有源层的宽度小于5微米时，可以通过在有源层下方设置一个金属块，使得在这个金属块的催化下，非晶硅转化为单晶硅，则仅存在一个晶粒，使得有源层内无晶界，提高半导体器件的迁移率。
在一种实施例中，如图1、图3所示，所述薄膜晶体管10的有源层15包括第一晶粒151，所述第一晶粒151与所述金属块141对应设置，所述第一晶粒151的数量与所述金属块141的数量相等。通过使第一晶粒与金属块对应设置，第一晶粒的数量与金属块的数量相等，则第一晶粒是在金属块的催化下形成，第一晶粒的直径较大，减少晶界的数量，提高半导体器件的迁移率。
具体的，在通过激光退火的工艺将非晶硅转换为多晶硅时，通过金属块的催化形成第一晶粒，即使由于工艺限制导致第一晶粒之间仍然存有小于第一晶粒的直径的晶粒，但由于第一晶粒的直径较大，仍然可以减少有源层的晶界的数量，提高半导体器件的迁移率。
在一种实施例中，所述第一晶粒为圆形或者类圆形，所述第一晶粒的直径为1微米至5微米。通过使第一晶粒的直径为1微米至5微米，使得第一晶粒较大，晶界的数量较少，提高半导体器件的迁移率。
具体的，如图1、图3所示，所述金属层14包括阵列设置的金属块141，所述有源层15包括多个第一晶粒151，所述金属块141的数量与所述第一晶粒151的数量相等，所述第一晶粒的晶界152位于相邻两个金属块141之间。通过使金属块的数量与第一晶粒的数量相等，使得每个第一晶粒都是通过金属块的催化形成，各个第一晶粒的宽度较大，从而可以减少晶界的数量，提高半导体器件的迁移率，且第一晶粒会沿金属块所处位置向四周生长，从而使第一晶粒的晶界位于相邻两个金属块之间，通过金属块的间距的调整，可以对第一晶粒的宽度进行调整，使晶界数量减少，提高半导体器件的迁移率。
具体的，金属层的厚度范围为0.05微米至0.5微米，通过使金属层的厚度为0.05微米至0.5微米，避免金属层的厚度过大导致缓冲层的厚度较小，出现水氧从缓冲层厚度较小的位置入侵。
具体的，金属块之间的间距为1微米至5微米，通过使金属块的阵列周期为1微米至5微米，使得晶粒的宽度为1微米至5微米，增加晶粒的宽度，减少晶界的数量，提高半导体器件的迁移率。
具体的，金属块的宽度范围为0.5微米至2微米，在设置金属块时，金属块的宽度过小会导致晶粒的宽度较小，从而导致晶界的数量较多，半导体器件的迁移率较低，而使得金属块的宽度过大时，会导致显示面板的开口率较低，影响显示面板的透过率，且金属块的宽度较大时，金属块上可能会存在多个形核位点，导致一个金属块会形成多个晶粒，使得晶粒的宽度较小，晶界较多，因此，设置金属块的宽度为0.5微米至2微米，并控制相邻金属阵列的周期为1微米至5微米，制备晶粒宽度为1微米至5微米的晶粒，使得形成的晶粒的宽度较大，晶界数量较少，提高半导体器件的迁移率。
在一种实施例中，如图3所示，所述有源层15包括沟道部251和位于所述沟道部251两侧的第一掺杂部252和第二掺杂部253，所述第一掺杂部252及所述第二掺杂部253沿着所述沟道部251之间的连线的形状与所述薄膜晶体管的第一掺杂部252和第二掺杂部253对应的金属块141沿所述沟道部的连线的形状相同。通过使第一掺杂部及第二掺杂部沿着沟道部之间的连线的形状与薄膜晶体管的第一掺杂部和第二掺杂部对应的金属块沿着沟道部的连线的形状相同，使得对于不同设置方式的有源层，可以通过金属阵列的设置方式的改变，使得位于沟道部、第一掺杂部和第二掺杂部的有源层的晶粒的宽度较大，从而可以减少晶界的数量，提高半导体器件的迁移率。
具体的，相较于采用非晶硅作为催化剂来增加晶粒尺寸，由于本申请中可以使金属块阵列排布，根据需求的有源层的形状来设置金属块的间距、宽度，从而可以使得有源层的晶粒的宽度较大，晶界数量较少，在有源层的宽度较小时，还可以形成单晶硅，提高半导体器件的迁移率。
在一种实施例中，如图3所示，所述第一掺杂部252和所述第二掺杂部253沿着所述沟道部251之间的连线的形状为直线，所述金属块141沿着所述直线阵列设置。通过使金属块沿直线阵列设置，则位于金属块所处区域的晶粒能够沿着金属块的方向生长，使得晶粒的宽度较大，晶界的数量较少，提高半导体器件的迁移率。
具体的，如图3中的（a）所示，在形成有源层时，对非晶硅层进行处理得到多晶硅层25，具体可以采用激光退火的方式对非晶硅层进行处理，由于有源层15的区域设置有金属块141，使得有源层15的晶粒在金属块141的催化下生长较快，晶粒的宽度较大，而位于有源层15外的区域由于无金属块，使得无效部分26的晶粒的宽度较小，晶界的数量较多；然后对多晶硅层进行刻蚀，如图3中的（b）所示，去除无效部分26并形成有源层的图案，得到有源层15，此时有第一掺杂部及第二掺杂部沿着沟道部之间的连线的形状与第一掺杂部和第二掺杂部对应的金属块沿着沟道部的连线的形状相同，沟道部、第一掺杂部和第二掺杂部沿着金属块的设置方向设置，得到“一字型沟道”的有源层，且该有源层的晶粒的宽度较大，晶界的数量较少，半导体器件的迁移率较高。
在一种实施例中，如图4所示，所述第一掺杂部252与所述第二掺杂部253位于同一水平线上，所述第一掺杂部252及所述第二掺杂部253沿着所述沟道部251之间的连线的形状为折线，所述金属块141沿着所述折线阵列设置。通过使金属块包括沿着折线阵列设置，使得形成的沟道部、第一掺杂部和第二掺杂部能够形成金属块所形成的形状，且由于金属块的催化作用，沟道部、第一掺杂部和第二掺杂部的晶粒的宽度较大，晶界数量较少，从而提高了半导体器件的迁移率。
在一种实施例中，如图4所示，所述沟道部251包括设置于所述第一掺杂部252的垂线方向的第一部分、设置于所述第二掺杂部253的垂线方向的第二部分和与所述第一部分和所述第二部分垂直连接的第三部分，所述第一掺杂部252及所述第二掺杂部253沿着所述沟道部251之间的连线沿着所述第一部分、所述第三部分和所述第二部分设置，所述金属块141沿着所述第一部分、所述第三部分和所述第二部分阵列设置。通过使金属块包括沿着水平线的方向设置的部分、与水平设置的部分垂直的部分以及连接的部分，使得形成的沟道部、第一掺杂部和第二掺杂部能够形成金属块所形成的形状，且由于金属块的催化作用，沟道部、第一掺杂部和第二掺杂部的晶粒的宽度较大，晶界数量较少，从而提高了半导体器件的迁移率。
具体的，如图4中的（a）所示，在形成有源层时，对非晶硅层进行处理得到多晶硅层25，具体可以采用激光退火的方式对非晶硅层进行处理，由于有源层15的区域设置有金属块141，使得有源层15的晶粒在金属块141的催化下生长较快，晶粒的宽度较大，而位于有源层15外的区域由于无金属块，使得无效部分26的晶粒的宽度较小，晶界的数量较多；然后对多晶硅层进行刻蚀，如图4中的（b）所示，去除无效部分26并形成有源层的图案，得到有源层15，此时有源层的沟道部、第一掺杂部和第二掺杂部的沿着金属块的设置方向设置，得到“几字型沟道”的有源层，且该有源层的晶粒的宽度较大，晶界的数量较少，半导体器件的迁移率较高。
在一种实施例中，如图5所示，所述沟道部251包括连接所述第一掺杂部252和所述第二掺杂部253的第四部分和第五部分，所述第四部分和所述第五部分垂直设置，所述金属块141沿所述第四部分和所述第五部分的方向阵列设置。通过使金属块包括相互垂直的部分，使得在形成有源层时，有源层能够沿着金属块形成，且由于金属块的催化作用，沟道部、第一掺杂部和第二掺杂部的晶粒的宽度较大，晶界数量较少，从而提高了半导体器件的迁移率。
具体的，如图5中的（a）所示，在形成有源层时，对非晶硅层进行处理得到多晶硅层25，具体可以采用激光退火的方式对非晶硅层进行处理，由于有源层15的区域设置有金属块141，使得有源层15的晶粒在金属块141的催化下生长较快，晶粒的宽度较大，而位于有源层15外的区域由于无金属块，使得无效部分26的晶粒的宽度较小，晶界的数量较多；然后对多晶硅层进行刻蚀，如图5中的（b）所示，去除无效部分26并形成有源层的图案，得到有源层15，此时有源层的沟道部、第一掺杂部和第二掺杂部的沿着金属块的设置方向设置，得到“L字型沟道”的有源层，且该有源层的晶粒的宽度较大，晶界的数量较少，半导体器件的迁移率较高。
需要说明的是，在图3、图4和图5中使位于有源层外的多晶硅下不设置金属块，有源层外的多晶硅的晶粒的宽度较小且晶界的数量较多，但本申请实施例不限于此，例如可以使有源层外的多晶硅下也设置有金属块。
在一种实施例中，如图1所示，所述第一晶粒的直径L1与相邻所述金属块的中心点之间的间距L2相等。通过使金属块的中心点之间的间距与第一晶粒的直径相等，从而可以通过金属块的间距和宽度对有源层中的晶粒的宽度进行调整，使有源层中的晶界的数量较少，提高半导体器件的迁移率。
具体的，金属块等间距设置，在第一晶粒的截面为梯形时，第一晶粒的直径是指梯形的中线处的宽度。
具体的，上述实施例以金属块等间距设置为例进行了详细描述，但本申请实施例不限于此，例如在沟道部和掺杂部需要的晶粒宽度不同时，可以使金属块的间距不等，且金属块的尺寸不等，则可以使得沟道部和掺杂部的晶粒宽度不同。
具体的，相较于当前半导体器件中通过在缓冲层内设置非晶硅，然后沉积非晶硅以提高晶粒宽度的方式，当前半导体器件中在缓冲层内设置非晶硅会导致非晶硅的厚度增加，且在激光退火时位于缓冲层内的非晶硅会增加形核位点，容易导致晶粒数量增加，晶粒尺寸增加效果不明显；而本申请实施例采用金属块作为催化剂，由于金属块与非晶硅的材料不同，不会与非晶硅结合导致非晶硅的厚度增大性能改变，且金属块与非晶硅材料不同，不会增加形核位点，能够增大晶粒的宽度，减少晶界的数量，提高半导体器件的迁移率。且相较于采用非晶硅提高晶粒宽度，本申请中采用金属块可以阵列设置，根据有源层的形状设定金属块的间距、宽度，减少有源层内的晶界数量，在有源层的宽度较小时，还可以得到单晶硅，提高半导体器件的迁移率。
在一种实施例中，如图1所示，半导体器件1还包括遮光层12，遮光层12对应有源层15设置。
在一种实施例中，如图1所示，所述半导体器件1还包括栅极绝缘层16、栅极层17、层间绝缘层18、源漏极层19、平坦化层20、第一电极层21、钝化层22和第二电极层23，栅极绝缘层16设置于有源层15远离缓冲层13的一侧，栅极层17设置于栅极绝缘层16远离有源层15的一侧，层间绝缘层18设置于栅极层17远离栅极绝缘层16的一侧，源漏极层19设置于层间绝缘层18远离栅极层17的一侧，平坦化层20设置于源漏极层19远离层间绝缘层18的一侧，第一电极层21设置于平坦化层20远离源漏极层19的一侧，钝化层22设置于第一电极层21远离平坦化层20的一侧，第二电极层23设置于钝化层22远离第一电极层21的一侧。
同时，本申请实施例提供一种半导体器件的制备方法，该半导体器件的制备方法包括：
提供衬底，并在衬底上形成遮光层，在遮光层上沉积缓冲层，并通过曝光显影刻蚀工艺形成凹槽；该步骤对应的半导体器件的结构如图6中的（a）所示；
然后在缓冲层上沉积金属层；该步骤对应的半导体器件的结构如图6中的（b）所示；
具体的，如图6中的（b）所示，在缓冲层上沉积金属薄膜24时，由于缓冲层上设有凹槽，金属24会在形成有凹槽的位置形成金属块。
然后在金属层上形成光阻；该步骤对应的半导体器件的结构如图6中的（c）所示；
具体的，如图6中的（c）所示，通过设置光阻35，使半导体器件能够流平，便于后续制程。
然后通过干蚀刻将光阻和位于缓冲层上的金属薄膜进行整面刻蚀，并控制刻蚀过程使凹槽外的金属刻蚀完毕后结束刻蚀，保留凹槽内的金属；该步骤对应的半导体器件的结构如图6中的（d）所示；
然后在缓冲层上沉积非晶硅层；该步骤对应的半导体器件的结构如图7中的（a）所示；
具体的，如图7中的（a）所示，通过在缓冲层上形成非晶硅层41，使得可以通过非晶硅层形成多晶硅。
然后对非晶硅层进行激光退火处理，使得非晶硅层转变为多晶硅层；该步骤对应的半导体器件的结构如图7中的（b）所示；
具体的，如图7中的（b）所示，在由非晶硅层转变为多晶硅层25时，对于存在金属块的区域和不存在金属块的区域，多晶硅的晶粒的宽度不同，多晶硅的晶界的数量不同，且存在金属块的区域的多晶硅的晶粒的宽度较大，晶界数量较少，使得形成有源层时，有源层的晶粒的宽度较大，晶界数量较少，提高半导体器件的迁移率。
具体的，该步骤以非晶硅层转变为多晶硅层为例进行说明，但本申请实施例不限于此，例如可以由非晶硅层转变为单晶硅。
然后对多晶硅层进行曝光显影和刻蚀，形成有源层；该步骤对应的半导体器件的结构如图7中的（c）所示；
然后在有源层上形成栅极绝缘层、栅极层、层间绝缘层、源漏极层、平坦化层、第一电极层、钝化层和第二电极层，得到半导体器件。
同时，本申请实施例提供一种电子装置，该电子装置包括如上述实施例任一所述的半导体器件。
具体的，电子装置可以为液晶显示面板、也可以为有机发光二极管显示面板。
根据上述实施例可知：
本申请实施例提供一种半导体器件和电子装置；该半导体器件包括薄膜晶体管，薄膜晶体管包括衬底、缓冲层和有源层，缓冲层设置于衬底一侧，有源层设置于缓冲层远离衬底的一侧，其中，半导体器件还包括金属层，金属层设置于有源层朝向缓冲层的一侧，金属层包括至少一个金属块，且金属块与有源层的至少部分直接接触。本申请通过在有源层朝向缓冲层的一侧设置金属层，金属层包括至少一个金属块，使金属块与有源层的至少部分直接接触，则在将有源层由非晶硅转化为多晶硅时，由于金属块的催化作用，使得多晶硅中的晶粒的尺寸交大，减少了多晶硅中的晶界，提高了半导体器件的迁移率。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种半导体器件和电子装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种半导体器件，其包括薄膜晶体管，所述薄膜晶体管包括：
    衬底；
    缓冲层，设置于所述衬底一侧；
    有源层，设置于所述缓冲层远离所述衬底的一侧；
    其中，所述半导体器件还包括金属层，所述金属层设置于所述有源层朝向所述缓冲层的一侧，所述金属层包括至少一个金属块，且所述金属块与所述有源层的至少部分直接接触。
  2. 如权利要求1所述的半导体器件，其中，所述缓冲层在与所述有源层接触的区域设置有凹槽，所述金属块设置于所述凹槽内。
  3. 如权利要求1所述的半导体器件，其中，所述金属层的材料的熔点小于1410摄氏度。
  4. 如权利要求3所述的半导体器件，其中，所述金属层的材料包括铝、镍、镓、铟中的至少一个。
  5. 如权利要求1所述的半导体器件，其中，所述半导体器件包括多个薄膜晶体管，至少一个所述薄膜晶体管的有源层无晶界。
  6. 如权利要求1所述的半导体器件，其中，所述薄膜晶体管的有源层包括第一晶粒，所述第一晶粒与所述金属块对应设置，所述第一晶粒的数量与所述金属块的数量相等。
  7. 如权利要求6所述的半导体器件，其中，所述第一晶粒为圆形或者类圆形，所述第一晶粒的直径为1微米至5微米。
  8. 如权利要求6所述的半导体器件，其中，所述薄膜晶体管包括多个第一晶粒，所述金属层包括阵列设置的金属块，所述第一晶粒的晶界位于相邻两个金属块之间。
  9. 如权利要求8所述的半导体器件，其中，所述有源层包括沟道部和位于所述沟道部两侧的第一掺杂部和第二掺杂部，所述第一掺杂部及所述第二掺杂部沿着所述沟道部之间的连线的形状与所述薄膜晶体管的第一掺杂部和第二掺杂部对应的金属块沿所述沟道部的连线的形状相同。
  10. 如权利要求9所述的半导体器件，其中，所述第一掺杂部与所述第二掺杂部沿着所述沟道部之间的连线的形状为直线，所述金属块沿着所述直线阵列设置。
  11. 如权利要求10所述的半导体器件，其中，所述第一掺杂部与所述第二掺杂部位于同一水平线上，所述第一掺杂部及所述第二掺杂部沿着所述沟道部之间的连线的形状为折线，所述金属块沿着所述折线阵列设置。
  12. 如权利要求11所述的半导体器件，其中，所述沟道部包括设置于所述第一掺杂部的垂线方向的第一部分、设置于所述第二掺杂部的垂线方向的第二部分和与所述第一部分和所述第二部分垂直连接的第三部分，所述第一掺杂部及所述第二掺杂部沿着所述沟道部之间的连线沿着所述第一部分、所述第三部分和所述第二部分设置，所述金属块沿着所述第一部分、所述第三部分和所述第二部分阵列设置。
  13. 如权利要求11所述的半导体器件，其中，所述沟道部包括连接所述第一掺杂部和所述第二掺杂部的第四部分和第五部分，所述第四部分和所述第五部分垂直设置，所述金属块沿所述第四部分和所述第五部分的方向阵列设置。
  14. 如权利要求8所述的半导体器件，其中，所述第一晶粒的直径与相邻所述金属块的中心点之间的间距相等。
  15. 如权利要求8所述的半导体器件，其中，所述金属块的厚度范围为0.05微米至0.5微米。
  16. 如权利要求8所述的半导体器件，其中，所述金属块之间的间距为1微米至5微米。
  17. 如权利要求8所述的半导体器件，其中，所述金属块的宽度范围为0.5微米至2微米。
  18. 一种电子装置，其包括如权利要求1所述的半导体器件。
  19. 如权利要求18所述的电子装置，其中，所述电子装置包括液晶显示面板。
  20. 如权利要求18所述的电子装置，其中，所述电子装置包括有机发光二极管显示面板。
PCT/CN2022/108652 2022-07-08 2022-07-28 半导体器件和电子装置 Ceased WO2024007385A1 (zh)

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