WO2023010652A1 - 阵列基板及显示面板 - Google Patents
阵列基板及显示面板 Download PDFInfo
- Publication number
- WO2023010652A1 WO2023010652A1 PCT/CN2021/118026 CN2021118026W WO2023010652A1 WO 2023010652 A1 WO2023010652 A1 WO 2023010652A1 CN 2021118026 W CN2021118026 W CN 2021118026W WO 2023010652 A1 WO2023010652 A1 WO 2023010652A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- metal layer
- layer
- seed
- array substrate
- seed layer
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 115
- 229910052751 metal Inorganic materials 0.000 claims abstract description 217
- 239000002184 metal Substances 0.000 claims abstract description 217
- 239000013078 crystal Substances 0.000 claims abstract description 58
- 239000000463 material Substances 0.000 claims description 21
- 239000005078 molybdenum compound Substances 0.000 claims description 18
- 238000009826 distribution Methods 0.000 claims description 10
- UNQHSZOIUSRWHT-UHFFFAOYSA-N aluminum molybdenum Chemical compound [Al].[Mo] UNQHSZOIUSRWHT-UHFFFAOYSA-N 0.000 claims description 6
- ZPZCREMGFMRIRR-UHFFFAOYSA-N molybdenum titanium Chemical compound [Ti].[Mo] ZPZCREMGFMRIRR-UHFFFAOYSA-N 0.000 claims description 6
- MGRWKWACZDFZJT-UHFFFAOYSA-N molybdenum tungsten Chemical compound [Mo].[W] MGRWKWACZDFZJT-UHFFFAOYSA-N 0.000 claims description 6
- 229910052758 niobium Inorganic materials 0.000 claims description 5
- 239000010955 niobium Substances 0.000 claims description 5
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 238000002425 crystallisation Methods 0.000 abstract description 18
- 230000008025 crystallization Effects 0.000 abstract description 18
- 239000002800 charge carrier Substances 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 314
- 238000000034 method Methods 0.000 description 10
- 230000001427 coherent effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910016027 MoTi Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ZXTFQUMXDQLMBY-UHFFFAOYSA-N alumane;molybdenum Chemical compound [AlH3].[Mo] ZXTFQUMXDQLMBY-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
Definitions
- the present application relates to the display field, in particular to an array substrate and a display panel.
- Liquid crystal display Liquid Crystal Display, LCD
- LCD Liquid Crystal Display
- LTPS Low Temperature Poly-Silicon, low temperature polysilicon
- the first metal layer wires in the LTPS thin film transistor display products are limited by the high temperature process, if it needs to be around 600 degrees Celsius, molybdenum (Mo) metal is mostly used in the industry at present.
- Mo metal resistance is high, and it does not take advantage of the high charging rate product demand of high-resolution, high-frequency medium-sized products.
- the present application provides an array substrate and a display panel, which can reduce the resistivity of the first metal layer.
- the present application provides an array substrate, including: a substrate, a seed layer disposed on one side of the substrate, and a first metal layer disposed on the seed layer side and away from the substrate;
- the first metal layer is in direct contact with the seed layer.
- the lattice structure of the first metal layer is the same as the lattice structure of the seed crystal layer.
- the ratio between the difference between the lattice constant of the first metal layer and the lattice constant of the seed crystal layer and the lattice constant of the first metal layer is between Within 20%.
- the lattice constant of the first metal layer is the same as the lattice constant of the seed crystal layer.
- the lattice structure of the first metal layer and the seed layer is a body-centered cubic lattice, and the lattice constant is 3.14pm.
- the thickness of the seed layer is in the range of 50 to 1000 angstroms, and the material of the seed layer can be tungsten, niobium, tantalum, tungsten-molybdenum compound, aluminum-molybdenum compound or titanium-molybdenum compound. at least one.
- the distribution density of crystal grains in the seed crystal layer is greater than the distribution density of crystal grains in the first metal layer.
- the grain size of the first metal layer close to the seed layer is larger than the grain size of the first metal layer far away from the seed layer.
- the array substrate further includes a second metal layer located on the first metal layer, the second metal layer is made of the same material as the first metal layer, and the second metal layer is made of the same material as the first metal layer.
- the grain size of the metal layer is smaller than the grain size of the first metal layer.
- the embodiment of the present application also provides a display panel, the display panel includes an array substrate, and the array substrate includes: a substrate, a seed layer arranged on one side of the substrate, and a seed layer arranged on one side of the seed layer. side and away from the first metal layer of the substrate;
- the first metal layer is in direct contact with the seed layer.
- the lattice structure of the first metal layer is the same as the lattice structure of the seed crystal layer.
- the ratio between the difference between the lattice constant of the first metal layer and the lattice constant of the seed crystal layer and the lattice constant of the first metal layer is between Within 20%.
- the lattice constant of the first metal layer is the same as the lattice constant of the seed crystal layer.
- the lattice structure of the first metal layer and the seed layer is a body-centered cubic lattice, and the lattice constant is 3.14pm.
- the thickness of the seed layer ranges from 50 to 1000 angstroms.
- the distribution density of crystal grains in the seed crystal layer is greater than the distribution density of crystal grains in the first metal layer.
- the grain size of the first metal layer close to the seed layer is larger than the grain size of the first metal layer far away from the seed layer.
- the array substrate further includes a second metal layer located on the first metal layer, the second metal layer is made of the same material as the first metal layer, and the second metal layer is made of the same material as the first metal layer.
- the grain size of the metal layer is smaller than the grain size of the first metal layer.
- the material of the seed layer is at least one of tungsten, niobium, tantalum, tungsten-molybdenum compound, aluminum-molybdenum compound or titanium-molybdenum compound.
- the present application proposes an array substrate and a display panel, wherein the array substrate includes a substrate, a seed layer disposed on one side of the substrate, and a seed layer disposed on the side of the seed layer and away from the substrate.
- the first metal layer wherein the first metal layer is in direct contact with the seed layer
- the present application utilizes the seed layer in direct contact with the first metal layer to induce the crystallization of the metal in the first metal layer, so that the crystal formed by the first metal layer
- the grains are larger, the grain boundaries are less, the charge carriers are less scattered, and the resistivity of the first metal layer is reduced.
- the resistivity of the first metal layer is reduced without adding a photomask.
- FIG. 1 is a schematic structural diagram of an array substrate in the prior art
- FIG. 2 is a schematic structural diagram of an array substrate provided in an embodiment of the present application.
- FIG. 3 is another schematic structural view of the array substrate provided by the embodiment of the present application.
- Fig. 4 is a comparative schematic diagram of the grain size of the first metal layer provided by the embodiment of the present application.
- FIG. 5 is a schematic flowchart of a method for manufacturing an array substrate provided in an embodiment of the present application.
- FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
- first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
- a feature defined as “first” or “second” may explicitly or implicitly include one or more of said features.
- “plurality” means two or more, unless otherwise specifically defined.
- connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected, or electrically connected, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction of two components relation. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific situations.
- a first feature being "on” or “under” a second feature may include direct contact between the first and second features, and may also include the first and second features Not in direct contact but through another characteristic contact between them.
- “above”, “above” and “above” the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature.
- “Below”, “beneath” and “under” the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.
- the wires of the first metal layer in the display panel are limited by the high-temperature process, and molybdenum metal is mostly used at present.
- the array substrate 100 includes a substrate 110 and a first metal layer 130 disposed on the substrate 110 .
- the material of the first metal layer 130 is Mo metal.
- the high impedance of Mo metal is not conducive to the product demand for high-resolution, high-frequency, medium-sized products and high charging rates.
- the present application proposes the following technical solutions to solve the above technical problems.
- FIG. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
- the array substrate 100 includes a substrate 110, a seed layer 120 disposed on one side of the substrate 110, and a first metal layer 130 disposed on the side of the seed layer 120 and away from the substrate 110, the first metal layer 130 and the seed layer Layers 120 are in direct contact.
- the substrate 110 may be a rigid substrate or a flexible substrate.
- the material for making the substrate 101 includes glass, quartz or polyimide and the like.
- the grain size of the first metal layer 130 is larger than the first threshold.
- the first threshold is the grain size of the first metal layer 130 when no seed layer 120 is provided. Assuming that the grain size of the first metal layer 130 is 27.5 nm when the seed layer 120 is not provided, the first threshold value is 27.5 nm.
- the Mo metal grows on the seed layer 120 , that is, the crystallization of the first metal layer 130 is induced by the seed layer 120 .
- the crystal grains formed in the first metal layer 130 are larger, the grain boundaries are less, the scattering of charge carriers is less, and the resistivity of the first metal layer 130 is reduced.
- the resistivity of the first metal layer 130 is reduced without changing the machine or adding a photomask, providing a high-temperature-resistant and low-resistance first metal layer solution for medium and large-sized display products, and improving the display panel. competitiveness.
- the array substrate 100 includes a substrate 110 , a light shielding layer 111 , a buffer layer 112 , a semiconductor layer 113 , a gate insulating layer 114 , a seed layer 120 , a first metal layer 130 , and an interlayer insulating layer arranged in sequence. layer 115 and a second metal layer 116 .
- the array substrate 100 may further include other more film layers.
- the light-shielding layer 111 is disposed on the substrate 110 , and the light-shielding layer 111 is patterned. Patterning means that the material of the light-shielding layer coated on the entire substrate 110 is processed through processes such as exposure and etching, and a patterned light-shielding layer 111 is finally formed.
- the material of the light-shielding layer 111 is, for example, molybdenum-aluminum alloy, chromium metal, molybdenum metal, or other materials having both light-shielding function and conductive property.
- the buffer layer 112 is disposed on the light shielding layer 111 and the substrate 110 .
- the semiconductor layer 113 is disposed on the buffer layer 112 , and the semiconductor layer 113 is an active layer formed by patterning.
- the gate insulating layer 114 is disposed on the semiconductor layer 113 and the buffer layer 112 , and the gate insulating layer 114 may be made of silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiNxOy).
- the seed layer 120 is disposed on the gate insulating layer 114 , the first metal layer 130 is formed on the seed layer 120 , and then the first metal layer 130 is exposed and etched to form a patterned first metal layer 130 .
- the patterned first metal layer 130 includes a gate layer.
- the material for making the first metal layer is a high temperature resistant conductive material, such as metal Mo.
- the interlayer insulating layer 115 is disposed on the first metal layer 130 and the gate insulating layer 114, the second metal layer 116 is formed on the interlayer insulating layer, and then the second metal layer 116 is exposed and etched to form a patterned The second metal layer 116 .
- the patterned second metal layer 116 includes source and drain layers.
- the lattice structure of the seed layer 120 is the same as that of the first metal layer 130 .
- the lattice structure is body-centered cubic lattice, face-centered cubic lattice or hexagonal close-packed lattice.
- the seed layer 120 and the first metal layer 130 use the same lattice structure, which improves the effect of the seed layer 120 in inducing metal crystallization in the first metal layer 130 .
- the lattice constant of the seed layer 120 is similar to that of the first metal layer 130 .
- the lattice constant refers to the side length of the unit cell, that is, the side length of each parallelepiped unit.
- the ratio of the difference between the lattice constant of the first metal layer 130 and the lattice constant of the seed layer 120 to the lattice constant of the first metal layer 130 is within 20%.
- the lattice constant of the seed layer 120 is the same as the lattice constant of the first metal layer 130 .
- Using the seed layer 120 with a similar/same lattice constant as the first metal layer 130 can improve the effect of the lattice constant of the seed layer and metal crystallization in the first metal layer 130 .
- the lattice structure of the seed layer 120 is the same as that of the first metal layer 130 , and the lattice constant of the seed layer 120 is similar/same as that of the first metal layer 130 .
- the first metal The crystallization effect of the metal in the layer 130 is the best, such as the order of the induced crystallization is the best, the formed grain size is the largest, the grain is the most uniform, and the junction is the smallest, the scattering of the charge carrier is the least, and the maximum degree of reduction resistivity of the first metal layer 130 .
- the lattice structures of the first metal layer 130 and the seed layer 120 are both body-centered cubic lattices, and the lattice constants of the first metal layer 130 and the seed layer 120 are both 3.14 picometers (pm).
- the above-mentioned seed layer 120 has a thickness ranging from 50 to 1000 angstroms.
- the thickness of the first metal layer 130 can be determined according to the actual requirements of the array substrate, and the thickness of the first metal layer 130 is inversely proportional to the resistance. After the thickness of the seed layer 120 reaches a certain thickness, such as the thickness corresponding to the above-mentioned thickness range, the change of the resistivity caused by increasing the thickness is not large, and the thickness of the array substrate 100 will be increased, and the cost will be increased.
- the material of the aforementioned seed layer 120 may be at least one of tungsten, niobium, tantalum, tungsten-molybdenum compound, aluminum-molybdenum compound or titanium-molybdenum compound.
- the tungsten-molybdenum compound includes MoW 50
- the aluminum-molybdenum compound includes MoAl 20
- the titanium-molybdenum compound includes MoTi 50 and the like.
- the grain size in the seed crystal layer 120 is smaller than the crystal grain size in the first metal layer 130, correspondingly, the seed crystal layer
- the distribution density of crystal grains in 120 is greater than the distribution density of crystal grains in the first metal layer 130 .
- the grain size of the first metal layer 130 close to the seed layer 120 is larger than the grain size of the first metal layer 130 away from the seed layer 120 . This is because the crystal grains in the first metal layer close to the seed crystal layer 120 are crystallized first, and the crystal grains with larger sizes will also drop due to gravity.
- the array substrate further includes the second metal layer 116 located on the first metal layer 130.
- the first metal layer 130 and the second metal layer 116 are made of the same material, such as Mo, because The seed layer 120 is used in the first metal layer 130 to induce metal crystallization, so that the grain size of the second metal layer 116 is smaller than the grain size of the first metal layer 130 .
- the second metal layer 116 can be The first metal layer 130 overlaps to form a capacitor.
- the first metal layer 130 may be a gate layer, and the second metal layer 116 is also a metal layer, but not a source-drain layer.
- the crystal grains close to the seed layer 120 are larger and more evenly distributed, and the crystal grains farther away from the seed layer 120 are smaller and less uniform.
- the grain size in the middle area is larger than the grain size in the two sides, so that the impedance of the edge area is greater than the impedance of the middle area to avoid overloading, which is equivalent to making the first metal layer in the edge area
- a metal layer acts as a protective layer.
- the seed crystal layer 120 is used to induce the crystallization of the first metal layer 130.
- the crystal grains in the formed first metal layer 130 are larger and the grain boundaries are less.
- the charge carriers scatter, reducing the impedance of the first metal layer 130 .
- using the seed layer 120 to induce crystallization of the first metal layer 130 can reduce the impedance in the first metal layer 130 by 30% compared with that without using the seed layer 120, thereby obtaining an array substrate with high temperature resistance and reduced impedance.
- the corresponding coherent diffraction line size (coherently) for measuring the grain size in the first metal layer 130 diffracting domain size) is larger than the coherent diffraction line size corresponding to the non-used seed layer 120 .
- the larger the size of the coherent diffraction line the larger the crystal grain, and the smaller the corresponding resistivity.
- the crystallization of the first metal layer 130 is induced by using the seed crystal layer 120 , and the grain size of the obtained first metal layer 130 is larger than that corresponding to that without the seed crystal layer 120 .
- Table 1 below.
- the coherent diffraction line size corresponding to the use of the seed crystal layer 120 is 62.7nm, and the grain size is 38.7nm; while the coherent diffraction line size corresponding to the use of the seed crystal layer 120 is 48.7nm, The grain size is 27.5nm. It should be noted that the sizes shown in Table 1 and the examples of the present application are all average sizes, and the sizes shown are also average sizes.
- the size corresponding to the use of the seed layer 120 is larger than the size corresponding to the use of the seed layer 120 .
- the seed crystal layer 120 is used to induce crystallization of the first metal layer 130 , so that the crystal grains formed in the first metal layer are larger, with fewer grain boundaries, less scattering of charge carriers, and lower resistivity of the first metal layer.
- FIG. 4 it is a schematic diagram of the comparison of the grain size of the first metal layer provided by the embodiment of the present application.
- the longer horizontal line is a reference line
- the distance between two irregular vertical lines represents the distance between grain boundaries, corresponding to the grain size.
- the left figure corresponds to the grain size in the first metal layer without using the seed crystal layer 120
- the right figure corresponds to the grain size in the first metal layer corresponding to the seed crystal layer 120 . It can be seen that the (average) grain size in the right graph is larger than the (average) grain size in the left graph.
- the Mo metal in the first metal layer 130 grows on the seed crystals of the seed layer 120, and the seed layer 120 is used to induce the crystallization of the Mo metal, so that in the first metal layer 130
- the crystal grains become larger, the grain boundaries become less, and the charge carriers at the grain boundaries scatter less, which reduces the scattering of charge carriers and reduces the resistivity of the first metal layer 130 .
- the resistivity of the first metal layer 130 is reduced without changing the machine and without adding a photomask.
- FIG. 5 is a schematic flowchart of a method for manufacturing an array substrate provided in an embodiment of the present application.
- the manufacturing method of the array substrate includes the following steps.
- a seed layer 120 is deposited on the substrate 110 using a first temperature.
- the power of the corresponding construction equipment should be above 40kw, and the pressure when depositing the seed crystal layer 120 should be below 0.4pa.
- the first temperature may be any temperature between 150 and 300 degrees, such as 200 degrees.
- the seed layer 120 may be formed using a physical vapor deposition process or a magnetron sputtering process.
- the seed layer 120 and the first metal layer 130 may be formed using different temperatures in different chambers.
- the first temperature is higher than the second temperature, so that the formed seed layer 120 has better compactness, fewer defects, and better crystal form, which is beneficial to the growth of Mo crystal grains in the first metal layer 130 .
- the first metal layer 130 directly contacts the seed layer 120 , and the seed layer 120 is used to induce metal crystallization in the first metal layer 130 , which is beneficial to the growth of Mo grains in the first metal layer 130 .
- a seed layer is formed, and the first metal layer 130 is formed on the seed layer, and the seed layer is used to induce the crystallization of the metal in the first metal layer, so that Larger grains, fewer grain boundaries, less scattering of charge carriers, lower resistivity of the first metal layer.
- the resistivity of the first metal layer 130 is reduced without changing the machine tool or adding a mask.
- a light shielding layer 111, a buffer layer 112, a semiconductor layer 113, and a gate insulating layer 114 are sequentially formed on the substrate 110, a seed layer 120 is formed on the gate insulating layer 114, and a seed layer 120 is formed on the seed layer 120.
- a first metal layer 130 is formed, and the first metal layer 130 is patterned to obtain a patterned first metal layer 130 .
- an interlayer insulating layer 115 and a second metal layer 116 are sequentially formed.
- An embodiment of the present application further provides a display panel, which includes the array substrate corresponding to any one of the above embodiments.
- a display panel which includes the array substrate corresponding to any one of the above embodiments.
- the display panel further includes a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color filter substrate.
- the display panel further includes a light-emitting layer disposed on the array substrate, and the light-emitting layer may include OLED (Organic Light-Emitting Diode, organic light-emitting semiconductor) light-emitting devices, mini-LEDs, micro-LEDs, etc. either.
- OLED Organic Light-Emitting Diode, organic light-emitting semiconductor
- FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
- the display panel 1000 includes an array substrate 100 , a color filter substrate 300 disposed opposite to the array substrate, and a liquid crystal layer 200 located between the array substrate 100 and the color filter substrate 300 .
- the present application proposes an array substrate, a manufacturing method of the array substrate, and a display panel, wherein the array substrate includes a substrate, a seed layer disposed on one side of the substrate, and a seed layer disposed on the side of the seed layer and away from the substrate.
- the first metal layer wherein the grain size of the first metal layer is greater than a first threshold.
- the present application only uses the seed crystal layer to induce the crystallization of the metal in the first metal layer, so that the crystal grains formed by the first metal layer are larger and have fewer grain boundaries, which is beneficial to the electric current. Carrier scattering is less, the resistivity of the first metal layer is reduced, and a high-temperature-resistant and low-resistance first metal layer solution is provided for medium and large-sized display products, which improves the competitiveness of the display panel.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Manufacturing & Machinery (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
本申请公开了一种阵列基板及显示面板,其中,阵列基板包括衬底,设置于衬底一侧的种晶层,以及设置于种晶层一侧且远离衬底的第一金属层,第一金属层与种晶层直接接触,本申请利用与第一金属层直接接触的种晶层诱导第一金属层结晶,使得第一金属层形成的晶粒较大,晶界较少,对电荷载流子散射更少,降低第一金属层的电阻率。
Description
本申请涉及显示领域,特别涉及一种阵列基板及显示面板。
液晶显示器(Liquid Crystal
Display,LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点,而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品,成为显示装置中的主流。LCD有A-Si(非晶硅)薄膜晶体管/LTPS(Low Temperature Poly-Silicon,低温多晶硅)薄膜晶体管对应的两种显示技术,LTPS薄膜晶体管由于具有高迁移率的优点,被广泛用于高规格面板技术。
LTPS薄膜晶体管的显示产品中的第一金属层导线受限于高温制程,如需要600摄氏度左右,目前业界中大多使用钼(Mo)金属。然而Mo金属阻抗较高,不利用高分辨率、高频率中尺寸产品的高充电率的产品需求。
本申请提供一种阵列基板及显示面板,可降低第一金属层的电阻率。
本申请提供了一种阵列基板,包括:衬底,设置于所述衬底一侧的种晶层,以及设置于所述种晶层一侧且远离所述衬底的第一金属层;
其中,所述第一金属层与所述种晶层直接接触。
在本申请的阵列基板中,所述第一金属层中的晶格结构与所述种晶层的晶格结构相同。
在本申请的阵列基板中,所述第一金属层的晶格常数与所述种晶层的晶格常数之间的差值,与所述第一金属层的晶格常数之间的比例在20%以内。
在本申请的阵列基板中,所述第一金属层的晶格常数与所述种晶层的晶格常数相同。
在本申请的阵列基板中,所述第一金属层和所述种晶层的晶格结构为体心立方晶格,所述晶格常数为3.14pm。
在本申请的阵列基板中,所述种晶层的厚度范围为50至1000埃,所述种晶层的材料可以为钨、铌、钽、钨钼化合物、铝钼化合物或钛钼化合物中的至少一者。
在本申请的阵列基板中,所述种晶层中晶粒的分布密度大于所述第一金属层中晶粒的分布密度。
在本申请的阵列基板中,靠近所述种晶层的所述第一金属层的晶粒尺寸大于远离所述种晶层的所述第一金属层的晶粒尺寸。
在本申请的阵列基板中,所述阵列基板还包括位于所述第一金属层上的第二金属层,制作所述第二金属层和所述第一金属层的材料相同,所述第二金属层的晶粒尺寸小于所述第一金属层的晶粒尺寸。
本申请实施例还提供一种显示面板,所述显示面板包括阵列基板,所述阵列基板包括:衬底,设置于所述衬底一侧的种晶层,以及设置于所述种晶层一侧且远离所述衬底的第一金属层;
其中,所述第一金属层与所述种晶层直接接触。
在本申请的阵列基板中,所述第一金属层中的晶格结构与所述种晶层的晶格结构相同。
在本申请的阵列基板中,所述第一金属层的晶格常数与所述种晶层的晶格常数之间的差值,与所述第一金属层的晶格常数之间的比例在20%以内。
在本申请的阵列基板中,所述第一金属层的晶格常数与所述种晶层的晶格常数相同。
在本申请的阵列基板中,所述第一金属层和所述种晶层的晶格结构为体心立方晶格,所述晶格常数为3.14pm。
在本申请的阵列基板中,所述种晶层的厚度范围为50至1000埃。
在本申请的阵列基板中,所述种晶层中晶粒的分布密度大于所述第一金属层中晶粒的分布密度。
在本申请的阵列基板中,靠近所述种晶层的所述第一金属层的晶粒尺寸大于远离所述种晶层的所述第一金属层的晶粒尺寸。
在本申请的阵列基板中,所述阵列基板还包括位于所述第一金属层上的第二金属层,制作所述第二金属层和所述第一金属层的材料相同,所述第二金属层的晶粒尺寸小于所述第一金属层的晶粒尺寸。
在本申请的阵列基板中,所述种晶层的材料为钨、铌、钽、钨钼化合物、铝钼化合物或钛钼化合物中的至少一者。
本申请提出了阵列基板及显示面板,其中,所述阵列基板包括衬底,设置于所述衬底一侧的种晶层,以及设置于所述种晶层一侧且远离所述衬底的第一金属层,其中,第一金属层与种晶层直接接触,本申请利用与第一金属层直接接触的种晶层诱导第一金属层的金属的结晶,使得第一金属层形成的晶粒较大,晶界较少,对电荷载流子散射更少,降低第一金属层的电阻率,本申请实施例在不增加光罩的前提下,降低第一金属层的电阻率。
为了更清楚地说明本申请实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为现有技术中阵列基板的结构示意图;
图2为本申请实施例提供的阵列基板的结构示意图;
图3为本申请实施例提供的阵列基板的另一结构示意图;
图4为本申请实施例提供的第一金属层的晶粒尺寸的对比示意图;
图5为本申请实施例提供的阵列基板的制作方法的流程示意图;
图6为本申请实施例提供的显示面板的结构示意图。
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述。显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
在本申请的描述中,需要理解的是,术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本申请和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本申请的限制。此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中,“多个”的含义是两个或两个以上,除非另有明确具体的限定。
在本申请的描述中,需要说明的是,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接或可以相互通讯;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中,除非另有明确的规定和限定,第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触,也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且,第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方,或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方,或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开,下文中对特定例子的部件和设置进行描述。当然,它们仅仅为示例,并且目的不在于限制本申请。此外,本申请可以在不同例子中重复参考数字和/或参考字母,这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施方式和/或设置之间的关系。此外,本申请提供了的各种特定的工艺和材料的例子,但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
现有技术中,显示面板中的第一金属层导线受限于高温制程,目前大多使用的是钼金属。如图1所示,阵列基板100包括衬底110,以及设置于衬底110之上的第一金属层130。其中,制成第一金属层130的材料为Mo金属。然而Mo金属阻抗较高,不利于高分辨率、高频率中尺寸产品的高充电率的产品需求。本申请提出了下列技术方案以解决上述技术问题。
图2是本申请实施例提供的阵列基板的结构示意图。阵列基板100包括衬底110,设置于衬底110一侧的种晶层120,以及设置于种晶层120一侧且远离衬底110的第一金属层130,第一金属层130与种晶层120直接接触。其中,衬底110可以是刚性衬底基板,也可以是柔性衬底基板。制成衬底101的材料包括玻璃、石英或者聚酰亚胺等。
其中,第一金属层130的晶粒尺寸大于第一阈值。第一阈值为未设置种晶层120时形成第一金属层130的晶粒尺寸。假设未设置种晶层120时形成第一金属层130的晶粒尺寸为27.5nm,则第一阈值为27.5nm。
该实施例通过设置与第一金属层130直接接触的种晶层120,使得Mo金属在种晶层120上生长,即利用种晶层120诱导第一金属层130的结晶。如此,使得第一金属层130形成的晶粒较大,晶界较少,对电荷载流子散射更少,降低第一金属层130的电阻率。
本申请中在不改变机台,不增加光罩的前提下,降低了第一金属层130的电阻率,为中大尺寸显示产品提供耐高温低阻的第一金属层的方案,提升显示面板的竞争力。
以下以任一一薄膜晶体管为例来说明本申请中的阵列基板的结构。如图3所示,阵列基板100包括依次层叠设置的衬底110、遮光层111、缓冲层112、半导体层113、栅极绝缘层114、种晶层120、第一金属层130、层间绝缘层115以及第二金属层116。在其他实施例中,阵列基板100还可以包括其他更多的膜层。
其中,遮光层111设置于衬底110之上,遮光层111是经过图案化后的。图案化是指通过对涂于整个衬底110上的遮光层材料进行曝光刻蚀等工艺加工而成,最终形成图案化的遮光层111。遮光层111的材质例如为钼铝合金、铬金属、钼金属或是其它同时具有遮光功能与导电性质的材质。缓冲层112设置于遮光层111和衬底110之上。半导体层113设置于缓冲层112之上,半导体层113是经过图案化形成的有源层。栅极绝缘层114设置于半导体层113和缓冲层112之上,栅极绝缘层114可以采用氧化硅(SiOx)、氮化硅(SiNx)或氮氧化硅(SiNxOy)等材料制成。
种晶层120设置于栅极绝缘层114之上,在种晶层120之上形成第一金属层130,然后对第一金属层130进行曝光蚀刻以形成图案化的第一金属层130。图案化的第一金属层130包括栅极层。其中,制成第一金属层的材料为耐高温的导电材料,如金属Mo。
层间绝缘层115设置于第一金属层130和栅极绝缘层114之上,在层间绝缘层之上形成第二金属层116,然后对第二金属层116进行曝光蚀刻以形成图案化的第二金属层116。图案化的第二金属层116包括源漏极层。
在一实施例中,种晶层120的晶格结构与第一金属层130的晶格结构相同。如晶格结构都为体心立方晶格或者面心立方晶格或者密排六方晶格。种晶层120和第一金属层130使用同一种晶格结构,提高种晶层120诱导第一金属层130中金属结晶的效果。
在一实施例中,种晶层120的晶格常数与第一金属层130的晶格常数相近。其中,晶格常数指的是晶胞的边长,也就是每一个平行六面体单元的边长。例如,第一金属层130的晶格常数与种晶层120的晶格常数之间的差值,与第一金属层130的晶格常数之间的比例在20%以内。在一些情况下,种晶层120的晶格常数与第一金属层130的晶格常数相同。
使用与第一金属层130的晶格常数相近/相同的种晶层120,提高种晶层的晶格常数与第一金属层130中金属结晶的效果。
在一实施例中,种晶层120的晶格结构与第一金属层130的晶格结构相同,且种晶层120的晶格常数与第一金属层130的晶格常数相近/相同。尤其是在种晶层120的晶格结构与第一金属层130的晶格结构相同,且种晶层120的晶格常数与第一金属层130的晶格常数相同的情况下,第一金属层130中金属的结晶效果最好,如诱导结晶的有序性最好,形成的晶粒尺寸最大,晶粒最均匀,且结界最小,对电荷载流子散射最少,最大程度的降低了第一金属层130的电阻率。
例如,第一金属层130和种晶层120的晶格结构均为体心立方晶格,第一金属层130和种晶层120的晶格常数均为3.14皮米(pm)。
上述所述的种晶层120的厚度范围为50至1000埃。其中,第一金属层130的厚度可根据实际所需的阵列基板的需求来确定,第一金属层130的厚度和电阻成反比。而种晶层120的厚度在达到一定厚度后,如上述厚度范围所对应的厚度,再增加厚度所带来的电阻率的变化不大,且会增加阵列基板100的厚度,以及增加成本。
上述所述的种晶层120的材料可以为钨、铌、钽、钨钼化合物、铝钼化合物或钛钼化合物中的至少一者。其中,钨钼化合物包括MoW
50,铝钼化合物包括MoAl
20、MoAl
20Ti
10,钛钼化合物包括MoTi
50等。
上述实施例中,由于种晶层120诱导第一金属层130中的金属结晶,因此,种晶层120中的晶粒尺寸小于第一金属层130中的晶粒尺寸,对应地,种晶层120中晶粒的分布密度大于第一金属层130中晶粒的分布密度。
上述实施例中,在第一金属层130中,靠近种晶层120的第一金属层130的晶粒尺寸大于远离种晶层120的第一金属层130的晶粒尺寸。这是因为靠近种晶层120的第一金属层中的晶粒先进行结晶,且尺寸较大的晶粒也会因为重力原因下降。
上述实施例中,阵列基板中还包括位于第一金属层130之上的第二金属层116,当制作第一金属层130和第二金属层116的材料相同时,如都为Mo时,由于第一金属层130中使用种晶层120来诱导金属结晶,因此,第二金属层116的晶粒尺寸小于第一金属层130的晶粒尺寸。
在第一金属层130和第二金属层116的材料相同且第二金属层116的晶粒尺寸小于第一金属层130的晶粒尺寸时,在一实施例中,第二金属层116可以与第一金属层130重叠,用于形成电容。在该实施例中,第一金属层130可以为栅极层,第二金属层116也为金属层,但不为源漏极层。
在一实施例中,第一金属层130中,靠近种晶层120的晶粒较大且分布更均匀,远离种晶层120的晶粒较小且均匀度较小。
在一实施例中,第一金属层130中,中间区域的晶粒大小大于两侧的晶粒大小,如此,实现边缘区的阻抗大于中间区域的阻抗,避免过载,相当于将边缘区的第一金属层作为保护层。
上述阵列基板100中,采用种晶层120诱导第一金属层130结晶,与未采用种晶层120相比,所形成的第一金属层130中的晶粒更大,晶界处更少的电荷载流子散射,降低了第一金属层130的阻抗。其中,采用种晶层120诱导第一金属层130结晶,与未采用种晶层120相比,可以将第一金属层130中的阻抗降低30%,从而得到耐高温且阻抗降低的阵列基板。
采用种晶层120诱导第一金属层130结晶,所对应的测量第一金属层130中的晶粒尺寸的相干衍射线尺寸(coherently
diffracting domain size)要大于未采用种晶层120所对应的相干衍射线尺寸。其中,相干衍射线尺寸越大,晶粒越大,所对应的电阻率越小。而且,采用种晶层120诱导第一金属层130结晶,所得到的第一金属层130的晶粒尺寸大于未采用种晶层120所对应的晶粒尺寸。具体请参看如下表1所示。
表1 采用种晶层和未采用种晶层所对应的衍射线尺寸和晶粒尺寸对比
薄膜层 | 相干衍射线尺寸(nm) | 晶粒大小(nm) |
第一金属层(Mo) | 48.7 | 27.5 |
种晶层+第一金属层(Mo) | 62.7 | 38.7 |
从表1中可以看出,采用种晶层120时所对应的相干衍射线尺寸为62.7nm,晶粒大小为38.7nm;而未采用种晶层120所对应的相干衍射线尺寸为48.7nm,晶粒大小为27.5nm。需要注意的是,表1中以及本申请实施例中所示的尺寸均为平均尺寸、所示的大小也为平均大小。
无论是相干衍射线尺寸还是晶粒大小,采用种晶层120时对应的尺寸比不采用种晶层120所对应的尺寸都要大。采用种晶层120诱导第一金属层130结晶,使得第一金属层形成的晶粒较大,晶界较少,对电荷载流子散射更少,降低第一金属层的电阻率。
如图4所示,为本申请实施例提供的第一金属层的晶粒尺寸的对比示意图。图2中,较长的横线为参考线,不规则的两条竖线之间表示晶界之间的距离,对应晶粒尺寸。左图对应的是未使用种晶层120所对应的第一金属层中的晶粒尺寸,右图对应的是使用种晶层120所对应的第一金属层中的晶粒尺寸。可以看出,右图中的(平均)晶粒尺寸大于左图中的(平均)晶粒尺寸。
上述实施例中,通过设置种晶层120,实现第一金属层130中的Mo金属在种晶层120的晶种上生长,利用种晶层120诱导Mo金属结晶,使得第一金属层130中的晶粒变大,晶界变少,晶界处的电荷载流子散射更少,降低了对电荷载流子的散射,降低了第一金属层130的电阻率。本申请实施例在不改变机台,不增加光罩的前提下,降低了第一金属层130的电阻率。
图5是本申请实施例提供的阵列基板的制作方法的流程示意图。该阵列基板的制作方法包括如下步骤。
S101,提供一衬底。
S102,在衬底上利用第一温度形成种晶层。
在衬底110上利用第一温度沉积种晶层120。沉积种晶层120时,所对应的建设设备的功率要在40kw以上,且沉积种晶层120时的压力要在0.4pa以下。
第一温度可以是150至300度之间的任一一个温度,如200度等。
具体地,可使用物理气相沉积工艺或者磁控溅射工艺等形成种晶层120。
S103,在种晶层远离衬底的一侧利用第二温度形成第一金属层,其中,第一温度大于第二温度,第一金属层直接接触种晶层。
由于形成种晶层的第一温度大于形成第一金属层的第二温度,可在不同腔室中利用不同温度来形成种晶层120和第一金属层130。
其中,第一温度大于第二温度,使得形成的种晶层120的致密性较好,缺陷少,晶型更好,有利于第一金属层130的Mo晶粒的生长。第一金属层130直接接触种晶层120,利用种晶层120诱导第一金属层130中的金属结晶,有利于第一金属层130的Mo晶粒的生长。
该实施例中形成的阵列基板100通过形成种晶层,并在种晶层上形成第一金属层130,利用种晶层诱导第一金属层的金属的结晶,使得第一金属层形成的晶粒较大,晶界较少,对电荷载流子散射更少,降低第一金属层的电阻率。该实施例在不改变机台,不增加光罩的前提下,降低了第一金属层130的电阻率。
在其他实施例中,在衬底110上依次形成遮光层111、缓冲层112、半导体层113、栅极绝缘层114,在栅极绝缘层114上形成种晶层120,在种晶层120上形成第一金属层130,对第一金属层130进行图案化,以得到图案化的第一金属层130。在图案化的第一金属层130和栅极绝缘层114之上,依次形成层间绝缘层115以及第二金属层116。
本申请实施例还提供了一种显示面板,该显示面板包括上述任一实施例所对应的阵列基板,阵列基板的内容和对应的有益效果请参看上述实施例中的描述。
在一实施例中,显示面板还包括与阵列基板相对设置的彩膜基板、以及位于阵列基板和彩膜基板之间的液晶层。
在一实施例中,显示面板还包括设置于阵列基板上的发光层,所述发光层可以包括OLED(Organic Light-Emitting Diode,有机发光半导体)发光器件、mini-LED、micro-LED等中的任一者。
图6是本申请实施例提供的显示面板的结构示意图。显示面板1000包括阵列基板100、与阵列基板相对设置的彩膜基板300、以及位于阵列基板100和彩膜基板300之间的液晶层200。
本申请提出了一种阵列基板、阵列基板的制作方法及显示面板,其中,阵列基板包括衬底,设置于衬底一侧的种晶层,以及设置于种晶层一侧且远离衬底的第一金属层,其中,第一金属层的晶粒尺寸大于第一阈值。本申请在不改变机台,不增加光罩的前提下,仅利用种晶层诱导第一金属层的金属的结晶,使得第一金属层形成的晶粒较大,晶界较少,对电荷载流子散射更少,降低第一金属层的电阻率,为中大尺寸显示产品提供耐高温低阻的第一金属层的方案,提升显示面板的竞争力。
在上述实施例中,对各个实施例的描述都各有侧重,某个实施例中没有详述的部分,可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种电子装置进行了详细介绍,本文中应用了具体个例对本申请的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想;本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。
Claims (20)
- 一种阵列基板,其包括:衬底,设置于所述衬底一侧的种晶层,以及设置于所述种晶层一侧且远离所述衬底的第一金属层;其中,所述第一金属层与所述种晶层直接接触。
- 根据权利要求1所述的阵列基板,其中,所述第一金属层中的晶格结构与所述种晶层的晶格结构相同。
- 根据权利要求2所述的阵列基板,其中,所述第一金属层的晶格常数与所述种晶层的晶格常数之间的差值,与所述第一金属层的晶格常数之间的比例在20%以内。
- 根据权利要求3所述的阵列基板,其中,所述第一金属层的晶格常数与所述种晶层的晶格常数相同。
- 根据权利要求4所述的阵列基板,其中,所述第一金属层和所述种晶层的晶格结构为体心立方晶格,所述晶格常数为3.14pm。
- 根据权利要求1所述的阵列基板,其中,所述种晶层的厚度范围为50至1000埃。
- 根据权利要求1所述的阵列基板,其中,所述种晶层中晶粒的分布密度大于所述第一金属层中晶粒的分布密度。
- 根据权利要求1所述的阵列基板,其中,靠近所述种晶层的所述第一金属层的晶粒尺寸大于远离所述种晶层的所述第一金属层的晶粒尺寸。
- 根据权利要求1所述的阵列基板,其中,所述阵列基板还包括位于所述第一金属层上的第二金属层,制作所述第二金属层和所述第一金属层的材料相同,所述第二金属层的晶粒尺寸小于所述第一金属层的晶粒尺寸。
- 根据权利要求1所述的阵列基板,其中,所述种晶层的材料为钨、铌、钽、钨钼化合物、铝钼化合物或钛钼化合物中的至少一者。
- 一种显示面板,其包括阵列基板,所述阵列基板包括:衬底,设置于所述衬底一侧的种晶层,以及设置于所述种晶层一侧且远离所述衬底的第一金属层;其中,所述第一金属层与所述种晶层直接接触。
- 根据权利要求11所述的显示面板,其中,所述第一金属层中的晶格结构与所述种晶层的晶格结构相同。
- 根据权利要求12所述的显示面板,其中,所述第一金属层的晶格常数与所述种晶层的晶格常数之间的差值,与所述第一金属层的晶格常数之间的比例在20%以内。
- 根据权利要求13所述的显示面板,其中,所述第一金属层的晶格常数与所述种晶层的晶格常数相同。
- 根据权利要求14所述的显示面板,其中,所述第一金属层和所述种晶层的晶格结构为体心立方晶格,所述晶格常数为3.14pm。
- 根据权利要求11所述的显示面板,其中,所述种晶层的厚度范围为50至1000埃。
- 根据权利要求11所述的显示面板,其中,所述种晶层中晶粒的分布密度大于所述第一金属层中晶粒的分布密度。
- 根据权利要求11所述的显示面板,其中,靠近所述种晶层的所述第一金属层的晶粒尺寸大于远离所述种晶层的所述第一金属层的晶粒尺寸。
- 根据权利要求11所述的显示面板,其中,所述阵列基板还包括位于所述第一金属层上的第二金属层,制作所述第二金属层和所述第一金属层的材料相同,所述第二金属层的晶粒尺寸小于所述第一金属层的晶粒尺寸。
- 根据权利要求11所述的显示面板,其中,所述种晶层的材料为钨、铌、钽、钨钼化合物、铝钼化合物或钛钼化合物中的至少一者。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/600,143 US20240030228A1 (en) | 2021-08-04 | 2021-09-13 | Array substrate and display panel |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110891996.X | 2021-08-04 | ||
CN202110891996.XA CN113629076A (zh) | 2021-08-04 | 2021-08-04 | 阵列基板及显示面板 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2023010652A1 true WO2023010652A1 (zh) | 2023-02-09 |
Family
ID=78382630
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2021/118026 WO2023010652A1 (zh) | 2021-08-04 | 2021-09-13 | 阵列基板及显示面板 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20240030228A1 (zh) |
CN (1) | CN113629076A (zh) |
WO (1) | WO2023010652A1 (zh) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7166502B1 (en) * | 1999-11-10 | 2007-01-23 | Lg. Philips Lcd Co., Ltd. | Method of manufacturing a thin film transistor |
CN1941325A (zh) * | 2005-09-28 | 2007-04-04 | 株式会社液晶先端技术开发中心 | 形成布线结构的方法、布线结构、形成半导体器件的方法、以及显示器 |
CN101315888A (zh) * | 2007-06-01 | 2008-12-03 | 三星电子株式会社 | 低阻导电结构、包括其的器件和系统以及形成其的方法 |
US20090117333A1 (en) * | 2007-11-01 | 2009-05-07 | Byeong-Jin Lee | Method of manufacturing display device and display device therefrom |
CN101447490A (zh) * | 2007-11-14 | 2009-06-03 | 三星电子株式会社 | 阵列基板及其制造方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102446811B (zh) * | 2010-09-30 | 2014-06-25 | 中国科学院微电子研究所 | 金属互连结构及金属层间通孔和互连金属线的形成方法 |
US9805976B2 (en) * | 2016-01-08 | 2017-10-31 | Applied Materials, Inc. | Co or Ni and Cu integration for small and large features in integrated circuits |
CN111883551A (zh) * | 2020-07-31 | 2020-11-03 | 京东方科技集团股份有限公司 | 基板、其制作方法、显示面板及显示装置 |
-
2021
- 2021-08-04 CN CN202110891996.XA patent/CN113629076A/zh active Pending
- 2021-09-13 WO PCT/CN2021/118026 patent/WO2023010652A1/zh active Application Filing
- 2021-09-13 US US17/600,143 patent/US20240030228A1/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7166502B1 (en) * | 1999-11-10 | 2007-01-23 | Lg. Philips Lcd Co., Ltd. | Method of manufacturing a thin film transistor |
CN1941325A (zh) * | 2005-09-28 | 2007-04-04 | 株式会社液晶先端技术开发中心 | 形成布线结构的方法、布线结构、形成半导体器件的方法、以及显示器 |
CN101315888A (zh) * | 2007-06-01 | 2008-12-03 | 三星电子株式会社 | 低阻导电结构、包括其的器件和系统以及形成其的方法 |
US20090117333A1 (en) * | 2007-11-01 | 2009-05-07 | Byeong-Jin Lee | Method of manufacturing display device and display device therefrom |
CN101447490A (zh) * | 2007-11-14 | 2009-06-03 | 三星电子株式会社 | 阵列基板及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN113629076A (zh) | 2021-11-09 |
US20240030228A1 (en) | 2024-01-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI697054B (zh) | 電晶體,液晶顯示裝置及其製造方法 | |
US8319217B2 (en) | Oxide semiconductor thin film transistor, method of manufacturing the same, and organic electroluminescent device including the same | |
JP5704790B2 (ja) | 薄膜トランジスタ、および、表示装置 | |
WO2010032386A1 (ja) | 半導体装置 | |
US10394098B2 (en) | Conductive pattern structure and its array substrate and display device | |
US9406730B2 (en) | Thin film transistor and organic light emitting device including polycrystalline silicon layer | |
WO2020177080A1 (en) | Method of forming crystallized semiconductor layer, method of fabricating thin film transistor, thin film transistor, and display apparatus | |
WO2015039381A1 (zh) | 阵列基板及其制备方法与显示装置 | |
US11245037B2 (en) | Method of fabricating array substrate, array substrate, and display apparatus | |
WO2019179137A1 (zh) | 阵列基板及其制造方法、显示面板、电子装置 | |
WO2015188476A1 (zh) | 薄膜晶体管及其制作方法、oled背板和显示装置 | |
US9263467B2 (en) | Thin film transistor array panel and manufacturing method thereof | |
CN103489900B (zh) | 一种阻挡层及其制备方法、薄膜晶体管、阵列基板 | |
WO2023010652A1 (zh) | 阵列基板及显示面板 | |
JP5593025B2 (ja) | 半導体装置 | |
US20200203391A1 (en) | Array Substrate, Display Device, Thin Film Transistor, and Method for Manufacturing Array Substrate | |
WO2016000363A1 (zh) | 低温多晶硅薄膜晶体管阵列基板及其制备方法、显示装置 | |
WO2019227521A1 (zh) | 电极结构及其制备方法、阵列基板 | |
US10475822B2 (en) | Array substrate, display panel and display apparatus having the same, and fabricating method thereof | |
TWI658587B (zh) | 顯示裝置之薄膜電晶體及其形成方法 | |
CN107946367B (zh) | 一种薄膜晶体管的制作方法及薄膜晶体管 | |
KR20120014380A (ko) | 버티컬 산화물 반도체 및 그 제조방법 | |
US20220399465A1 (en) | Thin film transistor, display apparatus, and method of fabricating thin film transistor | |
WO2020113622A1 (zh) | Tft基板的制作方法及tft基板 | |
CN113097258B (zh) | 显示面板及显示面板的制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 17600143 Country of ref document: US |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 21952521 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |