WO2024119795A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024119795A1
WO2024119795A1 PCT/CN2023/104290 CN2023104290W WO2024119795A1 WO 2024119795 A1 WO2024119795 A1 WO 2024119795A1 CN 2023104290 W CN2023104290 W CN 2023104290W WO 2024119795 A1 WO2024119795 A1 WO 2024119795A1
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WO
WIPO (PCT)
Prior art keywords
ohmic contact
layer
substrate
insulating layer
contact layer
Prior art date
Application number
PCT/CN2023/104290
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English (en)
French (fr)
Inventor
李治福
刘广辉
艾飞
宋德伟
李壮
Original Assignee
武汉华星光电技术有限公司
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Publication of WO2024119795A1 publication Critical patent/WO2024119795A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel and a display device.
  • Integrating pixel drive circuits, gate drive circuits, multiplexed power circuits, source drive circuits, timing controllers and other circuits on a glass substrate can greatly improve the integration of display panels, reduce dependence on integrated circuit chips, and thus reduce costs.
  • SOG system on glass
  • the architecture of the thin film transistor of the existing display panel cannot further reduce the footprint of the thin film transistor, and the device integration level needs to be improved.
  • Embodiments of the present application provide a display panel and a display device to solve the technical problem that the thin film transistors of the existing display panels occupy a large area.
  • the present application provides a display panel, comprising a substrate and a boss structure arranged on the substrate, wherein the boss structure comprises at least two stacked ohmic contact layers and at least one insulating layer, and an insulating layer is arranged between two adjacent ohmic contact layers;
  • the display panel also includes a semiconductor layer, at least part of which is located on the sidewalls of the boss structure, and the sidewalls include a first sidewall of the ohmic contact layer and a second sidewall of the insulating layer arranged on the same side; the semiconductor layer includes at least one channel, and the channel is located on the second sidewall.
  • the display panel further includes a gate, the gate is located on a side of the semiconductor layer away from the boss structure, and the orthographic projection of the gate on the side wall covers the orthographic projection of the channel on the side wall.
  • the at least two ohmic contact layers include a first ohmic contact layer and a second ohmic contact layer sequentially stacked on the substrate, and the at least one insulating layer includes a first insulating layer, and the first insulating layer is located between the first ohmic contact layer and the second ohmic contact layer;
  • the at least one channel further includes a second channel, and the second channel is located on the second side wall of the second insulating layer.
  • the display panel further includes:
  • a gate insulating layer disposed between the gate and the semiconductor layer
  • An interlayer dielectric layer disposed on a side of the gate away from the substrate, the interlayer dielectric layer covering the gate and the gate insulating layer;
  • a source-drain metal layer disposed on a side of the interlayer dielectric layer away from the substrate, the source-drain metal layer comprising a first drain, a source, and a second drain;
  • the source electrode is connected to the second ohmic contact layer through the first contact hole
  • the first drain electrode is connected to the first ohmic contact layer by penetrating the second contact hole
  • the second drain electrode is connected to the third ohmic contact layer through the third contact hole.
  • the first ohmic contact layer includes a first protrusion, and the orthographic projection of the second ohmic contact layer on the substrate does not overlap with the orthographic projection of the first protrusion on the substrate; the second ohmic contact layer includes a second protrusion, and the orthographic projection of the third ohmic contact layer on the substrate does not overlap with the orthographic projection of the second protrusion on the substrate.
  • the first drain electrode and the second drain electrode are respectively located on two opposite sides of the source electrode.
  • the orthographic projections of the first drain, the second drain, and the source on the substrate are all located on the same side of the orthographic projection of the gate on the substrate.
  • the side wall, the first side wall and the second side wall are located in the same plane.
  • the semiconductor layer includes an inclined portion, a first horizontal portion and a second horizontal portion
  • the inclined portion is the portion of the semiconductor layer located on the side wall of the boss structure
  • the inclined portion is located between the first horizontal portion and the second horizontal portion
  • the first horizontal portion is located on one side of the substrate
  • the second horizontal portion is located on the side of the boss structure away from the substrate.
  • the angle between the first horizontal portion and the inclined portion is 90° to 135°; and the thickness of each insulating layer is in the range of 0.0071 to 1 micrometer.
  • the present application provides a display device, comprising a display panel; wherein the display panel comprises a substrate and a boss structure arranged on the substrate, the boss structure comprises at least two ohmic contact layers and at least one insulating layer stacked, and an insulating layer is arranged between two adjacent ohmic contact layers;
  • the display panel also includes a semiconductor layer, at least part of which is located on the sidewalls of the boss structure, and the sidewalls include a first sidewall of the ohmic contact layer and a second sidewall of the insulating layer arranged on the same side; the semiconductor layer includes at least one channel, and the channel is located on the second sidewall.
  • the display panel further includes a gate, the gate is located on a side of the semiconductor layer away from the boss structure, and the orthographic projection of the gate on the side wall covers the orthographic projection of the channel on the side wall.
  • the at least two ohmic contact layers include a first ohmic contact layer and a second ohmic contact layer sequentially stacked on the substrate, and the at least one insulating layer includes a first insulating layer, and the first insulating layer is located between the first ohmic contact layer and the second ohmic contact layer;
  • the at least one channel includes a first channel, and the first channel is located on the second sidewall of the first insulating layer.
  • the at least two ohmic contact layers further include a third ohmic contact layer disposed on the second ohmic contact layer, and the at least one insulating layer further includes a second insulating layer, and the second insulating layer is located between the second ohmic contact layer and the third ohmic contact layer;
  • the at least one channel further includes a second channel, and the second channel is located on the second side wall of the second insulating layer.
  • the display panel further includes:
  • a gate insulating layer disposed between the gate and the semiconductor layer
  • An interlayer dielectric layer disposed on a side of the gate away from the substrate, the interlayer dielectric layer covering the gate and the gate insulating layer;
  • a source-drain metal layer disposed on a side of the interlayer dielectric layer away from the substrate, the source-drain metal layer comprising a first drain, a source, and a second drain;
  • the source electrode is connected to the second ohmic contact layer through the first contact hole
  • the first drain electrode is connected to the first ohmic contact layer by penetrating the second contact hole
  • the second drain electrode is connected to the third ohmic contact layer through the third contact hole.
  • the first ohmic contact layer, the second ohmic contact layer and the third ohmic contact layer are in a stepped shape
  • the first ohmic contact layer includes a first protrusion, and the orthographic projection of the second ohmic contact layer on the substrate does not overlap with the orthographic projection of the first protrusion on the substrate; the second ohmic contact layer includes a second protrusion, and the orthographic projection of the third ohmic contact layer on the substrate does not overlap with the orthographic projection of the second protrusion on the substrate.
  • the first drain electrode and the second drain electrode are respectively located on two opposite sides of the source electrode.
  • the orthographic projections of the first drain, the second drain, and the source on the substrate are all located on the same side of the orthographic projection of the gate on the substrate.
  • the side wall, the first side wall and the second side wall are located in the same plane.
  • the display panel and display device provided by the present application form a boss structure by stacking an ohmic contact layer and an insulating layer on a substrate
  • the boss structure includes at least two stacked ohmic contact layers and at least one insulating layer, an insulating layer is arranged between two adjacent ohmic contact layers, at least part of the semiconductor layer is located on the side wall of the boss structure, the semiconductor layer is in contact with the first side wall of the ohmic contact layer, and the channel of the semiconductor is located on the second side wall of the insulating layer, so that the channel length can be controlled by adjusting the length and inclination angle of the second side wall, which not only reduces the channel length, but also realizes the superposition of multiple thin film transistors in the thickness direction of the display panel, reduces the volume of thin devices, reduces the device footprint, is conducive to improving the device integration, and is conducive to realizing IC circuit integration on the substrate.
  • FIG1 is a schematic diagram of a planar structure of a thin film transistor provided in an embodiment of the present application.
  • Fig. 2 is a schematic cross-sectional view along the B-B direction in Fig. 1;
  • Fig. 3 is a schematic cross-sectional view along the A-A direction in Fig. 1;
  • FIG4 is a schematic diagram of a planar structure of another thin film transistor provided in an embodiment of the present application.
  • Fig. 5 is a schematic cross-sectional view along the B-B direction in Fig. 4;
  • Fig. 6 is a schematic cross-sectional view along the A-A direction in Fig. 4;
  • FIGS. 7A to 7G are schematic diagrams of the structure of a manufacturing process of a display panel provided in an embodiment of the present application.
  • Figure 1 is a schematic diagram of a planar structure of a thin film transistor provided in an embodiment of the present application
  • Figure 2 is a schematic diagram of a cross-section along the B-B direction in Figure 1
  • Figure 3 is a schematic diagram of a cross-section along the A-A direction in Figure 1.
  • An embodiment of the present application provides a display panel, the display panel comprising a substrate 10 and a thin film transistor disposed on the substrate 10.
  • the thin film transistor can be applied to many circuits in the display panel, such as a pixel driving circuit, a gate driving circuit, a source driving circuit, a timing controller, a multiplexing circuit, etc.
  • the display panel includes a substrate 10 and a boss structure 20 disposed on the substrate 10.
  • the boss structure 20 includes at least two stacked ohmic contact layers 21 and at least one insulating layer 22, with one insulating layer 22 disposed between two adjacent ohmic contact layers 21;
  • the display panel also includes a semiconductor layer 30, at least part of which is located on a side wall 20a of the boss structure 20, and the side wall 20a includes a first side wall 21a of the ohmic contact layer 21 and a second side wall 22a of the insulating layer 22 disposed on the same side;
  • the semiconductor layer 30 includes at least one channel 31, and the channel 31 is located on the second side wall 22a.
  • the active layers of thin film transistors in the prior art are prepared on the same plane, and multiple thin film transistors are laid flat, resulting in a large circuit footprint.
  • the length of the channel 31 is generally more than 2 microns, and the transistor size cannot be further reduced.
  • the display panel provided in the embodiment of the present application forms a boss structure 20 by stacking the ohmic contact layer 21 and the insulating layer 22 on the substrate 10, wherein the boss structure 20 includes at least two stacked layers of the ohmic contact layer 21 and at least one insulating layer 22, wherein a layer of the insulating layer 22 is arranged between two adjacent layers of the ohmic contact layer 21, and at least a portion of the semiconductor layer 30 is located on the side wall 20a of the boss structure 20, the semiconductor layer 30 is in contact with the first side wall 21a of the ohmic contact layer 21, and the channel 31 of the semiconductor layer 30 is located on the second side wall 22a of the insulating layer 22.
  • the channel length can be controlled by adjusting the length and inclination angle of the second side wall 22a, which not only reduces the channel length, but also realizes the superposition of multiple thin film transistors in the thickness direction of the display panel, reduces the volume of thin devices, reduces the device footprint, is beneficial to improving the device integration, and is beneficial to realizing IC circuit integration on the substrate 10.
  • the substrate 10 includes a substrate 11 , a light shielding layer 12 and a buffer layer 13 .
  • the light shielding layer 12 is disposed on the substrate 11
  • the buffer layer 13 covers the substrate 11 and the light shielding layer 12 .
  • the substrate 11 may be a glass substrate 11, but is not limited thereto.
  • the substrate 11 may also be a flexible substrate 11.
  • the light shielding layer 12 is used to shield the ambient light incident on the semiconductor layer 30.
  • the light shielding layer 12 is used to shield the ambient light incident on the channel 31 to prevent the external light from causing adverse effects on the device performance.
  • the light shielding layer 12 is made of a metal material, which includes but is not limited to at least one of molybdenum, aluminum, titanium, copper and silver; the light shielding layer 12 may also be made of a black matrix or the like.
  • the buffer layer 13 is made of at least one of silicon nitride or silicon oxide.
  • the thickness of the buffer layer 13 is greater than or equal to 2500 angstroms and less than or equal to 3500 angstroms, for example, 2500 angstroms, 2800 angstroms, 3000 angstroms, 3200 angstroms or 3500 angstroms.
  • the material of the ohmic contact layer 21 can be the same as the material of the semiconductor layer 30.
  • the ohmic contact layer 21 is doped with ions.
  • the ohmic contact layer 21 is all N-type heavily doped amorphous silicon material.
  • the ohmic contact layer 21 can also be doped with impurity elements such as phosphorus or arsenic.
  • the insulating layer 22 is used to separate two adjacent layers of the ohmic contact layer 21.
  • the insulating layer 22 includes at least one of an inorganic insulating layer and an organic insulating layer.
  • the inorganic insulating layer is made of materials including but not limited to silicon oxide or silicon nitride.
  • the organic insulating layer is made of materials including but not limited to polyimide, polyacrylate, and silicone.
  • the semiconductor layer 30 at least covers the first side walls 21a of the at least two layers of the ohmic contact layer 21 and the second side wall 22a of the at least one layer of the insulating layer 22.
  • the first side wall 21a and the second side wall 22a are located on the same side of the boss structure 20, and the side wall 20a, the first side wall 21a and the second side wall 22a are located on the same plane, that is, the angles between the side wall 20a, the first side wall 21a and the second side wall 22a and the substrate 10 are equal.
  • the semiconductor layer 30 includes an inclined portion 34, a first horizontal portion 35 and a second horizontal portion 36.
  • the inclined portion 34 is a portion of the semiconductor layer 30 located on the side wall 20a of the boss structure 20.
  • the inclined portion 34 is located between the first horizontal portion 35 and the second horizontal portion 36.
  • the first horizontal portion 35 is located on one side of the substrate 10, and the second horizontal portion 36 is located on a side of the boss structure 20 away from the substrate 10.
  • the side of the inclined portion 34 close to the substrate 10 is connected to the first horizontal portion 35, and the side of the inclined portion 34 away from the substrate 10 is connected to the second horizontal portion 36.
  • the material of the first horizontal portion 35 is amorphous silicon material.
  • the semiconductor layer 30 before crystallization is more likely to form a seed crystal at the corner between the buffer layer 13 and the side wall 20a, that is, the semiconductor layer 30 before crystallization is more likely to form a seed crystal at the corner between the first horizontal portion 35 and the inclined portion 34.
  • the length of the channel 31 located on the side wall 20a is less than 1 micron, which provides formation conditions for the channel 31 on the side wall 20a to be composed of a single grain.
  • the channel 31 is composed of a single grain and there is no grain boundary, thereby providing formation conditions for forming a semiconductor device including a single grain channel and having high mobility.
  • the mobility of the device is greatly improved, which is beneficial to improving the driving capability of the device.
  • the adhesion between the semiconductor layer 30 and the film layer can be increased, thereby improving the stability of the thin film transistor device.
  • the preparation of the semiconductor layer 30 of a small size can be achieved with the accuracy of the existing exposure machine without changing the process.
  • the angle between the first horizontal portion 35 and the inclined portion 34 is 90° to 135°
  • the angle ⁇ is also the angle between the side wall 20a and the substrate 10, and is also the angle between the first side wall 21a and the second side wall 22a and the substrate 10.
  • the thickness of each insulating layer 22 is in the range of 0.0071 to 1 micron.
  • the display panel further includes a gate 50, which is located on a side of the semiconductor layer 30 away from the boss structure 20, and the orthographic projection of the gate 50 on the side wall 20a covers the orthographic projection of the channel 31 on the side wall 20a, so as to facilitate the control of the formation position and length of the channel 31.
  • the gate 50 is made of at least one material selected from molybdenum, aluminum, titanium, copper and silver.
  • the boss structure 20 is composed of two layers of the ohmic contact layer 21 and one layer of the insulating layer 22, that is, the device includes a thin film transistor.
  • the at least two layers of ohmic contact layer 21 include a first ohmic contact layer 211 and a second ohmic contact layer 212 stacked in sequence on the substrate 10
  • the at least one insulating layer 22 includes a first insulating layer 221
  • the first insulating layer 221 is located between the first ohmic contact layer 211 and the second ohmic contact layer 212
  • the at least one channel includes a first channel 32, and the first channel 32 is located on the second sidewall 22a of the first insulating layer 221.
  • the semiconductor layer 30 is in contact with the first ohmic contact layer 211 and the second ohmic contact layer 212, and the portion of the semiconductor layer 30 located between the first ohmic contact layer 211 and the second ohmic contact layer 212 forms the first channel 32 of a thin film transistor, that is, the length of the first channel 32 can be determined by the length and inclination angle of the second side wall 22a of the first insulating layer 221 between the first ohmic contact layer 211 and the second ohmic contact layer 212.
  • the lengths of the first channel 32 and the second channel 33 can be controlled by adjusting the length and inclination angle of the second side wall 22a of the first insulating layer 221, and the length of the first channel 32 can be easily controlled to be less than 1 micron under the existing process.
  • two thin film transistors may be stacked, but this is not limited to three, four or more thin film transistors.
  • the present application embodiment is described by taking the stacking of two thin film transistors as an example.
  • Figure 4 is a schematic diagram of a planar structure of another thin film transistor provided in an embodiment of the present application
  • Figure 5 is a schematic diagram of a cross-section along the B-B direction in Figure 4
  • Figure 6 is a schematic diagram of a cross-section along the A-A direction in Figure 4.
  • the at least two layers of ohmic contact layers 21 further include a third ohmic contact layer 213 disposed on the second ohmic contact layer 212, the at least one layer of insulating layer further includes a second insulating layer 222, and the second insulating layer 222 is located between the second ohmic contact layer 212 and the third ohmic contact layer 213; the at least one channel 31 further includes a second channel 33, and the second channel 33 is located on the second sidewall 22a of the second insulating layer 222.
  • the boss structure 20 is composed of three layers of the ohmic contact layer and three layers of the insulating layer. Specifically, the boss structure 20 includes a first ohmic contact layer 211, a first insulating layer 221, a second ohmic contact layer 212, a second insulating layer 222 and a third ohmic contact layer 213 which are sequentially stacked on the substrate 10.
  • the device in this embodiment includes two thin film transistors stacked in the thickness direction of the display panel, and each of the two thin film transistors has a channel 31.
  • the semiconductor layer 30 is in contact with the first ohmic contact layer 211, the second ohmic contact layer 212 and the third ohmic contact layer 213, the portion of the semiconductor layer 30 located between the first ohmic contact layer 211 and the second ohmic contact layer 212 forms the first channel 32 of a thin film transistor, and the portion of the semiconductor layer 30 located between the second ohmic contact layer 212 and the third ohmic contact layer 213 forms the second channel 33 of another thin film transistor, that is, the length of the first channel 32 can be determined by the length of the first ohmic contact layer 211 and the second ohmic contact layer 212.
  • the length of the second channel 32 and the second channel 33 can be determined by the length and the tilt angle of the second side wall 22a of the first insulating layer 221 between the second ohmic contact layer 212 and the third ohmic contact layer 213. Therefore, in this embodiment, the lengths of the first channel 32 and the second channel 33 can be controlled by adjusting the lengths and the tilt angles of the second side walls 22a of the first insulating layer 221 and the second side walls 22a of the second insulating layer 222. In this way, the lengths of the first channel 32 and the second channel 33 can be easily controlled to be less than 1 micron under the existing process.
  • the display panel further includes a gate insulating layer 40, an interlayer dielectric layer 60, a source-drain metal layer 70, a first contact hole 701, a second contact hole 702, and a third contact hole 703.
  • the gate insulating layer 40 is disposed between the gate 50 and the semiconductor layer 30; the interlayer dielectric layer 60 is disposed on a side of the gate insulating layer 40 away from the substrate 10, and the interlayer dielectric layer 60 covers the gate 50 and the gate insulating layer 40; the source-drain metal layer 70 is disposed on a side of the interlayer dielectric layer 60 away from the substrate 10, and the source-drain metal layer 70 includes a first drain 72, a source 71, and a second drain 73; the first contact hole 701, the second contact hole 702, and the third contact hole 703 penetrate the interlayer dielectric layer 60 and the gate insulating layer 40.
  • the two thin film transistors in this embodiment share one source electrode 71. Since the second ohmic contact layer 212 is located between the first ohmic contact layer 211 and the second ohmic contact layer 212, in order to facilitate wiring, in this embodiment, the source electrode 71 is in contact with the second ohmic contact layer 212, and the drain electrodes (the first drain electrode 72 and the second drain electrode 73) of the two thin film transistors are respectively in contact with the first ohmic contact layer 211 and the second ohmic contact layer 212.
  • the source electrode 71 is connected to the second ohmic contact layer 212 through the first contact hole 701
  • the first drain electrode 72 is connected to the first ohmic contact layer 211 by penetrating the second contact hole 702
  • the second drain electrode 73 is connected to the third ohmic contact layer 213 through the third contact hole 703.
  • the actual width of the device in this embodiment is the sum of the width of the first channel 32 and the width of the second channel 33, so that the width of the device can be increased within a limited space, which is conducive to increasing the on-state current and improving the driving ability of the device.
  • the two thin film transistors are superimposed in the thickness direction of the display panel, which is conducive to reducing the volume of the device and reducing the area occupied by the device, thereby improving the integration of the device.
  • the multi-layer ohmic contact layer needs to be adaptively designed.
  • the first ohmic contact layer 211, the second ohmic contact layer 212 and the third ohmic contact layer 213 are stepped;
  • the first ohmic contact layer 211 includes a first protrusion 2111, and the orthographic projection of the second ohmic contact layer 212 on the substrate 10 does not overlap with the orthographic projection of the first protrusion 2111 on the substrate 10;
  • the second ohmic contact layer 212 includes a second protrusion 2121, and the orthographic projection of the third ohmic contact layer 213 on the substrate 10 does not overlap with the orthographic projection of the second protrusion 2121 on the substrate 10.
  • the first ohmic contact layer 211 is made to protrude beyond the second ohmic contact layer 212 and the third ohmic contact layer 213, so that the first drain electrode 72 can be prevented from passing through the second ohmic contact layer 212 and the third ohmic contact layer 213; and the second ohmic contact layer 212 is made to protrude beyond the third ohmic contact layer 213, so that the source electrode 71 can be prevented from passing through the third ohmic contact layer 213.
  • the first drain electrode 72 and the second drain electrode 73 are respectively located on two opposite sides of the source electrode 71 to facilitate wiring design.
  • the orthographic projections of the first drain 72, the second drain 73 and the source 71 on the substrate 10 are all located on the same side of the orthographic projection of the gate 50 on the substrate 10 to ensure that the position of the formed channel is located on the second side wall 22a.
  • the above embodiment is a superposition of one or two thin film transistors, and other embodiments of superposition of more thin film transistors are similar to the above embodiment, and reference may be made to the above description.
  • the present application also provides a preparation method, comprising the following steps:
  • the step S10 includes the following steps: providing a substrate 11 ; forming a light shielding layer 12 on the substrate 11 ; and forming a buffer layer 13 covering the substrate 11 and the light shielding layer 12 .
  • boss structure 20 forming a boss structure 20 on the substrate 10, wherein the boss structure 20 comprises at least two stacked ohmic contact layers and at least one insulating layer 22, wherein an insulating layer 22 is disposed between two adjacent ohmic contact layers.
  • the material of the first ohmic contact layer 211, the material of the first insulating layer 221, the material of the second ohmic contact layer 212, the material of the second insulating layer 222, the material of the third ohmic contact layer 213, the material of the third insulating layer and the material of the fourth ohmic contact layer are sequentially stacked on the buffer layer 13; and then etching of different depths is performed to form the first ohmic contact layer 211, the first insulating layer 221, the second ohmic contact layer 212, the second insulating layer 222 and the third ohmic contact layer 213. It should be noted that the etching process of different depths can be performed through the same grayscale mask or in multiple photomasks, which is not limited here.
  • S30 forming a semiconductor layer 30 at least partially located on the sidewall 20a of the boss structure 20, wherein the sidewall 20a includes the first sidewall 21a of the ohmic contact layer 21 and the second sidewall 22a of the insulating layer 22 arranged on the same side.
  • an amorphous silicon material is deposited on the third ohmic contact layer 213, and the amorphous silicon is crystallized, and then the amorphous silicon material is etched to form the pattern of the semiconductor layer 30.
  • the amorphous silicon material can be crystallized by an excimer laser annealing process. Since the energy of the excimer laser annealing process is limited and is completely absorbed by the amorphous silicon, when the amorphous silicon layer is crystallized, the ohmic contact layer 21 can still maintain the amorphous silicon structure.
  • the crystallization of amorphous silicon can also be performed after the oxidation treatment, which is not limited here.
  • the preparation method further includes: as shown in FIG. 7D, S40: forming a gate insulating layer 40 covering the substrate 10 and the boss structure 20; as shown in FIG. 7E, S50: forming a gate 50 on a side of the gate insulating layer 40 away from the boss structure 20; as shown in FIG. 7F, S60: forming an interlayer dielectric layer 60 covering the gate 50 and the gate insulating layer 40; as shown in FIG. 7D, S40: forming a gate insulating layer 40 covering the substrate 10 and the boss structure 20; as shown in FIG. 7E, S50: forming a gate 50 on a side of the gate insulating layer 40 away from the boss structure 20; as shown in FIG. 7F, S60: forming an interlayer dielectric layer 60 covering the gate 50 and the gate insulating layer 40; as shown in FIG.
  • S70 forming a first contact hole 701, a second contact hole 702 and a third contact hole 703 penetrating the interlayer dielectric layer 60 and the gate insulating layer 40; Hole 703; as shown in Figure 7G, S80: a source-drain metal layer 70 is formed on the side of the interlayer dielectric layer 60 away from the substrate 10, and the source-drain metal layer 70 includes a first drain 72, a source 71 and a second drain 73, the first drain 72 is connected to the first ohmic contact layer 211 by penetrating the first contact hole 701, the source 71 is connected to the second ohmic contact layer 212 through the second contact hole 702, and the second drain 73 is connected to the third ohmic contact layer 213 through the third contact hole 703.
  • An embodiment of the present application further provides a display device, which includes the display panel in the above embodiment.
  • the display device includes but is not limited to electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc.
  • the display panel and the display device provided in the embodiments of the present application form a boss structure by stacking an ohmic contact layer and an insulating layer on a substrate
  • the boss structure includes at least two stacked ohmic contact layers and at least one insulating layer, an insulating layer is arranged between two adjacent ohmic contact layers, at least part of the semiconductor layer is located on the side wall of the boss structure, the semiconductor layer contacts the first side wall of the ohmic contact layer, and the channel of the semiconductor is located on the second side wall of the insulating layer, so that the channel length can be controlled by adjusting the length and inclination angle of the second side wall, which not only reduces the channel length, but also realizes the superposition of multiple thin film transistors in the thickness direction of the display panel, reduces the volume of thin devices, reduces the device footprint, is beneficial to improve the device integration, and is beneficial to realize IC circuit integration on the substrate.

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Abstract

一种显示面板及显示装置，显示面板包括基板（10）和凸台结构（20），凸台结构（20）包括堆叠设置的至少两层欧姆接触层（21）和至少一层绝缘层（22），相邻两层欧姆接触层（21）之间设置有一层绝缘层（22）；至少部分半导体层（30）位于凸台结构（20）的侧壁（20a）上，侧壁（20a）包括同侧设置的欧姆接触层（21）的第一侧壁（21a）和绝缘层（22）的第二侧壁（22a）；半导体层（30）包括位于第二侧壁（22a）上的至少一沟道（31）。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及显示装置。
 背景技术
将像素驱动电路、栅极驱动电路、复用电力路、源极驱动电路、时序控制器等电路集成在玻璃基板上（system on glass，SOG），可以极大提高显示面板的集成度，降低对于集成电路芯片的依赖性，从而降低成本。实现SOG需要提高现有显示面板中的薄膜晶体管的集成度、最大工作频率和电流密度，这些都要求薄膜晶体管具有更短的沟道长度、更高的迁移率和更小的体积。
然而，现有显示面板的薄膜晶体管的架构无法进一步减小薄膜晶体管的占地面积，器件集成度有待提高。
 发明概述
本申请实施例提供一种显示面板及显示装置，以解决现有的显示面板的薄膜晶体管的占地面积较大的技术问题。
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种显示面板，包括基板以及设置于所述基板上的凸台结构，所述凸台结构包括堆叠设置的至少两层欧姆接触层和至少一层绝缘层，相邻两层所述欧姆接触层之间设置有一层所述绝缘层；
所述显示面板还包括半导体层，至少部分所述半导体层位于所述凸台结构的侧壁上，所述侧壁包括同侧设置的所述欧姆接触层的第一侧壁和所述绝缘层的第二侧壁；所述半导体层包括至少一沟道，所述沟道位于所述第二侧壁上。
根据本申请提供的显示面板，所述显示面板还包括栅极，所述栅极位于所述半导体层远离所述凸台结构的一侧，所述栅极在所述侧壁上的正投影覆盖所述沟道在所述侧壁上的正投影。
根据本申请提供的显示面板，所述至少两层欧姆接触层包括依次堆叠设置于所述基板上的第一欧姆接触层和第二欧姆接触层，所述至少一层绝缘层包括第一绝缘层，所述第一绝缘层位于所述第一欧姆接触层和所述第二欧姆接触层之间；
所述至少一沟道包括第一沟道，所述第一沟道位于所述第一绝缘层的所述第二侧壁上。
根据本申请提供的显示面板，所述至少两层欧姆接触层还包括设置于所述第二欧姆接触层上的第三欧姆接触层，所述至少一层绝缘层还包括第二绝缘层，所述第二绝缘层位于所述第二欧姆接触层和所述第三欧姆接触层之间；
所述至少一沟道还包括第二沟道，所述第二沟道位于所述第二绝缘层的所述第二侧壁上。
根据本申请提供的显示面板，所述显示面板还包括：
栅极绝缘层，设置于所述栅极与所述半导体层之间；
层间介质层，设置于所述栅极远离所述基板的一侧，所述层间介质层覆盖所述栅极和所述栅极绝缘层；
源漏极金属层，设置于所述层间介质层远离所述基板的一侧，所述源漏极金属层包括第一漏极、源极和第二漏极；以及
第一接触孔、第二接触孔和第三接触孔，贯穿所述层间介质层和所述栅极绝缘层；
其中，所述源极通过所述第一接触孔与所述第二欧姆接触层连接，所述第一漏极通过贯穿所述第二接触孔与所述第一欧姆接触层连接，所述第二漏极通过所述第三接触孔与所述第三欧姆接触层连接。
根据本申请提供的显示面板，所述第一欧姆接触层、所述第二欧姆接触层和所述第三欧姆接触层呈阶梯状；
所述第一欧姆接触层包括第一突出部，所述第二欧姆接触层在所述基板上的正投影与所述第一凸出部在所述基板上的正投影不重叠；所述第二欧姆接触层包括第二突出部，所述第三欧姆接触层在所述基板上的正投影与所述第二凸出部在所述基板上的正投影不重叠。
根据本申请提供的显示面板，所述第一漏极和所述第二漏极分别位于所述源极的相对两侧。
根据本申请提供的显示面板，所述第一漏极、所述第二漏极和所述源极在所述基板上的正投影均位于所述栅极在所述基板上的正投影的同一侧。
根据本申请提供的显示面板，所述侧壁、所述第一侧壁和所述第二侧壁位于同一平面。
根据本申请提供的显示面板，所述半导体层包括倾斜部、第一水平部和第二水平部，所述倾斜部为所述半导体层位于所述凸台结构的侧壁上的部分，所述倾斜部位于所述第一水平部和所述第二水平部之间，所述第一水平部位于所述基板一侧，所述第二水平部位于所述凸台结构远离所述基板的一侧。
根据本申请提供的显示面板，所述第一水平部与所述倾斜部之间的夹角为90°~135°；每一所述绝缘层的厚度范围为0.0071~1微米。
本申请提供一种显示装置，包括显示面板；其中，所述显示面板包括基板以及设置于所述基板上的凸台结构，所述凸台结构包括堆叠设置的至少两层欧姆接触层和至少一层绝缘层，相邻两层所述欧姆接触层之间设置有一层所述绝缘层；
所述显示面板还包括半导体层，至少部分所述半导体层位于所述凸台结构的侧壁上，所述侧壁包括同侧设置的所述欧姆接触层的第一侧壁和所述绝缘层的第二侧壁；所述半导体层包括至少一沟道，所述沟道位于所述第二侧壁上。
根据本申请提供的显示装置，所述显示面板还包括栅极，所述栅极位于所述半导体层远离所述凸台结构的一侧，所述栅极在所述侧壁上的正投影覆盖所述沟道在所述侧壁上的正投影。
根据本申请提供的显示装置，所述至少两层欧姆接触层包括依次堆叠设置于所述基板上的第一欧姆接触层和第二欧姆接触层，所述至少一层绝缘层包括第一绝缘层，所述第一绝缘层位于所述第一欧姆接触层和所述第二欧姆接触层之间；
所述至少一沟道包括第一沟道，所述第一沟道位于所述第一绝缘层的所述第二侧壁上。
根据本申请提供的显示装置，所述至少两层欧姆接触层还包括设置于所述第二欧姆接触层上的第三欧姆接触层，所述至少一层绝缘层还包括第二绝缘层，所述第二绝缘层位于所述第二欧姆接触层和所述第三欧姆接触层之间；
所述至少一沟道还包括第二沟道，所述第二沟道位于所述第二绝缘层的所述第二侧壁上。
根据本申请提供的显示装置，所述显示面板还包括：
栅极绝缘层，设置于所述栅极与所述半导体层之间；
层间介质层，设置于所述栅极远离所述基板的一侧，所述层间介质层覆盖所述栅极和所述栅极绝缘层；
源漏极金属层，设置于所述层间介质层远离所述基板的一侧，所述源漏极金属层包括第一漏极、源极和第二漏极；以及
第一接触孔、第二接触孔和第三接触孔，贯穿所述层间介质层和所述栅极绝缘层；
其中，所述源极通过所述第一接触孔与所述第二欧姆接触层连接，所述第一漏极通过贯穿所述第二接触孔与所述第一欧姆接触层连接，所述第二漏极通过所述第三接触孔与所述第三欧姆接触层连接。
根据本申请提供的显示装置，所述第一欧姆接触层、所述第二欧姆接触层和所述第三欧姆接触层呈阶梯状；
所述第一欧姆接触层包括第一突出部，所述第二欧姆接触层在所述基板上的正投影与所述第一凸出部在所述基板上的正投影不重叠；所述第二欧姆接触层包括第二突出部，所述第三欧姆接触层在所述基板上的正投影与所述第二凸出部在所述基板上的正投影不重叠。
根据本申请提供的显示装置，所述第一漏极和所述第二漏极分别位于所述源极的相对两侧。
根据本申请提供的显示装置，所述第一漏极、所述第二漏极和所述源极在所述基板上的正投影均位于所述栅极在所述基板上的正投影的同一侧。
根据本申请提供的显示装置，所述侧壁、所述第一侧壁和所述第二侧壁位于同一平面。
有益效果
本申请的有益效果为：本申请提供的显示面板及显示装置，通过在基板上叠加欧姆接触层和绝缘层形成一凸台结构，凸台结构包括堆叠设置的至少两层欧姆接触层和至少一层绝缘层，相邻两层所述欧姆接触层之间设置有一层所述绝缘层，至少部分半导体层位于凸台结构的侧壁上，半导体层与欧姆接触层的第一侧壁接触，半导体的沟道位于绝缘层的第二侧壁上，如此，只需调整第二侧壁的长度和倾斜角度即可控制沟道长度，不仅减小了沟道长度，还可实现多个薄膜晶体管在显示面板厚度方向上的叠加，降低薄器件体积，减小器件占地面积，有利于提高器件集成度，有利于实现基板上的IC电路集成。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种薄膜晶体管的平面结构示意图；
图2为图1中沿B-B方向的剖面示意图；
图3为图1中沿A-A方向的剖面示意图；
图4为本申请实施例提供的另一种薄膜晶体管的平面结构示意图；
图5为图4中沿B-B方向的剖面示意图；
图6为图4中沿A-A方向的剖面示意图；
图7A~7G为本申请实施例提供的显示面板的制备过程的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
请参阅图1~图3，图1为本申请实施例提供的一种薄膜晶体管的平面结构示意图；图2为图1中沿B-B方向的剖面示意图；图3为图1中沿A-A方向的剖面示意图。本申请实施例提供一种显示面板，所述显示面板包括基板10和设置于所述基板10上的薄膜晶体管。所述薄膜晶体管可应用于显示面板中的像素驱动电路、栅极驱动电路、源极驱动电路、时序控制器、复用电路等诸多电路中。
所述显示面板包括基板10以及设置于所述基板10上的凸台结构20。所述凸台结构20包括堆叠设置的至少两层欧姆接触层21和至少一层绝缘层22，相邻两层所述欧姆接触层21之间设置有一层所述绝缘层22；所述显示面板还包括半导体层30，至少部分所述半导体层30位于所述凸台结构20的侧壁20a上，所述侧壁20a包括同侧设置的所述欧姆接触层21的第一侧壁21a和所述绝缘层22的第二侧壁22a；所述半导体层30包括至少一沟道31，所述沟道31位于所述第二侧壁22a上。
现有技术中的薄膜晶体管的有源层制备在同一平面，多个薄膜晶体管平铺设置，导致形成的电路占地面积较大，且受曝光、刻蚀工艺限制，所述沟道31的长度一般在2微米以上，晶体管尺寸无法进一步缩小。有鉴于此，本申请实施例提供的显示面板，通过在基板10上叠加所述欧姆接触层21和所述绝缘层22形成一凸台结构20，所述凸台结构20包括堆叠设置的至少两层所述欧姆接触层21和至少一层所述绝缘层22，相邻两层所述欧姆接触层21之间设置有一层所述绝缘层22，至少部分半导体层30位于凸台结构20的侧壁20a上，半导体层30与所述欧姆接触层21的第一侧壁21a接触，所述半导体层30的所述沟道31位于所述绝缘层22的第二侧壁22a上，如此，只需调整第二侧壁22a的长度和倾斜角度即可控制沟道长度，不仅减小了沟道长度，还可实现多个薄膜晶体管在显示面板厚度方向上的叠加，降低薄器件体积，减小器件占地面积，有利于提高器件集成度，有利于实现基板10上的IC电路集成。
在本实施例中，所述基板10包括衬底11、遮光层12和缓冲层13，所述遮光层12设置于所述衬底11上，所述缓冲层13覆盖所述衬底11和遮光层12。
所述衬底11可以为玻璃衬底11，但不限于此，所述衬底11也可以为柔性衬底11。所述遮光层12用于对入射至所述半导体层30的环境光进行遮挡，具体地，所述遮光层12用于对入射至所述沟道31的环境光进行遮挡，以避免外界光线对器件性能造成不良影响。可选地，所述遮光层12的制备材料为金属材料，金属材料包括但不限于钼、铝、钛、铜以及银中的至少一种；所述遮光层12的制备材料也可以为黑色矩阵等。可选地，所述缓冲层13的制备材料包括氮化硅或氧化硅中的至少一种。缓冲层13的厚度大于或等于2500埃且小于或等于3500埃，例如为2500埃、2800埃、3000埃、3200埃或3500埃。
在本实施例中，所述欧姆接触层21的材料可以与所述半导体层30的材料相同，所述欧姆接触层21中掺杂有离子，所述欧姆接触层21均为N型重掺杂非晶硅材料，所述欧姆接触层21中还可以掺杂有磷或砷等杂质元素。所述绝缘层22用于隔开相邻两层所述欧姆接触层21，可选地，所述绝缘层22包括无机绝缘层和有机绝缘层中的至少一种，所述无机绝缘层的制备材料包括但不限于氧化硅或氮化硅，所述有机绝缘层的制备材料包括但不限于聚酰亚胺、聚丙烯酸酯以及有机硅等。
所述半导体层30至少覆盖所述至少两层所述欧姆接触层21的第一侧壁21a以及所述至少一层所述绝缘层22的第二侧壁22a，在本实施例中，所述第一侧壁21a和所述第二侧壁22a位于所述凸台结构20的同一侧，所述侧壁20a、所述第一侧壁21a和所述第二侧壁22a位于同一平面，也即，所述侧壁20a、所述第一侧壁21a和所述第二侧壁22a与所述基板10之间夹角相等。
具体地，所述半导体层30包括倾斜部34、第一水平部35和第二水平部36，所述倾斜部34为所述半导体层30位于所述凸台结构20的所述侧壁20a上的部分，所述倾斜部34位于所述第一水平部35和所述第二水平部36之间，所述第一水平部35位于所述基板10一侧，所述第二水平部36位于所述凸台结构20远离所述基板10的一侧，所述倾斜部34靠近所述基板10的一侧与所述第一水平部35连接，所述倾斜部34远离所述基板10的一侧与所述第二水平部36连接。
如此设置的原因在于，一方面，所述第一水平部35的材料为非晶硅材料，在结晶化以形成所述半导体层30的过程中，结晶之前的所述半导体层30在所述缓冲层13与所述侧壁20a之间的拐角处更容易形成籽晶，也即，结晶之前的所述半导体层30在所述第一水平部35与所述倾斜部34之间的拐角处更容易形成籽晶，籽晶沿着所述侧壁20a生长形成单晶粒时，配合位于所述侧壁20a上的所述沟道31的长度小于1微米，为所述侧壁20a上的所述沟道31由单晶粒组成提供形成条件，如此可使得一个所述沟道31内仅存在一个晶粒，即所述沟道31由单颗晶粒构成，不存在晶界，进而为形成包括单晶粒沟道且具有高迁移率的半导体器件提供形成条件，相比于存在多晶界的现有的薄膜晶体管器件，在减小器件尺寸的同时，大幅提升器件的迁移率，有利于提升器件的驱动能力。
另一方面，通过延长所述倾斜部34以形成所述第一水平部35和所述第二水平部36，可增大所述半导体层30与膜层之间的附着力，提高薄膜晶体管器件的稳定性，此外，还可在现有工艺的曝光机的精度上便能实现小尺寸的所述半导体层30的制备，无需更改工艺。
具体地，在本实施例中，所述第一水平部35与所述倾斜部34之间的夹角为90°~135°，该夹角θ也为所述侧壁20a与所述基板10之间的夹角，也为所述第一侧壁21a和第二侧壁22a与所述基板10之间的夹角。在本实施例中，每一所述绝缘层22的厚度范围为0.0071~1微米，通过控制上述夹角和厚度，可控制所述沟道31的长度在1微米以下。
所述显示面板还包括栅极50，所述栅极50位于所述半导体层30远离所述凸台结构20的一侧，所述栅极50在所述侧壁20a上的正投影覆盖所述沟道31在所述侧壁20a上的正投影，如此便于控制所述沟道31的形成位置及长短。可选地，所述栅极50的制备材料选自钼、铝、钛、铜以及银中的至少一种。
在一种实施例中，请继续参阅图1~图3，所述凸台结构20由两层所述欧姆接触层21和一层所述绝缘层22构成，即，器件包括一个薄膜晶体管。具体地，所述至少两层欧姆接触层21包括依次堆叠设置于所述基板10上的第一欧姆接触层211和第二欧姆接触层212，所述至少一层绝缘层22包括第一绝缘层221，所述第一绝缘层221位于所述第一欧姆接触层211和所述第二欧姆接触层212之间；所述至少一沟道包括第一沟道32，所述第一沟道32位于所述第一绝缘层221的所述第二侧壁22a上。
可以理解的是，在本实施例中，所述半导体层30与所述第一欧姆接触层211和所述第二欧姆接触层212接触连接，所述半导体层30位于所述第一欧姆接触层211和所述第二欧姆接触层212之间的部分形成一薄膜晶体管的所述第一沟道32，即所述第一沟道32的长度可由第一欧姆接触层211和第二欧姆接触层212之间的第一绝缘层221的第二侧壁22a的长度和倾斜角度决定，只需调整所述第一绝缘层221的第二侧壁22a的长度和倾斜角度即可控制所述第一沟道32和所述第二沟道33的长度，可以很容易在现有工艺下将所述第一沟道32的长度控制在1微米以下。
进一步地，在其他实施例中，还可以叠加两个薄膜晶体管，但不以此为限，还可叠加三个、四个或更多个的薄膜晶体管。本申请实施例以叠加两个薄膜晶体管为例进行阐述说明。
请参阅图4~图6，图4为本申请实施例提供的另一种薄膜晶体管的平面结构示意图；图5为图4中沿B-B方向的剖面示意图；图6为图4中沿A-A方向的剖面示意图。图4~图6与图1~图3的不同之处在于，所述至少两层欧姆接触层21还包括设置于所述第二欧姆接触层212上的第三欧姆接触层213，所述至少一层绝缘层还包括第二绝缘层222，所述第二绝缘层222位于所述第二欧姆接触层212和所述第三欧姆接触层213之间；所述至少一沟道31还包括第二沟道33，所述第二沟道33位于所述第二绝缘层222的所述第二侧壁22a上。
在本实施例中，所述凸台结构20由三层所述欧姆接触层和三层所述绝缘层构成，具体地，所述凸台结构20包括依次层叠设置于所述基板10上的第一欧姆接触层211、第一绝缘层221、第二欧姆接触层212、第二绝缘层222和第三欧姆接触层213。本实施例中的器件包括在所述显示面板的厚度方向上层叠设置的两个薄膜晶体管，两个薄膜晶体管分别具有一个沟道31。
可以理解的是，在本实施例中，所述半导体层30与所述第一欧姆接触层211、所述第二欧姆接触层212和所述第三欧姆接触层213接触连接，所述半导体层30位于所述第一欧姆接触层211和所述第二欧姆接触层212之间的部分形成一薄膜晶体管的所述第一沟道32，所述半导体层30位于所述第二欧姆接触层212和所述第三欧姆接触层213之间的部分形成另一薄膜晶体管的所述第二沟道33，即所述第一沟道32的长度可由第一欧姆接触层211和第二欧姆接触层212之间的第一绝缘层221的第二侧壁22a的长度和倾斜角度决定，所述第二沟道33的长度可由第二欧姆接触层212和第三欧姆接触层213之间的第二绝缘层222的第二侧壁22a的长度和倾斜角度决定，因此，在本实施例中，只需调整所述第一绝缘层221的第二侧壁22a和第二绝缘层222的第二侧壁22a的长度和倾斜角度即可控制所述第一沟道32和所述第二沟道33的长度，如此，可以很容易在现有工艺下将所述第一沟道32和所述第二沟道33的长度均控制在1微米以下。
所述显示面板还包括栅极绝缘层40、层间介质层60、源漏极金属层70、第一接触孔701、第二接触孔702和第三接触孔703。所述栅极绝缘层40设置于所述栅极50与所述半导体层30之间；所述层间介质层60设置于所述栅极绝缘层40远离所述基板10的一侧，所述层间介质层60覆盖所述栅极50和所述栅极绝缘层40；所述源漏极金属层70设置于所述层间介质层60远离所述基板10的一侧，所述源漏极金属层70包括第一漏极72、源极71和第二漏极73；所述第一接触孔701、所述第二接触孔702和所述第三接触孔703，贯穿所述层间介质层60和所述栅极绝缘层40。
为实现两个薄膜晶体管的并联，本实施例中的两个薄膜晶体管共用一个所述源极71，由于所述第二欧姆接触层212位于所述第一欧姆接触层211和所述第二欧姆接触层212之间，为了方便布线，本实施例将所述源极71与所述第二欧姆接触层212接触连接，两个薄膜晶体管的漏极（第一漏极72和第二漏极73）分别与所述第一欧姆接触层211和所述第二欧姆接触层212接触连接。具体地，所述源极71通过所述第一接触孔701与所述第二欧姆接触层212连接，所述第一漏极72通过贯穿所述第二接触孔702与所述第一欧姆接触层211连接，所述第二漏极73通过所述第三接触孔703与所述第三欧姆接触层213连接。
可以理解的是，在本实施例中，通过将两个层叠设置的薄膜晶体管并联连接，即两条沟道31（所述第一沟道32和所述第二沟道33）并联设置，因此，本实施例中的器件实际宽度为第一沟道32的宽度和第二沟道33的宽度之和，从而能够在有限空间内增大器件宽度，有利于增大开态电流，提高了器件的驱动能力。此外，两个薄膜晶体管在显示面板厚度方向上叠加，有利于降低器件体积，减小器件占地面积，从而提高了器件的集成度。
需要说明的是，为了实现所述源极71、所述第一漏极72和所述第二漏极73通过接触孔与相应的欧姆接触层21连接，需将多层欧姆接触层进行适应性设计，具体地，在本实施例中，所述第一欧姆接触层211、所述第二欧姆接触层212和所述第三欧姆接触层213呈阶梯状；所述第一欧姆接触层211包括第一突出部2111，所述第二欧姆接触层212在所述基板10上的正投影与所述第一突出部2111在所述基板10上的正投影不重叠；所述第二欧姆接触层212包括第二突出部2121，所述第三欧姆接触层213在所述基板10上的正投影与所述第二突出部2121在所述基板10上的正投影不重叠。本实施例通过将所述第一欧姆接触层211突出于所述第二欧姆接触层212和所述第三欧姆接触层213，可避免第一漏极72穿过所述第二欧姆接触层212和所述第三欧姆接触层213；通过将所述第二欧姆接触层212突出于所述第三欧姆接触层213，可避免所述源极71穿过所述第三欧姆接触层213。
在本实施例中，所述第一漏极72和所述第二漏极73分别位于所述源极71的相对两侧，以便于布线设计。
在本实施例中，所述第一漏极72、所述第二漏极73和所述源极71在所述基板10上的正投影均位于所述栅极50在所述基板10上的正投影的同一侧，以保证形成的所述沟道的位置位于所述第二侧壁22a上。
需要说明的是，上述实施例为一个和两个薄膜晶体管的叠加，其他更多个薄膜晶体管的叠加的实施例与上述实施例相似，可参考上述描述。
请参阅图，本申请实施例还提供一种制备方法，包括以下步骤：
S10：提供一基板10。
具体地，如图7A所示，所述S10包括以下步骤：提供一衬底11；在所述衬底11上形成遮光层12；以及，形成覆盖所述衬底11和所述遮光层12的缓冲层13。
S20：在基板10上形成凸台结构20，所述凸台结构20包括堆叠设置的至少两层欧姆接触层和至少一层绝缘层22，相邻两层所述欧姆接触层之间设置有一层所述绝缘层22。
具体地，以两个薄膜晶体管为例，如图7B所示，依次在所述缓冲层13上依次层叠第一欧姆接触层211的材料、第一绝缘层221的材料、第二欧姆接触层212的材料、第二绝缘层222的材料、第三欧姆接触层213的材料、第三绝缘层的材料以及第四欧姆接触层的材料；之后进行不同深度的刻蚀，以形成第一欧姆接触层211、第一绝缘层221、第二欧姆接触层212、第二绝缘层222和第三欧姆接触层213。需要说明的是，该不同深度的刻蚀工艺可经过同一灰度掩模板进行，也可分多次光罩进行，这里不做限制。
S30：形成至少部分位于所述凸台结构20的侧壁20a上的半导体层30，所述侧壁20a包括同侧设置的所述欧姆接触层21的第一侧壁21a和所述绝缘层22的第二侧壁22a。
具体地，如图7C所示，在所述第三欧姆接触层213上沉积非晶硅材料，并对非晶硅进行结晶处理，再对非晶硅材料进行刻蚀以形成所述半导体层30的图案。可以通过准分子激光退火工艺对非晶硅材料进行结晶处理。由于准分子激光退火工艺的能量有限，且全部被非晶硅所吸收，在对非晶硅层进行结晶处理时，所述欧姆接触层21仍然可以保持非晶硅结构。非晶硅的结晶处理也可在氧化处理之后进行，这里不做限制。
所述制备方法还包括：如图7D所示，S40：形成覆盖所述基板10和所述凸台结构20的栅极绝缘层40；如图7E所示，S50：在所述栅极绝缘层40远离所述凸台结构20的一侧形成栅极50；如图7F所示，S60：形成覆盖所述栅极50和所述栅极绝缘层40的层间介质层60；如图7F所示，S70：形成贯穿所述层间介质层60和所述栅极绝缘层40的第一接触孔701、第二接触孔702和第三接触孔703；如图7G所示，S80：在所述层间介质层60远离所述基板10的一侧形成源漏极金属层70，所述源漏极金属层70包括第一漏极72、源极71和第二漏极73，所述第一漏极72通过贯穿所述第一接触孔701与所述第一欧姆接触层211连接，所述源极71通过所述第二接触孔702与所述第二欧姆接触层212连接，所述第二漏极73通过所述第三接触孔703与所述第三欧姆接触层213连接。
本申请实施例还提供一种显示装置，所述显示装置包括上述实施例中的显示面板，所述显示装置包括但不限于电子纸、移动电话、平板电脑、电视机、显示器、笔记本电脑、数码相册、GPS等。
有益效果为：本申请实施例提供的显示面板及显示装置，通过在基板上叠加欧姆接触层和绝缘层形成一凸台结构，凸台结构包括堆叠设置的至少两层欧姆接触层和至少一层绝缘层，相邻两层所述欧姆接触层之间设置有一层所述绝缘层，至少部分半导体层位于凸台结构的侧壁上，半导体层与欧姆接触层的第一侧壁接触，半导体的沟道位于绝缘层的第二侧壁上，如此，只需调整第二侧壁的长度和倾斜角度即可控制沟道长度，不仅减小了沟道长度，还可实现多个薄膜晶体管在显示面板厚度方向上的叠加，降低薄器件体积，减小器件占地面积，有利于提高器件集成度，有利于实现基板上的IC电路集成。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，包括基板以及设置于所述基板上的凸台结构，其中，所述凸台结构包括堆叠设置的至少两层欧姆接触层和至少一层绝缘层，相邻两层所述欧姆接触层之间设置有一层所述绝缘层；
    所述显示面板还包括半导体层，至少部分所述半导体层位于所述凸台结构的侧壁上，所述侧壁包括同侧设置的所述欧姆接触层的第一侧壁和所述绝缘层的第二侧壁；所述半导体层包括至少一沟道，所述沟道位于所述第二侧壁上。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括栅极，所述栅极位于所述半导体层远离所述凸台结构的一侧，所述栅极在所述侧壁上的正投影覆盖所述沟道在所述侧壁上的正投影。
  3. 根据权利要求2所述的显示面板，其中，所述至少两层欧姆接触层包括依次堆叠设置于所述基板上的第一欧姆接触层和第二欧姆接触层，所述至少一层绝缘层包括第一绝缘层，所述第一绝缘层位于所述第一欧姆接触层和所述第二欧姆接触层之间；
    所述至少一沟道包括第一沟道，所述第一沟道位于所述第一绝缘层的所述第二侧壁上。
  4. 根据权利要求3所述的显示面板，其中，所述至少两层欧姆接触层还包括设置于所述第二欧姆接触层上的第三欧姆接触层，所述至少一层绝缘层还包括第二绝缘层，所述第二绝缘层位于所述第二欧姆接触层和所述第三欧姆接触层之间；
    所述至少一沟道还包括第二沟道，所述第二沟道位于所述第二绝缘层的所述第二侧壁上。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板还包括：
    栅极绝缘层，设置于所述栅极与所述半导体层之间；
    层间介质层，设置于所述栅极远离所述基板的一侧，所述层间介质层覆盖所述栅极和所述栅极绝缘层；
    源漏极金属层，设置于所述层间介质层远离所述基板的一侧，所述源漏极金属层包括第一漏极、源极和第二漏极；以及
    第一接触孔、第二接触孔和第三接触孔，贯穿所述层间介质层和所述栅极绝缘层；
    其中，所述源极通过所述第一接触孔与所述第二欧姆接触层连接，所述第一漏极通过贯穿所述第二接触孔与所述第一欧姆接触层连接，所述第二漏极通过所述第三接触孔与所述第三欧姆接触层连接。
  6. 根据权利要求5所述的显示面板，其中，所述第一欧姆接触层、所述第二欧姆接触层和所述第三欧姆接触层呈阶梯状；
    所述第一欧姆接触层包括第一突出部，所述第二欧姆接触层在所述基板上的正投影与所述第一凸出部在所述基板上的正投影不重叠；所述第二欧姆接触层包括第二突出部，所述第三欧姆接触层在所述基板上的正投影与所述第二凸出部在所述基板上的正投影不重叠。
  7. 根据权利要求6所述的显示面板，其中，所述第一漏极和所述第二漏极分别位于所述源极的相对两侧。
  8. 根据权利要求7所述的显示面板，其中，所述第一漏极、所述第二漏极和所述源极在所述基板上的正投影均位于所述栅极在所述基板上的正投影的同一侧。
  9. 根据权利要求1所述的显示面板，其中，所述侧壁、所述第一侧壁和所述第二侧壁位于同一平面。
  10. 根据权利要求9所述的显示面板，其中，所述半导体层包括倾斜部、第一水平部和第二水平部，所述倾斜部为所述半导体层位于所述凸台结构的侧壁上的部分，所述倾斜部位于所述第一水平部和所述第二水平部之间，所述第一水平部位于所述基板一侧，所述第二水平部位于所述凸台结构远离所述基板的一侧。
  11. 根据权利要求10所述的显示面板，其中，所述第一水平部与所述倾斜部之间的夹角为90°~135°；每一所述绝缘层的厚度范围为0.0071~1微米。
  12. 一种显示装置，包括显示面板；其中，所述显示面板包括基板以及设置于所述基板上的凸台结构，所述凸台结构包括堆叠设置的至少两层欧姆接触层和至少一层绝缘层，相邻两层所述欧姆接触层之间设置有一层所述绝缘层；
    所述显示面板还包括半导体层，至少部分所述半导体层位于所述凸台结构的侧壁上，所述侧壁包括同侧设置的所述欧姆接触层的第一侧壁和所述绝缘层的第二侧壁；所述半导体层包括至少一沟道，所述沟道位于所述第二侧壁上。
  13. 根据权利要求12所述的显示装置，其中，所述显示面板还包括栅极，所述栅极位于所述半导体层远离所述凸台结构的一侧，所述栅极在所述侧壁上的正投影覆盖所述沟道在所述侧壁上的正投影。
  14. 根据权利要求13所述的显示装置，其中，所述至少两层欧姆接触层包括依次堆叠设置于所述基板上的第一欧姆接触层和第二欧姆接触层，所述至少一层绝缘层包括第一绝缘层，所述第一绝缘层位于所述第一欧姆接触层和所述第二欧姆接触层之间；
    所述至少一沟道包括第一沟道，所述第一沟道位于所述第一绝缘层的所述第二侧壁上。
  15. 根据权利要求14所述的显示装置，其中，所述至少两层欧姆接触层还包括设置于所述第二欧姆接触层上的第三欧姆接触层，所述至少一层绝缘层还包括第二绝缘层，所述第二绝缘层位于所述第二欧姆接触层和所述第三欧姆接触层之间；
    所述至少一沟道还包括第二沟道，所述第二沟道位于所述第二绝缘层的所述第二侧壁上。
  16. 根据权利要求15所述的显示装置，其中，所述显示面板还包括：
    栅极绝缘层，设置于所述栅极与所述半导体层之间；
    层间介质层，设置于所述栅极远离所述基板的一侧，所述层间介质层覆盖所述栅极和所述栅极绝缘层；
    源漏极金属层，设置于所述层间介质层远离所述基板的一侧，所述源漏极金属层包括第一漏极、源极和第二漏极；以及
    第一接触孔、第二接触孔和第三接触孔，贯穿所述层间介质层和所述栅极绝缘层；
    其中，所述源极通过所述第一接触孔与所述第二欧姆接触层连接，所述第一漏极通过贯穿所述第二接触孔与所述第一欧姆接触层连接，所述第二漏极通过所述第三接触孔与所述第三欧姆接触层连接。
  17. 根据权利要求16所述的显示装置，其中，所述第一欧姆接触层、所述第二欧姆接触层和所述第三欧姆接触层呈阶梯状；
    所述第一欧姆接触层包括第一突出部，所述第二欧姆接触层在所述基板上的正投影与所述第一凸出部在所述基板上的正投影不重叠；所述第二欧姆接触层包括第二突出部，所述第三欧姆接触层在所述基板上的正投影与所述第二凸出部在所述基板上的正投影不重叠。
  18. 根据权利要求17所述的显示装置，其中，所述第一漏极和所述第二漏极分别位于所述源极的相对两侧。
  19. 根据权利要求18所述的显示装置，其中，所述第一漏极、所述第二漏极和所述源极在所述基板上的正投影均位于所述栅极在所述基板上的正投影的同一侧。
  20. 根据权利要求12所述的显示装置，其中，所述侧壁、所述第一侧壁和所述第二侧壁位于同一平面。
PCT/CN2023/104290 2022-12-08 2023-06-29 显示面板及显示装置 WO2024119795A1 (zh)

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