WO2023284384A1 - 一种堆叠结构及堆叠方法 - Google Patents

一种堆叠结构及堆叠方法 Download PDF

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Publication number
WO2023284384A1
WO2023284384A1 PCT/CN2022/091768 CN2022091768W WO2023284384A1 WO 2023284384 A1 WO2023284384 A1 WO 2023284384A1 CN 2022091768 W CN2022091768 W CN 2022091768W WO 2023284384 A1 WO2023284384 A1 WO 2023284384A1
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solder
layer
dielectric layer
nth
opening
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PCT/CN2022/091768
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English (en)
French (fr)
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张春艳
曹立强
曾淑文
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上海先方半导体有限公司
华进半导体封装先导技术研发中心有限公司
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Publication of WO2023284384A1 publication Critical patent/WO2023284384A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a stacking structure and a stacking method.
  • the three-dimensional integration technology represented by Through Silicon Via (TSV) technology has attracted more and more attention from the electronics industry.
  • Through-silicon via technology makes it possible for multiple chips to be stacked and integrated, thereby extending chip integration from two-dimensional integration to three-dimensional integration.
  • the three-dimensional stacked structure obtained by using the TSV process includes: several chips with TSVs stacked in sequence, organic fillers and several micro-bumps located between two adjacent chips, the organic fillers are used for The gap between two adjacent chips is packaged, and the micro-bumps are connected to the through-silicon vias of the two adjacent chips, thereby realizing the connection and vertical interconnection of adjacent chips.
  • the normal operation of the three-dimensional stack structure is related to the connection strength of the chips in the three-dimensional stack structure.
  • the connection strength of the chips is high, the three-dimensional stacking structure maintains a stable connection, thereby ensuring the normal operation of the three-dimensional stacking structure; It affects the normal operation of the three-dimensional stacked structure.
  • the technical problem to be solved in the present application is to overcome the defect of low connection strength of the existing three-dimensional stacking structure, so as to provide a stacking structure and a stacking method.
  • the present application provides a stacked structure, including the first package module to the Nth package module that are vertically stacked in sequence and electrically connected, N is an integer greater than or equal to 2, the nth package module includes an nth semiconductor unit, and the nth semiconductor unit It has a first surface and a second surface opposite to each other, n is an integer greater than or equal to 1 and less than or equal to N; the jth encapsulation module further includes: a first dielectric layer covering the first surface of the jth semiconductor unit, and j is greater than or equal to 1 Integers less than or equal to N-1; the first solder piece penetrating through the first dielectric layer; the j+1th packaging module further includes: a second dielectric layer covering the second surface of the j+1th semiconductor unit; penetrating through the The second solder piece of the second dielectric layer; wherein, the first dielectric layer of the jth packaging module and the second dielectric layer of the j+1th packaging module are bonded to each other; the first
  • the first dielectric layer has a first opening penetrating through the first dielectric layer, and the first solder piece is located in the first opening; the second dielectric layer has a penetrating through the first opening.
  • the second opening of the second dielectric layer, the second solder part is located in the second opening; for the first solder part and the second solder part welded together, the distance from the first solder part to the second solder part In the direction, the cross-sectional area of the first solder piece decreases gradually, and in the direction from the second solder piece to the first solder piece, the cross-sectional area of the second solder piece gradually decreases.
  • the nth packaging module further includes: an nth conductive member penetrating through the nth semiconductor unit; both ends of the kth conductive member are connected to the first solder member and the second The solder part is electrically connected, k is an integer greater than or equal to 2 and less than or equal to N-1; one end of the first conductive part is electrically connected to the first solder part in the first packaging module, and the Nth conductive part in the Nth semiconductor unit One end is electrically connected to the second solder member in the Nth packaging module; the first packaging module further includes a first conductive circuit layer on the first surface of the first semiconductor unit, and the first conductive circuit layer is connected to the first semiconductor unit.
  • the j+1th packaging module further includes a j+1th conductive circuit layer located on the second surface of the j+1th semiconductor unit, and the j+1th conductive circuit layer is connected to the j+1th conductive circuit layer The j+1th conductive element is electrically connected.
  • a first conductive protection layer located at the bottom of the first solder part is also provided in the first opening; a second conductive protection layer located at the bottom of the second solder part is also provided in the second opening. layer.
  • the thickness of the first dielectric layer is 2 ⁇ m-10 ⁇ m
  • the thickness of the second dielectric layer is 2 ⁇ m-10 ⁇ m.
  • the inner diameter of the first opening is 5 ⁇ m-30 ⁇ m
  • the inner diameter of the second opening is 5 ⁇ m-30 ⁇ m.
  • a volume ratio of the first solder piece to the first opening is 0.8-1.2
  • a volume ratio of the second solder piece to the second opening is 0.8-1.2
  • materials of the first solder piece and the second solder piece include tin alloy; materials of the first dielectric layer and the second dielectric layer include silicon oxide.
  • the material of the first solder piece and the second solder piece is SnAg.
  • the nth semiconductor unit includes a dynamic random access memory.
  • the present application also provides a stacking method, including: forming the first packaging module to the Nth packaging module that are vertically stacked and electrically connected in sequence, N is an integer greater than or equal to 2, the nth packaging module includes an nth semiconductor unit, and the The n semiconductor unit has a first surface and a second surface oppositely arranged, and n is an integer greater than or equal to 1 and less than or equal to N; the step of forming the jth packaging module further includes: forming a first medium covering the first surface of the jth semiconductor unit layer, j is an integer greater than or equal to 1 and less than or equal to N-1; forming a first solder piece penetrating through the first dielectric layer; the step of forming the j+1th packaging module further includes: forming a covering j+1th semiconductor unit The second dielectric layer on the second surface; forming a second solder piece penetrating through the second dielectric layer; forming the steps of vertically stacking and electrically connecting the first packaging module to the Nth packaging module
  • the thickness of the first solder layer is greater than or equal to two-thirds of the inner diameter of the first opening and less than the thickness of the first dielectric layer; the thickness of the second solder layer is greater than or equal to the first Two-thirds of the inner diameter of the two openings is less than the thickness of the second dielectric layer.
  • the process of soldering the first solder layer of the jth packaging module to the second solder layer of the j+1th semiconductor module includes a reflow soldering process.
  • the parameters of the reflow soldering process include: the reflow soldering temperature is 220°C-280°C, and the reflow soldering time is 30s-60s.
  • the stacking method further includes: before forming the first solder layer in the first opening, forming a first conductive protection layer covering the jth semiconductor unit in the first opening; After the first solder layer is formed, the first conductive protection layer is located at the bottom of the first solder layer; before the second solder layer is formed in the second opening, a protective layer covering the first The second conductive protection layer of the j+1 semiconductor unit; after forming the second solder layer, the second conductive protection layer is located at the bottom of the second solder layer.
  • the first dielectric layer of the jth packaging module and the second dielectric layer of the j+1th packaging module are bonded to each other, which has a relatively large connection strength; at the same time, the The first solder piece of the j-th packaging module is also welded together with the second solder piece of the j+1-th semiconductor module, which significantly improves the connection strength between the j-th packaging module and the j+1-th packaging module. Adjacent packaged modules are not easy to be separated, thereby improving the structural stability of the stacked structure, avoiding the separation of adjacent packaged modules under the influence of the environment or external force, and ensuring the normal operation of the stacked structure.
  • the thermal conductivity of the first dielectric layer and the second dielectric layer is better than that of organic fillers, which can improve the heat dissipation efficiency of the stacked structure, thereby effectively avoiding the adverse effects of excessive internal temperature on the stacked structure, which is conducive to the normal operation of the stacked structure. Work.
  • the cross-sectional area of the first solder piece Gradually decreasing, there is a gap between the first solder piece and the first dielectric layer; from the second solder piece to the direction of the first solder piece, the cross-sectional area of the second solder piece gradually decreases Small, there is a gap between the second solder piece and the second dielectric layer, while ensuring the vertical interconnection of adjacent packaging modules, reducing the amount of the first solder piece and the second solder piece, saving costs.
  • the first conductive protective layer located at the bottom of the first solder part is provided in the first opening, which isolates the first solder part from the conductive part, avoiding the problem of reflow soldering.
  • the electrical transmission performance of the conductive part caused by the reaction between the first solder part and the conductive part is affected; by arranging a second conductive protective layer at the bottom of the second solder part in the second opening, the said The second solder part and the conductive part avoid the impact on the electrical transmission performance of the conductive part caused by the reaction between the second solder part and the conductive part during the reflow soldering process.
  • the thickness of the first dielectric layer is 2 ⁇ m-10 ⁇ m
  • the thickness of the second dielectric layer is 2 ⁇ m-10 ⁇ m.
  • the thickness of the first solder piece is limited by the thickness of the first dielectric layer
  • the thickness of the second solder piece is limited by the thickness of the second dielectric layer. Therefore, the thickness of the first solder piece is 2 ⁇ m-10 ⁇ m, so The thickness of the second solder piece is 2 ⁇ m-10 ⁇ m.
  • the spacing between adjacent packaging modules is controlled, thereby increasing the integration density;
  • the overall length of the formed vertical interconnection structure reduces the overall resistance value of the vertical interconnection structure, thereby reducing the heat generated by the vertical interconnection structure, and finally reducing the total heat generated by the stacked structure.
  • the first dielectric layer of the jth packaging module and the second dielectric layer of the j+1th packaging module are bonded to each other, so that the jth packaging module and the The j+1 package module has a relatively large connection strength; and the first solder piece of the jth package module is welded together with the second solder piece of the j+1th semiconductor module, which significantly improves the jth package module.
  • the connection strength between the packaging module and the j+1th packaging module makes it difficult for adjacent packaging modules to be separated, thereby improving the structural stability of the stack structure and ensuring the normal operation of the stack structure.
  • the thermal conductivity of the first dielectric layer and the second dielectric layer is better than that of organic fillers, which can increase the heat dissipation rate of the stacked structure, thereby effectively avoiding the adverse effects of excessive temperature in the stacked structure on the performance of the stacked structure, which is beneficial to the stacked structure. normal work.
  • the stacking method provided in this application utilizes the hemispherical characteristic of solder after melting. Specifically, during the soldering process, the first solder layer and the second solder layer melt into a hemispherical liquid state, which increases the height of the first solder layer and the second solder layer, so that the liquid first solder layer and the second solder layer
  • the layers are in contact with each other and connected as a whole after cooling, wherein the deformed first solder layer constitutes the first solder part, and the deformed second solder layer constitutes the second solder part, so the first solder layer does not need to fill up the The first opening and the second solder layer do not need to fill the second opening, which reduces the amount of solder; by forming the first solder layer in the first opening and forming the second solder layer in the second opening, the second solder layer is defined.
  • the formation area of the first solder layer and the second solder layer facilitates the control of the formation volumes of the first solder layer and the second solder layer;
  • the melted first solder layer and the second solder layer are arranged opposite to each other, so as to ensure that the melted hemispherical liquid first solder layer and the second solder layer are connected together after cooling, that is, the first dielectric layer and the second dielectric layer.
  • the setting of not only can connect adjacent packaging modules, but also facilitates the smooth connection of the first solder piece and the second solder piece.
  • the thickness of the first solder layer is greater than or equal to two-thirds of the inner diameter of the first opening and less than the thickness of the first dielectric layer; the thickness of the second solder layer greater than or equal to two-thirds of the inner diameter of the second opening and less than the thickness of the second dielectric layer.
  • FIG. 1 is a schematic structural diagram of a stacked structure provided in an embodiment of the present application.
  • Fig. 2 is a process flow chart of the stacking method provided by the embodiment of the present application.
  • Figure 3- Figure 17 is a schematic structural diagram during the stacking process
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.
  • this embodiment also provides a stacked structure, including the first package module to the Nth package module that are vertically stacked and electrically connected in sequence, N is an integer greater than or equal to 2, and the nth package module includes the nth semiconductor unit 1n , the nth semiconductor unit 1n has a first surface and a second surface oppositely arranged, and n is an integer greater than or equal to 1 and less than or equal to N;
  • the jth packaging module further includes: a first surface covering the first surface of the jth semiconductor unit Dielectric layer 3, j is an integer greater than or equal to 1 and less than or equal to N-1; the first solder piece 32 runs through the first dielectric layer 3;
  • the j+1th packaging module also includes: the j+1th semiconductor unit covering The second dielectric layer 4 on the two surfaces; the second solder member 42 penetrating through the second dielectric layer 4; wherein, the first dielectric layer 3 of the jth packaging module and the second dielectric layer 3 of the j+1th packaging module
  • N is
  • the first dielectric layer 3 of the jth packaging module and the second dielectric layer 4 of the j+1th packaging module are bonded to each other, which has a relatively large connection strength; at the same time, the jth packaging module
  • the first solder piece 32 of the packaging module is also welded together with the second solder piece 42 of the j+1th semiconductor module, which significantly improves the connection strength between the jth packaging module and the j+1th packaging module, so that adjacent The packaged modules are not easy to be separated, thereby improving the structural stability of the stacked structure, avoiding the separation of adjacent packaged modules under the influence of the environment or external force, and ensuring the normal operation of the stacked structure.
  • the thermal conductivity of the first dielectric layer 3 and the second dielectric layer 4 is better than that of organic fillers, which can improve the heat dissipation efficiency of the stacked structure, thereby effectively avoiding the adverse effects of the high internal temperature of the stacked structure on the stacked structure, which is beneficial to the stacked structure. normal work.
  • the thickness of the first dielectric layer 3 is 2 ⁇ m-10 ⁇ m
  • the thickness of the second dielectric layer 4 is 2 ⁇ m-10 ⁇ m.
  • the thickness of the first solder piece 32 is limited by the thickness of the first dielectric layer 3, and the thickness of the second solder piece 42 is limited by the thickness of the second dielectric layer 4. Therefore, the thickness of the first solder piece 32 is 2 ⁇ m-10 ⁇ m, the thickness of the second solder piece 42 is 2 ⁇ m-10 ⁇ m.
  • the distance between adjacent packaging modules is controlled, thereby increasing the integration density; and at the same time, it is also reduced
  • the overall length of the vertical interconnection structure formed by the two solder pieces 42 reduces the overall resistance value of the vertical interconnection structure, thereby reducing the heat generated by the vertical interconnection structure, and finally reducing the total heat generated by the stacked structure.
  • the first dielectric layer 3 has a first opening 31 penetrating through the first dielectric layer 3, the first solder piece 32 is located in the first opening 31; the second dielectric layer There is a second opening 41 through the second dielectric layer 4 in the layer 4, and the second solder piece 42 is located in the second opening 41; for the first solder piece 32 and the second solder piece 42 welded together , from the first solder piece 32 to the direction of the second solder piece 42, the cross-sectional area of the first solder piece 32 gradually decreases, from the second solder piece 42 to the direction of the first solder piece 32 Above, the cross-sectional area of the second solder piece 42 decreases gradually.
  • the inner diameter of the first opening 31 is 5 ⁇ m-30 ⁇ m
  • the inner diameter of the second opening 41 is 5 ⁇ m-30 ⁇ m.
  • the size of the first solder piece 32 is limited by the size of the first opening
  • the size of the second solder piece 42 is limited by the size of the second opening 41, by connecting the first opening 31 and the second opening 41
  • the inner diameter is limited to the above range, so that the amount of the first solder piece 32 and the second solder piece 42 can be controlled.
  • the amount of the first solder piece 32 and the second solder piece 42 is reduced, saving costs.
  • the volume ratio of the first solder piece 32 to the first opening 31 is 0.8-1.2
  • the volume ratio of the second solder piece 42 to the second opening 41 is 0.8-1.2.
  • the material of the first solder piece 32 and the second solder piece 42 includes tin alloy; specifically, the material of the first solder piece 32 and the second solder piece 42 can be SnAg .
  • the material of the first dielectric layer 3 and the second dielectric layer 4 includes silicon oxide.
  • the material of the conductive member includes but not limited to copper.
  • the nth packaging module further includes an nth conductive member 2n penetrating through the nth semiconductor unit 1n; both ends of the kth conductive member are respectively connected to the first solder member 32 and The second solder member 42 is electrically connected, k is an integer greater than or equal to 2 and less than or equal to N-1; one end of the first conductive member 21 is electrically connected to the first solder member 32 in the first packaging module, in the Nth semiconductor unit 1N One end of the Nth conductive member 2N is electrically connected to the second solder member 42 in the Nth packaging module. As shown in FIG.
  • the second conductive member 22 runs through the second semiconductor unit 12, and the third conductive member 23 runs through the third Semiconductor unit 13;
  • the first packaging module also includes a first conductive circuit layer (not shown in the figure) located on the first surface of the first semiconductor unit 11, the first conductive circuit layer and the first conductive member 21 electrical connection;
  • the j+1th packaging module further includes a j+1th conductive circuit layer located on the second surface of the j+1th semiconductor unit, and the j+1th conductive circuit layer is connected to the jth +1 Conductor for electrical connection.
  • the first solder piece 32 and the second solder piece 42, as well as the second solder piece 42 in the Nth packaging module constitute an interconnection structure of a stacked structure to achieve electrical communication.
  • the diameter of the nth conductive member 2n is 5 ⁇ m-30 ⁇ m.
  • the nth semiconductor unit 1n is provided with an nth functional structure (not shown in the figure), the nth functional structure is located under the nth conductive circuit layer and is electrically connected to the nth conductive circuit layer , the conductive member is located at the side of the nth functional structure.
  • the interconnection structure is used to drive the first functional structure to the Nth functional structure to work.
  • a first conductive protective layer located at the bottom of the first solder piece 32 is also provided in the first opening 31, isolating the first solder piece and The conductive part avoids the impact on the electrical transmission performance of the conductive part caused by the reaction between the first solder part and the conductive part during the reflow soldering process; the second opening 41 is also provided at the bottom of the second solder part 42 The second conductive protective layer (not shown in the figure) isolates the second solder part and the conductive part, avoiding the electric transmission performance of the conductive part being affected by the reaction between the second solder part and the conductive part during the reflow soldering process. influences.
  • the material of the first conductive protection layer and the second conductive protection layer includes a Ti/Cu/Ni composite layer, wherein the Ni layer is in contact with the solder piece.
  • the thickness of the first conductive protection layer and the second conductive protection layer is 1 ⁇ m-2 ⁇ m.
  • the second surface of the first semiconductor unit 11 is provided with a first UBM layer, and the first UBM layer is electrically connected to the first conductive member 21, so A number of solder balls are provided on the surface of the first UBM layer away from the first conductive member 21 for electrical connection with other semiconductor structures; the first surface of the Nth semiconductor unit 1N is provided with The second UBM layer, the surface of the second UBM layer facing away from the Nth conductive member 2N is provided with several solder balls for electrical connection with other semiconductor structures.
  • the nth semiconductor unit 1n includes but not limited to dynamic random access memory; when the first semiconductor unit to the Nth semiconductor unit 1N are all dynamic random access memories, the stack structure is suitable for Logic chips make up high-bandwidth memory.
  • This embodiment also provides a stacking method, including: forming the first packaging module to the Nth packaging module that are vertically stacked in sequence and electrically connected, N is an integer greater than or equal to 2, and the nth packaging module includes the nth semiconductor unit 1n, so The nth semiconductor unit 1n has a first surface and a second surface oppositely arranged, and n is an integer greater than or equal to 1 and less than or equal to N; the step of forming the jth packaging module further includes: forming a surface covering the first surface of the jth semiconductor unit For the first dielectric layer 3, j is an integer greater than or equal to 1 and less than or equal to N-1; forming a first solder piece 32 penetrating through the first dielectric layer 3; the step of forming the j+1th packaging module further includes: forming The second dielectric layer 4 on the second surface of the j+1 semiconductor unit; forming the second solder member 42 penetrating through the second dielectric layer 4; forming the first packaging module to the Nth packaging module that
  • the first dielectric layer 3 of the jth packaging module and the second dielectric layer 4 of the j+1th packaging module are bonded to each other, so that the jth packaging module and the j+1th packaging module
  • the module has a relatively large connection strength; and the first solder piece 32 of the jth packaging module is also welded together with the second solder piece 42 of the j+1th semiconductor module, which significantly improves the connection between the jth packaging module and the jth packaging module.
  • the connection strength of the j+1 packaged modules makes it difficult for adjacent packaged modules to be separated, thereby improving the structural stability of the stacked structure and ensuring the normal operation of the stacked structure.
  • the thermal conductivity of the first dielectric layer 3 and the second dielectric layer 4 is better than that of organic fillers, which can increase the heat dissipation rate of the stacked structure, thereby effectively avoiding the adverse effects of excessive temperature in the stacked structure on the performance of the stacked structure, which is beneficial to normal operation of the stacked structure.
  • the step of forming the first solder piece 32 penetrating the first dielectric layer 3 includes: forming a first opening 31 penetrating the first dielectric layer 3 in the first dielectric layer 3;
  • the first solder layer 33 covering the jth semiconductor unit is formed in the first opening 31;
  • the step of forming the second solder member 42 penetrating through the second dielectric layer 4 includes: in the second dielectric layer 4 forming a second opening 41 through the second dielectric layer 4; forming a second solder layer 43 covering the j+1th semiconductor unit in the second opening 41; 33 is soldered to the second solder layer 43 of the j+1th semiconductor module, the first solder layer 33 is deformed to form the first solder piece 32 , and the second solder layer 43 is deformed to form the second solder piece 42 .
  • the step of forming the first solder piece 32 and the second solder piece 42 in this embodiment utilizes the hemispherical characteristic of the solder after melting. Specifically, during the soldering process, the first solder layer 33 and the second solder layer 43 are melted into a hemispherical liquid state, which increases the height of the first solder layer 33 and the second solder layer 43, so that the liquid first solder layer 33 is in contact with the second solder layer 43, and is connected as a whole after cooling, wherein the deformed first solder layer 33 forms the first solder piece 32, and the deformed second solder layer 43 forms the second solder piece 42, Therefore the first solder layer 33 does not need to fill the first opening 31 and the second solder layer 43 does not need to fill the second opening 41, which reduces the amount of solder; by forming the first solder layer in the first opening 31 33 and form the second solder layer 43 in the second opening 41, which limits the formation area of the first solder layer 33 and the second solder layer 43, on the one hand
  • the solder layer 33 and the second solder layer 43 are connected together after cooling, that is, the setting of the first dielectric layer 3 and the second dielectric layer 4 can not only connect adjacent packaging modules, but also facilitate the first solder member 32 and the second The solder piece 42 is connected smoothly.
  • the thickness of the first solder layer 33 is greater than or equal to two-thirds of the inner diameter of the first opening 31 and less than the thickness of the first dielectric layer 3; the thickness of the second solder layer 43 is greater than It is equal to two-thirds of the inner diameter of the second opening 41 and less than the thickness of the second dielectric layer 4 .
  • the step of forming the nth initial packaging module includes:
  • an nth semiconductor unit 1n where an nth conductive circuit layer is disposed on a front surface of the nth semiconductor unit 1n.
  • an nth functional structure is further provided in the nth semiconductor unit 1n, and the nth functional structure is located under the nth conductive circuit layer and electrically connected to the nth conductive circuit layer.
  • an nth conductive member 2n extending to a partial depth of the nth semiconductor unit 1n is formed, and the front side of the nth semiconductor unit 1n exposes one side surface of the nth conductive member 2n, so The nth conductive element 2n is electrically connected to the nth conductive circuit layer. Specifically, the nth conductive member 2n is located at the side of the nth functional structure.
  • the front of the first semiconductor unit 11 constitutes the first surface of the first semiconductor unit 11
  • the back of the first semiconductor unit 11 constitutes the second surface of the first semiconductor unit 11
  • the j+1th semiconductor unit constitutes the first surface of the j+1th semiconductor unit
  • the front surface of the j+1th semiconductor unit constitutes the second surface of the j+1th semiconductor unit.
  • the process for forming the nth conductive member 2n is a through-silicon via (TSV) process.
  • the first dielectric material layer 5 located on the surface of the first semiconductor unit 11 forms the first dielectric layer 3 of the first initial packaging module, and the opening 7 located in the first dielectric layer 3 forms the first opening 31;
  • the first dielectric material layer 5 on the surface of the j+1th semiconductor unit constitutes the second dielectric layer 4 of the j+1th initial packaging module, and the opening 7 in the second dielectric layer 4 constitutes the second opening 41 .
  • the process of forming the opening through the first dielectric material layer 5 includes a photolithography process.
  • solder layer 8 inside the opening 7 of the first dielectric material layer 5 to obtain an nth initial packaging module.
  • the solder layer 8 located on the surface of the first semiconductor unit 11 constitutes the first solder layer 33 of the first initial packaging module
  • the solder layer 8 located on the surface of the j+1th semiconductor unit constitutes the j+1th initial package
  • the second solder layer 43 of the module includes an electroplating process.
  • the first dielectric layer 3 of the jth initial packaging module and the second dielectric layer 4 of the j+1th initial packaging module bonded together.
  • bonding the first dielectric layer 3 of the jth packaging module and the second dielectric layer 4 of the j+1th packaging module includes activation, alignment and bonding steps.
  • solder the first solder layer 33 of the jth primary packaging module and the second solder layer 43 of the j+1th primary packaging module together.
  • the process of soldering the first solder layer 33 of the jth packaging module to the second solder layer 43 of the j+1th semiconductor module includes a reflow soldering process, the temperature of the reflow soldering process is easy to control and oxidation can be avoided during the soldering process .
  • the parameters of the reflow soldering process include: the reflow soldering temperature is 220°C-280°C, and the reflow soldering time is 30s-60s.
  • the first dielectric layer 3 on the back of the kth initial packaging module has a first opening 31, k is an integer greater than or equal to 2 and less than or equal to N-1;
  • the steps of the first dielectric layer 3 on the back side of the initial encapsulation module include:
  • the process of forming the first opening 31 through the second dielectric material layer 6 includes a photolithography process.
  • forming a first solder layer 33 located in the first opening 31 of the second dielectric material layer 6 forming a first solder layer 33 located in the first opening 31 of the second dielectric material layer 6 .
  • the process of forming the first solder layer 33 in the first opening 31 of the second dielectric material layer 6 includes an electroplating process.
  • the first dielectric layer 3 and the first solder piece 32 on the first surface constitute a first packaging module.
  • the process of thinning the second surface of the first initial packaging module includes a chemical mechanical polishing process.
  • the second initial packaging module is placed on the first initial packaging module; then the first dielectric layer 3 of the first initial packaging module and the first initial packaging module The second dielectric layer 4 of the two initial packaging modules is bonded together; subsequently, as shown in Figure 8, the first solder layer 33 of the first initial packaging module and the second solder layer 43 of the second initial packaging module are reflowed Processing, the first solder layer 33 and the second solder layer 43 are deformed to obtain the first solder piece 32 and the second solder piece 42, and the first solder piece 32 and the second solder piece 42 are welded together; subsequently, as shown in FIG.
  • the second surface of the first initial packaging module is not thinned, but the following steps are performed : sequentially forming the first dielectric layer 3 and the first solder layer 33 of the second initial packaging module on the first surface of the second initial packaging module; then placing the third initial packaging module on the second initial packaging module, sequentially Carry out the bonding of the first dielectric layer 3 of the second initial packaging module and the second dielectric layer 4 of the third initial packaging module, the first solder piece 32 of the first initial packaging module and the second solder piece of the second initial packaging module 42 welding, the thinning of the first surface of the third initial packaging module, and the thinning of the second surface of the first initial packaging module, the first packaging module, the second packaging module and the third packaging module that are electrically connected can be obtained.
  • Packaging modules When the number of packaging modules in the stacked structure is greater than 3, repeat the above steps until the first surface of the Nth initial packaging module is thinned to expose one side surface of the Nth conductive member 2N, and the first surface of the Nth initial packaging module After the surface is thinned, the second surface of the first initial packaging module is thinned.
  • the stacking method further includes: before forming the first solder layer 33 in the first opening 31, forming a first conductive protective layer covering the jth semiconductor unit in the first opening 31 layer; after forming the first solder layer 33, the first conductive protective layer is located at the bottom of the first solder layer 33; before forming the second solder layer 43 in the second opening 41, in A second conductive protective layer covering the j+1th semiconductor unit is formed in the second opening 41; after the second solder layer 43 is formed, the second conductive protective layer is located at the bottom of the second solder layer 43 .
  • the process of forming the first conductive protection layer and the second conductive protection layer includes an electroplating process.

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Abstract

本申请提供一种堆叠结构及堆叠方法，堆叠结构包括依次垂直层叠且电学连接的第一封装模块至第N封装模块，N为大于等于2的整数，第n封装模块包括第n半导体单元，n为大于等于1小于等于N的整数；第j封装模块还包括：覆盖第j半导体单元的第一表面的第一介质层，j为大于等于1小于等于N-1的整数；贯穿第一介质层的第一焊料件；第j+1封装模块还包括：覆盖第j+1半导体单元的第二表面的第二介质层；贯穿第二介质层的第二焊料件；其中，第j封装模块的第一介质层与第j+1封装模块的第二介质层相互键合；第j封装模块的第一焊料件与第j+1半导体模块的第二焊料件焊接在一起。堆叠结构具有较高的结构稳定性，保证了堆叠结构的正常工作。

Description

一种堆叠结构及堆叠方法
本申请要求在2021年07月12日提交中国专利局、申请号为202110784789.4、发明名称为“一种堆叠结构及堆叠方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，具体涉及一种堆叠结构及堆叠方法。
背景技术
随着便携式设备的智能化、小型化和普及化，以硅通孔(Through Silicon Via，TSV)技术为代表的三维立体集成技术越发受到电子行业的关注。硅通孔技术使得多个芯片相互堆叠集成成为可能，从而将芯片集成从二维集成扩展到三维集成。具体地，采用硅通孔工艺得到的三维堆叠结构包括：依次堆叠设置的若干个具有硅通孔的芯片、位于相邻两个芯片之间的有机填料和若干个微凸块，有机填料用于对相邻两个芯片之间的间隙进行封装，微凸块与相邻两个芯片的硅通孔连接，从而实现了相邻芯片的连接以及垂直互联。
三维堆叠结构的正常工作与三维堆叠结构中芯片的连接强度相关。当芯片的连接强度较大时，三维堆叠结构保持稳定连接，从而保证了三维堆叠结构的正常工作；当芯片连接强度较小时，相邻两个芯片容易在环境影响或外力作用下发生分离，从而影响了三维堆叠结构正常工作。
发明内容
因此，本申请要解决的技术问题在于克服现有三维堆叠结构的连接强度较小的缺陷，从而提供一种堆叠结构及堆叠方法。
本申请提供一种堆叠结构，包括依次垂直层叠且电学连接的第一封装模块至第N封装模块，N为大于等于2的整数，第n封装模块包括第n半导体单元，所述第n半导体单元具有相对设置的第一表面和第二表面，n为大于等于1小于等于N的整数；第j封装模块还包括：覆盖第j半导体单元的第一表面的第一介质层，j为大于等于1小于等于N-1的整数；贯穿所述第一介质层的第一焊料件；第j+1封装模块还包括：覆盖第j+1半导体单元的第二表面的第二介质层；贯穿所述第二介质层的第二焊料件；其中，所述第j封装模块的第一介质层与所述第j+1封装模块的第二介质层相互键合；所述第j封装模块的第一焊料件与所述第j+1半导体模块的第二焊料件焊接在一起。
可选地，所述第一介质层中具有贯穿所述第一介质层的第一开口，所述第一焊料件位于所述第一开口中；所述第二介质层中具有贯穿所述第二介质层的第二开口，所述第二焊料件位于所述第二开口中；对于焊接在一起的第一焊料件和第二焊料件，自所述第一焊料件至第二焊料件的方向上，所述第一焊料件的横截面积逐渐减小，自所述第二焊料件至第一焊料件的方向上，所述第二焊料件的横截面积逐渐减小。
可选地，所述第一焊料件与所述第一介质层之间具有间隙，所述第二焊料件与所述第二介质层之间具有间隙。
可选地，所述第n封装模块还包括:贯穿所述第n半导体单元的第n导电件；所述第k导电件的两端分别与第k封装模块中的第一焊料件和第二焊料件电学连接，k为大于等于2且小于等于N-1的整数；第一导电件的一端与第一封装模块中的第一焊料件电学连接，第N半导体单元中的第N导电件的一端与第N封装模块中的第二焊料件电学连接；所述第一封装模块还包括位于第一半导体单元的第一表面的第一导电线路层，所述第一导电线路层与所述第一导电件电学连接；所述第j+1封装模块还包括位于所述第j+1半导体单元的第二表面的第j+1导电线路层，所述第j+1导电线路层与所述第j+1导电件电学连接。
可选地，所述第一开口内还设置有位于所述第一焊料件底部的第一导电保护层；所述第二开口内还设置有位于所述第二焊料件底部的第二导电保护层。
可选地，所述第一介质层的厚度为2μm-10μm，所述第二介质层的厚度为2μm-10μm。
可选地，所述第一开口的内径为5μm-30μm，所述第二开口的内径为5μm-30μm。
可选地，所述第一焊料件的体积与所述第一开口的体积比值为0.8-1.2，所述第二焊料件的体积与所述第二开口的体积比值为0.8-1.2。
可选地，所述第一焊料件和所述第二焊料件的材料包括锡合金；所述第一介质层和所述第二介质层的材料包括氧化硅。
可选地，所述第一焊料件和所述第二焊料件的材料为SnAg。
可选地，所述第n半导体单元包括动态随机存取存储器。
本申请还提供一种堆叠方法，包括：形成依次垂直层叠且电学连接的第一封装模块至第N封装模块，N为大于等于2的整数，第n封装模块包括第n半导体单元，所述第n半导体单元具有相对设置的第一表面和第二表面，n为大于等于1小于等于N的整数；形成第j封装模块的步骤还包括：形成覆盖第j半导体单元的第一表面的第一介质层，j为大于等于1小于等于N-1的整数；形成贯穿所述第一介质层的第一焊料件；形成第j+1封装模块的步骤还包括：形成覆盖第j+1半导体单元的第二表面的第二介质层；形成贯穿所述第二介质层的第二焊料件；形成依次垂直层叠且电学连接的第一封装模块至第N封装模块的步骤包括：将所述第j封装模块的第一介质层与所述第j+1封装模块的第二介质层相互键合之后，将所述第j封装模块的第一焊料件与所述第j+1半导体模块的第二焊料件焊接在一起。
可选地，形成贯穿所述第一介质层的第一焊料件的步骤包括：在所述 第一介质层中形成贯穿所述第一介质层的第一开口；在所述第一开口中形成覆盖第j半导体单元的第一焊料层；形成贯穿所述第二介质层的所述第二焊料件的步骤包括：在所述第二介质层中形成贯穿所述第二介质层的第二开口；在所述第二开口中形成覆盖第j+1半导体单元的第二焊料层；将所述第j封装模块的第一焊料层与所述第j+1半导体模块的第二焊料层焊接后，所述第一焊料层变形构成第一焊料件，所述第二焊料层变形构成第二焊料件。
可选地，所述第一焊料层的厚度大于等于所述第一开口的内径的三分之二且小于所述第一介质层的厚度；所述第二焊料层的厚度大于等于所述第二开口的内径的三分之二且小于所述第二介质层的厚度。
可选地，将所述第j封装模块的第一焊料层与所述第j+1半导体模块的第二焊料层焊接的工艺包括回流焊工艺。
可选地，所述回流焊工艺的参数包括：回流焊的温度为220℃-280℃，回流焊的时间为30s-60s。
可选地，所述堆叠方法还包括：在所述第一开口中形成所述第一焊料层之前，在所述第一开口中形成覆盖第j半导体单元的第一导电保护层；在形成所述第一焊料层之后，所述第一导电保护层位于所述第一焊料层的底部；在所述第二开口中形成所述第二焊料层之前，在所述第二开口中形成覆盖第j+1半导体单元的第二导电保护层；在形成所述第二焊料层之后，所述第二导电保护层位于所述第二焊料层的底部。
本申请技术方案，具有如下优点：
1.本申请提供的堆叠结构，所述第j封装模块的第一介质层与所述第j+1封装模块的第二介质层相互键合，具有较大的连接强度；与此同时，所述第j封装模块的第一焊料件还与所述第j+1半导体模块的第二焊料件焊接在一起，这显著提高了第j封装模块和第j+1封装模块的连接强度，使相邻封装模块不易发生分离，进而提高了堆叠结构的结构稳定性，避免了相邻封 装模块在环境影响或外力作用下发生分离，保证了堆叠结构的正常工作。此外，第一介质层和第二介质层的导热性能优于有机填料，从而能够提高堆叠结构的散热效率，进而有效避免堆叠结构内部温度过高对堆叠结构造成不良影响，有利于堆叠结构的正常工作。
2.本申请提供的堆叠结构，对于焊接在一起的第一焊料件和第二焊料件，自所述第一焊料件至第二焊料件的方向上，所述第一焊料件的横截面积逐渐减小，所述第一焊料件与所述第一介质层之间具有间隙；自所述第二焊料件至第一焊料件的方向上，所述第二焊料件的横截面积逐渐减小，所述第二焊料件与所述第二介质层之间具有间隙，在保证了相邻封装模块垂直互联的同时，缩小了第一焊料件和第二焊料件的用量，节约了成本。
3.本申请提供的堆叠结构，通过在所述第一开口内设置位于所述第一焊料件底部的第一导电保护层，隔离了所述第一焊料件和导电件，避免了在回流焊工艺过程中第一焊料件与导电件发生反应导致的导电件电传输性能受到影响；通过在所述第二开口内设置位于所述第二焊料件底部的第二导电保护层，隔离了所述第二焊料件和导电件，避免了在回流焊工艺过程中第二焊料件与导电件发生反应导致的导电件电传输性能受到影响。
4.本申请提供的堆叠结构，所述第一介质层的厚度为2μm-10μm，所述第二介质层的厚度为2μm-10μm。所述第一焊料件的厚度受到第一介质层厚度的限制，所述第二焊料件的厚度受到第二介质层厚度的限制，因此，所述第一焊料件的厚度为2μm-10μm，所述第二焊料件的厚度为2μm-10μm。通过将第一介质层和第二介质层的厚度进行上述限定，控制了相邻封装模块的间距，从而提高了集成密度；同时也减小了由导电件、第一焊料件和第二焊料件构成的垂直互联结构的整体长度，从而减小了垂直互联结构的整体电阻值，继而减小了垂直互联结构产生的热量，最终减小了堆叠结构产生的总热量。
5.本申请提供的堆叠方法，通过所述第j封装模块的第一介质层与所述第j+1封装模块的第二介质层相互键合，使所述第j封装模块与所述第j+1 封装模块具有较大的连接强度；并还通过所述第j封装模块的第一焊料件与所述第j+1半导体模块的第二焊料件焊接在一起，这显著提高了第j封装模块和第j+1封装模块的连接强度，使相邻封装模块不易发生分离，进而提高了堆叠结构的结构稳定性，保证了堆叠结构的正常工作。此外，第一介质层和第二介质层的导热性能优于有机填料，能够增加堆叠结构的散热速度，从而能够有效避免堆叠结构内温度过高对堆叠结构的性能造成不良影响，有利于堆叠结构的正常工作。
6.本申请提供的堆叠方法，利用了焊料在熔化后呈半球形的特点。具体的，在焊接过程中第一焊料层和第二焊料层熔化呈半球形液态，这使第一焊料层和第二焊料层的高度增大，从而使液态的第一焊料层和第二焊料层相接触，并在冷却后连接为一体，其中，变形后的第一焊料层构成第一焊料件，变形后的第二焊料层构成第二焊料件，因此第一焊料层无需填充满所述第一开口并且第二焊料层无需填充满所述第二开口，这减少了焊料的用量；通过在第一开口内形成第一焊料层以及在第二开口内形成第二焊料层，限定了第一焊料层和第二焊料层的形成区域，一方面便于实现对第一焊料层和第二焊料层的形成体积的控制，另一方面仅需保证第一开口和第二开口相对设置即可保证熔化后的第一焊料层和第二焊料层相对设置，从而保证熔化呈半球形液态的第一焊料层和第二焊料层在冷却后连接在一起，即，第一介质层和第二介质层的设置不仅能够连接相邻封装模块，还有利于第一焊料件和第二焊料件顺利连接。
7.本申请提供的堆叠方法，所述第一焊料层的厚度大于等于所述第一开口的内径的三分之二且小于所述第一介质层的厚度；所述第二焊料层的厚度大于等于所述第二开口的内径的三分之二且小于所述第二介质层的厚度。通过对所述第一焊料层和第二焊料层的厚度进行上述限定，保证了熔化后的第一焊料层和第二焊料层能够接触并在冷却后连接为一体。
附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下 面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的堆叠结构的结构示意图；
图2为本申请实施例提供的堆叠方法的工艺流程图；
图3-图17为堆叠过程中的结构示意图；
附图标记说明：
11-第一半导体单元；12-第二半导体单元；13-第三半导体单元；1n-第n半导体单元；1N-第N半导体单元；21-第一导电件；22-第二导电件；23-第三导电件；2n-第n导电件；2N第N导电件；3-第一介质层；31-第一开口；32-第一焊料件；33-第一焊料层；4-第二介质层；41-第二开口；42-第二焊料件；43-第二焊料层；5-第一介质材料层；6-第二介质材料层；7-开口；8-焊料层。
具体实施方式
下面将结合附图对本申请的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相 对重要性。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
参见图1，本实施例还提供一种堆叠结构，包括依次垂直层叠且电学连接的第一封装模块至第N封装模块，N为大于等于2的整数，第n封装模块包括第n半导体单元1n，所述第n半导体单元1n具有相对设置的第一表面和第二表面，n为大于等于1小于等于N的整数；第j封装模块还包括：覆盖第j半导体单元的第一表面的第一介质层3，j为大于等于1小于等于N-1的整数；贯穿所述第一介质层3的第一焊料件32；第j+1封装模块还包括：覆盖第j+1半导体单元的第二表面的第二介质层4；贯穿所述第二介质层4的第二焊料件42；其中，所述第j封装模块的第一介质层3与所述第j+1封装模块的第二介质层4相互键合；所述第j封装模块的第一焊料件32与所述第j+1半导体模块的第二焊料件42焊接在一起。
上述堆叠结构，所述第j封装模块的第一介质层3与所述第j+1封装模块的第二介质层4相互键合，具有较大的连接强度；与此同时，所述第j封装模块的第一焊料件32还与所述第j+1半导体模块的第二焊料件42焊接在一起，这显著提高了第j封装模块和第j+1封装模块的连接强度，使相邻封装模块不易发生分离，进而提高了堆叠结构的结构稳定性，避免了相邻封装模块在环境影响或外力作用下发生分离，保证了堆叠结构的正常工作。此外，第一介质层3和第二介质层4的导热性能优于有机填料，从而能够提高堆叠结构的散热效率，进而有效避免堆叠结构内部温度过高对堆叠结构造成不良影响，有利于堆叠结构的正常工作。
具体地，所述第一介质层3的厚度为2μm-10μm，所述第二介质层4的厚度为2μm-10μm。所述第一焊料件32的厚度受到第一介质层3厚度的限制，所述第二焊料件42的厚度受到第二介质层4厚度的限制，因此，所述第一焊料件32的厚度为2μm-10μm，所述第二焊料件42的厚度为2μm-10μm。通过将第一介质层3和第二介质层4的厚度进行上述限定，控制了相邻封装模块的间距，从而提高了集成密度；同时也减小了由导电件、第一焊料件32和第二焊料件42构成的垂直互联结构的整体长度，从而减小了垂直互联结构的整体电阻值，继而减小了垂直互联结构产生的热量，最终减小了堆叠结构产生的总热量。
在本实施例中，所述第一介质层3中具有贯穿所述第一介质层3的第一开口31，所述第一焊料件32位于所述第一开口31中；所述第二介质层4中具有贯穿所述第二介质层4的第二开口41，所述第二焊料件42位于所述第二开口41中；对于焊接在一起的第一焊料件32和第二焊料件42，自所述第一焊料件32至第二焊料件42的方向上，所述第一焊料件32的横截面积逐渐减小，自所述第二焊料件42至第一焊料件32的方向上，所述第二焊料件42的横截面积逐渐减小。
具体地，所述第一开口31的内径为5μm-30μm，所述第二开口41的内径为5μm-30μm。所述第一焊料件32的尺寸受到第一开口31尺寸的限制，所述第二焊料件42的尺寸受到第二开口41尺寸的限制，通过将所述第一开口31和第二开口41的内径限定在上述范围，能够控制第一焊料件32和第二焊料件42的用量。
可选地，在一个实施例中，所述第一焊料件32与所述第一介质层3之间具有间隙，所述第二焊料件42与所述第二介质层4之间具有间隙，在保证了相邻封装模块垂直互联的同时，缩小了第一焊料件32和第二焊料件42的用量，节约了成本。具体地，所述第一焊料件32的体积与所述第一开口31的体积比值为0.8-1.2，所述第二焊料件42的体积与所述第二开口41的体积比值为0.8-1.2。
在本实施例中，所述第一焊料件32和所述第二焊料件42的材料包括 锡合金；具体地，所述第一焊料件32和所述第二焊料件42的材料可以为SnAg。所述第一介质层3和所述第二介质层4的材料包括氧化硅。所述导电件的材料包括但不限于铜。
在本实施例中，所述第n封装模块还包括贯穿所述第n半导体单元1n的第n导电件2n；第k导电件的两端分别与第k封装模块中的第一焊料件32和第二焊料件42电学连接，k为大于等于2且小于等于N-1的整数；第一导电件21的一端与第一封装模块中的第一焊料件32电学连接，第N半导体单元1N中的第N导电件2N的一端与第N封装模块中的第二焊料件42电学连接，正如图1中所示，第二导电件22贯穿第二半导体单元12，第三导电件23贯穿第三半导体单元13；所述第一封装模块还包括位于第一半导体单元11的第一表面的第一导电线路层(图中未示出)，所述第一导电线路层与所述第一导电件21电学连接；所述第j+1封装模块还包括位于所述第j+1半导体单元的第二表面的第j+1导电线路层，所述第j+1导电线路层与所述第j+1导电件电学连接。第一导电件21至第N导电件2N、第一导电线路层至第N导电线路层、第一封装模块中的第一焊料件32、第二封装模块至第N-1封装模块中的第一焊料件32和第二焊料件42、以及第N封装模块中的第二焊料件42构成堆叠结构的互连结构，实现了电气连通。具体地，所述第n导电件2n的直径为5μm-30μm。
在本实施例中，所述第n半导体单元1n内设置有第n功能结构(图中未示出)，所述第n功能结构位于第n导电线路层下方且与第n导电线路层电学连接，所述导电件位于所述第n功能结构侧部。所述互联结构用于驱动第一功能结构至第N功能结构工作。作为一个可选的实施方式，所述第一开口31内还设置有位于所述第一焊料件32底部的第一导电保护层(图中未示出)，隔离了所述第一焊料件和导电件，避免了在回流焊工艺过程中第一焊料件与导电件发生反应导致的导电件电传输性能受到影响；所述第二开口41内还设置有位于所述第二焊料件42底部的第二导电保护层(图中未示出)，隔离了所述第二焊料件和导电件，避免了在回流焊工艺过程中第二焊料件与导电件发生反应导致的导电件电传输性能受到影响。
具体地，所述第一导电保护层和所述第二导电保护层的材料包括Ti/Cu/Ni复合层，其中，Ni层与焊料件接触。所述第一导电保护层和所述第二导电保护层的厚度为1μm-2μm。
在本实施例中，所述第一半导体单元11的第二表面设置有第一凸点下金属化层，所述第一凸点下金属化层与所述第一导电件21电学连接，所述第一凸点下金属化层背离所述第一导电件21的一侧表面设置有若干焊球，用于与其他半导体结构进行电学连接；所述第N半导体单元1N的第一表面设置有第二凸点下金属化层，所述第二凸点下金属化层背离所述第N导电件2N的一侧表面设置有若干焊球用于与其他半导体结构进行电学连接。
在本实施例中，所述第n半导体单元1n包括但不限于动态随机存取存储器；当第1半导体单元至第N半导体单元1N均为动态随机存取存储器时，所述堆叠结构适于与逻辑芯片组成高带宽存储器。
本实施例还提供一种堆叠方法，包括：形成依次垂直层叠且电学连接的第一封装模块至第N封装模块，N为大于等于2的整数，第n封装模块包括第n半导体单元1n，所述第n半导体单元1n具有相对设置的第一表面和第二表面，n为大于等于1小于等于N的整数；形成第j封装模块的步骤还包括：形成覆盖第j半导体单元的第一表面的第一介质层3，j为大于等于1小于等于N-1的整数；形成贯穿所述第一介质层3的第一焊料件32；形成第j+1封装模块的步骤还包括：形成覆盖第j+1半导体单元的第二表面的第二介质层4；形成贯穿所述第二介质层4的第二焊料件42；形成依次垂直层叠且电学连接的第一封装模块至第N封装模块的步骤包括：将所述第j封装模块的第一介质层3与所述第j+1封装模块的第二介质层4相互键合之后，将所述第j封装模块的第一焊料件32与所述第j+1半导体模块的第二焊料件42焊接在一起。
上述堆叠方法通过所述第j封装模块的第一介质层3与所述第j+1封装模块的第二介质层4相互键合，使所述第j封装模块与所述第j+1封装模块具有较大的连接强度；并通过所述第j封装模块的第一焊料件32还与所述第j+1半导体模块的第二焊料件42焊接在一起，显著提高第j封装模块和 第j+1封装模块的连接强度，使相邻封装模块不易发生分离，进而提高了堆叠结构的结构稳定性，保证了堆叠结构的正常工作。此外，第一介质层3和第二介质层4的导热性能优于有机填料，能够增加堆叠结构的散热速度，从而能够有效避免堆叠结构内温度过高对堆叠结构的性能造成不良影响，有利于堆叠结构的正常工作。
在本实施例中，形成贯穿所述第一介质层3的第一焊料件32的步骤包括：在所述第一介质层3中形成贯穿所述第一介质层3的第一开口31；在所述第一开口31中形成覆盖第j半导体单元的第一焊料层33；形成贯穿所述第二介质层4的所述第二焊料件42的步骤包括：在所述第二介质层4中形成贯穿所述第二介质层4的第二开口41；在所述第二开口41中形成覆盖第j+1半导体单元的第二焊料层43；将所述第j封装模块的第一焊料层33与所述第j+1半导体模块的第二焊料层43焊接后，所述第一焊料层33变形构成第一焊料件32，所述第二焊料层43变形构成第二焊料件42。
本实施例形成第一焊料件32和第二焊料件42的步骤利用了焊料在熔化后呈半球形的特点。具体地，在焊接过程中第一焊料层33和第二焊料层43熔化呈半球形液态，这使第一焊料层33和第二焊料层43的高度增大，从而使液态的第一焊料层33和第二焊料层43相接触，并在冷却后连接为一体，其中，变形后的第一焊料层33构成第一焊料件32，变形后的第二焊料层43构成第二焊料件42，因此第一焊料层33无需填充满所述第一开口31以及第二焊料层43无需填充满所述第二开口41，这减少了焊料的用量；通过在第一开口31内形成第一焊料层33以及在第二开口41内形成第二焊料层43，限定了第一焊料层33和第二焊料层43的形成区域，一方面便于实现对第一焊料层33和第二焊料层43的形成体积的控制，一方面仅需保证第一开口31和第二开口41相对设置即可保证熔化后的第一焊料层33和第二焊料层43相对设置，从而保证熔化呈半球形液态的第一焊料层33和第二焊料层43在冷却后连接在一起，即，第一介质层3和第二介质层4的设置不仅能够连接相邻封装模块，还有利于第一焊料件32和第二焊料件42顺利连接。
可选地，所述第一焊料层33的厚度大于等于所述第一开口31的内径的三分之二且小于所述第一介质层3的厚度；所述第二焊料层43的厚度大于等于所述第二开口41的内径的三分之二且小于所述第二介质层4的厚度。通过对所述第一焊料层33和第二焊料层43的厚度进行上述限定，保证了熔化后的第一焊料层33和第二焊料层43能够接触并在冷却后连接为一体。
下面结合图2-图15对本实施例提供的堆叠方法进行清楚、完整地描述。
S1、参见图6，提供第一初始封装模块至第N初始封装模块。
具体地，形成第n初始封装模块的步骤包括：
S11、提供第n半导体单元1n，所述第n半导体单元1n的正面设置有第n导电线路层。具体地，所述第n半导体单元1n内还设置有第n功能结构，所述第n功能结构位于第n导电线路层下方且与第n导电线路层电学连接。
S12、参见图3，形成延伸至所述第n半导体单元1n的部分深度的第n导电件2n，所述第n半导体单元1n的正面暴露出所述第n导电件2n的一侧表面，所述第n导电件2n与所述第n导电线路层电学连接。具体地，所述第n导电件2n位于所述第n功能结构的侧部。第一半导体单元11的正面构成所述第一半导体单元11的第一表面，所述第一半导体单元11的背面构成所述第一半导体单元11的第二表面，所述第j+1半导体单元的背面构成所述第j+1半导体单元的第一表面，所述第j+1半导体单元的正面构成所述第j+1半导体单元的第二表面。形成所述第n导电件2n的工艺为硅通孔(TSV)工艺。
S13、参见图4，形成覆盖第n导电线路层和所述第n导电件2n的第一介质材料层5；具体地，形成所述第一介质材料层5的工艺包括化学气相淀积工艺。
S14、参见图5，形成贯穿所述第一介质材料层5的开口7，以暴露所述第n导电件2n。具体地，位于所述第一半导体单元11表面的第一介质材料层5构成第一初始封装模块的第一介质层3，位于第一介质层3中的开口 7构成第一开口31；位于所述第j+1半导体单元表面的第一介质材料层5构成第j+1初始封装模块的第二介质层4，位于第二介质层4中的开口7构成第二开口41。形成贯穿所述第一介质材料层5的开口的工艺包括光刻工艺。
S15、参见图6，形成位于所述第一介质材料层5的开口7内的焊料层8，得到第n初始封装模块。具体地，位于所述第一半导体单元11表面的焊料层8构成第一初始封装模块的第一焊料层33，位于所述第j+1半导体单元表面的焊料层8构成第j+1初始封装模块的第二焊料层43。形成位于所述第一介质材料层5的开口7内的焊料层8的工艺包括电镀工艺。
S2、参见图7，将第j+1初始封装模块放置在第j初始封装模块上之后，将第j初始封装模块的第一介质层3与第j+1初始封装模块的第二介质层4键合在一起。具体地，将所述第j封装模块的第一介质层3与所述第j+1封装模块的第二介质层4相互键合包括激活、对位和键合步骤。
S3、参见图8，将第j初始封装模块的第一焊料层33与第j+1初始封装模块的第二焊料层43焊接在一起。将所述第j封装模块的第一焊料层33与所述第j+1半导体模块的第二焊料层43焊接的工艺包括回流焊工艺，回流焊工艺的温度易于控制焊接过程中还能避免氧化。具体地，所述回流焊工艺的参数包括：回流焊的温度为220℃-280℃，回流焊的时间为30s-60s。
S4、参见图9，对第j+1初始封装模块的背面进行减薄，暴露出第j+1导电件的表面；具体地，对第j+1初始封装模块的背面进行减薄的工艺包括化学机械研磨工艺。
S5、形成位于第k初始封装模块背面的第一介质层3，所述第一介质层3具有第一开口31，k为大于等于2且小于等于N-1的整数；具体地，形成位于第k初始封装模块背面的第一介质层3的步骤包括：
S51、参见图10，形成覆盖第k初始封装模块背面的第二介质材料层6；具体地，形成所述第二介质材料层6的工艺包括化学气相淀积工艺。
S52、参见图11，形成贯穿所述第二介质材料层6的第一开口31，以暴露所述第k导电件，得到第一介质层3。具体地，形成贯穿所述第二介质 材料层6的第一开口31的工艺包括光刻工艺。
S6、参见图12，形成位于所述第二介质材料层6的第一开口31内的第一焊料层33。具体地，形成位于所述第二介质材料层6的第一开口31内的第一焊料层33的工艺包括电镀工艺。
S7、参见图13-图16，重复进行步骤S2-S6，至第N-1初始封装模块的第一焊料件32和第N初始封装模块的第二焊料件42焊接在一起；其中，所述第N半导体单元1N、第N导电件2N、第N半导体单元1N的第二表面的第二介质层4和第二焊料件42构成第N封装模块；所述第k半导体单元、第k导电件、以及位于第k半导体单元两侧的第一介质层3、第二介质层4、第一焊料件32和第二焊料件42构成第k封装模块。
S8、参见图17，对所述第一初始封装模块的第二表面进行减薄，以暴露第一导电件21；所述第一半导体单元11、第一导电件21、第一半导体单元11的第一表面的第一介质层3和第一焊料件32构成第一封装模块。具体地，对所述第一初始封装模块的第二表面进行减薄的工艺包括化学机械研磨工艺。
S9、在所述第一半导体单元11的第二表面形成第一凸点下金属化层(图中未示出)，随后在所述第一凸点下金属化层背离所述第一导电件21的一侧表面设置若干焊球；在所述第N半导体单元1N的第一表面形成第二凸点下金属化层，随后在所述第二凸点下金属化层背离所述第N导电件2N的一侧表面设置若干焊球。
下面对步骤S2-S8进行简要说明：
当堆叠结构中封装模块的数量为2时，首先，如图7所示，将第二初始封装模块放置在第一初始封装模块上；随后将第一初始封装模块的第一介质层3与第二初始封装模块的第二介质层4键合在一起；随后，如图8所示，对第一初始封装模块的第一焊料层33与第二初始封装模块的第二焊料层43进行回流焊处理，第一焊料层33和第二焊料层43变形得到第一焊料件32和第二焊料件42，且第一焊料件32和第二焊料件42焊接在一起；随后，如图9所示，对第二初始封装模块背离所述第一初始封装模块的一 侧表面即第二初始封装模块的第一表面进行减薄，暴露出第二导电件的一侧表面；随后，对所述第一初始封装模块的第二表面进行减薄以暴露第一导电件21的一侧表面，从而得到电学连接的第一封装模块和第二封装模块。
当堆叠结构中封装模块的数量为3时，则在对第二初始封装模块的第一表面进行减薄后，不对所述第一初始封装模块的第二表面进行减薄，而是进行以下步骤：在所述第二初始封装模块的第一表面依次形成第二初始封装模块的第一介质层3和第一焊料层33；随后将第三初始封装模块放置在第二初始封装模块上，依次进行第二初始封装模块的第一介质层3与第三初始封装模块的第二介质层4的键合、第一初始封装模块的第一焊料件32与第二初始封装模块的第二焊料件42的焊接、第三初始封装模块的第一表面的减薄、所述第一初始封装模块的第二表面的减薄，即可得到电学连接的第一封装模块、第二封装模块和第三封装模块。当堆叠结构中封装模块的数量大于3时，重复上述步骤至减薄第N初始封装模块的第一表面以暴露出第N导电件2N的一侧表面，并在第N初始封装模块的第一表面减薄后，对所述第一初始封装模块的第二表面进行减薄。
在本实施例中，所述堆叠方法还包括：在所述第一开口31中形成所述第一焊料层33之前，在所述第一开口31中形成覆盖第j半导体单元的第一导电保护层；在形成所述第一焊料层33之后，所述第一导电保护层位于所述第一焊料层33的底部；在所述第二开口41中形成所述第二焊料层43之前，在所述第二开口41中形成覆盖第j+1半导体单元的第二导电保护层；在形成所述第二焊料层43之后，所述第二导电保护层位于所述第二焊料层43的底部。具体地，形成第一导电保护层和第二导电保护层的工艺包括电镀工艺。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本申请的保护范围之中。

Claims (17)

  1. 一种堆叠结构，其特征在于，包括依次垂直层叠且电学连接的第一封装模块至第N封装模块，N为大于等于2的整数，第n封装模块包括第n半导体单元，所述第n半导体单元具有相对设置的第一表面和第二表面，n为大于等于1小于等于N的整数；
    第j封装模块还包括：覆盖第j半导体单元的第一表面的第一介质层，j为大于等于1小于等于N-1的整数；贯穿所述第一介质层的第一焊料件；
    第j+1封装模块还包括：覆盖第j+1半导体单元的第二表面的第二介质层；贯穿所述第二介质层的第二焊料件；
    其中，所述第j封装模块的第一介质层与所述第j+1封装模块的第二介质层相互键合；
    所述第j封装模块的第一焊料件与所述第j+1半导体模块的第二焊料件焊接在一起。
  2. 根据权利要求1所述的堆叠结构，其特征在于，所述第一介质层中具有贯穿所述第一介质层的第一开口，所述第一焊料件位于所述第一开口中；所述第二介质层中具有贯穿所述第二介质层的第二开口，所述第二焊料件位于所述第二开口中；对于焊接在一起的第一焊料件和第二焊料件，自所述第一焊料件至第二焊料件的方向上，所述第一焊料件的横截面积逐渐减小，自所述第二焊料件至第一焊料件的方向上，所述第二焊料件的横截面积逐渐减小。
  3. 根据权利要求2所述的堆叠结构，其特征在于，所述第一焊料件与所述第一介质层之间具有间隙，所述第二焊料件与所述第二介质层之间具有间隙。
  4. 根据权利要求2或3所述的堆叠结构，其特征在于，所述第n封装模块还包括:贯穿所述第n半导体单元的第n导电件；第k导电件的两端分 别与第k封装模块中的第一焊料件和第二焊料件电学连接，k为大于等于2且小于等于N-1的整数；第一导电件的一端与第一封装模块中的第一焊料件电学连接，第N半导体单元中的第N导电件的一端与第N封装模块中的第二焊料件电学连接；
    所述第一封装模块还包括位于第一半导体单元的第一表面的第一导电线路层，所述第一导电线路层与所述第一导电件电学连接；所述第j+1封装模块还包括位于所述第j+1半导体单元的第二表面的第j+1导电线路层，所述第j+1导电线路层与所述第j+1导电件电学连接接。
  5. 根据权利要求4所述的堆叠结构，其特征在于，所述第一开口内还设置有位于所述第一焊料件底部的第一导电保护层；所述第二开口内还设置有位于所述第二焊料件底部的第二导电保护层。
  6. 根据权利要求1-3任一项所述的堆叠结构，其特征在于，所述第一介质层的厚度为2μm-10μm，所述第二介质层的厚度为2μm-10μm。
  7. 根据权利要求2所述的堆叠结构，其特征在于，所述第一开口的内径为5μm-30μm，所述第二开口的内径为5μm-30μm。
  8. 根据权利要求2或3所述的堆叠结构，其特征在于，所述第一焊料件的体积与所述第一开口的体积比值为0.8-1.2，所述第二焊料件的体积与所述第二开口的体积比值为0.8-1.2。
  9. 根据权利要求1所述的堆叠结构，其特征在于，所述第一焊料件和所述第二焊料件的材料包括锡合金；所述第一介质层和所述第二介质层的材料包括氧化硅。
  10. 根据权利要求9所述的堆叠结构，其特征在于，所述第一焊料件 和所述第二焊料件的材料为SnAg。
  11. 根据权利要求1所述的堆叠结构，其特征在于，所述第n半导体单元包括动态随机存取存储器。
  12. 一种堆叠方法，其特征在于，包括：
    形成依次垂直层叠且电学连接的第一封装模块至第N封装模块，N为大于等于2的整数，第n封装模块包括第n半导体单元，所述第n半导体单元具有相对设置的第一表面和第二表面，n为大于等于1小于等于N的整数；
    形成第j封装模块的步骤还包括：形成覆盖第j半导体单元的第一表面的第一介质层，j为大于等于1小于等于N-1的整数；形成贯穿所述第一介质层的第一焊料件；
    形成第j+1封装模块的步骤还包括：形成覆盖第j+1半导体单元的第二表面的第二介质层；形成贯穿所述第二介质层的第二焊料件；
    形成依次垂直层叠且电学连接的第一封装模块至第N封装模块的步骤包括：将所述第j封装模块的第一介质层与所述第j+1封装模块的第二介质层相互键合之后，将所述第j封装模块的第一焊料件与所述第j+1半导体模块的第二焊料件焊接在一起。
  13. 根据权利要求12所述的堆叠方法，其特征在于，形成贯穿所述第一介质层的第一焊料件的步骤包括：在所述第一介质层中形成贯穿所述第一介质层的第一开口；在所述第一开口中形成覆盖第j半导体单元的第一焊料层；
    形成贯穿所述第二介质层的所述第二焊料件的步骤包括：在所述第二介质层中形成贯穿所述第二介质层的第二开口；在所述第二开口中形成覆盖第j+1半导体单元的第二焊料层；
    将所述第j封装模块的第一焊料层与所述第j+1半导体模块的第二焊料 层焊接后，所述第一焊料层变形构成第一焊料件，所述第二焊料层变形构成第二焊料件。
  14. 根据权利要求13所述的堆叠方法，其特征在于，所述第一焊料层的厚度大于等于所述第一开口的内径的三分之二且小于所述第一介质层的厚度；所述第二焊料层的厚度大于等于所述第二开口的内径的三分之二且小于所述第二介质层的厚度。
  15. 根据权利要求13所述的堆叠方法，其特征在于，将所述第j封装模块的第一焊料层与所述第j+1半导体模块的第二焊料层焊接的工艺包括回流焊工艺。
  16. 根据权利要求15所述的堆叠方法，其特征在于，所述回流焊工艺的参数包括：回流焊的温度为220℃-280℃，回流焊的时间为30s-60s。
  17. 根据权利要求13所述的堆叠方法，其特征在于，还包括：
    在所述第一开口中形成所述第一焊料层之前，在所述第一开口中形成覆盖第j半导体单元的第一导电保护层；在形成所述第一焊料层之后，所述第一导电保护层位于所述第一焊料层的底部；
    在所述第二开口中形成所述第二焊料层之前，在所述第二开口中形成覆盖第j+1半导体单元的第二导电保护层；在形成所述第二焊料层之后，所述第二导电保护层位于所述第二焊料层的底部。
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