WO2023273582A1 - 芯片封装结构的形成方法 - Google Patents

芯片封装结构的形成方法 Download PDF

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Publication number
WO2023273582A1
WO2023273582A1 PCT/CN2022/089778 CN2022089778W WO2023273582A1 WO 2023273582 A1 WO2023273582 A1 WO 2023273582A1 CN 2022089778 W CN2022089778 W CN 2022089778W WO 2023273582 A1 WO2023273582 A1 WO 2023273582A1
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WO
WIPO (PCT)
Prior art keywords
layer
die
forming
carrier
stretchable
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PCT/CN2022/089778
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English (en)
French (fr)
Inventor
谭富耀
谢雷
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矽磐微电子(重庆)有限公司
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Publication of WO2023273582A1 publication Critical patent/WO2023273582A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a method for forming a chip packaging structure.
  • suction heads are required to transfer each die to a carrier board, and then package.
  • the suction head transfers the die, it needs to be grasped one by one, and it needs to be aligned one by one with reference to the alignment marks on the carrier board.
  • the placement cost is high and the efficiency is low.
  • the object of the present invention is to provide a method for forming a chip packaging structure, which reduces mounting costs and improves mounting efficiency.
  • the present invention provides a method for forming a chip packaging structure, comprising:
  • the beneficial effects of the present invention lie in: 1) Using the stretchable layer, multiple bare chips after wafer cutting can be transferred at one time, and the mounting efficiency is high. 2) No chip mounting equipment is required, and the mounting cost is low. 3) Multiple bare chips transferred to the carrier board retain the original layout of the wafer, and simple yield testing techniques can be used to trace defects. 4) By selecting stretchable layer carrier films with different stretch coefficients, different stretch sizes can be controlled to meet the different size requirements of the packaging structure.
  • Fig. 1 is the flow chart of the manufacturing method of the forming method of the chip packaging structure of the first embodiment of the present invention
  • Figures 2 to 10 are schematic diagrams of intermediate structures corresponding to the process in Figure 1;
  • 11 to 13 are schematic diagrams of intermediate structures corresponding to the manufacturing method of the chip packaging structure according to the second embodiment of the present invention.
  • FIG. 14 is a schematic diagram of an intermediate structure corresponding to the chip packaging structure of the third embodiment of the present invention.
  • 15 is a schematic diagram of an intermediate structure corresponding to the chip packaging structure of the fourth embodiment of the present invention.
  • FIG. 16 is a flowchart of a manufacturing method of a method for forming a chip packaging structure according to a fifth embodiment of the present invention.
  • 17 to 25 are schematic diagrams of intermediate structures corresponding to the process in FIG. 16 .
  • the first support plate 30 The first redistribution layer 14
  • the first dielectric layer 16 Chip package structure 1a The first dielectric layer 16 Chip package structure 1a
  • the first end 22a of the conductive plug The second end 22b of the conductive plug
  • FIG. 1 is a flow chart of a manufacturing method of a method for forming a chip package structure according to a first embodiment of the present invention
  • FIGS. 2 to 10 are schematic diagrams of intermediate structures corresponding to the process in FIG. 1 .
  • FIG. 2 is a top view of the wafer and the stretchable layer
  • FIG. 3 is a cross-sectional view along line AA in FIG. 2 .
  • the wafer 10 includes an active surface 10a and a back surface 10b opposite to each other, and the active surface 10a may expose several pads (not shown).
  • An adhesive layer may be provided between the back surface 10b of the wafer 10 and the stretchable layer 11, so as to realize the fixation between the two.
  • the adhesive layer can use an easily peelable material so that the stretchable layer 11 can be peeled off, for example, a thermal separation material that can lose its viscosity by heating or a UV separation material that can lose its viscosity by ultraviolet irradiation can be used.
  • the stretch coefficient of the stretchable layer 11 perpendicular to the thickness direction is linear. In other embodiments, the stretch coefficient of the stretchable layer 11 perpendicular to the thickness direction may be non-linear, and the change curve of stretch length with stretch force is fixed.
  • the material of the stretchable layer 11 can be an elastic polymer film material, or an elastic copolymer film material, such as at least one of polyethylene, polyvinyl chloride, polypropylene, polyamide and polyamide, and can also be modified After polyethylene, polyvinyl chloride, polypropylene, polyamide or polyamide to enhance tensile properties.
  • the dicing can be controlled by the cutting depth to stay above the stretchable layer 11 .
  • the die 12 may be a power die (POWER DIE), a storage die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE), etc.
  • POWER DIE power die
  • MEMORY DIE storage die
  • SENSOR DIE sensor die
  • RADIO FREQUENCE DIE radio frequency die
  • the die 12 includes an active surface 12 a and a back surface 12 b opposite to each other.
  • the pad 121 is exposed to the active surface 12a.
  • Die 12 may include various devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device.
  • the pads 121 are connected with the electrical interconnection structure, and are used for inputting/outputting electrical signals of various devices.
  • the active surface 12 a of the die 12 is provided with a protection layer 120 .
  • the active surface of the die 12 may also omit the protection layer 120 .
  • the protective layer 120 is an insulating material, specifically an organic polymer insulating material, or an inorganic insulating material or a composite material.
  • the organic polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, or other organic materials with similar insulating properties.
  • the inorganic insulating material is, for example, at least one of silicon dioxide and silicon nitride.
  • the composite material is an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as SiO 2 /resin polymer composite material.
  • an opening 120 a exposing the pad 121 is opened in the protection layer 120 .
  • the distance between the stretchable layer 11 and the adjacent die 12 is a predetermined distance L.
  • Stretching the stretchable layer 11 can cause the dies 12 to spread apart from each other. According to the variation curve of the stretching length with the stretching force, by controlling the stretching force, the distance between adjacent dies 12 can be controlled.
  • the distance between adjacent dies 12 includes the distance in the up-down direction and the distance in the left-right direction.
  • the distance in the up-down direction and the distance in the left-right direction may be the same or different.
  • step S3 in FIG. 1 and shown in FIG. 6 the active surface 12a of the die 12 faces the carrier 20, and the stretched stretchable layer 11 and the carried dies 12 are integrally transferred to the carrier. 20.
  • FIG. 7 remove the stretchable layer 11 after stretching.
  • the stretchable layer 11 can be used to transfer multiple bare chips 12 after the wafer 10 has been cut, and the mounting efficiency is high. In addition, chip mounting equipment is not required, and the mounting cost is low.
  • the removal method of the stretchable layer 11 may be existing removal methods such as laser peeling and UV irradiation.
  • the carrier board 20 is a rigid board, which may include a plastic board, a glass board, a ceramic board or a metal board.
  • An adhesive layer may be provided between the active surface 12 a of the bare chip 12 and the carrier 20 , so as to realize the fixing between the two.
  • the adhesive layer can be made of an easily peelable material so that the carrier 20 can be peeled off, for example, a thermal separation material that can lose its viscosity by heating or a UV separation material that can lose its viscosity by ultraviolet irradiation can be used.
  • a plastic encapsulation layer 13 is formed on the carrier 20 to cover each die 12 .
  • the plastic encapsulation layer 13 includes opposite front surfaces 13 a and back surfaces 13 b. 13a is in the same orientation as the active surface 12a of the bare chip 12, and the back surface 13b of the plastic encapsulation layer 13 is oriented in the same direction as the back surface 12b of the bare chip 12; as shown in FIG.
  • the front side 13 a of the layer 13 an electrical connection structure is formed on the active side 12 a of each die 12 and the front side 13 a of the plastic encapsulation layer 13 .
  • the material of the plastic sealing layer 13 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate Glycol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol, etc.
  • the material of the plastic sealing layer 13 can also be various polymers or a composite material of resin and polymer.
  • the encapsulation can be carried out by filling liquid molding compound between each die 12 and then curing at high temperature through a plastic molding mold.
  • the plastic sealing layer 13 can also be molded by plastic materials such as thermocompression molding and transfer molding.
  • the plastic encapsulation layer 13 includes a front side 13a and a back side 13b opposite to each other.
  • the front surface 13 a of the plastic encapsulation layer 13 exposes the protection layer 120 and the pad 121 .
  • the removal method of the carrier plate 20 may be existing removal methods such as laser lift-off and UV irradiation.
  • a first supporting board 30 can be disposed on the back surface 13 b of the plastic encapsulation layer 13 .
  • the first support plate 30 is a rigid plate, which may include a plastic plate, a glass plate, a ceramic plate, or a metal plate.
  • forming an electrical connection structure on the active surface 12 a of each die 12 and the front surface 13 a of the plastic encapsulation layer 13 includes the following steps S41 - S43 .
  • Step S41 forming the first redistribution layer 14 on the pad 121 and the front surface 13 a of the plastic encapsulation layer 13 .
  • step S41 includes the following steps S411-S414.
  • Step S411 forming a photoresist layer on the protection layer 120 of each die 12 , the pad 121 exposed by the protection layer 120 , and the front surface 13 a of the plastic encapsulation layer 13 .
  • the formed photoresist layer may be a photosensitive film.
  • the photosensitive film can be torn off from the adhesive tape, and pasted on the protection layer 120 of each die 12 , the exposed pad 121 of the protection layer 120 and the front surface 13 a of the plastic encapsulation layer 13 .
  • the photoresist layer can also be formed by first coating a liquid photoresist and then heating and curing.
  • Step S412 exposing and developing the photoresist layer, and retaining the photoresist layer in a first predetermined area, which is complementary to the area where the metal pattern block 14a of the first redistribution layer 14 to be formed is located.
  • Step S413 filling the metal layer in the complementary area of the first predetermined area to form the metal pattern block 14 a of the first redistribution layer 14 .
  • This step S413 can be completed by an electroplating process.
  • the process of electroplating copper or aluminum is relatively mature.
  • the protective layer 120 of each die 12, the pad 121 exposed by the protective layer 120, and the front surface 13a of the plastic encapsulation layer 13 may be formed by physical vapor deposition or chemical vapor deposition.
  • a layer of seed layer (Seed Layer) is formed on it.
  • the seed layer can be used as a power supply layer for electroplating copper or aluminum.
  • Electroplating may include electrolytic plating or electroless plating.
  • Electrolytic plating is to use the part to be electroplated as a cathode to electrolyze the electrolyte to form a layer of metal on the part to be electroplated.
  • Electroless electroplating is a method of reducing and precipitating metal ions in the solution to form a metal layer on the part to be electroplated.
  • the metal pattern block 14a may also be formed by sputtering first and then etching.
  • Step S414 ashing to remove the remaining photoresist layer in the first predetermined region.
  • the seed layer in the first predetermined region is removed by dry etching or wet etching.
  • the upper surface of the metal pattern block 14a of the first redistribution layer 14 can be flattened by a polishing process, such as a chemical mechanical polishing method.
  • the metal pattern blocks 14a of the first redistribution layer 14 in this step S41 are arranged according to design requirements, and the distribution of the first redistribution layer 14 on different dies 12 may be the same or different.
  • Step S42 forming conductive bumps 15 on the first redistribution layer 14 , the conductive bumps 15 are external electrical connection structures.
  • step S42 includes the following steps S421-S424.
  • Step S421 forming a photoresist layer on the metal pattern block 14 a , the protection layer 120 exposed by the metal pattern block 14 a and the front surface 13 a of the plastic encapsulation layer 13 .
  • the formed photoresist layer may be a photosensitive film.
  • the photosensitive film can be torn off from the adhesive tape, and pasted on the metal pattern block 14a, the exposed protective layer 120 of the metal pattern block 14a, and the front surface 13a of the plastic sealing layer 13 .
  • the photoresist layer can also be formed by first coating a liquid photoresist and then heating and curing.
  • Step S422 exposing and developing the photoresist layer, and retaining the photoresist in the second predetermined area.
  • the second predetermined area is complementary to the area where the conductive bump 15 is to be formed.
  • the photoresist layer is patterned.
  • other easily removable sacrificial materials may also be used instead of the photoresist layer.
  • Step S423 filling the metal layer in the complementary area of the second predetermined area to form the conductive bump 15 .
  • This step S423 can be completed by an electroplating process.
  • the process of electroplating copper or aluminum is relatively mature.
  • a seed layer (Seed Layer) can also be deposited by physical vapor deposition or chemical vapor deposition as a power supply layer.
  • Step S424 ashing to remove the remaining photoresist layer in the second predetermined area.
  • the upper surface of the conductive bump 15 can be flattened by a polishing process, such as a chemical mechanical polishing method.
  • Step S43 forming a first dielectric layer 16 embedding the first redistribution layer 14 and the conductive bump 15 , so that the conductive bump 15 is exposed outside the first dielectric layer 16 .
  • first dielectric layer 16 on the conductive bump 15, the metal pattern block 14a, the exposed protective layer 120 of the metal pattern block 14a and the front surface 13a of the plastic encapsulation layer 13; thin the first dielectric layer 16 until The conductive bump 15 is exposed.
  • the first dielectric layer 16 is an insulating material, specifically an organic polymer insulating material, or an inorganic insulating material or a composite material.
  • the organic polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, or other organic materials with similar insulating properties.
  • the composite material is an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as SiO 2 /resin polymer composite material.
  • the organic polymer insulating material can be laminated on the first redistribution layer 14, the conductive bump 15, the protective layer 120 not covering the first redistribution layer 14, and the front surface 13a of the plastic sealing layer 13 by a) lamination process, or b) coating on the first redistribution layer 14, the conductive bump 15, the protective layer 120 not covering the first redistribution layer 14, and the front surface 13a of the plastic encapsulation layer 13, followed by curing, or c) curing by injection molding process On the first redistribution layer 14 , the conductive bump 15 , the protective layer 120 not covering the first redistribution layer 14 , and the front surface 13 a of the plastic encapsulation layer 13 .
  • the material of the first dielectric layer 16 is an inorganic insulating material such as silicon dioxide or silicon nitride, it can be formed on the first redistribution layer 14, the conductive bump 15, and the protection layer not covering the first redistribution layer 14 through a deposition process. layer 120 and the front surface 13 a of the plastic encapsulation layer 13 .
  • organic polymer insulating materials and composite materials Compared with inorganic insulating materials, organic polymer insulating materials and composite materials have lower tensile stress, which can prevent the plastic package from warping when the first dielectric layer 16 is formed in a large area.
  • the first dielectric layer 16 may include one or more layers.
  • the first dielectric layer 16 covers the conductive bump 15 , the first dielectric layer 16 is polished until the conductive bump 15 is exposed.
  • the first support plate 30 is removed.
  • steps S42 and S43 can be replaced by: firstly forming the first dielectric layer 16 on the entire surface of the first redistribution layer 14, and then forming the conductive bump 15 in the first dielectric layer 16, the conductive bump 15 is connected to the first redistribution layer 14 .
  • a window exposing the first redistribution layer 14 is formed in the second dielectric layer 16 , and a metal layer is filled in the window to form the conductive bump 15 .
  • the conductive bumps 15 and the first dielectric layer 16 are formed on the first redistribution layer 14 , and the conductive bumps 15 are exposed outside the first dielectric layer 16 .
  • each chip package structure 1 a includes a die 12 .
  • the horizontal distance between the plastic sealing layer 13 and the die 12 (the thickness of the sidewall of the plastic sealing layer 13) is equal to the distance between the stretchable layer 11 and the adjacent die 12 in step S2.
  • the first redistribution layer 14 in step S4 can be electrically connected to two or more adjacent bare chips 12, thus, after cutting in step S5, each chip package structure 1a includes two or more More than two numbers of dice 12 .
  • the wafer 10 may be tested to generate a yield map; the yield map is used for tracking the yield of the chip package structure 1a. For example, it can be determined whether the unqualified product of the chip package structure 1a is due to the quality problem of the bare chip 12 or the rewiring alignment problem in step S4.
  • step S1 before the stretchable layer 11 is adhered to the back surface 10b of the wafer 10, the intermediate carrier layer 21 is first adhered to the back surface 10b of the wafer, and the hardness of the intermediate carrier layer 21 is greater than that of the stretchable layer 11;
  • step S2 as shown in FIG. 12 , while cutting the wafer 10 , the intermediate carrier layer 21 is cut; referring to FIG. 13 , when the stretchable layer 11 is stretched, the intermediate carrier layer 21 does not spread out with the stretchable layer 11 .
  • step S3 while transferring the die 12 as a whole, the intermediate carrier layer 21 is transferred; in step S3 , the formed plastic encapsulation layer 13 wraps the intermediate carrier layer 21 . In other words, the intermediate carrier layer 21 remains in the chip packaging structure 1a.
  • the intermediate carrier layer 21 can prevent the stretchable layer 11 from being deformed when the wafer 10 is cut.
  • the material of the intermediate bearing layer 21 may be polyvinyl chloride.
  • FIG. 14 is a schematic diagram of an intermediate structure corresponding to the chip packaging structure of the third embodiment of the present invention.
  • the manufacturing method of the chip packaging structure in this embodiment is substantially the same as the manufacturing method of the chip packaging structure of the previous embodiment, the only difference is that the bare chip 12 includes a back electrode 122, and the back electrode 122 is exposed on the bare chip. 12 on the back side 12b.
  • the bare chip 12 may be an IGBT integrated with other functions, and two of the pads 121 may be source and gate respectively.
  • the back electrode 122 may be a drain electrode.
  • step S4 of forming the electrical connection structure and before the step S5 of cutting and forming a plurality of chip packaging structures 1a, the following steps S431 to S433 are also included.
  • Step S431 Thinning the plastic encapsulation layer 13 until the back electrode 122 of each die 12 is exposed.
  • a second support plate 31 may be disposed on the first dielectric layer 16 .
  • Step S432 Form a plurality of conductive plugs 22 in the plastic sealing layer 13 through the back surface 13b of the plastic sealing layer 13, the conductive plugs 22 are located on the side of the die 12; the first end 22a of the conductive plugs 22 is connected to the first redistribution layer 14 , the second end 22b of the conductive plug 22 is exposed on the back surface 13b of the plastic encapsulation layer 13 .
  • Step S433 forming a second redistribution layer 23 on each back electrode 122, the second end 22b of the conductive plug 22, and the back surface 13b of the plastic encapsulation layer 13, for electrically connecting the back electrode 122 of the die 12 through the conductive plug 22. lead to the active surface 12 a of the die 12 ; and form the second dielectric layer 24 embedding the second redistribution layer 23 .
  • the second redistribution layer 23 includes a layer of metal pattern blocks 23a. In other embodiments, the second redistribution layer 23 may include two or more metal pattern layers.
  • the formation method of the second redistribution layer 23 and the second dielectric layer 24 can refer to the formation method of the first redistribution layer 14 and the first dielectric layer 16 .
  • the conductive bump 15 can also be formed on the second redistribution layer 23 , and the conductive bump 15 is exposed outside the second dielectric layer 24 .
  • the conductive pillar 25 electrically leads the pad 121 of the die 12 to the backside 12 b of the die 12 , and the external electrical connection structure is close to the backside 12 b of the die 12 .
  • the solution of using the stretchable layer 11 to complete the transfer of multiple dies 12 cut from the wafer 10 at one time can be used not only for single-sided wiring in the chip packaging structure 1a, but also for double-sided wiring.
  • FIG. 15 is a schematic diagram of an intermediate structure corresponding to the chip packaging structure of the fourth embodiment of the present invention.
  • the manufacturing method of the chip packaging structure in this embodiment is substantially the same as that of the third embodiment, the only difference being that the conductive plug 22 is replaced by the conductive pillar 25 .
  • a plurality of conductive pillars 25 are arranged on the carrier 20, and the conductive pillars 25 are located on the side of the die 12; the first ends 25a of the conductive pillars 25 face the carrier 20.
  • the material of the conductive pillar 25 can be a metal with excellent conductivity such as copper.
  • the number and position of the conductive posts 25 can be determined according to a preset circuit layout.
  • the height of the conductive pillar 25 may be greater than the thickness of the die 12 , at least the height of the conductive pillar 25 is equal to the thickness of the die 12 .
  • the first redistribution layer 14 formed in step S4 is also located at the first end 25 a of the conductive pillar 25 .
  • step S4 of forming the electrical connection structure and before the step S5 of cutting and forming a plurality of chip packaging structures 1a, the following steps S431' to S432' are also included.
  • Step S431' Thinning the plastic encapsulation layer 13 until the back electrode 122 of each die 12 and the second end 25b of the conductive pillar 25 are exposed;
  • Step S432' forming a second redistribution layer 23 on each back electrode 122, the second end 25b of the conductive pillar 25 and the back surface 13b of the plastic encapsulation layer 13, for electrically connecting the back electrode 122 of the die 12 through the conductive pillar 25 to the active side 12 a of the die 12 ; forming a second dielectric layer 24 embedding the second redistribution layer 23 .
  • FIG. 16 is a flow chart of a manufacturing method of a method for forming a chip packaging structure according to a fifth embodiment of the present invention
  • FIGS. 17 to 25 are schematic diagrams of intermediate structures corresponding to the process in FIG. 16 .
  • step S1' in FIG. 16 the wafer 10 is cut to form each die 12; the active surface 12a of each die 12 faces the stretchable layer 11, keeping the wafer 10 The arrangement of each die 12 is transferred to the stretchable layer 11 as a whole.
  • the step S1 ′ of this embodiment is substantially the same as the step S1 of the first embodiment, the difference is only that: the wafer 10 is first cut to form the die 12 , and then transferred to the stretchable layer 11 .
  • the distance between the stretchable layer 11 and the adjacent die 12 is a predetermined distance L.
  • Step S2 of this embodiment may refer to step S2 of Embodiment 1.
  • step S3' in FIG. 16 and shown in FIG. 20 the back side 12b of each die 12 faces the carrier 20, and the stretched stretchable layer 11 and the carried die 12 are transferred to the carrier as a whole. Plate 20; as shown in FIG. 21, the stretchable layer 11 after stretching is removed.
  • the step S3' of this embodiment is substantially the same as the step S3 of the first embodiment, the only difference is that since the active surface 12a of the die 12 is attached to the stretchable layer 11, when each die 12 is transferred as a whole, the die The back side 12b of 12 faces the carrier 20 .
  • a plastic encapsulation layer 13 is formed on the carrier 20 to cover each die 12.
  • the plastic encapsulation layer 13 includes opposite front surfaces 13a and back surfaces 13b.
  • the front side 13a faces the same direction as the back side 12b of the bare chip 12, and the back side 13b of the plastic sealing layer 13 faces the same direction as the active surface 12a of the bare chip 12; as shown in FIG.
  • the active surface 12 a of each die 12 referring to FIG. 24 , an electrical connection structure is formed on the active surface 12 a of each die 12 and the back surface 13 b of the plastic encapsulation layer 13 .
  • the step S4' of this embodiment is substantially the same as the step S4 of the first embodiment, the difference is only that: since the back surface 12b of the die 12 faces the carrier 20, when the electrical connection structure is formed on the active surface 12a of each die 12, The plastic encapsulation layer 13 needs to be thinned until the active surface 12 a of each die 12 is exposed.
  • each chip package structure 1 a includes a die 12 .
  • Step S5' of this embodiment is substantially the same as step S5 of Embodiment 1.
  • the carrier 20 can be removed in step S5', or can be removed after thinning the plastic encapsulant layer 13 in step S4'.
  • the first supporting board 30 can be formed on the backside 12 b of each die 12 and the front side 13 a of the molding layer 13 .
  • step S431 can be omitted in this embodiment.
  • step S3 and before step S4 forms the plastic sealing layer 13 a plurality of conductive wires are arranged on the carrier board 20
  • the pillar 25 , the conductive pillar 25 is located at the side of the die 12 ; the second end 25 b of the conductive pillar 25 faces the carrier 20 .
  • the first redistribution layer 14 formed in step S4 is also located at the second end 25 b of the conductive pillar 25 .
  • step S431' is omitted.
  • step S432' form the second redistribution layer 23 on each back electrode 122, the first end 25a of the conductive pillar 25, and the back surface 13b of the plastic encapsulation layer 13, so as to connect the back of the die 12 through the conductive pillar 25.
  • the electrodes 122 are electrically connected to the active surface 12 a of the die 12 ; forming the second dielectric layer 24 embedding the second redistribution layer 23 .

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Abstract

本发明提供了一种芯片封装结构的形成方法，包括：提供承载于可拉伸层的多个裸片，各个裸片在可拉伸层上的排布保持晶圆切割后的排布；拉伸可拉伸层至相邻裸片之间的距离为预设距离；将拉伸后的可拉伸层以及所承载的各个裸片整体转移至载板；去除拉伸后的可拉伸层；在载板上形成塑封层，以包覆各个裸片；去除载板，在各个裸片的活性面与塑封层上形成电连接结构；切割形成多个芯片封装结构，每个芯片封装结构至少包括一个裸片。根据本发明的实施例，1)利用可拉伸层可将晶圆切割后的多个裸片一次完成转移，贴装效率高；不需要芯片装贴设备，贴装成本低。2)转移至载板的裸片保留了晶圆原本的布局，可使用简单的良率测试技术进行不良追溯。

Description

芯片封装结构的形成方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种芯片封装结构的形成方法。
背景技术
近年来，在封装过程中，为了提高封装效率，行业内发展了面板级封装技术。
面板级封装技术中，需采用吸头将各个裸片转移至载板上，后进行封装。
吸头转移裸片时，需逐一抓取，且需参照载板上的对位标记逐一对位，贴装成本高且效率低。
发明内容
本发明的发明目的是提供一种芯片封装结构的形成方法，降低贴装成本、提高贴装效率。
为实现上述目的，本发明提供一芯片封装结构的形成方法，包括：
提供承载于可拉伸层的多个裸片，各个所述裸片在所述可拉伸层上的排布保持晶圆切割后的排布；
拉伸所述可拉伸层以使相邻所述裸片之间的距离达到预设距离；
将拉伸后的所述可拉伸层以及所承载的各个所述裸片整体转移至所述载板；去除拉伸后的所述可拉伸层；
在所述载板上形成塑封层，以包覆各个所述裸片；去除所述载板，在各个所述裸片的活性面与所述塑封层上形成电连接结构；
切割形成多个芯片封装结构，每个所述芯片封装结构至少包括一个所述裸片。
与现有技术相比，本发明的有益效果在于：1)利用可拉伸层可将晶圆切割后的多个裸片一次完成转移，贴装效率高。2)不需要芯片装贴设备，贴装成本低。3)转移至载板的多个裸片保留了晶圆原本的布局，可以使用简单的良率测试技术进行不良追溯。4)可通过选择拉伸系数不同的可拉伸层承载膜， 控制拉伸尺寸不同，以满足封装结构的不同尺寸需求。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
图1是本发明第一实施例的芯片封装结构的形成方法的制作方法的流程图；
图2至图10是图1中的流程对应的中间结构示意图；
图11至图13是本发明第二实施例的芯片封装结构的制作方法对应的中间结构示意图；
图14是本发明第三实施例的芯片封装结构对应的中间结构示意图；
图15是本发明第四实施例的芯片封装结构对应的中间结构示意图；
图16是本发明第五实施例的芯片封装结构的形成方法的制作方法的流程图；
图17至图25是图16中的流程对应的中间结构示意图。
为方便理解本发明，以下列出本发明中出现的所有附图标记：
晶圆10                          晶圆的活性面10a
晶圆的背面10b                   可拉伸层11
裸片12                          裸片的活性面12a
裸片的背面12b                   焊盘121
保护层120                       开口120a
载板20                          塑封层13
塑封层的背面13b                 塑封层的正面13a
第一支撑板30                    第一再分布层14
金属图案块14a、23a              导电凸块15
第一介电层16                     芯片封装结构1a
中间承载层21                     背电极122
第二支撑板31                     导电插塞22
导电插塞的第一端22a              导电插塞的第二端22b
第二再分布层23                   第二介电层24
具体实施方式
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明第一实施例的芯片封装结构的形成方法的制作方法的流程图；图2至图10是图1中的流程对应的中间结构示意图。
首先，参照图1中的步骤S1、图2、图3与图4所示，提供晶圆10，在晶圆10的背面10b黏附可拉伸层11；切割晶圆10形成多个裸片12。其中，图2是晶圆和可拉伸层的俯视图；图3是沿着图2中的AA线的剖视图。
晶圆10包括相对的活性面10a与背面10b，活性面10a可以暴露若干焊盘(未标示)。
晶圆10的背面10b与可拉伸层11之间可以设置粘结层，以此实现两者之间的固定。
粘结层可以采用易剥离的材料，以便将可拉伸层11剥离下来，例如可以采用通过加热能够使其失去粘性的热分离材料或通过紫外照射能够使其失去粘性的UV分离材料。
本实施例中，可拉伸层11在垂直于厚度方向的拉伸系数呈线性。其它实施例中，可拉伸层11在垂直于厚度方向的拉伸系数可以呈非线性，拉伸长度随拉伸力的变化曲线固定即可。
可拉伸层11的材料可以为弹性高分子薄膜材料，或弹性的共聚物薄膜材料，例如聚乙烯、聚氯乙烯、聚丙烯、聚酰胺和聚酰胺中的至少一种，也可以为改性后的聚乙烯、聚氯乙烯、聚丙烯、聚酰胺或聚酰胺，以增强拉伸性能。
切割晶圆10时，可通过切割深度控制切割停留在可拉伸层11上方。
裸片12可以为电力裸片(POWER DIE)、存储裸片(MEMORY DIE)、传感裸片(SENSOR DIE)、或射频裸片(RADIO FREQUENCE DIE)等。
参照图4所示，裸片12包括相对的活性面12a与背面12b。焊盘121暴露于活性面12a。裸片12内可以包含形成于半导体衬底上的多种器件，以及与各个器件电连接的电互连结构。焊盘121与电互连结构连接，用于将各个器件的电信号输入/输出。
需要说明的是，本发明中，“/”表示“或”。
本实施例中，裸片12的活性面12a设置有保护层120。其它实施例中，裸片12的活性面也可以省略保护层120。
保护层120为绝缘材料，具体可以为有机高分子聚合物绝缘材料，也可以为无机绝缘材料或复合材料。有机高分子聚合物绝缘材料例如为聚酰亚胺、环氧树脂、ABF(Ajinomoto buildup film)、PBO(Polybenzoxazole)、有机聚合物膜或者其它具有类似绝缘性能的有机材料等。无机绝缘材料例如为二氧化硅、氮化硅中的至少一种。复合材料为无机-有机复合材料，可以为无机-有机聚合物复合材料，例如SiO 2/树脂聚合物复合材料。
本实施例中，参照图4所示，保护层120内开设有暴露焊盘121的开口120a。
接着，参照图1中的步骤S2与图5所示，拉伸可拉伸层11至相邻裸片12之间的距离为预设距离L。
拉伸可拉伸层11可带动裸片12相互散开。根据拉伸长度随拉伸力的变化曲线，通过控制拉伸力，可实现相邻裸片12之间距离的控制。
需要说明的是，相邻裸片12之间的距离包括上下方向距离与左右方向距离。上下方向距离与左右方向距离可以相同或不同。
之后，参照图1中的步骤S3与图6所示，裸片12的活性面12a朝向载板20，将拉伸后的可拉伸层11以及所承载的各个裸片12整体转移至载板20；参照图7所示，去除拉伸后的可拉伸层11。
利用可拉伸层11可将晶圆10切割后的多个裸片12一次完成转移，贴装 效率高。此外，不需要芯片装贴设备，贴装成本低。
可拉伸层11的去除方式可以为激光剥离、UV照射等现有去除方式。
载板20为硬质板件，可以包括塑料板、玻璃板、陶瓷板或金属板等。
裸片12的活性面12a与载板20之间可以设置粘结层，以此实现两者之间的固定。
粘结层可以采用易剥离的材料，以便将载板20剥离下来，例如可以采用通过加热能够使其失去粘性的热分离材料或通过紫外照射能够使其失去粘性的UV分离材料。
接着，参照图1中的步骤S4与图8所示，在载板20上形成塑封层13，以包覆各个裸片12，塑封层13包括相对的正面13a与背面13b，塑封层13的正面13a与裸片12的活性面12a朝向相同，塑封层13的背面13b与裸片12的背面12b朝向相同；参照图9所示，去除载板20，暴露各个裸片12的活性面12a与塑封层13的正面13a；在各个裸片12的活性面12a与塑封层13的正面13a上形成电连接结构。
塑封层13的材料可以为环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、乙烯-醋酸乙烯共聚物或聚乙烯醇等。塑封层13的材料还可以为各种聚合物或者树脂与聚合物的复合材料。对应地，封装可以采用在各个裸片12之间填充液态塑封料、后经塑封模具高温固化进行。一些实施例中，塑封层13也可以采用热压成型、传递成型等塑性材料成型的方式成型。
塑封层13包括相对的正面13a与背面13b。本实施例中，塑封层13的正面13a暴露保护层120与焊盘121。
载板20的去除方式可以为激光剥离、UV照射等现有去除方式。
载板20去除后，可在塑封层13的背面13b设置第一支撑板30。
第一支撑板30为硬质板件，可以包括塑料板、玻璃板、陶瓷板或金属板等。
参照图9所示，本实施例中，在各个裸片12的活性面12a与塑封层13 的正面13a上形成电连接结构包括如下步骤S41～S43。
步骤S41：在焊盘121以及塑封层13的正面13a上形成第一再分布层14。
具体地，步骤S41包括如下步骤S411～S414。
步骤S411：在各个裸片12的保护层120、保护层120暴露出的焊盘121以及塑封层13的正面13a上形成光刻胶层。
本步骤S411中，一个可选方案中，形成的光刻胶层可为感光膜。感光膜可以从胶带上撕下，贴敷在各个裸片12的保护层120、保护层120暴露出的焊盘121以及塑封层13的正面13a上。其它可选方案中，光刻胶层也可以采用先涂布液体光刻胶，后加热固化形成。
步骤S412：曝光显影光刻胶层，保留第一预定区域的光刻胶层，第一预定区域与待形成的第一再分布层14的金属图案块14a所在区域互补。
步骤S413：在第一预定区域的互补区域填充金属层以形成第一再分布层14的金属图案块14a。
本步骤S413可以采用电镀工艺完成。电镀铜或铝的工艺较为成熟。
具体地，步骤S411形成光刻胶层之前，可以先通过物理气相沉积法或化学气相沉积法在各个裸片12的保护层120、保护层120暴露出的焊盘121以及塑封层13的正面13a上形成一层籽晶层(Seed Layer)。籽晶层可以作为电镀铜或铝的供电层。
电镀可以包括电解电镀或无极电镀。电解电镀是将待电镀件作为阴极，对电解液进行电解，从而在待电镀件上形成一层金属。无极电镀是将溶液中的金属离子还原析出在待电镀件上形成金属层的方法。一些实施例中，还可以采用先溅射、后刻蚀的方法形成金属图案块14a。
步骤S414：灰化去除第一预定区域剩余的光刻胶层。
灰化完后，通过干法刻蚀或湿法刻蚀去除第一预定区域的籽晶层。
第一再分布层14的金属图案块14a可以通过抛光工艺，例如化学机械研磨法实现上表面平整。
需要说明的是，本步骤S41中的第一再分布层14的金属图案块14a根据设计需要进行布置，不同裸片12上的第一再分布层14的分布可以相同，也 可以不同。
步骤S42：在第一再分布层14上形成导电凸块15，导电凸块15为对外电连接结构。
具体地，步骤S42包括如下步骤S421～S424。
步骤S421：在金属图案块14a、金属图案块14a暴露出的保护层120以及塑封层13的正面13a上形成光刻胶层。
本步骤S421中，一个可选方案中，形成的光刻胶层可为感光膜。感光膜可以从胶带上撕下，贴敷在金属图案块14a、金属图案块14a暴露出的保护层120以及塑封层13的正面13a上。其它可选方案中，光刻胶层也可以采用先涂布液体光刻胶，后加热固化形成。
步骤S422：曝光显影光刻胶层，保留第二预定区域的光刻胶。第二预定区域与待形成导电凸块15的区域互补。
本步骤S422对光刻胶层进行了图案化。其它可选方案中，也可以使用其它易去除的牺牲材料代替光刻胶层。
步骤S423：在第二预定区域的互补区域填充金属层以形成导电凸块15。
本步骤S423可以采用电镀工艺完成。电镀铜或铝的工艺较为成熟。电镀铜或铝之前，还可以先物理气相沉积或化学气相沉积一层籽晶层(Seed Layer)作为供电层。
步骤S424：灰化去除第二预定区域剩余的光刻胶层。
导电凸块15可以通过抛光工艺，例如化学机械研磨法实现上表面平整。
步骤S43：形成包埋第一再分布层14与导电凸块15的第一介电层16，使导电凸块15暴露在第一介电层16外。
具体地：在导电凸块15、金属图案块14a、金属图案块14a暴露出的保护层120以及塑封层13的正面13a上形成第一介电层16；减薄第一介电层16，直至暴露出导电凸块15。
第一介电层16为绝缘材料，具体可以为有机高分子聚合物绝缘材料，也可以为无机绝缘材料或复合材料。有机高分子聚合物绝缘材料例如为聚酰亚胺、环氧树脂、ABF(Ajinomoto buildup film)、PBO(Polybenzoxazole)、有 机聚合物膜或者其它具有类似绝缘性能的有机材料等。复合材料为无机-有机复合材料，可以为无机-有机聚合物复合材料，例如SiO 2/树脂聚合物复合材料。
有机高分子聚合物绝缘材料可通过a)层压工艺压合在第一再分布层14、导电凸块15、未覆盖第一再分布层14的保护层120以及塑封层13的正面13a上，或b)先涂布在第一再分布层14、导电凸块15、未覆盖第一再分布层14的保护层120以及塑封层13的正面13a上、后固化，或c)通过注塑工艺固化在第一再分布层14、导电凸块15、未覆盖第一再分布层14的保护层120以及塑封层13的正面13a上。
第一介电层16的材料为二氧化硅或氮化硅等无机绝缘材料时，可通过沉积工艺形成在第一再分布层14、导电凸块15、未覆盖第一再分布层14的保护层120以及塑封层13的正面13a上。
相对于无机绝缘材料，有机高分子聚合物绝缘材料与复合材料的张应力较小，可防止第一介电层16大面积形成时引发塑封体出现翘曲。
第一介电层16可以包括一层或多层。
当第一介电层16包覆导电凸块15时，抛光第一介电层16直至暴露出导电凸块15。
第一介电层16形成完后，去除第一支撑板30。
其它实施例中，步骤S42与S43可以替换为：先在第一再分布层14上整面形成第一介电层16，再在第一介电层16内形成导电凸块15，导电凸块15连接第一再分布层14。例如在第二介电层16内形成暴露第一再分布层14的窗口，在窗口内填充金属层以形成导电凸块15。换言之，在第一再分布层14上形成导电凸块15与第一介电层16，导电凸块15暴露在第一介电层16外即可。
之后，参照图1中的步骤S5与图10所示，切割形成多个芯片封装结构1a，每个芯片封装结构1a包括一个裸片12。
参照图10所示，芯片封装结构1a中，塑封层13与裸片12的水平间距(塑封层13的侧墙厚度)等于步骤S2中拉伸可拉伸层11至相邻裸片12之间的预设距离L的一半。因而，可根据塑封层13的侧墙厚度需求，设定步骤 S2中的预设距离L。
其它实施例中，步骤S4中的第一再分布层14可以电连接相邻的两个或两个以上数目的裸片12，因而，步骤S5切割后，每个芯片封装结构1a包括两个或两个数目以上的裸片12。
此外，步骤S1切割晶圆10前，可对晶圆10进行测试，生成良率图；该良率图用于芯片封装结构1a的良率追踪。例如，可判断芯片封装结构1a的不合格产品是由于裸片12的质量问题还是步骤S4再布线对位问题。
图11至图13是本发明第二实施例的芯片封装结构的制作方法对应的中间结构示意图。参照图11至图13、图3至图5所示，本实施例中的芯片封装结构的制作方法与图1所示实施例一的芯片封装结构的制作方法大致相同，区别仅在于：步骤S1中，参照图11所示，在晶圆10的背面10b黏附可拉伸层11前，先在晶圆背面10b黏附中间承载层21，中间承载层21的硬度大于可拉伸层11的硬度；步骤S2中，参照图12所示，切割晶圆10的同时，切割中间承载层21；参照图13所示，拉伸可拉伸层11时，中间承载层21不随可拉伸层11散开。
此外，步骤S3中，裸片12整体转移的同时，转移中间承载层21；步骤S3中，形成的塑封层13包覆中间承载层21。换言之，中间承载层21保留在芯片封装结构1a中。
中间承载层21可以在切割晶圆10时，防止拉伸可拉伸层11变形。对应地，中间承载层21的材料可以为聚氯乙烯。
图14是本发明第三实施例的芯片封装结构对应的中间结构示意图。参照图14所示，本实施例中的芯片封装结构的制作方法与前述实施例的芯片封装结构的制作方法大致相同，区别仅在于：裸片12包括背电极122，背电极122暴露在裸片12的背面12b。例如，裸片12可以为IGBT集成其它功能的裸片，若干焊盘121中的两个可以分别为源极与栅极。背电极122可以为漏极。
对应地，步骤S4形成电连接结构步骤后，步骤S5切割形成多个芯片封装结构1a步骤前，还包括如下步骤S431至S433。
步骤S431：减薄塑封层13，直至露出每个裸片12的背电极122。
步骤S43进行前，可在第一介电层16上设置第二支撑板31。
步骤S432：经塑封层13的背面13b在塑封层13内形成多个导电插塞22，导电插塞22位于裸片12的侧边；导电插塞22的第一端22a连接第一再分布层14，导电插塞22的第二端22b暴露在塑封层13的背面13b。
步骤S433：在各个背电极122、导电插塞22的第二端22b与塑封层13的背面13b上形成第二再分布层23，用于通过导电插塞22将裸片12的背电极122电引至裸片12的活性面12a；形成包埋第二再分布层23的第二介电层24。
本实施例中，第二再分布层23包括一层金属图案块23a。其它实施例中，第二再分布层23可以包括两层及两层以上的金属图案层。
第二再分布层23与第二介电层24的形成方法可以参照第一再分布层14与第一介电层16的形成方法。
其它实施例中，导电凸块15也可以形成在第二再分布层23上，导电凸块15暴露在第二介电层24外。换言之，导电柱25将裸片12的焊盘121电引至裸片12的背面12b，对外电连接结构靠近裸片12的背面12b。
换言之，利用可拉伸层11将晶圆10切割后的多个裸片12一次完成转移的方案，不仅可以用于芯片封装结构1a中的单面布线，也可以用于双面布线。
图15是本发明第四实施例的芯片封装结构对应的中间结构示意图。参照图15所示，本实施例中的芯片封装结构的制作方法与第三实施例的芯片封装结构的制作方法大致相同，区别仅在于：采用导电柱25替换导电插塞22。
具体地，步骤S3之后，步骤S4形成塑封层13前，在载板20上排布多个导电柱25，导电柱25位于裸片12的侧边；导电柱25的第一端25a朝向载板20。
导电柱25的材料可以为铜等导电性优良的金属。
导电柱25的数目及位置可根据预设电路布局而定。
导电柱25的高度可以大于裸片12的厚度，至少导电柱25的高度等于裸片12的厚度。
步骤S4形成的第一再分布层14还位于导电柱25的第一端25a。
对应地，步骤S4形成电连接结构步骤后，步骤S5切割形成多个芯片封装结构1a步骤前，还包括如下步骤S431'至S432'。
步骤S431'：减薄塑封层13，直至露出每个裸片12的背电极122与导电柱25的第二端25b；
步骤S432'：在各个背电极122、导电柱25的第二端25b与塑封层13的背面13b上形成第二再分布层23，用于通过导电柱25将裸片12的背电极122电引至裸片12的活性面12a；形成包埋第二再分布层23的第二介电层24。
图16是本发明第五实施例的芯片封装结构的形成方法的制作方法的流程图；图17至图25是图16中的流程对应的中间结构示意图。
首先，参照图16中的步骤S1'、图17与图18所示，切割晶圆10形成各个裸片12；各个裸片12的活性面12a朝向可拉伸层11，保持晶圆10切割后的排布，将各个裸片12整体转移至可拉伸层11。
本实施例的步骤S1'与实施例一的步骤S1大致相同，区别仅在于：先切割晶圆10形成裸片12，后转移至可拉伸层11。
接着，参照图16中的步骤S2与图19所示，拉伸可拉伸层11至相邻裸片12之间的距离为预设距离L。
本实施例的步骤S2可以参照实施例一的步骤S2。
之后，参照图16中的步骤S3'与图20所示，各个裸片12的背面12b朝向载板20，将拉伸后的可拉伸层11以及所承载的各个裸片12整体转移至载板20；参照图21所示，去除拉伸后的可拉伸层11。
本实施例的步骤S3'与实施例一的步骤S3大致相同，区别仅在于：由于裸片12的活性面12a贴附于可拉伸层11，因而，各个裸片12整体转移时，裸片12的背面12b朝向载板20。
之后，参照图16中的步骤S4'与图22所示，在载板20上形成塑封层13，以包覆各个裸片12，塑封层13包括相对的正面13a与背面13b，塑封层13的正面13a与裸片12的背面12b朝向相同，塑封层13的背面13b与裸片12的活性面12a朝向相同；参照图23所示，自塑封层13的背面13b减薄塑封层13，直至露出各个裸片12的活性面12a；参照图24所示，在各个裸片12 的活性面12a与塑封层13的背面13b上形成电连接结构。
本实施例的步骤S4'与实施例一的步骤S4大致相同，区别仅在于：由于裸片12的背面12b朝向载板20，因而在各个裸片12的活性面12a上形成电连接结构时，需减薄塑封层13直至露出各个裸片12的活性面12a。
再接着，参照图16中的步骤S5'与图25所示，去除载板20，切割形成多个芯片封装结构1a，每个芯片封装结构1a包括一个裸片12。
本实施例的步骤S5'与实施例一的步骤S5大致相同。载板20可以在步骤S5'中去除，也可以在步骤S4'减薄塑封层13后去除。减薄塑封层13后去除载板20的方案中，可以在各个裸片12的背面12b与塑封层13的正面13a上形成第一支撑板30。
相应地，对于第三实施例的双面布线的芯片封装结构的制作方法，本实施例可以省略步骤S431。
相应地，对于第四实施例的双面布线的芯片封装结构的制作方法，本实施例中，一方面，步骤S3之后，步骤S4形成塑封层13前，在载板20上排布多个导电柱25，导电柱25位于裸片12的侧边；导电柱25的第二端25b朝向载板20。步骤S4形成的第一再分布层14还位于导电柱25的第二端25b。
第二方面，省略步骤S431'。
第三方面，步骤S432'：在各个背电极122、导电柱25的第一端25a与塑封层13的背面13b上形成第二再分布层23，用于通过导电柱25将裸片12的背电极122电引至裸片12的活性面12a；形成包埋第二再分布层23的第二介电层24。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (10)

  1. 一种芯片封装结构的形成方法，其特征在于，包括：
    提供承载于可拉伸层的多个裸片，各个所述裸片在所述可拉伸层上的排布保持晶圆切割后的排布；
    拉伸所述可拉伸层以使相邻所述裸片之间的距离达到预设距离；
    将拉伸后的所述可拉伸层以及所承载的各个所述裸片整体转移至载板；去除拉伸后的所述可拉伸层；
    在所述载板上形成塑封层，以包覆各个所述裸片；去除所述载板，在各个所述裸片的活性面与所述塑封层上形成电连接结构；
    切割形成多个芯片封装结构，每个所述芯片封装结构至少包括一个所述裸片。
  2. 根据权利要求1所述的芯片封装结构的形成方法，其特征在于，提供承载于可拉伸层的多个裸片包括：在晶圆的背面黏附可拉伸层，切割所述晶圆形成各个所述裸片；
    将拉伸后的所述可拉伸层以及所承载的各个所述裸片整体转移至所述载板时，各个所述裸片的活性面朝向所述载板；在所述载板上形成塑封层后，所述塑封层包括相对的正面与背面，所述塑封层的正面与所述裸片的活性面朝向相同，所述塑封层的背面与所述裸片的背面朝向相同；去除所述载板后，暴露各个所述裸片的活性面与所述塑封层的正面。
  3. 根据权利要求2所述的芯片封装结构的形成方法，其特征在于，在所述晶圆的背面黏附可拉伸层前，先在所述晶圆的背面黏附中间承载层，所述中间承载层的硬度大于所述可拉伸层的硬度；切割所述晶圆的同时，切割所述中间承载层；整体转移拉伸后的所述可拉伸层以及所承载的各个所述裸片 的同时，转移所述中间承载层；形成的所述塑封层包覆所述中间承载层。
  4. 根据权利要求1所述的芯片封装结构的形成方法，其特征在于，提供承载于可拉伸层的多个裸片包括：切割晶圆形成各个裸片；各个所述裸片的活性面朝向可拉伸层，保持所述晶圆切割后的排布，将各个所述裸片整体转移至所述可拉伸层；
    将拉伸后的所述可拉伸层以及所承载的各个所述裸片整体转移至所述载板时，各个所述裸片的背面朝向所述载板；在所述载板上形成塑封层后，所述塑封层包括相对的正面与背面，所述塑封层的正面与所述裸片的背面朝向相同，所述塑封层的背面与所述裸片的活性面朝向相同；去除所述载板前，自所述塑封层的背面减薄所述塑封层，直至露出各个所述裸片的活性面。
  5. 根据权利要求1至4任一项所述的芯片封装结构的形成方法，其特征在于，所述可拉伸层在垂直于厚度方向的拉伸系数呈线性。
  6. 根据权利要求1至4任一项所述的芯片封装结构的形成方法，其特征在于，所述可拉伸层的材料为弹性高分子薄膜材料，或弹性的共聚物薄膜材料。
  7. 根据权利要求1至4任一项所述的芯片封装结构的形成方法，其特征在于，所述可拉伸层的材料为聚乙烯、聚氯乙烯、聚丙烯、聚酰胺和聚酰胺中的至少一种。
  8. 根据权利要求1所述的芯片封装结构的形成方法，其特征在于，每个所述裸片包括多个焊盘，多个所述焊盘暴露在所述活性面；
    在所述各个裸片的活性面与所述塑封层上形成电连接结构包括：
    在所述焊盘以及所述塑封层上形成第一再分布层；
    在所述第一再分布层上形成导电凸块与第一介电层，所述导电凸块暴露在所述第一介电层外，所述导电凸块为所述芯片封装结构的对外电连接结构。
  9. 根据权利要求8所述的芯片封装结构的形成方法，其特征在于，所述裸片包括背电极，所述背电极暴露在所述裸片的背面；
    所述形成电连接结构步骤后，所述切割形成多个芯片封装结构步骤前，还包括：
    在所述塑封层内形成多个导电插塞，所述导电插塞位于所述裸片的侧边；所述导电插塞的第一端连接所述第一再分布层，所述导电插塞的第二端暴露在所述塑封层外；
    在各个所述背电极、所述导电插塞的第二端与所述塑封层上形成第二再分布层，用于通过所述导电插塞将所述裸片的背电极电引至所述裸片的活性面；形成包埋所述第二再分布层的第二介电层。
  10. 根据权利要求1所述的芯片封装结构的形成方法，其特征在于，切割所述晶圆前，对所述晶圆进行测试，生成良率图；所述良率图用于所述芯片封装结构的良率追踪。
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