WO2022012498A1 - 芯片封装结构及其制作方法 - Google Patents

芯片封装结构及其制作方法 Download PDF

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Publication number
WO2022012498A1
WO2022012498A1 PCT/CN2021/105913 CN2021105913W WO2022012498A1 WO 2022012498 A1 WO2022012498 A1 WO 2022012498A1 CN 2021105913 W CN2021105913 W CN 2021105913W WO 2022012498 A1 WO2022012498 A1 WO 2022012498A1
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WO
WIPO (PCT)
Prior art keywords
layer
electrical connection
edge connector
chip package
package structure
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Application number
PCT/CN2021/105913
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English (en)
French (fr)
Inventor
周辉星
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矽磐微电子(重庆)有限公司
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Publication of WO2022012498A1 publication Critical patent/WO2022012498A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • the present application relates to the technical field of chip packaging, and in particular, to a chip packaging structure and a manufacturing method thereof.
  • the present application provides a new chip package structure and a manufacturing method thereof, so as to meet the requirements of small size, compact structure and high integration of the package structure.
  • the application purpose of the present application is to provide a chip package structure and a manufacturing method thereof, so as to meet the requirements of small size, compact structure and high integration of the package structure.
  • a chip packaging structure including:
  • the plurality of components include electrical connection points, the electrical connection points are located on the functional surfaces of the plurality of components;
  • a component protective layer covering the functional surfaces of the plurality of components, and the component protective layer exposing the electrical connection points;
  • an edge connector including a coupling face
  • a plastic encapsulation layer covering the edge connector and the plurality of components, and the front surface of the plastic encapsulation layer exposes the component protection layer, the electrical connection point and the coupling surface of the edge connector;
  • redistribution layer located on the electrical connection point, the component protection layer and the front surface of the plastic encapsulation layer, the redistribution layer is used to electrically connect the various components through the electrical connection point;
  • the plurality of conductive plugs are used to lead the edge connector and the redistribution layer to the back of the plastic sealing layer;
  • connecting wires located on the back of the plastic encapsulation layer, to electrically connect the conductive plugs
  • the second dielectric layer embeds the connection lines.
  • a second aspect of the present application provides a method for fabricating a chip package structure, including:
  • a carrier board and a plurality of sets of components to be packaged are provided, each set of the components to be packaged including edge connectors and a plurality of components including electrical connection points located on the plurality of components
  • the functional surface is covered with a component protection layer, and the edge connector includes a coupling surface; the plurality of groups of components to be packaged are fixed on the surface of the carrier board, wherein the component protection layer and the coupling surface of the edge connector faces the carrier board;
  • a redistribution layer is formed on the component protection layer, the electrical connection points and the front surface of the plastic encapsulation layer, so as to electrically connect the various components in the group through the electrical connection points; and the edge is formed to bury the edge the coupling surface of the connector and the first dielectric layer of the redistribution layer;
  • connecting lines on the back of the plastic encapsulation layer to electrically connect the respective conductive plugs in the group; forming a second dielectric layer burying the connecting lines;
  • a plurality of chip package structures are formed by cutting, and each chip package structure includes a group of components to be packaged.
  • the edge connector and a plurality of components are encapsulated in the plastic encapsulation layer.
  • the components include electrical connection points.
  • the electrical connection points are located on the functional surface of the component.
  • the functional surface is covered with a component protective layer exposing the electrical connection points.
  • the edge connector Including a coupling surface; then, on the one hand, a redistribution layer is formed on the component protection layer, the electrical connection point and the front surface of the plastic sealing layer to electrically connect each component in the group through the electrical connection point;
  • the back side forms a plurality of conductive plugs in the plastic sealing layer to lead the edge connectors and the redistribution layer to the back of the plastic sealing layer; and forms connecting lines on the back side of the plastic sealing layer to electrically connect each conductive plug in the group.
  • the rewiring layer is combined with the connecting lines, and the circuit layout on two sides can improve the density of wiring compared with the circuit layout on one side only through the rewiring layer, and form a more complex wiring and smaller package structure.
  • the chip package structure realizes external circuit connection through edge connectors, so that the performance of the chip package structure is reliable.
  • multiple chip packaging structures can be fabricated at one time, which is beneficial to mass production and cost reduction.
  • the rewiring layer can be directly formed on the surface of the component protective layer and the plastic sealing layer after the plastic sealing process, instead of forming a dielectric layer on the entire panel; in panel packaging, due to the panel area Larger, it is more difficult to form a dielectric layer on a large-area panel, more materials are used for the dielectric layer, and the presence of a component protection layer reduces the process difficulty and cost of packaging.
  • FIG. 1 is a schematic top-view structural diagram of a chip packaging structure according to a first embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structural diagram of the chip package structure according to the first embodiment of the present application.
  • FIG. 3 is a flowchart of a method for fabricating the chip package structure in FIGS. 1 and 2 .
  • 4 to 12 are schematic diagrams of intermediate structures corresponding to the process in FIG. 3 .
  • FIG. 13 is a schematic cross-sectional structural diagram of a chip package structure according to a second embodiment of the present application.
  • FIG. 14 is a schematic top-view structural diagram of a chip packaging structure according to a third embodiment of the present application.
  • FIG. 15 is a schematic cross-sectional structural diagram of a chip package structure according to a third embodiment of the present application.
  • Edge connector 12 Coupling surface 12a
  • Plastic layer 13 The front of the plastic layer 13a
  • the first dielectric layer 17 The second dielectric layer 18
  • FIG. 1 is a schematic top-view structural diagram of a chip packaging structure according to a first embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structural diagram of the chip package structure according to the first embodiment of the present application.
  • the chip package structure 1 includes:
  • the components 11 include electrical connection points, and the electrical connection points are located on the functional surface 11a of the components 11;
  • the component protective layer 110 covers the functional surface 11a of the component 11, and the component protective layer 110 exposes the electrical connection points;
  • edge connector 12 (Edge connector), the edge connector 12 includes a coupling surface 12a;
  • the plastic encapsulation layer 13 covers the edge connector 12 and the plurality of components 11 , and the front surface 13 a of the plastic encapsulation layer 13 exposes the coupling surface 12 a of the component protection layer 110 and the edge connector 12 ;
  • the redistribution layer 14 is located on the electrical connection point, the component protection layer 110 and the front surface 13a of the plastic sealing layer 13, and the redistribution layer 14 is used to electrically connect each component 11 through the electrical connection point;
  • a plurality of conductive plugs 15 are located in the plastic sealing layer 13, and the plurality of conductive plugs 15 are used to lead the edge connector 12 and the redistribution layer 14 to the back surface 13b of the plastic sealing layer 13;
  • the connecting wires 16 are located on the back surface 13b of the plastic sealing layer 13 to electrically connect the respective conductive plugs 15;
  • the first dielectric layer 17 embeds the redistribution layer 14, and the first dielectric layer 17 exposes the coupling surface 12a of the edge connector 12;
  • the second dielectric layer 18 embeds the connection lines 16 .
  • the component 11 includes a bare chip 111 .
  • the number of the bare chips 111 may also be two or other numbers, which are not limited in this application.
  • the functions of the respective dies 111 may be the same or different.
  • the die 111 may be a power die (POWER DIE), a memory die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE).
  • POWER DIE power die
  • MEMORY DIE memory die
  • SENSOR DIE sensor die
  • RADIO FREQUENCE DIE radio frequency die
  • the active surface 111a of the die is provided with a pad 112, and the die 111 may contain various devices formed on the semiconductor substrate, and an electrical interconnection structure electrically connected with each device.
  • the pads 112 are connected to the electrical interconnection structure for inputting/outputting electrical signals of the respective devices.
  • the active surface 111a of the die corresponds to the functional surface 11a of the component 11, and the pads 112 correspond to electrical connection points.
  • the component protection layer 110 is an insulating material, specifically an insulating resin material or an inorganic material.
  • the insulating resin material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, organic polymer composite material or other organic materials with similar insulating properties.
  • the inorganic material is, for example, at least one of silicon dioxide and silicon nitride.
  • the edge connector 12 is located on one side of the plurality of components 11 .
  • the edge connector 12 includes a coupling surface 12 a for realizing the external circuit connection of the chip package structure 1 .
  • the material of the edge connector 12 may be a metal with excellent electrical conductivity such as copper.
  • An anti-oxidation layer may be provided on the coupling surface 12a of the edge connector 12 to prevent oxidation of copper, thereby preventing deterioration of electrical connection performance caused by oxidation of copper.
  • the anti-oxidation layer may include: a) a tin layer, or b) a bottom-up stack of nickel and gold layers, or c) a bottom-up stack of nickel, palladium, and gold layers.
  • the material of the plastic sealing layer 13 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate Diol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol, etc.
  • the molding layer can be various polymers, resins or resins, polymer composite materials, such as resins with fillers, or other materials with similar properties.
  • the plastic sealing layer 13 includes a front side 13a and a back side 13b opposite to each other.
  • the front surface 13 a of the plastic encapsulation layer 13 exposes the component protection layer 110 , the electrical connection points, and the coupling surface 12 a of the edge connector 12 .
  • the redistribution layer 14 includes a plurality of metal blocks 14 a with one layer, and the metal blocks 14 a are electrically connected to the pads 112 .
  • some of the conductive plugs 15 are in contact with the edge connector 12 , and some of the conductive plugs 15 are in contact with the redistribution layer 14 .
  • the number and position of the conductive plugs 15 in contact with the redistribution layer 14 and the layout of the connection lines 16 may be determined according to a predetermined circuit layout.
  • the materials of the first dielectric layer 17 and the second dielectric layer 18 may be insulating resin materials or inorganic materials.
  • the insulating resin material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, organic polymer composite material or other organic materials with similar insulating properties.
  • the inorganic material is, for example, at least one of silicon dioxide and silicon nitride. Compared with the inorganic material, the tensile stress of the insulating resin material is smaller, which can prevent the surface of the chip package structure 1 from warping.
  • the external circuit connection of a plurality of chips is realized through the edge connector 12 .
  • the rewiring layer 14 is used to realize the circuit layout on the front side 13a of the plastic packaging layer 13, and on the other hand, the circuit layout on the back side 13b of the plastic packaging layer 13 is achieved by the conductive plugs 15 and the connecting wires 16.
  • the circuit layout on both sides of this embodiment can improve the density of wiring, and form a chip package structure 1 with more complex wiring and smaller volume.
  • the chip package structure 1 realizes external circuit connection through the edge connector 12 , so that the performance of the chip package structure 1 is reliable.
  • FIG. 3 is a flowchart of a production method.
  • 4 to 12 are schematic diagrams of intermediate structures corresponding to the process in FIG. 3 .
  • a carrier board 2 and a plurality of groups of components to be packaged 10 are provided, and each group of components to be packaged 10 includes an edge connector 12 and a plurality of components 11 .
  • 11 includes an electrical connection point, the electrical connection point is located on the functional surface 11a of the component 11, the functional surface 11a is covered with a component protective layer 110, and the component protective layer 110 has an opening 110a that exposes the electrical connection point, and the edge connector 12 includes a coupling Surface 12a ; the plurality of groups of components to be packaged 10 are fixed on the surface of the carrier board 2 , wherein the coupling surface 12a of the component protection layer 110 and the edge connector 12 faces the carrier board 2 .
  • 4 is a top view of the carrier board and a plurality of groups of components to be packaged;
  • FIG. 5 is a cross-sectional view along the line AA in FIG. 4 .
  • the component 11 includes a bare chip 111 .
  • a bare chip 111 As shown in FIG. 2 , three dies 111 are included. In other embodiments, the number of the bare chips 111 may also be two or other numbers, which are not limited in this application.
  • the functions of the respective dies 111 may be the same or different.
  • the die 111 may be a power die (POWER DIE), a memory die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE).
  • POWER DIE power die
  • MEMORY DIE memory die
  • SENSOR DIE sensor die
  • RADIO FREQUENCE DIE radio frequency die
  • the bare chip 111 is formed by dividing a wafer, the wafer includes an active surface of the wafer, and the active surface of the wafer is provided with a pad 112 and an insulating layer (not shown) for protecting the pad 112 .
  • the die 111 is formed after the wafer is diced.
  • the die 111 includes an active surface 111a of the die, and the active surface 111a of the die is provided with a pad 112 and an insulating layer for protecting the pad 112.
  • the component protection layer 110 is applied on the active surface 111a of the die.
  • the application process of the component protection layer 110 may be as follows: before the wafer is cut into the bare chips 111, the component protection layer 110 is applied on the active surface of the wafer, and the cutting has The wafer of the component protection layer 110 forms the bare chip 111 with the component protection layer 110 , or the component protection layer 110 is applied on the bare chip 111 after the wafer is diced into the bare chips 111 .
  • applying the component protection layer 110 on the bare chip 111 before plastic sealing can avoid large-area production of the dielectric layer, which wastes materials on the one hand, and wastes materials on the other hand. On the one hand, warping of the plastic body can be avoided.
  • Die 111 may include various devices formed on a semiconductor substrate, as well as electrical interconnect structures that electrically connect the various devices.
  • the pads 112 on the active surface 111a of the die are connected to the electrical interconnection structure for inputting/outputting electrical signals of the respective devices.
  • the active surface 111a of the die corresponds to the functional surface 11a of the component 11, and the pads 112 correspond to electrical connection points.
  • the component protection layer 110 is an insulating material, specifically an insulating resin material or an inorganic material.
  • the insulating resin material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, organic polymer composite material or other organic materials with similar insulating properties.
  • the insulating resin material may be pressed on the pads 112 and the insulating layer between the adjacent pads 112 by a) lamination process, or b) firstly coated or printed on the pads 112 and between the adjacent pads 112. On the insulating layer, post-curing, or c) curing on the pad 112 and the insulating layer between adjacent pads 112 by an injection molding process.
  • the material of the component protection layer 110 is an inorganic material such as silicon dioxide or silicon nitride, it can be formed on the pads 112 and the insulating layer between the adjacent pads 112 through a deposition process.
  • the component protection layer 110 may include one or more layers.
  • the component protection layer 110 has openings 110 a that expose the pads 112 .
  • the pads 112 on the die 111 may be embedded in the component protection layer 110, and the openings 110a are formed before the redistribution layer 14 (see FIG. 8) forming process.
  • an opening 110a exposes a partial area of a pad 112 .
  • one opening 110a may also expose partial regions of two or more pads 112 .
  • the wafer may be thinned from the backside before being diced to reduce the thickness of the die 111 .
  • the carrier plate 2 is a rigid plate, which may include a plastic plate, a glass plate, a ceramic plate, a metal plate, or the like.
  • An adhesive layer may be provided between the bare chip 111 and the carrier board 2 and between the edge connector 12 and the carrier board 2, so as to realize the fixing between the two.
  • a whole-surface adhesive layer may be coated on the surface of the carrier board 2, and the plurality of dies 111 and the plurality of edge connectors 12 are placed on the adhesive layer.
  • the adhesive layer can be made of an easily peelable material so that the carrier plate 2 can be peeled off, for example, a thermal separation material that can lose its adhesiveness by heating or a UV separation material that can be made to lose its adhesiveness by ultraviolet irradiation.
  • the height of edge connector 12 is less than the thickness of die 111 .
  • the height of the edge connector 12 refers to the maximum dimension of the edge connector 12 in the direction perpendicular to the coupling surface 12a.
  • the edge connector 12 is a preform that is directly bonded to the surface of the carrier board 2 .
  • the metal sheet may also be bonded on the carrier board 2 first, and then the edge connector 12 may be formed by etching at a predetermined position of the carrier board 2 .
  • the arrangement of the edge connector 12 and the plurality of dies 111 on the carrier board 2 is not sequential, and may also be arranged simultaneously.
  • a plurality of edge connectors 12 or a plurality of dies 111 may be arranged on a transfer carrier before being transferred to the carrier 2 .
  • a whole-surface adhesive layer may be coated on the surface of the transfer carrier, and a plurality of edge connectors 12 or a plurality of dies 111 may be placed on the adhesive layer.
  • the adhesive layer can be of a peelable material to release the edge connectors 12, the dies 111 from the transfer carrier, such as a thermal release material that can be debonded by heating or by UV light Irradiate a UV separation material that can make it lose its tack.
  • a group of components 10 to be packaged are located in an area on the surface of the carrier board 2 to facilitate subsequent cutting.
  • a plurality of groups of components 10 to be packaged can be fixed on the surface of the carrier board 2, so as to manufacture a plurality of chip packaging structures 1 at the same time, which is beneficial to mass production and reduces costs.
  • a plastic encapsulation layer 13 is formed on the surface of the carrier board 2 to embed each group of components to be packaged 10 ; as shown in FIG. 7 , the carrier board 2 is removed to expose the elements The device protection layer 110 , the electrical connection points, the coupling surface 12 a of the edge connector 12 , and the front surface 13 a of the plastic encapsulation layer 13 .
  • the material of the plastic sealing layer 13 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate Diol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol, etc.
  • the molding layer can be various polymers, resins or resins, polymer composite materials, such as resins with fillers, or other materials with similar properties.
  • the encapsulation may be performed by filling liquid plastic sealing compound between each component 11 and each edge connector 12 , and then curing at a high temperature in a plastic packaging mold.
  • the plastic encapsulation layer 13 may also be formed by means of plastic material forming such as thermocompression forming and transfer forming.
  • the plastic encapsulation layer 13 may include opposite front surfaces 13a and back surfaces 13b.
  • the plastic sealing layer 13 can be thinned from the back surface 13b by mechanical grinding, such as grinding with a grinding wheel, so as to reduce the volume.
  • the component protection layer 110 can prevent the bonding pads 112 and the electrical interconnection structures in the die 111 from being damaged.
  • the plastic package of the component to be packaged 10 is formed.
  • a first support plate 3 may also be disposed on the back surface 13 b of the plastic sealing layer 13 . The first support plate 3 can support each component 11 embedded in the plastic sealing layer 13 in the subsequent process.
  • the first support plate 3 is a hard plate, which may include a glass plate, a ceramic plate, a metal plate, and the like.
  • a redistribution layer 14 is formed on the component protection layer 110 , the electrical connection points and the front surface 13 a of the plastic encapsulation layer 13 to electrically connect the various components through the electrical connection points. 11 ; forming the first dielectric layer 17 of the redistribution layer 14 and the coupling surface 12 a of the embedded edge connector 12 .
  • forming the redistribution layer 14 includes the following steps S31-S34.
  • Step S31 forming a photoresist layer on the component protective layer 110 , the electrical connection points, the coupling surfaces 12 a of each edge connector 12 and the front surface 13 a of the plastic encapsulation layer 13 disposed on each component 11 .
  • the formed photoresist layer may be a photosensitive film.
  • the photosensitive film can be peeled off from the tape and applied to the component protection layer 110 , the electrical connection points of each component 11 , the coupling surface 12 a of each edge connector 12 and the front surface 13 a of the plastic sealing layer 13 .
  • the photoresist layer can also be formed by first coating a liquid photoresist and then heating and curing.
  • Step S32 exposing and developing the photoresist layer, retaining the photoresist layer in the first predetermined area, and the first predetermined area is complementary to the area where the metal block 14 a of the rewiring layer 14 to be formed is located.
  • the photoresist layer is patterned.
  • other easily removable sacrificial materials can also be used in place of the photoresist layer.
  • Step S33 filling a metal layer in a complementary region of the first predetermined region to form the metal block 14 a of the redistribution layer 14 .
  • metal blocks 14a are positioned so that one or more pads 112 of the components 11 can be electrically connected.
  • This step S33 may be completed by an electroplating process.
  • the process of electroplating copper or aluminum is relatively mature.
  • step S31 physical vapor deposition method or chemical vapor deposition method may be used on the component protective layer 110, the electrical connection point, and the coupling surface 12a of the edge connector 12 disposed on each component 11.
  • a seed layer (Seed Layer) is formed on the front surface 13a of the plastic encapsulation layer 13 .
  • the seed layer can be used as a power supply layer for electroplating copper or aluminum.
  • Electroplating may include electrolytic plating or electroless plating.
  • Electrolytic plating is to use the part to be plated as a cathode and electrolyze the electrolyte to form a layer of metal on the part to be plated.
  • Electroless plating is a method of reducing and precipitation of metal ions in a solution to form a metal layer on the part to be plated.
  • the metal block 14a may also be formed by sputtering first and then etching.
  • Step S34 removing the remaining photoresist layer in the first predetermined region by ashing.
  • the seed layer in the first predetermined region is removed by dry etching or wet etching.
  • the upper surface of the metal block 14a of the redistribution layer 14 may be flattened by a polishing process, such as chemical mechanical polishing.
  • the metal blocks 14a of the redistribution layer 14 in this step S3 are arranged according to design requirements, and the distribution of the redistribution layers 14 on the components 11 in different groups of the components 10 to be packaged may be the same or different. .
  • the first dielectric layer 17 may also be formed on the front surface 13 a of the plastic encapsulation layer 13 .
  • the first dielectric layer 17 is an insulating material, specifically an insulating resin material or an inorganic material.
  • the insulating resin material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, organic polymer composite material or other organic materials with similar insulating properties.
  • the insulating resin material may be pressed onto the coupling surface 12a of the edge connector 12, the redistribution layer 14 and the front surface 13a of the plastic encapsulation layer 13 by a) lamination process, or b) firstly coated on the coupling surface 12a of the edge connector 12 , on the front side 13a of the redistribution layer 14 and the plastic encapsulation layer 13, post-curing, or c) cured on the coupling surface 12a of the edge connector 12, the redistribution layer 14 and the front side 13a of the plastic encapsulation layer 13 by an injection molding process.
  • the material of the first dielectric layer 17 is an inorganic material such as silicon dioxide or silicon nitride, it can be formed on the coupling surface 12 a of the edge connector 12 , the redistribution layer 14 and the front surface 13 a of the plastic sealing layer 13 through a deposition process.
  • the insulating resin material has a smaller tensile stress, which can prevent the plastic package from warping when the first dielectric layer 17 is formed in a large area.
  • the first dielectric layer 17 may include one or more layers.
  • the first support plate 3 may be removed, and the second support plate 4 is disposed on the first dielectric layer 17 .
  • the removal method of the first support plate 3 may be a removal method such as laser lift-off and UV irradiation.
  • the second support plate 4 may play a supporting role in the subsequent steps of forming the conductive plugs 15 , and/or forming the connection lines 16 , and/or forming the second dielectric layer 18 .
  • the second support plate 4 is a rigid plate, which may include a glass plate, a ceramic plate, a metal plate, and the like.
  • a plurality of conductive plugs 15 are formed in the plastic packaging layer 13 through the back surface 13 b of the plastic packaging layer 13 to lead the edge connectors 12 and the redistribution layer 14 to the plastic packaging layer 13 on the back side 13b.
  • This step S4 may include the following steps S41-S42.
  • Step S41 forming a plurality of through holes 13 c in the plastic sealing layer 13 through the back surface 13 b of the plastic sealing layer 13 .
  • Step S42 filling the through hole 13 c with conductive material to form the conductive plug 15 .
  • the conductive material may be copper, aluminum, or the like.
  • the method of filling the conductive material may refer to the method of forming the metal block 14 a of the redistribution layer 14 .
  • the conductive material outside the through hole 13c can be removed by chemical mechanical polishing.
  • the number and position of the conductive plugs 15 in contact with the redistribution layer 14 may be determined according to a predetermined circuit layout.
  • connecting wires 16 are formed on the back surface 13 b of the plastic encapsulation layer 13 to connect the conductive plugs 15 ;
  • connection line 16 For the formation method of the connection line 16 , reference may be made to the formation method of the metal block 14 a in the redistribution layer 14 .
  • the layout of the connection lines 16 may be determined according to a predetermined layout.
  • connection line 16 may be performed in the same process as step S42, and the process of planarizing and removing the conductive material outside the through hole 13c may be omitted.
  • the material and formation method of the second dielectric layer 18 reference may be made to the material and formation method of the first dielectric layer 17 .
  • the second dielectric layer 18 may also be formed on the back surface 13 b of the plastic sealing layer 13 .
  • the second dielectric layer 18 may include one or more layers.
  • step S6 in FIG. 3 and as shown in FIG. 12 the first dielectric layer 17 burying the coupling surface 12 a of the edge connector 12 is removed.
  • the first dielectric layer 17 When the first dielectric layer 17 is a laser reactive material, it is removed by laser patterning. When the first dielectric layer 17 is a material that can be removed by dry etching or wet etching, it is removed by dry etching or wet etching. When the first dielectric layer 17 is a photosensitive material, it is removed by exposing first and then developing.
  • an anti-oxidation layer may also be formed on the coupling surface 12a.
  • the anti-oxidation layer may include: a) a tin layer, or b) a bottom-up stack of nickel and gold layers, or c) a bottom-up stack of nickel, palladium, and gold layers.
  • the anti-oxidation layer can be formed by an electroplating process.
  • the material of the edge connector 12 can be copper, and the above-mentioned anti-oxidation layer can prevent the oxidation of copper, thereby preventing the deterioration of electrical connection performance caused by the oxidation of copper.
  • the above-mentioned anti-oxidation layer may also be formed in the edge connector 12 provided in step S1.
  • the second support plate 4 can be removed.
  • the removal method of the second support plate 4 may be a removal method such as laser lift-off and UV irradiation.
  • each chip package structure 1 includes a group of components to be packaged 10 .
  • each component 11 in a group of components to be packaged 10 can be connected to an external circuit through the edge connector 12 , so that the performance of the chip package structure 1 is reliable.
  • FIG. 13 is a schematic cross-sectional structural diagram of a chip package structure according to a second embodiment of the present application.
  • the chip package structure 200 and the manufacturing method thereof in this embodiment are substantially the same as the chip package structure 1 and the manufacturing method thereof in FIG. 1 , except that the redistribution layer 14 includes two layers.
  • the metal block 14b of the second redistribution layer is selectively electrically interconnected with the metal block 14a of the first redistribution layer, which can realize a more complicated circuit layout.
  • the redistribution layer 14 may also include three or more layers.
  • FIG. 14 is a schematic top-view structural diagram of a chip packaging structure according to a third embodiment of the present application.
  • FIG. 15 is a schematic cross-sectional structural diagram of a chip package structure according to a third embodiment of the present application. Referring to FIGS. 14 and 15 , the chip package structure 300 and the manufacturing method thereof in this embodiment are substantially the same as the chip package structures 1 and 2 and the manufacturing method thereof in FIG. 2 and FIG. The die 111 and passive devices 113 are included.
  • Passive devices 113 may include resistive, inductive and capacitive elements, and their common feature is that they can work when there is a signal without adding power in the circuit.
  • the passive device 113 includes an electrical connection point, and the electrical connection point is located on the functional surface 113a of the component, so as to realize the electrical signal input/output of the passive device 113.
  • This embodiment does not limit the number and type of the bare chips 111 and the passive devices 113 in each to-be-packaged component 10 .
  • the chip packaging structure 300 in this embodiment realizes the connection between the chip and the external circuit of the passive device 113 through the edge connector 12 .

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Abstract

本申请提供了一种芯片封装结构及其制作方法，芯片封装结构中，边缘连接器和多个元器件封装在塑封层内，元器件包括电连接点，电连接点位于元器件的功能面，功能面覆盖有暴露电连接点的元器件保护层；电连接点、元器件保护层以及塑封层的正面上具有再布线层，以通过电连接点电连接各个元器件；塑封层内具有多个导电插塞，以将边缘连接器与再布线层引至塑封层的背面；塑封层的背面具有连接线，以连接各个导电插塞。再布线层结合连接线，通过两个面上的电路布局，相对于仅通过再布线层在一个面上的电路布局，可提高布线的密集程度，形成布线更复杂、体积更小的封装结构。此外，一次可实现多个芯片封装结构的制作，有利于批量化生产、降低成本。

Description

芯片封装结构及其制作方法 技术领域
本申请涉及芯片封装技术领域，尤其涉及一种芯片封装结构及其制作方法。
背景技术
近年来，随着电路集成技术的不断发展，电子产品越来越向小型化、智能化、高集成度、高性能以及高可靠性方向发展。封装技术不但影响产品的性能，而且还制约产品的小型化。
有鉴于此，本申请提供一种新的芯片封装结构及其制作方法，以实现封装结构的体积小、结构紧凑、集成度高的需求。
发明内容
本申请的申请目的是提供一种芯片封装结构及其制作方法，以实现封装结构的体积小、结构紧凑、集成度高的需求。
为实现上述目的，本申请的第一方面提供一种芯片封装结构，包括：
多个元器件，所述多个元器件包括电连接点，所述电连接点位于所述多个元器件的功能面；
元器件保护层，覆盖于所述多个元器件的功能面，所述元器件保护层暴露所述电连接点；
边缘连接器，所述边缘连接器包括耦合面；
塑封层，包覆所述边缘连接器与所述多个元器件，所述塑封层的正面暴露所述元器件保护层、所述电连接点以及所述边缘连接器的耦合面；
再布线层，位于所述电连接点、所述元器件保护层以及所述塑封层的正面上，所述再布线层用于通过所述电连接点电连接所述各个元器件；
多个导电插塞，位于所述塑封层内，所述多个导电插塞用于将所述边缘连接器与所述再布线层引至所述塑封层的背面；
连接线，位于所述塑封层的背面，以电连接所述各个导电插塞；
第一介电层，包埋所述再布线层，所述第一介电层暴露所述边缘连接器的耦合面；
第二介电层，包埋所述连接线。
本申请的第二方面提供一种芯片封装结构的制作方法，包括：
提供载板和多组待封装件，每组所述待封装件包括边缘连接器和多个元器件，所述多个元器件包括电连接点，所述电连接点位于所述多个元器件的功能面，所述功能面覆盖有元器件保护层，所述边缘连接器包括耦合面；将所述多组待封装件固定于所述载板的表面，其中，所述元器件保护层与所述边缘连接器的耦合面朝向所述载板；
在所述载板表面形成包埋所述各组待封装件的塑封层；去除所述载板，暴露所述元器件保护层、所述边缘连接器的耦合面以及所述塑封层的正面；
在所述元器件保护层、所述电连接点以及所述塑封层的正面上形成再布线层，以通过所述电连接点电连接组内的所述各个元器件；形成包埋所述边缘连接器的耦合面与所述再布线层的第一介电层；
经所述塑封层的背面在所述塑封层内形成多个导电插塞，以将所述边缘连接器与所述再布线层引至所述塑封层的背面；
在所述塑封层的背面形成连接线，以电连接组内的所述各个导电插塞；形成包埋所述连接线的第二介电层；
去除包埋所述边缘连接器的耦合面的第一介电层；
切割形成多个芯片封装结构，每个芯片封装结构中包含一组待封装件。
与现有技术相比，本申请的有益效果在于：
首先将边缘连接器和多个元器件封装在塑封层内，元器件包括电连接点，电连接点位于元器件的功能面，功能面覆盖有暴露电连接点的元器件保护层，边缘连接器包括耦合面；接着，一方面，在元器件保护层、电连接点以及塑封层的正面上形成再布线层，以通过电连接点电连接组内的各个元器件；另一方面经塑封层的背面在塑封层内形成多个导电插塞，以将边缘连接器与再布线层引至塑封层的背面；在塑封层的背面形成连接线，以电连接组内的各个导电插塞。再布线层结合连接线，通过两个面上的电路布局，相对于仅通过再布线层在一个面上的电路布局，可提高布线的密集程度，形成布线更复杂、体积更小的封装结构。芯片封装结构通过边缘连接器实现外部电路连接，使得芯片封装结构的性能可靠。此外，一次可实现多个芯片封装结构的制作，有利于批量化生产、 降低成本。
此外，由于元器件保护层的存在，可以在塑封工艺结束后直接在元器件保护层和塑封层表面形成再布线层，而不用在整个面板上形成介电层；在面板封装中，由于面板面积较大，在大面积面板上形成介电层工艺难度较大，介电层用料较多，元器件保护层的存在降低了封装的工艺难度以及成本。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
图1是本申请第一实施例的芯片封装结构的俯视结构示意图。
图2是本申请第一实施例的芯片封装结构的截面结构示意图。
图3是图1与图2中的芯片封装结构的制作方法的流程图。
图4至图12是图3中的流程对应的中间结构示意图。
图13是本申请第二实施例的芯片封装结构的截面结构示意图。
图14是本申请第三实施例的芯片封装结构的俯视结构示意图。
图15是本申请第三实施例的芯片封装结构的截面结构示意图。
为方便理解本申请，以下列出本申请中出现的所有附图标记：
芯片封装结构1、2、3                  元器件11
元器件的功能面11a                    元器件保护层110
边缘连接器12                         耦合面12a
塑封层13                             塑封层正面13a
塑封层背面13b                        再布线层14
导电插塞15                           连接线16
第一介电层17                         第二介电层18
裸片111                              裸片活性面111a
焊盘112                              金属块14a、14b
待封装件10                            载板2
开口110a                              第一支撑板3
第二支撑板4                           无源器件113
无源器件的功能面113a                  通孔13c
具体实施方式
为使本申请的上述目的、特征和优点能够更为明显易懂，下面结合附图对本申请的具体实施例做详细的说明。
图1是本申请第一实施例的芯片封装结构的俯视结构示意图。图2是本申请第一实施例的芯片封装结构的截面结构示意图。
参照图1与图2所示，芯片封装结构1包括：
多个元器件11，元器件11包括电连接点，电连接点位于元器件11的功能面11a；
元器件保护层110，覆盖于元器件11的功能面11a，元器件保护层110暴露电连接点；
边缘连接器12(Edge connector)，边缘连接器12包括耦合面12a；
塑封层13，包覆边缘连接器12与多个元器件11，塑封层13的正面13a暴露元器件保护层110与边缘连接器12的耦合面12a；
再布线层14，位于电连接点、元器件保护层110以及塑封层13的正面13a上，再布线层14用于通过电连接点电连接各个元器件11；
多个导电插塞15，位于塑封层13内，多个导电插塞15用于将边缘连接器12与再布线层14引至塑封层13的背面13b；
连接线16，位于塑封层13的背面13b，以电连接各个导电插塞15；
第一介电层17，包埋再布线层14，第一介电层17暴露边缘连接器12的耦合面12a；
第二介电层18，包埋连接线16。
参照图1与图2所示，本实施例中，元器件11包括裸片111。具体地，包括三个裸片111。其它实施例中，裸片111的数目还可以为两个或其它数目，本申请对此不加以限定。
各个裸片111的功能可以相同，也可以不同。裸片111可以为电力裸片(POWER DIE)、存储裸片(MEMORY DIE)、传感裸片(SENSOR DIE)、或射频裸片(RADIO FREQUENCE DIE)。
裸片活性面111a设置有焊盘112，裸片111内可以包含形成于半导体衬底上的多种器件，以及与各个器件电连接的电互连结构。焊盘112与电互连结构连接，用于将各个器件的电信号输入/输出。裸片活性面111a对应于元器件11的功能面11a，焊盘112对应于电连接点。
元器件保护层110为绝缘材料，具体可以为绝缘树脂材料，也可以为无机材料。绝缘树脂材料例如为聚酰亚胺、环氧树脂、ABF(Ajinomoto buildup film)、PBO(Polybenzoxazole)、有机聚合物膜、有机聚合物复合材料或者其它具有类似绝缘性能的有机材料等。无机材料例如为二氧化硅、氮化硅中的至少一种。
边缘连接器12，位于多个元器件11的一侧。边缘连接器12包括耦合面12a，用于实现芯片封装结构1的外部电路连接。
边缘连接器12的材料可以为铜等导电性优良的金属。边缘连接器12的耦合面12a上可以具有抗氧化层，以防止铜氧化，进而防止铜氧化导致的电连接性能变差。抗氧化层可以包括：a)锡层、或b)自下而上堆叠的镍层与金层、或c)自下而上堆叠的镍层、钯层与金层。
塑封层13的材料可以为环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、乙烯-醋酸乙烯共聚物或聚乙烯醇等。塑封层可以为各种聚合物、树脂或者树脂、聚合物复合材料，例如具有填充物的树脂，或者其它具有类似特性的材料。
塑封层13包括相对的正面13a与背面13b。本实施例中，塑封层13的正面13a暴露元器件保护层110、电连接点以及边缘连接器12的耦合面12a。
图2所示实施例中，再布线层14包括若干金属块14a，具有一层，金属块14a与焊盘112电连接。
多个导电插塞15中，部分数目导电插塞15与边缘连接器12接触，部分数目导电插塞15与再布线层14接触。与再布线层14接触的导电插塞15的数目及位置、以及连接线16的布局可根据预设电路布局而定。
第一介电层17与第二介电层18的材料可以为绝缘树脂材料或无机材料。绝缘树脂材料例如为聚酰亚胺、环氧树脂、ABF(Ajinomoto buildup film)、PBO(Polybenzoxazole)、有机聚合物膜、有机聚合物复合材料或者其它具有类似绝缘性能的有机材料等。无机材料例如为二氧化硅、氮化硅中的至少一种。相对于无机材料，绝缘树脂材的张应力较小，可防止芯片封装结构1表面出现翘曲。
参照图1与图2所示，本实施例中的芯片封装结构1，通过边缘连接器12实现了多个芯片的外部电路连接。
芯片封装结构1中，一方面，通过再布线层14在塑封层13的正面13a实现电路布局，另一方面，通过导电插塞15与连接线16实现在塑封层13的背面13b的电路布局。相对于仅通过再布线层14在一个面上的电路布局，本实施例的两面电路布局方式可提高布线的密集程度，形成布线更复杂、体积更小的芯片封装结构1。
此外，芯片封装结构1通过边缘连接器12实现外部电路连接，使得芯片封装结构1的性能可靠。
本申请一实施例提供了图1与图2中的芯片封装结构1的制作方法。图3是制作方法的流程图。图4至图12是图3中的流程对应的中间结构示意图。
首先，参照图3中的步骤S1、图4与图5所示，提供载板2和多组待封装件10，每组待封装件10包括边缘连接器12和多个元器件11，元器件11包括电连接点，电连接点位于元器件11的功能面11a，功能面11a覆盖有元器件保护层110，元器件保护层110内具有暴露电连接点的开口110a，边缘连接器12包括耦合面12a；将多组待封装件10固定于载板2的表面，其中，元器件保护层110与边缘连接器12的耦合面12a朝向载板2。其中，图4是载板和多组待封装件的俯视图；图5是沿着图4中的AA线的剖视图。
本实施例中，元器件11包括裸片111。具体地，如图2所示，包括三个裸片111。其它实施例中，裸片111的数目还可以为两个或其它数目，本申请对此不加以限定。
各个裸片111的功能可以相同，也可以不同。裸片111可以为电力裸片(POWER DIE)、存储裸片(MEMORY DIE)、传感裸片(SENSOR DIE)、或射频裸片(RADIO FREQUENCE DIE)。
裸片111为分割晶圆形成，晶圆包括晶圆活性面，晶圆活性面设置有焊盘112和保护焊盘112的绝缘层(未示出)。晶圆切割后形成裸片111，相应地，裸片111包括裸 片活性面111a，裸片活性面111a设置有焊盘112和保护焊盘112的绝缘层。在裸片活性面111a上施加元器件保护层110，元器件保护层110的施加过程可以为：在晶圆切割为裸片111之前在晶圆活性面上施加保元器件保护层110，切割具有元器件保护层110的晶圆形成具有元器件保护层110的裸片111，也可以为：在晶圆切割为裸片111之后，在裸片111上施加元器件保护层110。
相对于在多组待封装件10塑封完后，在塑封层上施加介电层，塑封前在裸片111上施加元器件保护层110可避免大面积制作介电层，一方面浪费材料，另一方面可避免塑封体翘曲。
裸片111中可以包含形成于半导体衬底上的多种器件，以及与各个器件电连接的电互连结构。裸片活性面111a上的焊盘112与电互连结构连接，用于将各个器件的电信号输入/输出。
裸片活性面111a对应于元器件11的功能面11a，焊盘112对应于电连接点。
元器件保护层110为绝缘材料，具体可以为绝缘树脂材料，也可以为无机材料。绝缘树脂材料例如为聚酰亚胺、环氧树脂、ABF(Ajinomoto buildup film)、PBO(Polybenzoxazole)、有机聚合物膜、有机聚合物复合材料或者其它具有类似绝缘性能的有机材料等。
绝缘树脂材料可通过a)层压工艺压合在焊盘112以及相邻焊盘112之间的绝缘层上，或b)先涂布或印刷在焊盘112以及相邻焊盘112之间的绝缘层上、后固化，或c)通过注塑工艺固化在焊盘112以及相邻焊盘112之间的绝缘层上。
元器件保护层110的材料为二氧化硅或氮化硅等无机材料时，可通过沉积工艺形成在焊盘112以及相邻焊盘112之间的绝缘层上。
元器件保护层110可以包括一层或多层。
参照图5所示，元器件保护层110中具有暴露焊盘112的开口110a。一些实施例中，裸片111上的焊盘112可以包埋在元器件保护层110内，开口110a在再布线层14(参见图8所示)形成工艺前制作。
图5所示实施例中，一个开口110a暴露一个焊盘112的部分区域。其它实施例中，一个开口110a也可以暴露两个或两个以上焊盘112的部分区域。
晶圆在切割前可以自背面减薄厚度，以降低裸片111的厚度。
载板2为硬质板件，可以包括塑料板、玻璃板、陶瓷板或金属板等。
裸片111与载板2之间、边缘连接器12与载板2之间都可以设置粘结层，以此实现两者之间的固定。具体地，可以在载板2表面涂布一整面粘结层，将多个裸片111与多个边缘连接器12置于该粘结层上。粘结层可以采用易剥离的材料，以便将载板2剥离下来，例如可以采用通过加热能够使其失去粘性的热分离材料或通过紫外照射能够使其失去粘性的UV分离材料。
边缘连接器12的高度小于裸片111的厚度。边缘连接器12的高度是指：在垂直耦合面12a的方向上边缘连接器12的最大尺寸。
一些实施例中，边缘连接器12为预成件，直接粘结在载板2的表面。另一些实施例中，也可以先将金属片粘结在载板2上，利用蚀刻的方式在载板2的预定位置处蚀刻形成边缘连接器12。
边缘连接器12与多个裸片111在载板2上的布置无先后顺序，也可以同时布置。
多个边缘连接器12或多个裸片111可以先布置在一转移载板，再转移至载板2上。具体地，可以在转移载板表面涂布一整面粘结层，将多个边缘连接器12或多个裸片111置于该粘结层上。粘结层可以采用易剥离的材料，以便将多个边缘连接器12、多个裸片111从转移载板上剥离开来，例如可以采用通过加热能够使其失去粘性的热分离材料或通过紫外照射能够使其失去粘性的UV分离材料。
一组待封装件10位于载板2表面的一块区域，便于后续切割。载板2表面可以固定多组待封装件10，以同时制作多个芯片封装结构1，有利于批量化生产、降低成本。
接着，参照图3中的步骤S2、图4与图6所示，在载板2表面形成包埋各组待封装件10的塑封层13；参照图7所示，去除载板2，暴露元器件保护层110、电连接点、边缘连接器12的耦合面12a以及塑封层13的正面13a。
塑封层13的材料可以为环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、乙烯-醋酸乙烯共聚物或聚乙烯醇等。塑封层可以为各种聚合物、树脂或者树脂、聚合物复合材料，例如具有填充物的树脂，或者其它具有类似特性的材料。对应地，封装可以采用在各元器件11以及各个边缘连接器12之间填充液态塑封料、后经塑封模具高温固化进行。一些实施例中，塑封层13也可以采用热压成型、传递成型等塑性材料成型的方式成型。
塑封层13可以包括相对的正面13a与背面13b。
塑封层13可采用机械研磨自背面13b减薄，例如采用砂轮研磨，以减少体积。
在形成塑封层13以及研磨塑封层13过程中，元器件保护层110可以防止焊盘112以及裸片111内的电互连结构受损坏。
本步骤形成了待封装件10的塑封体。
继续参照图7所示，去除载板2后，设置于各个元器件11的元器件保护层110与边缘连接器12的耦合面12a处于同一平面。此外，还可以在塑封层13的背面13b设置一第一支撑板3。该第一支撑板3在后续工艺中，可对包埋在塑封层13内的各个元器件11进行支撑。
第一支撑板3为硬质板件，可以包括玻璃板、陶瓷板、金属板等。
再接着，参照图3中的步骤S3与图8所示，在元器件保护层110、电连接点以及塑封层13的正面13a上形成再布线层14，以通过电连接点电连接各个元器件11；形成包埋边缘连接器12的耦合面12a与再布线层14的第一介电层17。
本实施例中，形成再布线层14包括如下步骤S31～S34。
步骤S31：在设置于各个元器件11上的元器件保护层110、电连接点、各个边缘连接器12的耦合面12a以及塑封层13的正面13a上形成光刻胶层。
本步骤S31中，一个可选方案中，形成的光刻胶层可为感光膜。感光膜可以从胶带上撕下，贴敷在设置于各个元器件11的元器件保护层110、电连接点、各个边缘连接器12的耦合面12a以及塑封层13的正面13a上。其它可选方案中，光刻胶层也可以采用先涂布液体光刻胶，后加热固化形成。
步骤S32：曝光显影光刻胶层，保留第一预定区域的光刻胶层，第一预定区域与待形成的再布线层14的金属块14a所在区域互补。
本步骤S32对光刻胶层进行了图案化。其它可选方案中，也可以使用其它易去除的牺牲材料代替光刻胶层。
步骤S33：在第一预定区域的互补区域填充金属层以形成再布线层14的金属块14a。
若干金属块14a的位置使得能电连接一个或多个元器件11的焊盘112。
本步骤S33可以采用电镀工艺完成。电镀铜或铝的工艺较为成熟。
具体地，步骤S31形成光刻胶层之前，可以先通过物理气相沉积法或化学气相沉积法在设置于各个元器件11的元器件保护层110、电连接点、边缘连接器12的耦合面12a以及塑封层13的正面13a上形成一层籽晶层(Seed Layer)。籽晶层可以作为电镀铜或铝的供电层。
电镀可以包括电解电镀或无极电镀。电解电镀是将待电镀件作为阴极，对电解液进行电解，从而在待电镀件上形成一层金属。无极电镀是将溶液中的金属离子还原析出在待电镀件上形成金属层的方法。一些实施例中，还可以采用先溅射、后刻蚀的方法形成金属块14a。
步骤S34：灰化去除第一预定区域剩余的光刻胶层。
灰化完后，通过干法刻蚀或湿法刻蚀去除第一预定区域的籽晶层。
再布线层14的金属块14a可以通过抛光工艺，例如化学机械研磨法实现上表面平整。
需要说明的是，本步骤S3中的再布线层14的金属块14a根据设计需要进行布置，不同组待封装件10内的各个元器件11上的再布线层14的分布可以相同，也可以不同。
形成第一介电层17步骤中，为防止工艺造成塑封层13刮擦，可以在塑封层13的正面13a也形成第一介电层17。
第一介电层17为绝缘材料，具体可以为绝缘树脂材料，也可以为无机材料。绝缘树脂材料例如为聚酰亚胺、环氧树脂、ABF(Ajinomoto buildup film)、PBO(Polybenzoxazole)、有机聚合物膜、有机聚合物复合材料或者其它具有类似绝缘性能的有机材料等。
绝缘树脂材料可通过a)层压工艺压合在边缘连接器12的耦合面12a、再布线层14以及塑封层13的正面13a上，或b)先涂布在边缘连接器12的耦合面12a、再布线层14以及塑封层13的正面13a上、后固化，或c)通过注塑工艺固化在边缘连接器12的耦合面12a、再布线层14以及塑封层13的正面13a上。
第一介电层17的材料为二氧化硅或氮化硅等无机材料时，可通过沉积工艺形成在边缘连接器12的耦合面12a、再布线层14以及塑封层13的正面13a上。
相对于无机材料，绝缘树脂材料的张应力较小，可防止第一介电层17大面积形成时引发塑封体出现翘曲。
第一介电层17可以包括一层或多层。
第一介电层17形成后，参照图9所示，可以去除第一支撑板3，在第一介电层17 上设置第二支撑板4。
第一支撑板3的去除方式可以为激光剥离、UV照射等去除方式。
第二支撑板4在后续形成导电插塞15、和/或形成连接线16、和/或形成第二介电层18工序中，可起支撑作用。
第二支撑板4为硬质板件，可以包括玻璃板、陶瓷板、金属板等。
之后，参照图3中的步骤S4与图10所示，经塑封层13的背面13b在塑封层13内形成多个导电插塞15，以将边缘连接器12与再布线层14引至塑封层13的背面13b。
本步骤S4可以包括如下步骤S41～S42。
步骤S41：经塑封层13的背面13b在塑封层13内形成多个通孔13c，部分数目的通孔13c暴露边缘连接器12，部分数目的通孔13c暴露再布线层14。
步骤S42：在通孔13c内填入导电材料，形成导电插塞15。
导电材料可以为铜、铝等。填入导电材料的方法可以参照再布线层14的金属块14a的形成方法。
通孔13c外的导电材料可以采用化学机械研磨法去除。
与再布线层14接触的导电插塞15的数目及位置可根据预设电路布局而定。
接着，参照图3中的步骤S5与图11所示，在塑封层13的背面13b形成连接线16，以连接各个导电插塞15；形成包埋连接线16的第二介电层18。
连接线16的形成方法可以参照再布线层14中的金属块14a的形成方法。连接线16的布局可根据预定布局而定。
连接线16的形成也可与步骤S42在同一工序中进行，可省略平坦化去除通孔13c外的导电材料的工序。
第二介电层18的材料及形成方法可以参照第一介电层17的材料及形成方法。
形成第二介电层18步骤中，为防止工艺造成塑封层13刮擦，可以在塑封层13的背面13b也形成第二介电层18。
第二介电层18可以包括一层或多层。
再接着，参照图3中的步骤S6与图12所示，去除包埋边缘连接器12的耦合面12a的第一介电层17。
当第一介电层17为激光反应性材料，采用激光图形化的方式去除。当第一介电层17为可干法刻蚀或湿法刻蚀去除材料时，采用干法刻蚀或湿法刻蚀去除。当第一介电层17为光敏材料时，采用先曝光后显影的方式去除。
暴露出边缘连接器12的耦合面12a后，还可以在耦合面12a上形成抗氧化层。
抗氧化层可以包括：a)锡层、或b)自下而上堆叠的镍层与金层、或c)自下而上堆叠的镍层、钯层与金层。抗氧化层可以采用电镀工艺形成。边缘连接器12的材料可以为铜，上述抗氧化层可以防止铜氧化，进而防止铜氧化导致的电连接性能变差。
一些实施例中，也可以在步骤S1提供的边缘连接器12中，上述抗氧化层已形成。
包埋边缘连接器12的耦合面12a的第一介电层17去除后，参照图12所示，可以去除第二支撑板4。
第二支撑板4的去除方式可以为激光剥离、UV照射等去除方式。
之后，参照图3中的步骤S7、图12与图2所示，切割形成多个芯片封装结构1，每个芯片封装结构1中包含一组待封装件10。
经过上述各步骤，一组待封装件10中的各个元器件11可通过边缘连接器12实现外部电路连接，使得芯片封装结构1的性能可靠。
图13是本申请第二实施例的芯片封装结构的截面结构示意图。参照图13所示，本实施例中的芯片封装结构200及其制作方法与图1中的芯片封装结构1及其制作方法大致相同，区别仅在于：再布线层14包括两层。
第二再布线层的金属块14b与第一再布线层的金属块14a选择性电互连，可实现更复杂的电路布局。
一些实施例中，再布线层14还可以包括三层及其以上。
图14是本申请第三实施例的芯片封装结构的俯视结构示意图。图15是本申请第三实施例的芯片封装结构的截面结构示意图。参照图14与图15所示，本实施例中的芯片封装结构300及其制作方法与图2、图13中的芯片封装结构1、2及其制作方法大致相同，区别仅在于：元器件11包括裸片111与无源器件113。
无源器件113可以包括电阻类、电感类和电容类元件，它们的共同特点是在电路中无需加电源即可在有信号时工作。无源器件113包括电连接点，电连接点位于元器 件的功能面113a，以实现无源器件113的电信号接入/接出。
本实施例不限定各个待封装件10中的裸片111与无源器件113的数目及种类。
本实施例中的芯片封装结构300，通过边缘连接器12实现了芯片与无源器件113的外部电路连接。
虽然本申请披露如上，但本申请并非限定于此。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各种更正与修改，因此本申请的保护范围应当以权利要求所限定的范围为准。

Claims (16)

  1. 一种芯片封装结构，其特征在于，包括：
    多个元器件，所述多个元器件包括电连接点，所述电连接点位于所述多个元器件的功能面；
    元器件保护层，覆盖于所述多个元器件的功能面，所述元器件保护层暴露所述电连接点；
    边缘连接器，所述边缘连接器包括耦合面；
    塑封层，包覆所述边缘连接器与所述多个元器件，所述塑封层的正面暴露所述元器件保护层、所述电连接点以及所述边缘连接器的耦合面；
    再布线层，位于所述电连接点、所述元器件保护层以及所述塑封层的正面上，所述再布线层用于通过所述电连接点电连接所述各个元器件；
    多个导电插塞，位于所述塑封层内，所述多个导电插塞用于将所述边缘连接器与所述再布线层引至所述塑封层的背面；
    连接线，位于所述塑封层的背面，以电连接所述各个导电插塞；
    第一介电层，包埋所述再布线层，所述第一介电层暴露所述边缘连接器的耦合面；
    第二介电层，包埋所述连接线。
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述多个元器件包括裸片，或所述多个元器件包括裸片与无源器件；所述裸片的电连接点为焊盘。
  3. 根据权利要求1或2所述的芯片封装结构，其特征在于，所述元器件保护层的材料为绝缘树脂材料或无机材料。
  4. 根据权利要求1至3任一所述的芯片封装结构，其特征在于，所述第一介电层的材料为绝缘树脂材料或无机材料；和/或所述第二介电层的材料为绝缘树脂材料或无机材料。
  5. 根据权利要求1至4任一所述的芯片封装结构，其特征在于，所述再布线层包括两层或两层以上。
  6. 根据权利要求1至5任一所述的芯片封装结构，其特征在于，所述耦合面包括抗氧化层。
  7. 根据权利要求2所述的芯片封装结构，其特征在于，所述再布线层包括至少一个金属块，所述至少一个金属块与所述焊盘电连接。
  8. 一种芯片封装结构的制作方法，其特征在于，包括：
    提供载板和多组待封装件，每组所述待封装件包括边缘连接器和多个元器件，所述 多个元器件包括电连接点，所述电连接点位于所述多个元器件的功能面，所述功能面覆盖有元器件保护层，所述边缘连接器包括耦合面；将所述多组待封装件固定于所述载板的表面，其中，所述元器件保护层与所述边缘连接器的耦合面朝向所述载板；
    在所述载板表面形成包埋所述各组待封装件的塑封层；
    去除所述载板，暴露所述元器件保护层、所述边缘连接器的耦合面以及所述塑封层的正面；
    在所述元器件保护层、所述电连接点以及所述塑封层的正面上形成再布线层，以通过所述电连接点电连接组内的所述各个元器件；
    形成包埋所述边缘连接器的耦合面与所述再布线层的第一介电层；
    经所述塑封层的背面在所述塑封层内形成多个导电插塞，以将所述边缘连接器与所述再布线层引至所述塑封层的背面；
    在所述塑封层的背面形成连接线，以电连接所述各个导电插塞；
    形成包埋所述连接线的第二介电层；
    去除包埋所述边缘连接器的耦合面的第一介电层；
    切割形成多个芯片封装结构，每个芯片封装结构中包含一组待封装件。
  9. 根据权利要求8所述的芯片封装结构的制作方法，其特征在于，所述元器件保护层内具有暴露所述电连接点的开口，所述方法还包括：去除所述载板后，暴露所述电连接点。
  10. 根据权利要求8或9所述的芯片封装结构的制作方法，其特征在于，经所述塑封层的背面在所述塑封层内形成多个导电插塞，以将所述边缘连接器与所述再布线层引至所述塑封层的背面，包括：
    经所述塑封层的背面在所述塑封层内形成多个通孔，部分数目的通孔暴露所述边缘连接器，部分数目的通孔暴露所述再布线层；
    在所述多个通孔中填入导电材料，形成所述多个导电插塞。
  11. 根据权利要求8至10任一所述的芯片封装结构的制作方法，所述方法还包括：在所述耦合面上形成抗氧化层。
  12. 根据权利要求8至11任一所述的芯片封装结构的制作方法，其特征在于，所述元器件包括裸片，或所述元器件包括裸片与无源器件；所述裸片的电连接点为焊盘。
  13. 根据权利要求8至12任一所述的芯片封装结构的制作方法，其特征在于，所述元器件保护层的材料为绝缘树脂材料或无机材料。
  14. 根据权利要求8至13任一所述的芯片封装结构的制作方法，其特征在于，所 述第一介电层的材料为绝缘树脂材料或无机材料；和/或所述第二介电层的材料为绝缘树脂材料或无机材料。
  15. 根据权利要求8至13任一所述的芯片封装结构的制作方法，其特征在于，所述第一介电层的材料为激光反应性材料，采用激光图形化的方式去除所述边缘连接器耦合面的所述第一介电层。
  16. 根据权利要求8至15任一所述的芯片封装结构的制作方法，其特征在于，所述再布线层包括两层或两层以上。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108962773A (zh) * 2018-07-26 2018-12-07 华进半导体封装先导技术研发中心有限公司 扇出型封装结构及其制造方法
CN110729256A (zh) * 2019-03-11 2020-01-24 Pep创新私人有限公司 芯片封装方法及芯片结构
CN111106090A (zh) * 2020-01-06 2020-05-05 广东佛智芯微电子技术研究有限公司 基于刚性框架的tmv扇出型封装结构及其制备方法
CN111128763A (zh) * 2019-12-06 2020-05-08 上海先方半导体有限公司 一种芯片封装结构的制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108962773A (zh) * 2018-07-26 2018-12-07 华进半导体封装先导技术研发中心有限公司 扇出型封装结构及其制造方法
CN110729256A (zh) * 2019-03-11 2020-01-24 Pep创新私人有限公司 芯片封装方法及芯片结构
CN111128763A (zh) * 2019-12-06 2020-05-08 上海先方半导体有限公司 一种芯片封装结构的制作方法
CN111106090A (zh) * 2020-01-06 2020-05-05 广东佛智芯微电子技术研究有限公司 基于刚性框架的tmv扇出型封装结构及其制备方法

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