WO2022134940A1 - 裸片及其制作方法、芯片封装结构及其制作方法 - Google Patents

裸片及其制作方法、芯片封装结构及其制作方法 Download PDF

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WO2022134940A1
WO2022134940A1 PCT/CN2021/130874 CN2021130874W WO2022134940A1 WO 2022134940 A1 WO2022134940 A1 WO 2022134940A1 CN 2021130874 W CN2021130874 W CN 2021130874W WO 2022134940 A1 WO2022134940 A1 WO 2022134940A1
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layer
copper
opening
manufacturing
aluminum
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PCT/CN2021/130874
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English (en)
French (fr)
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杨威源
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矽磐微电子(重庆)有限公司
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Priority to US18/020,349 priority Critical patent/US20230268299A1/en
Publication of WO2022134940A1 publication Critical patent/WO2022134940A1/zh

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
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    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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Definitions

  • the present disclosure relates to the technical field of chip packaging, and in particular, to a bare chip and a manufacturing method thereof, a chip packaging structure and a manufacturing method thereof.
  • the present disclosure provides a new bare chip and a manufacturing method thereof, a chip packaging structure and a manufacturing method thereof, so as to improve the yield of the packaging structure.
  • the present disclosure provides a bare chip and a manufacturing method thereof, a chip packaging structure and a manufacturing method thereof, so as to improve the yield of the packaging structure.
  • a first aspect of the present disclosure provides a bare chip, comprising: an aluminum pad and a passivation layer, which are located on the active surface of the bare chip, the passivation layer has a first opening, the first opening is An opening exposes a partial area of the aluminum pad; a copper layer is located on the aluminum pad and covers a partial area of the aluminum pad, and the boundary of the copper layer is connected to the blunt surface located on the boundary of the first opening. There is a space between the layers.
  • a second aspect of the present disclosure provides a method for fabricating a bare chip, including: providing a wafer, the wafer includes a passivation layer and a plurality of aluminum pads, the passivation layer and the plurality of aluminum pads are located in On the active surface of the wafer, the passivation layer has a plurality of first openings, and the first openings expose a partial area of the aluminum pads; on the passivation layer and the plurality of aluminum pads forming a patterned mask layer, the patterned mask layer has a second opening, the second opening exposes a partial area of the aluminum pad, and the patterned mask layer completely covers the passivation layer; removing the oxide layer on the aluminum pad, forming a copper layer in the second opening; removing the patterned mask layer; cutting the wafer to form a plurality of bare chips.
  • a third aspect of the present disclosure provides a chip packaging structure, comprising: the bare chip described in the first aspect; a plastic packaging layer covering the bare chip; pins located on the plastic packaging layer, and the pins are filled with A through hole in the plastic encapsulation layer is connected to the copper layer.
  • a fourth aspect of the present disclosure provides a method for fabricating a chip package structure, including: providing a bare chip fabricated according to the fabrication method described in the second aspect, forming a plastic encapsulation layer covering the bare chip; using a laser drilling method A through hole is formed in the plastic packaging layer to expose the copper layer; pins are formed on the plastic packaging layer and the copper layer; and a chip packaging structure is formed by cutting.
  • a copper layer is formed on a partial area of the aluminum pad, and there is a distance between the boundary of the copper layer and the passivation layer, so that on the one hand, the copper layer is completely located in the opening of the passivation layer, and the partial area of the copper layer is located in the passivation layer
  • the solution on the passivation layer can prevent the copper layer from being peeled off from the passivation layer due to the poor bonding performance of the copper layer and the passivation layer;
  • the copper layer can prevent the surface oxidation of the aluminum pad and reduce the resistance of the aluminum pad;
  • the copper layer can avoid excessive laser energy from penetrating the aluminum pads, thereby improving the process window and the yield of the packaging structure.
  • FIG. 1 is a flowchart of a method for fabricating a bare chip according to a first embodiment of the present disclosure
  • FIG. 2 to 6 are schematic diagrams of intermediate structures corresponding to the process in FIG. 1;
  • FIG. 7 is a schematic cross-sectional structure diagram of a die according to the first embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a method for fabricating a chip package structure according to a second embodiment of the present disclosure
  • 9 to 13 are schematic diagrams of intermediate structures corresponding to the process in FIG. 8;
  • FIG. 14 is a schematic cross-sectional structural diagram of a chip package structure according to a second embodiment of the present disclosure.
  • FIG. 15 is a schematic cross-sectional structural diagram of a chip package structure according to a third embodiment of the present disclosure.
  • FIG. 16 is a schematic cross-sectional structure diagram of a comparison chip package structure.
  • the first opening 111a The backside 11b of the wafer
  • the second opening 20a The patterned mask layer 20
  • Chip package structure 3 4 Dielectric layer 24
  • FIG. 1 is a flowchart of a method for fabricating a die according to a first embodiment of the present disclosure.
  • 2 to 6 are schematic diagrams of intermediate structures corresponding to the process in FIG. 1 ;
  • FIG. 7 is a schematic diagram of a cross-sectional structure of a die according to the first embodiment of the present disclosure.
  • FIG. 2 is a top view of the wafer
  • FIG. 3 is a cross-sectional view along the line AA in FIG. 2 .
  • the wafer 11 is provided. Including a passivation layer 111 and a plurality of aluminum pads 112, the passivation layer 111 and the plurality of aluminum pads 112 are located on the active surface 11a of the wafer 11, the passivation layer 111 has a plurality of first openings 111a, the first openings 111a Parts of the aluminum pads 112 are exposed.
  • the wafer 11 may include a plurality of regions arranged in an array, and each region may include a variety of devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device.
  • the aluminum pads 112 are connected to the electrical interconnect structure for input/output of electrical signals of the various devices.
  • the thickness of the aluminum pads 112 may be less than 3 ⁇ m, for example, may be less than 1 ⁇ m.
  • the material of the passivation layer 111 may be a dense material such as silicon nitride, so as to isolate external water vapor, oxygen, etc. from entering the device on the semiconductor substrate.
  • the first opening 111a in the passivation layer 111 may be formed by a dry etching method or a wet etching method.
  • a patterned mask layer 20 is formed on the passivation layer 111 and the plurality of aluminum pads 112, and the patterned mask layer 20 has a second opening 20a.
  • the second opening 20a exposes a partial area of the aluminum pad 112 , and the patterned mask layer 20 completely covers the passivation layer 111 .
  • the material of the patterned mask layer 20 may be photoresist.
  • the formed photoresist layer may be a photosensitive film.
  • the photosensitive film can be peeled off from the tape and attached to the passivation layer 111 and the plurality of aluminum pads 112 .
  • the photoresist layer can also be formed by first coating a liquid photoresist and then heating and curing.
  • the material of the patterned mask layer 20 may also be a dielectric material, which is different from the material of the passivation layer 111 .
  • the material of the passivation layer 111 is silicon nitride
  • the material of the patterned mask layer 20 can be silicon dioxide.
  • the passivation layer 111 is bombarded with oxygen plasma or argon plasma to enhance the bonding force between the passivation layer 111 and the patterned mask layer 20 .
  • the patterned mask layer 20 completely covers the passivation layer 111 means that the size of the second opening 20a is smaller than the size of the first opening 111a, and the distance between the boundary of the second opening 20a and the boundary of the first opening 111a is L.
  • the range of the spacing L is: 3 ⁇ m to 10 ⁇ m.
  • step S3 in FIG. 1 , FIG. 4 and FIG. 5 the oxide layer on the aluminum pad 112 is removed, and the copper layer 113 is formed in the second opening 20 a ; referring to FIG. 6 , the patterned mask is removed.
  • Membrane layer 20 is
  • the aluminum pad 112 is exposed to the environment and may be oxidized by oxygen in the environment to form an aluminum oxide layer.
  • the resistance of the aluminum oxide layer is much greater than that of aluminum, thus increasing the resistance of the aluminum pad 112 .
  • Removing the oxide layer on the aluminum pads 112 can avoid increasing the resistance of the aluminum pads 112 .
  • the oxide layer on the aluminum pad 112 can be removed by a micro-etching method.
  • the micro-etching method can use an acidic etching solution to react with the oxide layer to remove the oxide layer.
  • the acidic solution is, for example, sulfuric acid, hydrochloric acid, or nitric acid.
  • the copper layer 113 may be formed by an electroless plating method.
  • Electroless plating method is to reduce and precipitate metal ions in the solution to form a metal layer on the part to be plated.
  • the wafer 11 after the oxide layer is removed is placed in a copper ion solution, aluminum and copper ions undergo a substitution reaction, and a copper layer 113 is deposited on the aluminum pad 112 .
  • the advantage of the solution b) is at least that: the zinc layer can repair the rough surface of the aluminum pad 112, so that the copper layer 113 with higher flatness can be formed.
  • the upper surface of the copper layer 113 may be higher or lower than the upper surface of the passivation layer 111 . Considering the laser energy in the subsequent laser drilling process, the thickness of the copper layer 113 is preferably thicker.
  • the copper layer 113 is completely located in the opening 111a of the passivation layer 111, and compared with the solution in which a part of the copper layer 113 is located on the passivation layer 111, the poor bonding performance of the copper layer 113 and the passivation layer 111 can be avoided, and the copper layer 113 will The passivation layer 111 is peeled off.
  • the patterned mask layer 20 can be removed by a targeted method, for example, the photoresist can be removed by ashing, the photosensitive film can be removed by an acid solution, and the silicon dioxide can be removed by hydrofluoric acid.
  • step S4 in FIG. 1 the wafer 11 is diced to form a plurality of bare chips 1 .
  • the wafer 11 may be thinned from the backside 11 b of the wafer before being cut to reduce the thickness of the die 1 .
  • the bare chip 1 in this embodiment includes:
  • the aluminum pad 112 and the passivation layer 111 are located on the active surface 1a of the die 1, and the passivation layer 111 has a first opening 111a, and the first opening 111a exposes a partial area of the aluminum pad 112;
  • the copper layer 113 is located on the aluminum pad 112 and covers a part of the aluminum pad 112, and the distance between the boundary of the copper layer 113 and the passivation layer 111 located at the boundary of the first opening 111a is L.
  • the range of the spacing L is: 3 ⁇ m to 10 ⁇ m.
  • FIG. 8 is a flowchart of a method for fabricating a chip package structure according to a second embodiment of the present disclosure.
  • 9 to 13 are schematic diagrams of intermediate structures corresponding to the process in FIG. 8 ;
  • FIG. 14 is a schematic cross-sectional structure diagram of a chip package structure according to a second embodiment of the present disclosure.
  • step S5 in FIG. 8 , FIG. 9 and FIG. 10 the die 1 fabricated by referring to steps S1 to S4 in FIG. 1 is provided to form a plastic encapsulation layer 21 covering the die 1 .
  • each die 1 may be provided in this step.
  • the functions of each die 1 may be the same or different.
  • the die 1 may be a power die (POWER DIE), a memory die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE), etc. This embodiment does not limit the size of the die 1. Function.
  • the step of forming the plastic encapsulation layer 21 covering the die 1 may include: referring to FIG. 9 , fixing the plurality of dies 1 on the carrier 2 with the active surface 1 a of the die 1 away from the carrier 2 ; The surface of 2 forms a plastic encapsulation layer 21 that embeds each die 1 .
  • the carrier plate 2 is a rigid plate, which may include a glass plate, a ceramic plate, a metal plate, and the like.
  • An adhesive layer can be arranged between the bare chip 1 and the carrier board 2, so as to realize the fixation between the two. Specifically, a whole-surface adhesive layer can be coated on the surface of the carrier board 2, and a plurality of dies 1 can be placed on the adhesive layer.
  • the adhesive layer can be made of an easily peelable material so that the carrier plate 2 can be peeled off, for example, a thermal separation material that can lose its adhesiveness by heating or a UV separation material that can be made to lose its adhesiveness by ultraviolet irradiation.
  • the material of the plastic sealing layer 21 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate Diol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol, etc.
  • the plastic sealing layer 21 can also be various polymers, resins or polymer composite materials, such as resins with fillers or glass fibers, or other materials with similar properties.
  • the encapsulation can be performed by filling the liquid molding compound between the respective bare chips 1 , and then curing at a high temperature by a plastic encapsulation mold.
  • the plastic encapsulation layer 21 may also be formed by means of plastic material forming such as thermocompression forming and transfer forming.
  • the plastic encapsulation layer 21 may include opposite front surfaces 21a and back surfaces 21b.
  • the plastic encapsulation layer 21 can be thinned from the back surface 21 b, and mechanical grinding, such as grinding with a grinding wheel, can be used to reduce the thickness of the chip package structure.
  • through holes 211 are formed in the plastic sealing layer 21 by using a laser drilling method to expose the copper layer 113 .
  • a laser with a higher energy is generally selected.
  • the aluminum bonding pad 112 will be broken down, resulting in poor electrical connection reliability of the aluminum bonding pad 112 .
  • a copper layer 113 is disposed on the aluminum pad 112, and the copper layer 113 can prevent the laser energy from penetrating the aluminum pad 112 too much; on the other hand, the copper layer 113 can also prevent the surface of the aluminum pad 112 from being oxidized. Oxidation increases the resistance of the aluminum pads 112 .
  • the thickness of the copper layer 113 is preferably thicker to ensure that the aluminum pad 112 will not be broken down during the laser drilling process.
  • the size of the bottom of the via hole 211 is smaller than that of the copper layer 113 .
  • the bottom dimension of the through hole 211 is smaller than the top dimension.
  • the size of the bottom of the through hole 211 is generally greater than 75% of the size of the top, and generally not less than 60% of the size of the top.
  • leads 22 are formed on the plastic sealing layer 21 and the copper layer 113 .
  • forming the pins 22 includes the following steps S71 to S74.
  • Step S71 forming a photoresist layer on the copper layer 113 and the back surface 21 b of the plastic sealing layer 21 .
  • the formed photoresist layer may be a photosensitive film.
  • the photosensitive film can be peeled off from the tape and attached to the copper layer 113 and the back surface 21 b of the plastic sealing layer 21 .
  • the photoresist layer can also be formed by first coating a liquid photoresist and then heating and curing.
  • Step S72 Expose and develop the photoresist layer, retain the photoresist layer in the first predetermined area, and the first predetermined area is complementary to the area where the pins 22 to be formed are located.
  • the photoresist layer is patterned.
  • other easily removable sacrificial materials can also be used in place of the photoresist layer.
  • Step S73 filling a metal layer in the complementary region of the first predetermined region to form the lead 22 .
  • This step S73 may be completed by an electroplating process.
  • electroplating copper or aluminum.
  • a seed layer may be formed on the copper layer 113 and the back surface 21b of the plastic sealing layer 21 by physical vapor deposition or chemical vapor deposition.
  • the seed layer can be used as a power supply layer for electroplating copper or aluminum.
  • the electroplating method may include an electrolytic plating method or an electroless plating method.
  • the electrolytic plating method uses the part to be plated as a cathode, and electrolyzes the electrolyte to form a layer of metal on the part to be plated.
  • Electroless plating method is to reduce and precipitate metal ions in the solution to form a metal layer on the part to be plated.
  • the lead 22 may also be formed by sputtering first and then etching.
  • Step S74 removing the remaining photoresist layer in the first predetermined region by ashing.
  • the seed layer in the first predetermined region is removed by dry etching or wet etching.
  • step S8 in FIG. 8 the chip package structure 3 is formed by cutting.
  • the carrier plate 2 is removed.
  • the removal method of the carrier plate 2 may be laser lift-off, UV irradiation or the like.
  • each chip package structure 3 includes one die 1 after dicing.
  • the chip packaging structure 3 in this embodiment includes:
  • the pins 22 are located on the plastic packaging layer 21 , and the pins 22 fill the through holes 211 in the plastic packaging layer 21 to be connected to the copper layer 113 .
  • FIG. 15 is a schematic cross-sectional structural diagram of a chip package structure according to a third embodiment of the present disclosure.
  • the chip package structure 4 in this embodiment is substantially the same as the chip package structure 3 in FIG. 14 , the only difference being that the chip package structure 4 shown in FIG. 23 is located on the plastic encapsulation layer 21 , and the redistribution layer 23 fills the through holes 211 in the plastic encapsulation layer 21 to be electrically connected with the copper layer 113 ; the pins 22 are located on the redistribution layer 23 .
  • the redistribution layer 23 can be selectively electrically interconnected with a part of the number of aluminum pads 112 through the copper layer 113, and a more complicated circuit layout can be realized.
  • the redistribution layer 23 and the pins 22 may be covered with a dielectric layer 24 , and the pins 22 are exposed from the dielectric layer 24 .
  • the redistribution layer 23 may also include two or more layers.
  • FIG. 16 is a schematic cross-sectional structure diagram of a comparison chip package structure. It should be noted that, when the bare chip 1 in the chip package structure 4 includes a high-frequency device, the current has a skin effect at a high frequency. If the upper surface of the aluminum bonding pad 112 is a rough surface with unevenness, and the copper layer 113 is directly formed on the aluminum bonding pad 112, the upper surface of the copper layer 113 is also a rough surface with unevenness. Further, the rewiring layer 23 corresponds to The area of the copper layer 113 is also a rough surface with unevenness. Therefore, the current I flowing through the above-mentioned rough surface of the redistribution layer 23 increases power consumption.
  • the upper surface of the copper layer 113 is also a flat surface.
  • the rewiring layer 23 corresponds to the copper layer 113 area is also a flat surface. Therefore, the current I flowing through the above-mentioned flat surface of the redistribution layer 23 reduces power consumption.
  • the above repair method can refer to the b) scheme in the electroless electroplating process, and use the zinc layer to repair.
  • the difference between this embodiment and the manufacturing method of the chip packaging structure in FIG. 8 is only that: before the step of forming the lead 22 in step S7, the rewiring layer 23 is formed on the plastic sealing layer 21 and the copper layer 113; The pins 22 are formed on the rewiring layer 23 .
  • the process of forming the redistribution layer 23 may refer to the process of forming the pin 22 .

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Abstract

本公开提供了一种裸片及其制作方法、以及芯片封装结构及其制作方法，裸片包括：铝焊垫、钝化层以及铜层；铝焊垫与钝化层位于裸片的活性面上，钝化层具有第一开口，第一开口暴露铝焊垫的部分区域；铜层位于铝焊垫上，覆盖铝焊垫的部分区域，铜层的边界与位于第一开口的边界的钝化层之间具有间距。在铝焊垫的部分区域上形成铜层，且铜层的边界与钝化层之间具有间距，使得铜层完全位于钝化层的开口内。

Description

裸片及其制作方法、芯片封装结构及其制作方法 技术领域
本公开涉及芯片封装技术领域，尤其涉及一种裸片及其制作方法、芯片封装结构及其制作方法。
背景技术
近年来，随着电路集成技术的不断发展，电子产品越来越向小型化、智能化、高集成度、高性能以及高可靠性方向发展。封装技术不但制约产品的小型化，而且还影响产品的性能。
有鉴于此，本公开提供一种新的裸片及其制作方法、芯片封装结构及其制作方法，以提升封装结构的良率。
发明内容
本公开提供了一种裸片及其制作方法、芯片封装结构及其制作方法，以提升封装结构的良率。
为实现上述目的，本公开的第一方面提供一种裸片，包括：铝焊垫与钝化层，位于所述裸片的活性面上，所述钝化层具有第一开口，所述第一开口暴露所述铝焊垫的部分区域；铜层，位于所述铝焊垫上，覆盖所述铝焊垫的部分区域，所述铜层的边界与位于所述第一开口边界的所述钝化层之间具有间距。
本公开的第二方面提供一种裸片的制作方法，包括：提供晶圆，所述晶圆包括钝化层与多个铝焊垫，所述钝化层与所述多个铝焊垫位于所述晶圆的活性面上，所述钝化层具有多个第一开口，所述第一开口暴露所述铝焊垫的部分区域；在所述钝化层与所述多个铝焊垫上形成图形化的掩膜层，所述图形化的掩膜层具有第二开口，所述第二开口暴露所述铝焊垫的部分区域，且所述图形化的掩膜层完全包覆所述钝化层；去除所述铝焊垫上的氧化层，在所述第二开口内形成铜层；去除所述图形化的掩膜层；切割所述晶圆形成多个裸片。
本公开的第三方面提供一种芯片封装结构，包括：上述第一方面所述的裸片；包覆所述裸片的塑封层；引脚，位于所述塑封层上，所述引脚填充位于所述塑封层内的通孔以与所述铜层连接。
本公开的第四方面提供一种芯片封装结构的制作方法，包括：提供根据上述第二方 面所述的制作方法制作的裸片，形成包覆所述裸片的塑封层；采用激光开孔法在所述塑封层内形成通孔，以暴露所述铜层；在所述塑封层与所述铜层上形成引脚；切割形成芯片封装结构。
在铝焊垫的部分区域上形成铜层，且铜层的边界与钝化层之间具有间距，使得一方面，铜层完全位于钝化层的开口内，相对于铜层的部分区域位于钝化层上的方案，可避免铜层与钝化层的结合性能差导致铜层从钝化层上剥离；第二方面，铜层能防止铝焊垫表面氧化，降低铝焊垫的电阻；第三方面，采用激光开孔法在塑封层内形成开孔时，铜层可避免激光能量过大击穿铝焊垫，从而提升工艺窗口及封装结构的良率。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
图1是本公开第一实施例的裸片的制作方法的流程图；
图2至图6是图1中的流程对应的中间结构示意图；
图7是本公开第一实施例的裸片的截面结构示意图；
图8是本公开第二实施例的芯片封装结构的制作方法的流程图；
图9至图13是图8中的流程对应的中间结构示意图；
图14是本公开第二实施例的芯片封装结构的截面结构示意图；
图15是本公开第三实施例的芯片封装结构的截面结构示意图；
图16是对照芯片封装结构的截面结构示意图。
为方便理解本公开，以下列出本公开中出现的所有附图标记：
晶圆11                              钝化层111
铝焊垫112                           晶圆的活性面11a
第一开口111a                        晶圆的背面11b
第二开口20a                         图形化的掩膜层20
裸片1                               铜层113
塑封层21                            裸片的活性面1a
塑封层背面21b                       塑封层正面21a
通孔211                             载板2
再布线层23                          引脚22
芯片封装结构3、4                    介电层24
具体实施方式
为使本公开的上述目的、特征和优点能够更为明显易懂，下面结合附图对本公开的具体实施例做详细的说明。
图1是本公开第一实施例的裸片的制作方法的流程图。图2至图6是图1中的流程对应的中间结构示意图；图7是本公开第一实施例的裸片的截面结构示意图。
首先，参照图1中的步骤S1、图2与图3所示，其中，图2是晶圆的俯视图，图3是沿着图2中的AA线的剖视图，提供晶圆11，晶圆11包括钝化层111与多个铝焊垫112，钝化层111与多个铝焊垫112位于晶圆11的活性面11a上，钝化层111具有多个第一开口111a，第一开口111a暴露铝焊垫112的部分区域。
参照图2所示，晶圆11可以包括阵列式排布的多个区域，每个区域内可以包含形成于半导体衬底上的多种器件，以及与各个器件电连接的电互连结构。铝焊垫112与电互连结构连接，用于将各个器件的电信号输入/输出。
铝焊垫112的厚度可以小于3μm，例如，可以小于1μm。
钝化层111的材料可以为氮化硅等致密材料，以隔绝外界水汽、氧气等进入半导体衬底上的器件。
钝化层111内的第一开口111a可以通过干法刻蚀法或湿法刻蚀法形成。
接着，参照图1中的步骤S2与图4所示，在钝化层111与多个铝焊垫112上形成图形化的掩膜层20，图形化的掩膜层20具有第二开口20a，第二开口20a暴露铝焊垫112的部分区域，且图形化的掩膜层20完全包覆钝化层111。
图形化的掩膜层20的材料可以为光刻胶。一个可选方案中，形成的光刻胶层可为感光膜。感光膜可以从胶带上撕下，贴敷在钝化层111与多个铝焊垫112上。其它可选方案中，光刻胶层也可以采用先涂布液体光刻胶，后加热固化形成。此外，图形化的掩膜层20的材料也可以为介电材料，该介电材料与钝化层111的材料不同。例如钝化层111 的材料为氮化硅时，图形化的掩膜层20的材料可以为二氧化硅。
可选地，在形成图形化的掩膜层20之前，采用氧气等离子体或氩气等离子体轰击钝化层111，以增强钝化层111与图形化的掩膜层20之间的结合力。
图形化的掩膜层20完全包覆钝化层111意味着：第二开口20a的尺寸小于第一开口111a的尺寸，且第二开口20a的边界与第一开口111a的边界之间的间距为L。优选地，间距L的范围为：3μm至10μm。
需要说明的是，本实施例中的范围包括端点值。
之后，参照图1中的步骤S3、图4与图5所示，去除铝焊垫112上的氧化层，在第二开口20a内形成铜层113；参照图6所示，去除图形化的掩膜层20。
形成第一开口111a与第二开口20a后，铝焊垫112暴露在环境中，有可能被环境中的氧气氧化生成氧化铝层。氧化铝层的电阻远大于铝的电阻，因而会增加铝焊垫112的电阻。
去除铝焊垫112上的氧化层可避免增加铝焊垫112的电阻。
具体地，可以通过微蚀法实现去除铝焊垫112上的氧化层。微蚀法可以采用酸性腐蚀液与氧化层发生反应实现去除氧化层，酸性溶液例如为硫酸、盐酸、或硝酸等。
铜层113可以通过无极电镀法形成。
无极电镀法是将溶液中的金属离子还原析出在待电镀件上形成金属层。
无极电镀工艺中，a)将去除氧化层后的晶圆11置于铜离子溶液中，铝与铜离子发生置换反应，在铝焊垫112上析出铜层113。或b)将去除氧化层后的晶圆11先置于锌离子溶液中，铝与锌离子发生置换反应，在铝焊垫112上析出锌层；再将析出锌层后的晶圆11置于铜离子溶液中，锌与铜离子发生置换反应，在铝焊垫112上析出铜层113。相对于a)方案，b)方案的好处至少在于：锌层可修复铝焊垫112的粗糙表面，从而可形成平整度更高的铜层113。
铜层113的上表面可以高于或低于钝化层111的上表面。考虑到后续激光开孔工艺中的激光能量，铜层113的厚度优选较厚的。
铜层113完全位于钝化层111的开口111a内，相对于铜层113的部分区域位于钝化层111上的方案，可避免铜层113与钝化层111的结合性能差导致铜层113从钝化层111上剥离。
图形化的掩膜层20可采用针对性的方法去除，例如光刻胶可采用灰化法去除，感光膜可采用酸性溶液去除，二氧化硅可采用氢氟酸去除。
再接着，参照图1中的步骤S4、图6与图7所示，切割晶圆11形成多个裸片1。
晶圆11在切割前可以自晶圆的背面11b减薄厚度，以降低裸片1的厚度。
参照图7所示，本实施例中的裸片1包括：
铝焊垫112与钝化层111，位于裸片1的活性面1a上，钝化层111具有第一开口111a，第一开口111a暴露铝焊垫112的部分区域；
铜层113，位于铝焊垫112上，覆盖铝焊垫112的部分区域，铜层113的边界与位于第一开口111a边界的钝化层111之间的间距为L。
优选地，间距L的范围为：3μm至10μm。
图8是本公开第二实施例的芯片封装结构的制作方法的流程图。图9至图13是图8中的流程对应的中间结构示意图；图14是本公开第二实施例的芯片封装结构的截面结构示意图。
首先，参照图8中的步骤S5、图9与图10所示，提供参照图1中的步骤S1至S4制作的裸片1，形成包覆裸片1的塑封层21。
为提高封装效率，本步骤可以提供多个裸片1。各个裸片1的功能可以相同，也可以不同。
裸片1可以为电力裸片(POWER DIE)、存储裸片(MEMORY DIE)、传感裸片(SENSOR DIE)、或射频裸片(RADIO FREQUENCE DIE)等，本实施例不限定裸片1的功能。
具体地，形成包覆裸片1的塑封层21步骤可以包括：参照图9所示，将多个裸片1固定于载板2，裸片1的活性面1a远离载板2；在载板2的表面形成包埋各个裸片1的塑封层21。
载板2为硬质板件，可以包括玻璃板、陶瓷板、金属板等。
裸片1与载板2之间可以设置粘结层，以此实现两者之间的固定。具体地，可以在载板2表面涂布一整面粘结层，将多个裸片1置于该粘结层上。粘结层可以采用易剥离的材料，以便将载板2剥离下来，例如可以采用通过加热能够使其失去粘性的热分离材料或通过紫外照射能够使其失去粘性的UV分离材料。
塑封层21的材料可以为环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、乙烯-醋酸乙烯共聚物或聚乙烯醇等。塑封层21还可以为各种聚合物、树脂或聚合物复合材料，例如具有填充物或玻璃纤维布(glass fiber)的树脂，或者其它具有类似特性的材料。对应地，封装可以采用在各个裸片1之间填充液态塑封料、后经塑封模具高温固化进行。一些实施例中，塑封层21也可以采用热压成型、传递成型等塑性材料成型的方式成型。
塑封层21可以包括相对的正面21a与背面21b。
参照图10所示，可以自背面21b减薄塑封层21，可采用机械研磨例如采用砂轮研磨，以减小芯片封装结构的厚度。
之后，参照图8中的步骤S6与图11所示，采用激光开孔法在塑封层21内形成通孔211，以暴露铜层113。
相关激光开孔工艺中，为确保铝焊垫112完全露出，避免铝焊垫112上的塑封层21残留导致开路，一般选择能量较大的激光。但能量较大，又会击穿铝焊垫112，造成铝焊垫112的电连接可靠性变差。本实施例中，铝焊垫112上设置铜层113，铜层113可避免激光能量过大击穿铝焊垫112；另一方面，铜层113还能防止铝焊垫112的表面氧化，上述氧化会增大铝焊垫112的电阻。
铜层113的厚度优选较厚的，确保激光开孔工艺中不会击穿铝焊垫112。
通孔211的底部尺寸小于铜层113的尺寸。通孔211的底部尺寸小于顶部尺寸。实际工艺中，通孔211的底部尺寸一般大于顶部尺寸的75％，一般不小于顶部尺寸的60％。
再接着，参照图8中的步骤S7与图12所示，在塑封层21与铜层113上形成引脚22。
本实施例中，形成引脚22包括如下步骤S71至S74。
步骤S71：在铜层113与塑封层21的背面21b上形成光刻胶层。
本步骤S71中，一个可选方案中，形成的光刻胶层可为感光膜。感光膜可以从胶带上撕下，贴敷在铜层113与塑封层21的背面21b上。其它可选方案中，光刻胶层也可以采用先涂布液体光刻胶，后加热固化形成。
步骤S72：曝光显影光刻胶层，保留第一预定区域的光刻胶层，第一预定区域与待 形成的引脚22所在区域互补。
本步骤S72对光刻胶层进行了图案化处理。其它可选方案中，也可以使用其它易去除的牺牲材料代替光刻胶层。
步骤S73：在第一预定区域的互补区域填充金属层以形成引脚22。
本步骤S73可以采用电镀工艺完成。例如，电镀铜或铝。
具体地，步骤S71形成光刻胶层之前，可以先通过物理气相沉积法或化学气相沉积法在铜层113与塑封层21的背面21b上形成一层籽晶层(Seed Layer)。籽晶层可以作为电镀铜或铝的供电层。
电镀法可以包括电解电镀法或无极电镀法。电解电镀法是将待电镀件作为阴极，对电解液进行电解，从而在待电镀件上形成一层金属。无极电镀法是将溶液中的金属离子还原析出在待电镀件上形成金属层。一些实施例中，还可以采用先溅射、后刻蚀的方法形成引脚22。
步骤S74：灰化去除第一预定区域剩余的光刻胶层。
灰化完后，通过干法刻蚀或湿法刻蚀去除第一预定区域的籽晶层。
之后，参照图8中的步骤S8、图13与图14所示，切割形成芯片封装结构3。
参照图13所示，切割前，先去除载板2。
载板2的去除方式可以为激光剥离、UV照射等方式。
参照图14所示，当塑封层21包覆多个裸片1时，切割后，每个芯片封装结构3中包含一个裸片1。
参照图14所示，本实施例中的芯片封装结构3包括：
裸片1；
包覆裸片1的塑封层21；
引脚22，位于塑封层21上，引脚22填充位于塑封层21内的通孔211以与铜层113连接。
图15是本公开第三实施例的芯片封装结构的截面结构示意图。参照图15所示，本实施例中的芯片封装结构4与图14中的芯片封装结构3大致相同，区别仅在于：图15示出的芯片封装结构4还包括再布线层23，再布线层23位于塑封层21上，再布线层 23填充位于塑封层21内的通孔211以与铜层113电连接；引脚22位于再布线层23上。
再布线层23通过铜层113可与部分数目的铝焊垫112选择性电互连，可实现更复杂的电路布局。
再布线层23与引脚22可以包覆有介电层24，引脚22从介电层24露出。
一些实施例中，再布线层23还可以包括两层及以上。
图16是对照芯片封装结构的截面结构示意图。需要说明的是，当芯片封装结构4中的裸片1包含高频器件时，高频下，电流具有趋肤效应。若铝焊垫112的上表面为凹凸不平的粗糙表面，直接在铝焊垫112上形成铜层113时，则铜层113的上表面也为凹凸不平的粗糙表面，进一步，再布线层23对应铜层113的区域也为凹凸不平的粗糙表面。因此，电流I流经再布线层23的上述粗糙表面会增加能耗。
参照图15所示，形成铜层113前，若对铝焊垫112的粗糙表面进行修复，形成平坦表面，则铜层113的上表面也为平坦表面，进一步，再布线层23对应铜层113的区域也为平坦表面。因此，电流I流经再布线层23的上述平坦表面会降低能耗。
上述修复方法可参照无极电镀工艺中的b)方案，使用锌层修复。
相应地，对于制作方法，本实施例与图8中的芯片封装结构的制作方法的区别仅在于：步骤S7形成引脚22步骤前，在塑封层21与铜层113上形成再布线层23；引脚22形成在再布线层23上。
形成再布线层23的工艺可以参照引脚22的形成工艺。
虽然本公开披露如上，但本公开并非限定于此。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各种更动与修改，因此本公开的保护范围应当以权利要求所限定的范围为准。

Claims (14)

  1. 一种裸片，包括：
    铝焊垫与钝化层，位于所述裸片的活性面上，所述钝化层具有第一开口，所述第一开口暴露所述铝焊垫的部分区域；
    铜层，位于所述铝焊垫上，覆盖所述铝焊垫的部分区域，所述铜层的边界与位于所述第一开口边界的所述钝化层之间具有间距，所述间距的范围为：3μm至10μm。
  2. 一种裸片的制作方法，包括：
    提供晶圆，所述晶圆包括钝化层与多个铝焊垫，所述钝化层与所述多个铝焊垫位于所述晶圆的活性面上，所述钝化层具有多个第一开口，所述第一开口暴露所述铝焊垫的部分区域；
    在所述钝化层与所述多个铝焊垫上形成图形化的掩膜层，所述图形化的掩膜层具有第二开口，所述第二开口暴露所述铝焊垫的部分区域，且所述图形化的掩膜层完全包覆所述钝化层；
    去除所述铝焊垫上的氧化层，在所述第二开口内形成铜层；去除所述图形化的掩膜层；
    切割所述晶圆形成多个裸片。
  3. 根据权利要求2所述的裸片的制作方法，其特征在于，所述铜层边界与位于所述第一开口边界的所述钝化层之间的间距的范围为：3μm至10μm。
  4. 根据权利要求2或3所述的裸片的制作方法，其特征在于，所述图形化的掩膜层的材料为感光膜，形成所述图形化的掩膜层步骤前，采用氧气等离子体或氩气等离子体轰击所述钝化层。
  5. 根据权利要求2或3所述的裸片的制作方法，其特征在于，去除所述铝焊垫上的氧化层通过微蚀法实现。
  6. 根据权利要求2或3所述的裸片的制作方法，其特征在于，在所述第二开口内形成铜层通过无极电镀法形成。
  7. 根据权利要求6所述的裸片的制作方法，其特征在于，所述无极电镀法包括：先在所述第二开口内无极电镀锌层，所述锌层置换铜离子溶液中的铜，形成铜层。
  8. 一种芯片封装结构，包括：
    权利要求1所述的裸片；
    包覆所述裸片的塑封层；
    引脚，位于所述塑封层上，所述引脚填充位于所述塑封层内的通孔以与所述铜层连 接。
  9. 根据权利要求8所述的芯片封装结构，其特征在于，还包括：再布线层，位于所述塑封层上，所述再布线层填充位于所述塑封层内的通孔以与所述铜层连接；所述引脚位于所述再布线层上。
  10. 根据权利要求8所述的芯片封装结构，其特征在于，所述通孔的底部尺寸小于所述铜层的尺寸，所述通孔的底部尺寸小于所述通孔的顶部尺寸。
  11. 一种芯片封装结构的制作方法，包括：
    提供根据权利要求2至7任一项所述的制作方法制作的裸片，形成包覆所述裸片的塑封层；
    采用激光开孔法在所述塑封层内形成通孔，以暴露所述铜层；
    在所述塑封层与所述铜层上形成引脚；
    切割形成芯片封装结构。
  12. 根据权利要求11所述的芯片封装结构的制作方法，其特征在于，形成所述塑封层步骤中，所述塑封层包覆多个所述裸片；切割步骤中，每个所述芯片封装结构包括一个所述裸片。
  13. 根据权利要求11所述的芯片封装结构的制作方法，其特征在于，形成所述引脚步骤前，在所述塑封层与所述铜层上形成再布线层；所述引脚形成在所述再布线层上。
  14. 根据权利要求11所述的芯片封装结构的制作方法，其特征在于，所述通孔的底部尺寸小于所述铜层的尺寸，所述通孔的底部尺寸小于所述通孔的顶部尺寸。
PCT/CN2021/130874 2020-12-23 2021-11-16 裸片及其制作方法、芯片封装结构及其制作方法 WO2022134940A1 (zh)

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