TWI630695B - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TWI630695B
TWI630695B TW105137576A TW105137576A TWI630695B TW I630695 B TWI630695 B TW I630695B TW 105137576 A TW105137576 A TW 105137576A TW 105137576 A TW105137576 A TW 105137576A TW I630695 B TWI630695 B TW I630695B
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Taiwan
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layer
opening
conductive material
reconfiguration
semiconductor element
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TW105137576A
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TW201801276A (zh
Inventor
余振華
郭宏瑞
何明哲
吳逸文
李宗徽
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台灣積體電路製造股份有限公司
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Abstract

提供一種半導體元件及其製造方法。支撐結構用以提供導電構件額外的支撐以消除或減少有缺陷表面的形成，使得所形成的導電構件具有較薄結構而不會具有缺陷結構。

Description

半導體元件及其製造方法
本發明實施例是有關於一種半導體元件及其製造方法。
自從積體電路(integrated circuit，IC)發明以來，由於各種電子構件(亦即電晶體、二極體、電阻器、電容器等)的積集密度持續改進，半導體產業已經歷了快速成長。在大多數情況下，這種積集密度的改進來自最小特徵尺寸(minimum feature size)的一再減少，其允許更多構件積集在一給定面積中。
然而，僅是減少電晶體、二極體、電阻器、電容器及類似構件的最小特徵尺寸只是試圖改善並減少半導體元件整體尺寸的一種方面。其他方面則是目前正在檢視包括半導體元件的其他態樣。這些其他結構的改善正在研究用於尺寸縮小上。
本發明實施例提供一種半導體元件包括基板上的第一重 配置層。保護層位於第一重配置層上，所述保護層包括第一材料，且第一導電材料延伸通過在保護層中的第一開口，以與第一重配置層電性連接。保護層上的第一導電材料的第一厚度小於約3微米。支撐結構位於第一導電材料與第一重配置層之間，其中支撐結構包括所述第一材料，且在上視圖中所述支撐結構位於所述第一導電材料的中心。
本發明實施例提供一種半導體元件的製造方法包括沈積介電層於重配置層上，所述介電層包括第一介電材料。形成至少一開口於所述介電層中，其中所述至少一開口之個別部分之間形成所述第一介電材料的支撐結構。沈積導電材料於所述至少一開口中，且至少部分位於所述介電層上，其中所述沈積所述導電材料其沈積於所述介電層上的所述導電材料的厚度不大於約3微米。
本發明實施例提供另一種半導體元件的製造方法包括沈積晶種層於介電層上，其中所述晶種層的第一部分與重配置層在第一點物理接觸，所述晶種層的第二部分與所述重配置層在與所述第一點電性連接的第二點物理接觸，且部分所述介電層位於所述第一點與所述第二點之間。電鍍導電材料於所述光阻內的所述晶種層上。在所述介電層上的所述電鍍所述導電材料的一端與所述晶種層的合併厚度小於約3微米。
100‧‧‧半導體元件
101‧‧‧基板
103‧‧‧主動元件
105‧‧‧層間介電層
107‧‧‧金屬化層
109‧‧‧頂金屬層
111‧‧‧頂介電層
113‧‧‧第一鈍化層
115‧‧‧第一開口
117‧‧‧第一重配置層
121‧‧‧第一聚合物層(又稱保護層或第一材料)
123‧‧‧第二開口
125‧‧‧支撐結構
201‧‧‧第一晶種層
203‧‧‧第一光阻
301‧‧‧第一導電構件(又稱第一導電材料)
303‧‧‧蓋層
305‧‧‧第二重配置層
501‧‧‧探針
701‧‧‧第一載板
703‧‧‧黏著層
705‧‧‧聚合物層
707‧‧‧第二晶種層
711‧‧‧層窗
801‧‧‧包封體
900‧‧‧第一封裝
901‧‧‧第三重配置層
902‧‧‧第一外部端子
903‧‧‧第二半導體元件
904‧‧‧封裝基板
905‧‧‧第三半導體元件
906‧‧‧第二鈍化層
907‧‧‧接觸墊
909‧‧‧第二包封體
911‧‧‧第二外部端子
915‧‧‧基板穿孔
H1‧‧‧第一高度
P1‧‧‧第一間距
T1‧‧‧第一厚度
T2‧‧‧第二厚度
T3‧‧‧第三厚度
T4‧‧‧第四厚度
T5‧‧‧第五厚度
T6‧‧‧第六厚度
W1‧‧‧第一寬度
W2‧‧‧第二寬度
W3‧‧‧第三寬度
W4‧‧‧第四寬度
W5‧‧‧第五寬度
W6‧‧‧第六寬度
W7‧‧‧第七寬度
W8‧‧‧第八寬度
圖1繪示為依照一些實施例的一種重配置層上的聚合物層的形成。
圖2繪示為依照一些實施例的一種晶種層的形成。
圖3A至圖3C繪示為依照一些實施例的一種第一導電構件的形成。
圖4繪示為依照一些實施例的一種光阻的移除。
圖5繪示為依照一些實施例的一種測試。
圖6繪示為依照一些實施例的一種蓋層的移除。
圖7至圖9繪示為依照一些實施例的一種整合扇出型結構的形成。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第二特徵上方或在第二特徵上形成第一特徵可包括將第一特徵與第二特徵形成為直接接觸的實施例，且亦可包括第一特徵與第二特徵之間可形成有額外特徵使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露在各種實例中可重複使用元件符號以及/或字母。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在...上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向(旋轉90度或在其他定向)，而本文所用的空間相對術語相應地作出解釋。
參照圖1，半導體元件100具有基板101、位於基板101上的主動元件103、位於主動元件103上的層間介電(ILD)層105以及位於層間介電層105上的金屬化層107。基板101可具有小於103歐姆-公尺(ohm-meter)之電阻值的實質導體或半導體，且可包括塊狀矽(bulk silicon)、摻雜或未摻雜、或絕緣體上有矽(silicon-on-insulator，SOI)基板之主動層。一般而言，絕緣體上有矽基板包括一半導體材料層，例如矽、鍺、矽鍺、絕緣體上有矽、絕緣體上有矽鍺(silicon germanium on insulator，SGOI)，或其組合。其他可使用的基板包括多層基板、梯度基板(gradient substrate)或混合定向(hybrid orientation)基板。另外，在此製程中的這個階段的基板101可以是部分半導體晶圓(在圖1中並未繪示整個晶圓)，其將在後續步驟中被單體化(singulated)。
圖1中所示的主動元件103以單一個電晶體來表示。然而，所屬技術領域中具有通常知識者當可理解其可以是可用以生產設計半導體元件100所需的結構與功能要求的各種主動元件以及/或是被動元件(例如是電容器、電阻器、電感器及類似元件)。 主動元件103可使用任何合適方法形成在基板101內或是基板101的表面上。
層間介電層105可包括例如是硼磷矽玻璃(boron phosphorous silicate glass，BPSG)，然而，也可使用任何合適的介電質。層間介電層105可使用例如是電漿增強型化學氣相沉積(PECVD)製程來形成，然而，也可使用其他製程，例如是低壓化學氣相沈積(LPCVD)製程。所形成的層間介電層105的厚度在約100埃(Å)至約3,000Å之間。
金屬化層107形成在基板101、主動元件103以及層間介電層105上，並被設計成可以連接各種主動元件103，進而形成功能性電路(functional circuitry)。雖然圖1繪示為兩層，然而金屬化層107可以介電質與導電材料的交替層來形成，並藉由任何合適製程(例如是沈積製程、金屬鑲嵌製程、雙重金屬鑲嵌法製程)來形成。在一實施例中，金屬化層107可以是四層金屬化層，其藉由層間介電層105與基板101分隔。然而，金屬化層107的確切層數取決於半導體元件100的設計。
金屬化層107的頂部為頂金屬層109，頂金屬層109被頂介電層111環繞。在一實施例中，頂金屬層109包括導電材料(例如是銅或其他合適導體)，其形成在頂介電層111內。頂介電層111可以是任何合適的介電質，例如低介電常數材料。頂介電層111可先形成在其餘的金屬化層107上，然後，使用例如金屬鑲嵌製程或雙重金屬鑲嵌製程將頂金屬層109形成在頂介電層111中，然 而，也可使用任何合適的製程或材料。
第一鈍化層(first passivation layer)113可形成在基板101上的金屬化層107上(以及位於金屬化層107中的頂金屬層109與頂介電層111上)。第一鈍化層113可由一種或更多種合適的介電材料(例如氧化矽、氮化矽、低介電常數材料(例如碳摻雜氧化物)、極低介電常數材料(例如多孔碳摻雜二氧化矽)、其組合或類似的材料)所構成。第一鈍化層113可藉由一製程(例如化學氣相沈積製程)來形成，然而，也可使用任何合適的製程。第一鈍化層113的第一厚度T1在約7KÅ至約14KÅ之間，例如9.75KÅ。
在一具體實施例中，可將第一鈍化層113形成為例如是具有氮化矽層、未摻雜矽酸鹽玻璃(undoped silicate glass，USG)層以及另一氮化矽層的複合層。在此實施例中，第一氮化矽層可以是5KÅ厚，USG層4KÅ厚，而第二氮化矽層可以是750KÅ厚。然而，也可使用任何合適的材料與厚度的組合。
在形成第一鈍化層113之後，移除部分第一鈍化層113以於第一鈍化層113中形成第一開口115，第一開口115暴露頂金屬層109的至少一部分。第一開口115可以使得頂金屬層109與第一重配置層117接觸。第一開口115可使用合適的微影罩幕以及蝕刻製程來形成，然而，也可使用任何合適的製程以暴露部分頂金屬層109。所形成的第一開口115的第一寬度W1在約1.5微米至約20微米之間，例如約為2.7微米。
在形成第一開口115後，可形成第一重配置層117。第一 重配置層117可包括鋁，但亦可使用其他材料(例如銅)。第一重配置層117可使用沈積製程(例如濺鍍製程)形成材料層(未單獨繪示於圖1中)，接著藉由合適的製程(例如微影罩幕以及蝕刻製程)移除部分材料層來形成。然而，亦可使用任何其他合適製程來形成第一重配置層117。形成於第一鈍化層113上的第一重配置層117的第二厚度T2在約10KÅ至約40KÅ之間，例如約為28KÅ。
第一重配置層117亦可具有第一部分(例如著陸墊部分)，其延伸通過第一鈍化層113的第一開口115以與下方的頂金屬層109電性連接，以提供與頂金屬層109連接的電性連接，並提供與上方的導電結構連接的著陸墊區域。在一實施例中，所形成的第一部分的第二寬度W2在約30微米至約80微米之間，例如約為60微米。
此外，第一重配置層117的第二部分可形成在第一鈍化層113上。在一實施例中，第一重配置層117的第二部分可用以提供佈線以及電訊號的重配置。所形成的第二部分的第三寬度W3在約1微米至約20微米之間，例如約為3微米。然而，第一重配置層117的第一部分與第二部分亦可具有任何合適的尺寸。
圖1還繪示了在第一重配置層117與第一鈍化層113上方並與其直接物理接觸之第一聚合物層121(又可稱為保護層或第一材料)的形成。在一實施例中，第一聚合物層121可使用一製程(例如塗佈製程、層壓製程或類似製程)並以聚合物來形成。聚合物例如是聚醯亞胺(polyimide)、聚苯并噁唑(polybenzoxazole， PBO)、苯環丁烷(benzocyclobuten，BCB)及類似物。於第一鈍化層113上形成的第一聚合物層121的第三厚度T3在約為1微米至約7微米之間，例如約為4微米。
在一實施例中，第一聚合物層121可以在形成第一重配置層117之後，且在將第一重配置層117暴露於反應性氣體(例如是包括氧氣的空氣環境)之前，以原位(in situ)的方式形成。藉由原位並在暴露於反應性氣體之前形成第一聚合物層121，可以不需要為了在製程之間保護第一重配置層117，而在第一重配置層117上形成單獨的鈍化層。如此一來，在製程中可移除不必要的鈍化層，使得元件更薄、更小，並使得製造過程更有效率。
在形成第一聚合物層121之後，藉由移除部分第一聚合物層121以於第一聚合物層121中形成一個或更多個第二開口123，一個或更多個第二開口123暴露第一重配置層117的一個或更多個部分。第二開口123可使得第一重配置層117與第一導電構件301(亦可稱為第一導電材料或via 0，其未繪示於圖1中，但繪示並說明於後續圖3A中)接觸。第二開口123可使用合適的微影罩幕以及蝕刻製程來形成，然而，也可使用任何合適的製程以使得部分第一重配置層117暴露出來。此外，所形成的第二開口123的第四寬度W4在約3微米至約20微米之間。
在一實施例中，所形成的第二開口123的形狀，可以使得留下的第一聚合物層121材料構成支撐結構125。第一聚合物層121的材料所構成的支撐結構125，可以提供給上方的第一導電構 件301(未繪示於圖1中，但繪示並說明於後續圖3A中)額外的結構支撐。此額外支撐可提供給後續形成的較薄的第一導電構件301，而不會形成凹面。在一實施例中，支撐結構125可以是圓形，其第四厚度T4與(第一鈍化層113上的第一聚合物層121的)第三厚度T3以及(第一重配置層117的)第二厚度T2不同，例如介於約10KÅ至約40KÅ之間，例如28KÅ。然而，也可使用任何合適的尺寸。此外，所形成的支撐結構125的第五寬度W5在約10微米至約60微米之間，例如28微米。
圖2繪示為穿過第二開口123並與第一重配置層117電性連接的第一晶種層201的形成。在一實施例中，第一晶種層201是導電材料的薄層，其有助於在後續製程步驟期間形成厚層。第一晶種層201可包括約500Å厚的鈦層加上約3000Å厚的銅層。依據所需材料，第一晶種層201可使用例如是濺鍍製程、蒸鍍製程或PECVD製程來形成。所形成的第一晶種層201的厚度約0.1微米至約1微米之間，例如約0.3微米。
在形成第一晶種層201後，在第一晶種層201上形成第一光阻203並將其圖案化，以暴露出上方即將形成第一導電構件301的第一晶種層201。在一實施例中，第一光阻203可使用例如旋轉塗佈技術形成在第一晶種層201上，其高度約為3微米至約35微米之間，例如約為11微米。在形成第一光阻203後，接著可將第一光阻203圖案化。此圖案化是藉由將第一光阻203暴露於圖案化能源(例如圖案化光源)下，以產生化學反應。接著，依據 所需的圖案，將顯影劑施加於被暴露的第一光阻203上，以選擇性移除被暴露的部分第一光阻203或未被暴露的部分第一光阻203。在一實施例中，形成在第一光阻203中的圖案即為第一導電構件301的圖案。
如果需要，亦可選擇性地圖案化第一光阻203以形成第二重配置層305(未繪示於圖2中，但繪示並說明於後續圖3A中)的圖案。此圖案可使得第二重配置層305與第一導電構件301形成在同一層中。
圖3A繪示為圖案化後，使用電鍍製程以形成第一導電構件301，且如有需要，亦可形成第二重配置層305。在一實施例中，可使用電鍍製程，其中第一晶種層201與第一光阻203被浸入或浸沒在電鍍溶液中。第一晶種層201的表面與外部直流(DC)電源供應的負側(negative side)電性連接，以使得第一晶種層201在電鍍製程中做為陰極。固態導電陽極(例如銅陽極)也被浸沒在所述溶液中並與電源供應的正側(positive side)連接。來自陽極的原子溶於所述溶液中，從陰極(例如第一晶種層201)獲得被溶解的原子，藉此電鍍在第一光阻203開口內的第一晶種層201之被暴露的導電區上。
在一實施例中，第一導電構件301可形成在第一光阻203內，使得第一聚合物層121上的第一晶種層201與第一導電構件301之組合的第五厚度T5在約為2微米至約10微米之間，例如約3微米。在另一實施例中，第一聚合物層121上的第一晶種層201 與第一導電構件301之組合的第五厚度T5亦可小於約3微米或小於等於約3微米。此外，第一導電構件301的第六寬度W6在約為30微米至約70微米之間，例如約50微米。此導致第一導電構件301的懸突部(overhanging portion)的第七寬度W7在約為1微米至約15微米之間，例如約5微米。然而，亦可使用任何合適的尺寸。
圖3B繪示為沿著圖3A之B-B’線的第一導電構件301的上視圖。在此圖式可看出，在一些實施例中，支撐結構125可從第一重配置層117向上延伸並位於第一導電構件301的中心。因此，此上視圖中的第二開口123將形成圍繞支撐結構125的甜甜圈形狀開口。在一實施例中，支撐結構125具有第五寬度W5，而第二開口123具有第四寬度W4，第二開口123的面積(在圖3B的上視圖中)在約為942平方微米(當第四寬度W4為10微米，且第五寬度W5為10微米)至約為1177.5平方微米(當第四寬度W4為15微米，且第五寬度W5為10微米)之間。因此，使用具有支撐結構125的甜甜圈溝渠形狀，實際上將具有較大的面積與下方的第一重配置層117接觸。
當第一導電構件301形成時，支撐結構125的形成可提供第一導電構件301額外的支撐，其可避免當第一導電構件301的結構較薄時經常發生的一些缺陷。舉例來說，當其他結構為了避免凹面而需要23微米厚或更厚時，來自支撐結構125的額外的支撐有助於減少或消除凹面的產生(其在所述所需厚度時有不良之 影響)，且電鍍製程可形成凸面。這些第一導電構件301的薄化有助於避免缺陷，同時減少材料形成的成本。
圖3C繪示為在另一實施例中第一導電構件301的上視圖，其可利用多個第二開口123(其在填入導電材料後，可形成多個層窗(vias))以提供所需的連接，而所述結構的其餘部分提供額外的所需支撐。在一實施例中，雖然圖3C中繪示為四個第二開口123，但第二開口123的數量可以是兩個第二開口123或更多個第二開口123，例如三個第二開口123、四個第二開口123(如圖3C所繪示)、五個第二開口123、六個第二開口123或類似開口數量。亦可使用任何合適的第二開口123的數量以提供所需的導電性，同時仍能維持所需結構的支撐。
在一實施例中，各第二開口123的第八寬度W8在約為3微米至約20微米之間，例如約10微米。此外，在具有四個第二開口123(如圖3C所繪示)的實施例中，第二開口123(且導電材料在第二開口123內)的面積為各個單獨第二開口123的面積的四倍，例如在約為28.26平方微米至約1256平方微米之間，例如約為314平方微米。在一實施例中，第二開口123可以圓形方式環繞第一導電構件301的中心配置，且可彼此以第一間距P1間隔，第一間距P1在約6微米至約40微米之間，例如約為20微米。
此外，在本實施例中，支撐結構125為第一聚合物層121的一部分，其仍低於在第二開口123形成時未被移除的第一聚合 物層121的頂面。因此，支撐結構位於第二開口123之間的區域。然而，在第二開口123與支撐結構125之間亦可採用任何合適的配置。
回頭參照圖3A，在形成第一導電構件301之後，可於第一導電構件301上形成蓋層303，以在後續製程(例如測試)期間保護第一導電構件301。在一實施例中，蓋層303可以是焊料蓋(solder cap)，其使用(例如焊料電鍍製程)製程來形成，其第六寬度T6在約為1微米至約5微米之間，例如約2微米。然而，亦可以是任何合適的厚度。
圖4繪示為移除第一光阻203。在以第一光阻203與第一晶種層201形成第一導電構件301之後，可使用合適的移除製程來移除第一光阻203。在一實施例中，第一光阻203可以電漿灰化製程來移除，其中第一光阻203的溫度可能增加直到第一光阻203受熱分解並可被移除。然而，亦可使用任何合適的製程(例如濕式剝除製程)。移除第一光阻203可暴露出下方的部分第一晶種層201。
在移除第一光阻203以暴露出下方的第一晶種層201之後，移除所述部分第一晶種層201。在一實施例中，被暴露出來的部分第一晶種層201(例如是未被第一導電構件301所覆蓋的部分)可以例如是濕式蝕刻製程或乾式蝕刻製程來移除之。舉例來說，在乾式蝕刻製程中，使用第一導電構件301做為罩幕，反應物可直接朝向第一晶種層201。或者，可以噴灑或使用其他方式將蝕 刻劑與第一晶種層201接觸，以移除被暴露出來的部分第一晶種層201。
圖5繪示在此階段為了確認缺陷元件而進行的電路探針(circuit probe，CP)測試。在電路探針測試的一實施例中，當第一導電構件301被蓋層303保護時，一個探針或更多個探針(在圖5中以三角形標記501表示)與第一導電構件301電性連接，訊號被傳送至第一導電構件301。由於不具有凹面(在支撐結構125存在的狀態下)，不會有以CP測試時可能標記為缺陷的額外問題。假如沒有其他重大缺陷，探針將接收預定的輸出，並且可確定缺陷結構。一旦確定後，在下一步製程之前，缺陷結構可被移除，以確保所有製程能更有效率。
圖6繪示為在探針測試後移除蓋層303。在一實施例中，蓋層303可使用一道或更多道蝕刻製程來移除，所採用的蝕刻製程可選擇性移除蓋層303，而不移除或僅些許移除第一導電構件301。舉例來說，可使用濕式蝕刻製程或乾式蝕刻製程來選擇性移除蓋層303，並暴露出第一導電構件301。然而，亦可使用任何合適的方法移除蓋層303。
在移除蓋層303之後，可進行結構的單體化(singulation)。在一實施例中，單體化可使用雷射或切割刀具(未繪示)來進行，以切割環繞半導體元件100的結構，藉此將一部分與另一部分分離，以形成半導體元件100。然而，所屬技術領域具有通常知識者當理解使用切割刀具來單體化半導體元件100僅為一個例示性實 施例，並非用以限制。在單體化半導體元件100的其他方法中，亦可例如使用一道或更多道蝕刻製程來分離半導體元件100。所述方法與任何其他合適的方法亦可被使用來單體化半導體元件100。
藉由薄化第一導電構件301，可減少半導體元件100的整體高度。舉例來說，在一實施例中，第一聚合物層121上的第一導電構件301具有第五厚度T5，半導體元件100的第一高度H1在約為50微米至約300微米之間，例如約為200微米。然而，亦可是任何合適的高度。
圖7繪示為使用半導體元件100於整合扇出型(integrated fan out，InFO)結構內的之實施例其在剛開始時的示意圖。在一實施例中，在第一載板701上安置黏著層703、聚合物層705以及第二晶種層707。舉例來說，第一載板701包括矽基材料(例如玻璃或氧化矽)、其他材料(例如氧化鋁)、任何所述材料的組合或類似材料。第一載板701為平面，以便容納、附著上多個半導體元件100。
黏著層703置於第一載板701上，以助於上方的結構(例如聚合物層705)的黏著。在一實施例中，黏著層703可包括紫外線膠，其暴露在紫外線時將失去其黏著性。然而，亦可使用其他類型的黏著劑，例如壓敏性黏著劑(pressure sensitive adhesives)、輻射固化黏著劑(radiation curable adhesives)、環氧樹脂、上述黏著劑的組合或類似材料。黏著層703可以是在壓力下容易變形的一種半液態(semi-liquid)或凝膠形式置於第一載板701上。
將聚合物層705置於黏著層703上，聚合物層705用以保護例如半導體元件100(當半導體元件100已被附著時)。在一實施例中，聚合物層705可以是正調型材料(positive tone material)，例如聚苯並噁唑(polybenzoxazole，PBO，例如是HD8820材料)。然而，亦可使用任何合適的材料，例如聚醯亞胺或聚醯亞胺衍生物。聚合物層705可使用例如旋轉塗佈製程形成，其厚度在約0.5微米至約10微米之間，例如約為5微米。然而，亦可使用任何合適的方法與厚度。
在聚合物層705上形成第二晶種層707。在一實施例中，第二晶種層707可以是導電材料薄層，其在後續製程步驟期間有助於厚層的形成。第二晶種層707可包括約500Å厚的鈦層加上約3000Å厚的銅層。依據所需材料，第二晶種層707可使用例如是濺鍍製程、蒸鍍製程或PECVD製程來形成。所形成的第二晶種層707的厚度在約0.1微米至約1微米之間，例如約0.3微米。
在形成第二晶種層707之後，可在第二晶種層707上形成並圖案化第二光阻(未繪示)。在一實施例中，第二光阻可使用例如旋轉塗佈技術以形成於第二晶種層707上，其高度在約為80微米至約320微米之間，例如約為240微米。在安置之後，接著將第二光阻圖案化。此圖案化是藉由將第二光阻暴露於圖案化能源(例如圖案化光源)下，以產生化學反應。接著，依據所需的圖案，將顯影劑施加於被暴露的第二光阻上，以選擇性移除被暴露的部分第二光阻或未被暴露的部分第二光阻。
在一實施例中，形成在第二光阻中的圖案即為層窗711的圖案。在此配置下所形成的層窗711位於後續附著的元件(例如半導體元件100)的不同側上。然而，任何合適的配置的層窗711的圖案(例如將半導體元件100配置在層窗711的相對兩側上)亦可被使用。
在一實施例中，層窗711形成在第二光阻內，其中層窗711包括一種導電材料或更多種導電材料，例如銅、焊錫、鎢、其他導電金屬或類似材料，其可使用例如電鍍製程、化學鍍製程或類似製程來形成。在一實施例中，可使用電鍍製程，其中第二晶種層707與第二光阻被浸入或浸沒在電鍍溶液中。第二晶種層707的表面與外部直流電源供應的負側電性連接，使得第二晶種層707在電鍍製程中做為陰極。固態導電陽極(例如銅陽極)也被浸沒在所述溶液中並與電源供應的正側電性連接。來自陽極的原子溶入所述溶液中，從陰極(例如第二晶種層707)獲得被溶解的原子，藉此電鍍在第二光阻開口內的第二晶種層707之被暴露的導電區上。
在以第二光阻與第二晶種層707形成層窗711後，可使用合適的移除製程來移除第二光阻。在一實施例中，第二光阻可以電漿灰化製程來移除，其中第二光阻的溫度可增加直到第二光阻受熱分解並可被移除。然而，亦可使用任何合適的製程，例如濕式剝除製程。移除第二光阻後，可暴露下方的部分第二晶種層707。
當暴露後，以例如是濕式蝕刻製程或乾式蝕刻製程，移除第二晶種層707被暴露的部分(例如是未被層窗711所覆蓋的部 分)。舉例來說，在乾式蝕刻製程中，使用層窗711當作罩幕，反應物可直接朝向第二晶種層707。在另一實施例中，可噴灑或使用其他方式使蝕刻劑與第二晶種層707接觸，以移除第二晶種層707被暴露的部分。在蝕刻掉被暴露的部分第二晶種層707之後，於層窗711之間暴露出部分聚合物層705。
圖7亦繪示將半導體元件100置於層窗711之間的聚合物層705上。在一實施例中，可將晶粒貼覆膜(DAF，未繪示)置於半導體元件100上以助於將半導體元件100貼附在聚合物層705上。在一實施例中，晶粒貼覆膜可以是環氧樹脂、酚樹脂(phenol resin)、丙烯酸橡膠(acrylic rubber)、二氧化矽填料(silica filler)或其組合，並可利用層壓技術來實施。然而，亦可使用任何其他合適的材料與形成方法。在一實施例中，可使用例如取放製程(pick and place process)將半導體元件100置於聚合物層705上。然而，亦可使用任何其他方法來放置半導體元件100。
圖8繪示為層窗711與半導體元件100的包封(encapsulation)。包封可在一模製裝置(未繪示於圖8中)中進行，模製裝置可包括頂模部(top molding portion)以及與頂模部分離的底模部(bottom molding portion)。當頂模部降至與底模部相鄰，可形成第一載板701、層窗711以及半導體元件100的模腔(molding cavity)。
在包封製程期間，頂模部可置於鄰近底模部，藉此密合模腔內的第一載板701、層窗711以及半導體元件100。在密合 (enclosed)後，頂模部與底模部可形成氣密密封，以控制氣體流入與流出模腔。在密封後，包封體801可置於模腔內。包封體801可以是模製化合物樹脂(molding compound resin)，例如聚醯亞胺、聚苯硫醚(polyphenylene sulfide，PPS)、聚醚醚酮(polyether ether ketone，PEEK)、聚醚碸(Polyethersulfones，PES)、耐熱性透明樹脂(heat resistant crystal resin)、上述材料之組合或類似的材料。在頂模部與底模部對齊之前，包封體801置於模腔內，或者是可藉由射入部將包封體801射入模腔中。
在包封體801置於模腔使得包封體801包封第一載板701、層窗711以及半導體元件100後，可將包封體801固化，使包封體801硬化，以得到最佳保護。雖然確切的固化製程取決於被選做為包封體801的至少部分的具體材料，然而在選擇以模製化合物做為包封體801的一實施例中，固化可經由例如是加熱包封體801至約100℃至約130℃之間(例如是約125℃)並進行約60秒至約3000秒(例如是約600秒)的製程來實施。此外，在包封體801內可包含起始劑以及/或催化劑，以在更好的控制固化製程。
然而，所屬領域中具有通常知識者當可理解，上述固化製程僅為一種例示性製程並非用以限制於目前實施例。其他固化製程(例如照射或甚至可使得包封體801在環境溫度下硬化)亦可被使用。可使用任何合適的固化製程，且所有這些製程完全涵蓋於全文所討論的實施例的範疇內。
圖8還繪示為了使層窗711與半導體元件100暴露出來 的後續製程而進行的包封體801的薄化。薄化可以例如是使用機械研磨製程或化學機械研磨(CMP)製程來進行，其中可使用化學蝕刻劑與研磨顆粒，以與包封體801反應，並研磨包封體801直到暴露出層窗711與第一導電構件301(其位於半導體元件100上)。因此，半導體元件100與層窗711可具有平坦表面(其亦與包封體801共平面)。
然而，上述的CMP製程可視為一種例示性實施例，並用以限制在此實施例。任意其他合適的移除製程亦可被使用，以薄化包封體801與半導體元件100並且暴露出層窗711。舉例來說，可使用一連串的化學蝕刻品。此製程以及任何其他合適的製程亦可被交替使用，以薄化包封體801，且所有這些製程完全涵蓋在所述實施例的範疇內。
圖9繪示形成第三重配置層901以與半導體元件100、層窗711以及第一外部端子902內連線。在一實施例中，第三重配置層901可先藉由合適的形成製程(例如CVD或濺鍍)來形成鈦銅合金的晶種層(未繪示)，接著，形成光阻(未繪示)以覆蓋在晶種層上。之後，圖案化光阻，以暴露出部分晶種層預定形成第三重配置層901之處。
在形成光阻並將其圖案化之後，可藉由沈積製程(例如是電鍍製程)將導電材料(例如銅)形成在晶種層上。所形成的導電材料的厚度在約為1微米至約10微米之間，例如約5微米。然而，所討論之適合用以形成導電材料的材料與方法，這些材料僅為例 示。任何其他合適的材料(例如鋁銅或金)以及任何其他合適的形成製程(例如CVD或PVD)亦可使用來形成第三重配置層901。
在形成導電材料之後，可藉由合適的移除製程(例如灰化製程)來移除光阻。此外，在移除光阻後，這些被光阻所覆蓋的部分晶種層可以導電材料做為罩幕並藉由例如合適的蝕刻製程來移除。
圖9還繪示了在第三重配置層901上形成第二鈍化層906，以提供第三重配置層901與其他底層結構保護與隔絕。在一實施例中，第二鈍化層906可以是聚苯并噁唑(PBO)，但亦可使用任何合適的材料，例如聚醯亞胺或聚醯亞胺衍生物。第二鈍化層906可使用例如旋轉塗佈製程來形成，其厚度在約為1微米至約25微米之間，例如約7微米。然而，亦可採用任何合適的方法與厚度。
此外，雖然圖9僅繪示單一層第三重配置層901與單一層第二鈍化層906，但這是為了清楚起見，而不用以限制於此實施例。相對地，亦可重複一次或更多次上述用以形成單一層第三重配置層901與單一層第二鈍化層906的製程，以形成所需的多層第三重配置層901與多層第二鈍化層906。任何合適的第三重配置層901的層數亦可被使用。
圖9還繪示了形成第一外部端子902以及凸塊下金屬(未單獨繪示)，以與第三重配置層901電性連接。在一實施例中，凸塊下金屬可分別包括三層導電材料，例如鈦層、銅層以及鎳層。然而，所屬技術領域中具有通常知識者當可理解，許多合適的材料層 的配置(例如鉻/鉻銅合金/銅/金的配置、鈦/鈦鎢/銅的配置或銅/鎳/金的配置)亦適用於凸塊下金屬的形成。任何適用於凸塊下金屬的合適的材料或材料層將涵蓋於本實施例的範疇內。
在一實施例中，凸塊下金屬可以是由形成在第三重配置層901上並與之電性連接的各層所建構。各層的形成可使用電鍍製程(例如電化學鍍製程)來進行，然而，依據所需材料亦可使用其他形成製程(例如濺鍍製程、蒸鍍製程或PECVD製程)。所形成的凸塊下金屬的厚度在約為0.7微米至約10微米之間，例如約7微米。
在一實施例中，第一外部端子902可置在凸塊下金屬上且可以是球格陣列(ball grid array，BGA)，球格陣列包括例如是焊料的共晶材料，然而，亦可使用任何合適的材料。在第一外部端子902是焊球的實施例中，第一外部端子902可使用置球(ball drop)方法來形成，例如是直接置球製程。或者，焊球可先藉由合適方法(例如是蒸鍍製程、電鍍製程、印刷製程、銲料轉移(solder transfer))來形成錫層，接著進行回焊，以使所述材料成形為所需的凸塊形狀。在形成第一外部端子902後，可進行測試，以確保此結構適於後續的製程。
圖9還繪示了剝離第一載板701與半導體元件100。因此，在一實施例中，第一外部端子902與包含半導體元件100的結構可附著在環狀結構(未單獨繪示在圖9中)。此環狀結構可以是金屬環，用以在剝離製程期間或在剝離製程之後提供所述結構 的支撐與穩定。在一實施例中，第一外部端子902與半導體元件100可利用例如紫外線膠帶(亦未繪示在圖9中)來附著在環狀結構上，然而，亦可使用任何其他合適的黏膠或附著劑。
因此，在第一外部端子902與包含半導體元件100的結構附著在環狀結構後，可使用例如是熱製程改變黏著層703的附著特性，以將第一載板701與包含半導體元件100的結構剝離。在一具體實施例中，可使用能源(例如紫外線雷射、二氧化碳雷射或紅外線雷射)來照射並加熱黏著層703，直到黏著層703失去至少一些黏著性。在進行後，第一載板701與黏著層703可以是物理分離，且從包含第一外部端子902與半導體元件100的所述結構移除。
然而，當使用環狀結構來支撐第一外部端子902時，此描述僅是一種使用方法，並非用以限制在本實施例上。在另一實施例中，可使用例如第一膠帶，將第一外部端子902附著至第二載板上。在一實施例中，第二載板與第一載板701相似，然而亦可不同。在附著之後，可照射黏著層703，並將黏著層703與第一載板701物理性移除。
圖9還繪示了聚合物層705的圖案化以暴露層窗711(沿著相對應的第二晶種層707)。在一實施例中，可使用雷射鑽孔方法圖案化聚合物層705。在此方法中，保護層例如光熱轉換(light-to-heat conversion，LTHC)層或水溶性保護層(hogomax layer)(未單獨繪示在圖9中)先沈積在聚合物層705上。一旦保護， 雷射直接朝向希望被移除的聚合物層705的此部分，以暴露下方的層窗711。在雷射鑽孔製程期間，鑽孔能量可以是0.1mJ至約30mJ的範圍中，且鑽孔角度約為0度(垂直於聚合物層705)至約85度(相對於聚合物層705的法線)。在一實施例中，此圖案化可被用以形成層窗711上的開口，其具有約為100微米至約300微米的寬度，例如約200微米。
在另一實施例中，接著圖案化聚合物層705。此圖案化可藉由先將光阻(未單獨繪示在圖9中)置於聚合物層705上，接著將光阻暴露於圖案化能源(例如圖案化光源)下，以引起化學反應。接著，依據所需的圖案，將顯影劑施加於被暴露的光阻上，以選擇性移除被暴露的部分光阻或未被暴露的部分光阻，並利用例如乾式蝕刻製程移除下方被暴露的部分聚合物層705。然而，亦可使用任何其他合適的方法來圖案化聚合物層705。
圖9還繪示了接合第一封裝900。在一實施例中，第一封裝900可包括封裝基板904、第二半導體元件903、第三半導體元件905(與第二半導體元件903接合)、接觸墊907、第二包封體909以及第二外部端子911。在一實施例中，封裝基板904可例如是包括內部內連線(例如基板穿孔(through substrate vias)915)的封裝基板，此內部內連線將第二半導體元件903、第三半導體元件905連接至層窗711。
或者，封裝基板904可以是中介片(interposer)，用以做為中間基板，以將第二半導體元件903與第三半導體元件905連 接至層窗711。在此實施例中，封裝基板904可例如是矽基板、摻雜或未摻雜基板、或絕緣體上有矽(SOI)基板之主動層。然而，封裝基板904亦可以是玻璃基板、陶瓷基板、聚合物基板或可提供合適的保護以及/或內連線功能的任何其他基板。這些以及任何其他合適的材料亦可用於封裝基板904。
第二半導體元件903可以是一種為了預期目而設計的半導體元件，例如是用來做為邏輯晶粒、中央處理器(central processing unit，CPU)晶粒、記憶體晶粒(例如DRAM晶粒)、上述晶粒組合或類似晶粒。在一實施例中，根據所需的特定功能，第二半導體元件903包括積體電路元件(例如電晶體、電容器、電感器、電阻器)、第一金屬化層(未繪示)及類似元件。在一實施例中，第二半導體元件903與半導體元件100是設計為一起運作或同時運作。
第三半導體元件905可與第二半導體元件903相似。舉例來說，第三半導體元件905可以是為了預期目的而設計的一種半導體元件(例如DRAM晶粒)且包括所需功能的積體電路元件。在一實施例中，第三半導體元件905與半導體元件100以及/或第二半導體元件903是被設計為一起運作或同時運作。
第三半導體元件905可與第二半導體元件903接合。在一實施例中，第三半導體元件905僅與第二半導體元件903物理接合(例如藉由使用黏膠)。在此實施例中，第三半導體元件905與第二半導體元件903可以使用例如打線接合與封裝基板904電 性連接，然而，亦可使用任何合適的電性接合方式。
或者，第三半導體元件905可與第二半導體元件903物理接合且電性接合。在此實施例中，第三半導體元件905可包括第三外部端子(未單獨繪示在圖9中)，其與第二半導體元件903上的第四外部端子(未單獨繪示在圖9中)連接，以內連接第二半導體元件903與第三半導體元件905。
於封裝基板904上可形成接觸墊907，以形成第二半導體元件903與例如第二外部端子911之間的電性連接。在一實施例中，在封裝基板904內的電性佈線(例如基板穿孔915)上，可形成與其電性接觸的接觸墊907。接觸墊907可包括鋁，然而，亦可使用其他材料，例如銅。接觸墊907可使用沈積製程(例如濺鍍製程)以形成一材料層(未繪示)。接著，可藉由合適的製程(例如微影罩幕製程以及蝕刻製程)將部分材料層移除，以形成接觸墊907。然而，亦可使用任何其他合適的製程來形成接觸墊907。接觸墊907的厚度在約為0.5微米至約4微米之間，例如1.45微米。
第二包封體909可用以包封並保護第二半導體元件903、第三半導體元件905以及封裝基板904。在一實施例中，第二包封體909可以是模製化合物並可使用模製裝置(未繪示於圖9中)來形成。舉例來說，封裝基板904、第二半導體元件903以及第三半導體元件905可置於模製裝置的腔體中，此腔體可被密封(hermetically sealed)。第二包封體909可在密封前先置於腔體內，或者是可藉由射入部將第二包封體909射入腔體中。在一實施例 中，第二包封體909可以是模製化合物樹脂，例如是如聚醯亞胺、聚苯硫醚(PPS)、聚醚醚酮(PEEK)、聚醚碸(PES)、耐熱性透明樹脂、上述材料之組合或類似的材料。
在第二包封體909置於腔體中使得第二包封體909包封封裝基板904、第二半導體元件903以及第三半導體元件905周圍的區域之後，第二包封體909可被固化，以硬化第二包封體909，而得到最佳保護。雖然確切的固化製程至少有一部分是取決於被選做為第二包封體909的具體材料，在選擇模製化合物做為第二包封體909的實施例中，固化可經由例如是加熱第二包封體909至約100℃至約130℃之間(例如是約125℃)進行約60秒至約3000秒(例如是約600秒)的製程。此外，在第二包封體909內可包含起始劑以及/或催化劑，以在固化製程中得到更好的控制。
然而，所屬領域中具有通常知識者將理解，上述固化製程僅為一種例示性製程並非用以限制於目前的實施例。其他固化製程(例如照射或甚至可使第二包封體909在環境溫度下硬化)亦可被使用。任何合適的固化製程可被使用，且所有這些製程完全用以涵蓋在全文所討論的實施例的範疇內。
在一實施例中，第二外部端子911可用以提供封裝基板904與例如是層窗711之間的外部連接。第二外部端子911可以是接觸凸塊，例如微凸塊或可控塌陷晶片連接(controlled collapse chip connection，C4)凸塊，並可包括一種材料(例如錫)或是其他合適的材料(例如銀或銅)。在第二外部端子911可以是錫焊料 凸塊的實施例中，第二外部端子911可先藉由任何合適的方法(例如蒸鍍製程、電鍍製程、印刷製程、銲料轉移製程、置球製程等)形成錫層(厚度例如約為100微米)。將錫層形成在基板上後，進行回焊，以使所述材料的形狀形成為所需的凸塊形狀。
在形成第二外部端子911後，可將第二外部端子911對齊並置於層窗711上，並進行接合。舉例來說，在第二外部端子911是焊料凸塊的實施例中，接合製程可包括回焊製程，藉此將第二外部端子911的溫度升高至第二外部端子911將液化並流動的溫度點，以使得第二外部端子911重新固化後，將第一封裝900與層窗711接合。
在接合第一封裝900後，可將第一外部端子902從環狀結構剝離，並進行所述結構的單體化，以形成第一整合扇出型堆疊封裝(integrated fan out package-on-package，InFO-POP)結構。在一實施例中，可先藉由使用例如第二紫外線膠帶將第一封裝900接合至第二環狀結構，再將第一外部端子902從環狀結構剝離。在接合後，可將紫外線膠帶照射紫外線，且在紫外線膠帶失去其黏著性後，第一外部端子902可與環狀結構物理性分離。
在剝離後，對所述結構進行單體化，以形成第一整合扇出型堆疊封裝結構。在一實施例中，單體化可藉由使用雷射或切割刀具(未繪示)來進行，切割貫穿包封體801與層窗711之間的聚合物層705，藉此將一個部分與另一部分分離，以形成具有半導體元件100的第一整合扇出型堆疊封裝結構。然而，所屬技術領域 具有通常知識者應理解使用切割刀具來單體化第一整合扇出型堆疊封裝結構僅為一個例示性實施例，並非用以限制。在單體化第一整合扇出型堆疊封裝結構的替代性方法中，亦可例如使用一道蝕刻製程或更多道蝕刻製程來分離第一整合扇出型堆疊封裝結構。所述方法與任何其他合適的方法亦可被使用來單體化第一整合扇出型堆疊封裝結構。
藉由形成不大於第五厚度T5的第一導電構件301並藉由支撐結構125來防止凹面的形成，可使得所製造的結構的整體高度減少。藉由減少整體高度，可形成更小的元件，並可在製造過程期間產生較少缺陷。
根據一實施例，一種半導體元件包括提供基板上的第一重配置層。保護層位於第一重配置層上，所述保護層包括第一材料，且第一導電材料延伸通過在保護層中的第一開口，以與第一重配置層電性連接。保護層上的第一導電材料的第一厚度小於約3微米。支撐結構位於所述第一導電材料與所述第一重配置層之間，其中支撐結構包括所述第一材料且在上視圖中所述支撐結構位於所述第一導電材料的中心。
根據一實施例，在所述上視圖中所述第一開口環繞所述支撐結構。
根據一實施例，所述第一導電材料亦延伸通過所述保護層中與所述第一開口不同的第二開口，以與所述第一重配置層電性連接。
根據一實施例，所述第一導電材料亦延伸通過所述保護層中與所述第一開口不同的第二開口，以與所述第一重配置層電性連接，所述第一導電材料亦延伸通過所述保護層中與所述第一開口以及所述第二開口不同的第三開口，其中所述第一導電材料亦延伸通過所述保護層中與所述第一開口、所述第二開口以及所述第三開口不同的第四開口。
根據一實施例，所述的半導體元件更包括第二重配置層，位於所述保護層上，其中所述第二重配置層具有所述第一厚度。
根據一實施例，所述第一導電材料將所述第一重配置層連接至整合扇出型結構。
根據另一實施例，一種半導體元件的製造方法包括沈積介電層於重配置層上，所述介電層包括第一介電材料。形成至少一開口於所述介電層中，其中所述至少一開口之個別部分之間形成所述第一介電材料的支撐結構。沈積導電材料於所述至少一開口中，且亦至少部分位於所述介電層上，其中所述沈積所述導電材料其沈積於所述介電層上的所述導電材料的厚度不大於約3微米。
根據另一實施例，所述半導體元件的製造方法更包括於所述導電材料上形成蓋層。
根據另一實施例，所述半導體元件的製造方法更包括於所述導電材料上形成蓋層，所述蓋層包括焊料且厚度小於約2微米。
根據另一實施例，所述的半導體元件的製造方法，更包括：於所述導電材料上形成蓋層；將所述蓋層與探針連接；以及移除所述蓋層。
根據另一實施例，所述形成所述至少一開口包括形成環繞所述支撐結構的圓形開口。
根據另一實施例，所述形成所述至少一開口包括形成兩個個別的開口或更多個個別的開口。
根據另一實施例，所述形成所述至少一開口包括形成兩個個別的開口或更多個個別的開口，其中所述至少一開口的形成包括形成四個個別的開口。
根據另一實施例，所述至少一開口的形成包括形成四個個別的開口，各所述四個個別的開口的直徑約10微米。
根據又一實施例，一種半導體元件的製造方法包括沈積晶種層於介電層上，其中所述晶種層的第一部分與重配置層在第一點物理接觸，所述晶種層的第二部分與所述重配置層在與所述第一點電性連接的第二點物理接觸，且部分所述介電層位於所述第一點與所述第二點之間。形成並圖案化光阻於所述晶種層上。電鍍導電材料於所述光阻內的所述晶種層上，其中在所述介電層上的所述電鍍所述導電材料的一端與所述晶種層的合併厚度小於約3微米。
根據又一實施例，所述半導體元件的製造方法更包括電鍍焊料蓋層於所述光阻內的所述導電材料上。
根據又一實施例，所述半導體元件的製造方法更包括：電鍍焊料蓋層於所述光阻內的所述導電材料上；在所述電鍍所述焊料蓋層之後測試所述半導體元件；以及在所述測試所述半導體元件之後移除所述焊料蓋層。
根據又一實施例，所述第一點與所述第二點位於甜甜圈形狀溝渠內。
根據又一實施例，所述第一點位於第一開口中，且所述第二點位於與所述第一開口不同的第二開口中。
根據又一實施例，所述電鍍所述導電材料同時形成外部端子與重配置層。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更佳了解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。

Claims (10)

  1. 一種半導體元件，包括：第一重配置層，位於基板上；保護層，位於所述第一重配置層上，所述保護層包括第一材料；第一導電材料，延伸通過在所述保護層中的第一開口，以與所述第一重配置層電性連接，所述保護層上的所述第一導電材料的第一厚度小於約3微米；以及支撐結構，位於所述第一導電材料與所述第一重配置層之間，其中所述支撐結構包括所述第一材料且在上視圖中所述支撐結構位於所述第一導電材料的中心。
  2. 如申請專利範圍第1項所述的半導體元件，其中在所述上視圖中，所述第一開口環繞所述支撐結構。
  3. 如申請專利範圍第1項所述的半導體元件，其中所述第一導電材料亦延伸通過所述保護層中與所述第一開口不同的第二開口，以與所述第一重配置層電性連接。
  4. 如申請專利範圍第1項所述的半導體元件，其中所述第一導電材料將所述第一重配置層連接至整合扇出型結構。
  5. 一種半導體元件的製造方法，所述方法包括：沈積介電層於重配置層上，所述介電層包括第一介電材料；形成至少一開口於所述介電層中，其中所述至少一開口之個別部分之間形成所述第一介電材料的支撐結構；以及沈積導電材料於所述至少一開口中，且亦至少部分位於所述介電層上，其中所述沈積所述導電材料其沈積於所述介電層上的所述導電材料的厚度不大於約3微米，且在上視圖中所述支撐結構位於所述導電材料的中心。
  6. 如申請專利範圍第5項所述的半導體元件的製造方法，更包括：形成蓋層於所述導電材料上；連接所述蓋層與探針；以及移除所述蓋層。
  7. 如申請專利範圍第5項所述的半導體元件的製造方法，其中所述形成所述至少一開口包括形成環繞所述支撐結構的圓形開口。
  8. 一種半導體元件的製造方法，所述方法包括：沈積晶種層於介電層上，其中所述晶種層的第一部分與重配置層在第一點物理接觸，所述晶種層的第二部分與所述重配置層在與所述第一點電性連接的第二點物理接觸，且部分所述介電層位於所述第一點與所述第二點之間；形成並圖案化光阻於所述晶種層上；以及電鍍導電材料於所述光阻內的所述晶種層上，其中在所述介電層上的所述電鍍所述導電材料的一端與所述晶種層的合併厚度小於約3微米，所述導電材料自所述第一點延伸覆蓋所述部分所述介電層的頂面至所述第二點。
  9. 如申請專利範圍第8項所述的半導體元件的製造方法，其中所述第一點位於第一開口中，且所述第二點位於與所述第一開口不同的第二開口中。
  10. 如申請專利範圍第8項所述的半導體元件的製造方法，其中所述電鍍所述導電材料包括同時形成外部端子與重配置層。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9871009B2 (en) 2016-06-15 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10186462B2 (en) * 2016-11-29 2019-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10784220B2 (en) 2017-03-30 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer
US10971442B2 (en) * 2018-04-12 2021-04-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having via sidewall adhesion with encapsulant
US11189521B2 (en) * 2018-10-30 2021-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing redistribution circuit structures using phase shift mask
WO2020098470A1 (en) * 2018-11-15 2020-05-22 Changxin Memory Technologies, Inc. Redistribution layer (rdl) structure, semiconductor device and manufacturing method thereof
US20200161128A1 (en) * 2018-11-20 2020-05-21 Nanya Technology Corporation Semiconductor device and manufacturing method thereof
US11121088B2 (en) * 2019-10-16 2021-09-14 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
KR20210050951A (ko) 2019-10-29 2021-05-10 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR20220026809A (ko) 2020-08-26 2022-03-07 삼성전자주식회사 반도체 패키지
JP2022051283A (ja) * 2020-09-18 2022-03-31 新光電気工業株式会社 配線基板及びその製造方法
US11488916B2 (en) * 2021-01-12 2022-11-01 Innolux Corporation Conductive structure and electronic device comprising the same
TWI773360B (zh) * 2021-06-03 2022-08-01 矽品精密工業股份有限公司 電子封裝件及其承載結構與製法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200527557A (en) * 2004-02-06 2005-08-16 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
TW201128749A (en) * 2010-02-11 2011-08-16 Taiwan Semiconductor Mfg Pillar structure having a non-planar surface for semiconductor devices
TW201601248A (zh) * 2014-06-18 2016-01-01 台灣積體電路製造股份有限公司 半導體裝置與方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7364998B2 (en) * 2005-07-21 2008-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming high reliability bump structure
TWI295498B (en) * 2005-09-30 2008-04-01 Siliconware Precision Industries Co Ltd Semiconductor element with conductive bumps and fabrication method thereof
US7582966B2 (en) * 2006-09-06 2009-09-01 Megica Corporation Semiconductor chip and method for fabricating the same
US7667335B2 (en) * 2007-09-20 2010-02-23 Stats Chippac, Ltd. Semiconductor package with passivation island for reducing stress on solder bumps
IT1400096B1 (it) * 2010-05-12 2013-05-17 St Microelectronics Srl Processo di fabbricazione di circuiti elettronici integrati e circuiti cosi' ottenuti
US8963326B2 (en) * 2011-12-06 2015-02-24 Stats Chippac, Ltd. Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migration
TWI528876B (zh) * 2012-03-22 2016-04-01 矽品精密工業股份有限公司 中介板及其電性測試方法
TWI540722B (zh) * 2013-04-17 2016-07-01 Win Semiconductors Corp 異質接面雙極電晶體佈局結構
US9293551B2 (en) * 2013-11-25 2016-03-22 Globalfoundries Inc. Integrated multiple gate length semiconductor device including self-aligned contacts
CN103972160B (zh) * 2014-04-22 2017-01-18 上海华力微电子有限公司 一种降低在线wat测试对铜互连可靠性影响的方法
TWI556386B (zh) * 2015-03-27 2016-11-01 南茂科技股份有限公司 半導體結構
US9871009B2 (en) 2016-06-15 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200527557A (en) * 2004-02-06 2005-08-16 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
TW201128749A (en) * 2010-02-11 2011-08-16 Taiwan Semiconductor Mfg Pillar structure having a non-planar surface for semiconductor devices
TW201601248A (zh) * 2014-06-18 2016-01-01 台灣積體電路製造股份有限公司 半導體裝置與方法

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