JP2022051283A - 配線基板及びその製造方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
[配線基板の構造]
図1は、第1実施形態に係る配線基板を例示する図であり、図1(a)は部分平面図、図1(b)は図1(a)のA-A線に沿う部分断面図である。
次に、第1実施形態に係る配線基板の製造方法について説明する。図2及び図3は、第1実施形態に係る配線基板の製造工程を例示する図である。なお、本実施形態では、単品の配線基板を形成する工程を示すが、配線基板となる複数の部分を作製後、個片化して各配線基板とする工程としてもよい。
第1の実施の形態の変形例1では、補強配線の構造が異なる配線基板の例を示す。なお、第1の実施の形態の変形例1において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
応用例1では、配線基板1のパッド構造を含む多層配線基板の例を示す。なお、応用例1において、既に説明した実施形態と同一構成部品についての説明は省略する場合がある。
2 多層配線基板
10、111、113、121、123 絶縁層
10a 上面
10x、123z 溝
20、110、112、114、120、122、124 配線層
21、127 パッド
22、22A、128 補強配線
30、115、125 ソルダーレジスト層
30x、115x、125x、300x 開口部
100 コア層
111x、113x、121x、123x ビアホール
116 外部接続端子
201 シード層
202 電解めっき層
300 レジスト層
500 ピン
Claims (10)
- 第1絶縁層と、
前記第1絶縁層の一方の面に形成されたパッドと、
前記第1絶縁層の一方の面に形成され、前記パッドを露出する開口部を備えた第2絶縁層と、
前記第1絶縁層と接して形成され、平面視において、前記パッドと離隔して前記パッドの周囲を囲む補強配線と、を有し、
前記パッドは、前記第2絶縁層と接することなく前記開口部内に配置され、
前記第2絶縁層の前記開口部の内側面の前記第1絶縁層側の端部は、前記補強配線と接している、配線基板。 - 前記補強配線は、前記第1絶縁層の一方の面側に開口する溝の内部に形成されている、請求項1に記載の配線基板。
- 前記第1絶縁層の一方の面を基準として、前記補強配線の高さは、前記パッドの高さよりも低い、請求項1又は2に記載の配線基板。
- 前記補強配線は、前記第1絶縁層の一方の面から突出している、請求項1乃至3の何れか一項に記載の配線基板。
- 前記補強配線は、電気的な接続のないダミー配線である、請求項1乃至4の何れか一項に記載の配線基板。
- 前記補強配線の厚さは、前記パッドの厚さと同一である、請求項1乃至5の何れか一項に記載の配線基板。
- 前記第2絶縁層の熱膨張係数は、前記第1絶縁層の熱膨張係数よりも大きい、請求項1乃至6の何れか一項に記載の配線基板。
- 前記第2絶縁層の熱膨張係数と、前記第1絶縁層の熱膨張係数との差が10ppm/℃以上である、請求項7に記載の配線基板。
- 第1絶縁層の一方の面と接するように、パッド及び補強配線を形成する工程と、
前記第1絶縁層の一方の面に、前記パッド及び前記補強配線を被覆する第2絶縁層を形成し、前記第2絶縁層に開口部を形成する工程と、を有し、
前記パッド及び補強配線を形成する工程では、前記補強配線は、平面視において、前記パッドと離隔して前記パッドの周囲を囲むように形成され、
前記開口部を形成する工程では、前記パッドは前記第2絶縁層と接することなく前記開口部内に配置され、前記開口部の内側面の前記第1絶縁層側の端部が前記補強配線と接する、配線基板の製造方法。 - 前記第1絶縁層に、前記第1絶縁層の一方の面側に開口する溝を形成する工程を有し、
前記パッド及び補強配線を形成する工程では、前記補強配線は、前記溝の内部に形成される、請求項9に記載の配線基板の製造方法。
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JP2020157679A JP7519248B2 (ja) | 2020-09-18 | 2020-09-18 | 配線基板及びその製造方法 |
US17/447,608 US11688669B2 (en) | 2020-09-18 | 2021-09-14 | Wiring substrate |
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