WO2022134651A1 - 裸片及其制作方法、芯片封装结构及其制作方法 - Google Patents

裸片及其制作方法、芯片封装结构及其制作方法 Download PDF

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WO2022134651A1
WO2022134651A1 PCT/CN2021/115575 CN2021115575W WO2022134651A1 WO 2022134651 A1 WO2022134651 A1 WO 2022134651A1 CN 2021115575 W CN2021115575 W CN 2021115575W WO 2022134651 A1 WO2022134651 A1 WO 2022134651A1
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layer
aluminum
copper layer
copper
pad
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PCT/CN2021/115575
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English (en)
French (fr)
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霍炎
杨磊
杨威源
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矽磐微电子(重庆)有限公司
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Publication of WO2022134651A1 publication Critical patent/WO2022134651A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

Definitions

  • the present disclosure relates to the technical field of chip packaging, and in particular, to a bare chip and a manufacturing method thereof, a chip packaging structure and a manufacturing method thereof.
  • the present disclosure provides a new bare chip and a manufacturing method thereof, a chip packaging structure and a manufacturing method thereof, so as to improve the yield of the packaging structure.
  • the disclosure purpose of the present disclosure is to provide a bare chip and a manufacturing method thereof, a chip packaging structure and a manufacturing method thereof, so as to improve the yield of the packaging structure.
  • a first aspect of the present disclosure provides a bare chip, comprising: an aluminum pad and a passivation layer, located on an active surface of the bare chip, the passivation layer has an opening, and the opening exposes the A partial area of the aluminum bonding pad; a copper layer, filled in the opening of the passivation layer, and covering the surface of the aluminum bonding pad.
  • a second aspect of the present disclosure provides a method for fabricating a bare chip, including: providing a wafer, the wafer includes a passivation layer and a plurality of aluminum pads, the passivation layer and the plurality of aluminum pads are located in On the active surface of the wafer, the passivation layer has a plurality of openings, and the openings expose a partial area of the aluminum pad; remove the oxide layer on the aluminum pad;
  • a copper layer is formed on the aluminum pad, and the copper layer is filled in the opening; the wafer is cut to form a plurality of bare chips.
  • a third aspect of the present disclosure provides a chip packaging structure, comprising: the bare chip described in the first aspect; a plastic packaging layer covering the bare chip; pins located on the plastic packaging layer, and the pins are filled with A through hole in the plastic encapsulation layer is connected to the copper layer.
  • a fourth aspect of the present disclosure provides a method for fabricating a chip packaging structure, including: providing a bare chip fabricated according to the fabrication method described in the second aspect, forming a plastic encapsulation layer covering the bare chip; using a laser drilling method A through hole is formed in the plastic packaging layer to expose the copper layer; pins are formed on the plastic packaging layer and the copper layer; and a chip packaging structure is formed by cutting.
  • a copper layer is formed on the aluminum pad, and the copper layer is filled in the opening of the passivation layer, so that on the one hand, the copper layer can prevent the surface oxidation of the aluminum pad and reduce the resistance of the aluminum pad; on the other hand, the laser drilling method is adopted.
  • the general laser process needs to punch holes to ensure that the copper layer is completely exposed to avoid open circuits.
  • the copper layer can avoid excessive laser energy from penetrating the aluminum pad; thirdly, the copper layer is completely located in the passivation layer.
  • the poor bonding performance between the copper layer and the passivation layer can prevent the copper layer from peeling off the passivation layer, thereby improving the process window and the yield of the packaging structure.
  • FIG. 1 is a flowchart of a method for fabricating a bare chip according to a first embodiment of the present disclosure
  • FIG. 2 to 4 are schematic diagrams of intermediate structures corresponding to the process in FIG. 1;
  • FIG. 5 is a schematic cross-sectional structure diagram of a die according to the first embodiment of the present disclosure
  • FIG. 6 is a flowchart of a method for fabricating a chip package structure according to a second embodiment of the present disclosure
  • FIG. 7 to 11 are schematic diagrams of intermediate structures corresponding to the process in FIG. 6;
  • FIG. 12 is a schematic cross-sectional structural diagram of a chip package structure according to a second embodiment of the present disclosure.
  • FIG. 13 is a schematic cross-sectional structural diagram of a chip package structure according to a third embodiment of the present disclosure.
  • FIG. 14 is a schematic cross-sectional structure diagram of a control chip package structure
  • FIG. 15 is a schematic cross-sectional structural diagram of a chip package structure according to a fourth embodiment of the present disclosure.
  • the first aluminum pad 112a The dielectric layer 24
  • Chip package structure 3 4, 6
  • the second aluminum pad 112b is
  • FIG. 1 is a flowchart of a method for fabricating a die according to a first embodiment of the present disclosure.
  • 2 to 4 are schematic diagrams of intermediate structures corresponding to the process in FIG. 1 ;
  • FIG. 5 is a schematic diagram of a cross-sectional structure of a die according to the first embodiment of the present disclosure.
  • FIG. 2 is a top view of the wafer
  • FIG. 3 is a cross-sectional view along line AA in FIG. 2
  • a wafer 11 is provided, and the wafer 11 includes a
  • the passivation layer 111 and the plurality of aluminum bonding pads 112 are located on the active surface 11 a of the wafer 11
  • the passivation layer 111 has a plurality of openings 111 a , and the openings 111 a expose the aluminum bonding pads 112 partial area.
  • the wafer 11 may include a plurality of regions arranged in an array, and each region may include a variety of devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device.
  • the aluminum pads 112 are connected to the electrical interconnect structure for input/output of electrical signals of the various devices.
  • the thickness of the aluminum pads 112 may be less than 3 ⁇ m, for example, may be less than 1 ⁇ m.
  • the material of the passivation layer 111 may be a dense material such as silicon nitride, so as to isolate external water vapor, oxygen, etc. from entering the device on the semiconductor substrate.
  • the openings 111a in the passivation layer 111 may be formed by dry etching or wet etching.
  • step S2 in FIG. 1 the oxide layer on the aluminum pad 112 is removed.
  • the aluminum pad 112 is exposed to the environment, and may be oxidized by oxygen in the environment to form an aluminum oxide layer.
  • the resistance of the aluminum oxide layer is much greater than that of aluminum, thus increasing the resistance of the aluminum pad 112 .
  • Removing the oxide layer on the aluminum pads 112 can avoid increasing the resistance of the aluminum pads 112 .
  • the removal of the oxide layer on the aluminum pad 112 can be achieved by argon plasma bombardment or by micro-etching. Since the passivation layer 111 is an inorganic material, the performance of the passivation layer 111 will not be affected when the argon plasma is bombarded.
  • the micro-etching method can use an acidic etching solution to react with the oxide layer to remove the oxide layer, such as sulfuric acid, hydrochloric acid, or nitric acid.
  • a copper layer 113 is formed on the aluminum pad 112 , and the copper layer 113 is filled in the opening 111 a.
  • the copper layer 113 may be formed by electroplating.
  • the electroplating method may include an electrolytic plating method or an electroless plating method.
  • the electrolytic plating method uses the part to be plated as a cathode, and electrolyzes the electrolyte to form a layer of metal on the part to be plated.
  • Electroless plating method is to reduce and precipitate metal ions in the solution to form a metal layer on the part to be plated.
  • a seed layer (Seed Layer) is first formed on the aluminum pad 112 and the passivation layer 111; after that, a patterned mask layer is formed on the seed layer, and the patterned mask layer has The opening of the area to be plated is exposed, and the size and position of the opening are exactly the same as the size and position of the opening 111a of the passivation layer 111 .
  • the seed layer acts as a power supply layer for electroplating copper.
  • the material of the patterned mask layer may be photoresist. After electroplating, the patterned mask layer is removed, the seed layer is exposed, and the exposed seed layer is removed.
  • the wafer 11 after the oxide layer is removed is placed in a copper ion solution, aluminum and copper ions undergo a substitution reaction, and a copper layer 113 is deposited on the aluminum pad 112 .
  • the advantage of the solution b) is at least that: the zinc layer can repair the rough surface of the aluminum pad 112, so that the copper layer 113 with higher flatness can be formed.
  • the upper surface of the copper layer 113 is lower than the upper surface of the passivation layer 111 .
  • the thickness of the copper layer 113 may range from 2 ⁇ m to 5 ⁇ m.
  • the copper layer 113 is completely located in the opening 111a of the passivation layer 111. Compared with the scheme in which a part of the copper layer 113 is located on the passivation layer 111, the poor bonding performance between the copper layer 113 and the passivation layer 111 can be avoided and the copper layer 113 will be removed from the passivation layer. peel off on the chemical layer 111 .
  • step S4 in FIG. 1 the wafer 11 is diced to form a plurality of bare chips 1 .
  • the wafer 11 may be thinned from the backside 11 b of the wafer before being cut to reduce the thickness of the die 1 .
  • the die 1 in this embodiment includes: an aluminum pad 112 and a passivation layer 111 , which are located on the active surface 1 a of the die 1 , the passivation layer 111 has an opening 111 a , and the opening 111 a exposes the aluminum pad 112
  • the copper layer 113 is filled in the opening 111 a of the passivation layer 111 and covers the surface of the aluminum pad 112 .
  • FIG. 6 is a flowchart of a method for fabricating a chip package structure according to a second embodiment of the present disclosure.
  • 7 to 11 are schematic diagrams of intermediate structures corresponding to the process in FIG. 6 ;
  • FIG. 12 is a schematic cross-sectional structure diagram of a chip package structure according to a second embodiment of the present disclosure.
  • step S5 in FIG. 6 , FIG. 7 and FIG. 8 the die 1 fabricated by referring to steps S1 to S4 in FIG. 1 is provided to form a plastic encapsulation layer 21 covering the die 1 .
  • each die 1 may be provided in this step.
  • the functions of each die 1 may be the same or different.
  • the die 1 may be a power die (POWER DIE), a memory die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE), etc. This embodiment does not limit the size of the die 1. Function.
  • the step of forming the plastic encapsulation layer 21 covering the die 1 may include: referring to FIG. 7 , fixing the plurality of dies 1 on the carrier board 2 with the active surface 1 a of the die 1 away from the carrier board 2 ; The surface of 2 forms a plastic encapsulation layer 21 that embeds each die 1 .
  • the carrier plate 2 is a rigid plate, which may include a glass plate, a ceramic plate, a metal plate, and the like.
  • An adhesive layer can be arranged between the bare chip 1 and the carrier board 2, so as to realize the fixation between the two. Specifically, a whole-surface adhesive layer can be coated on the surface of the carrier board 2, and a plurality of dies 1 can be placed on the adhesive layer.
  • the adhesive layer can be made of an easily peelable material so that the carrier plate 2 can be peeled off, for example, a thermal separation material that can lose its adhesiveness by heating or a UV separation material that can be made to lose its adhesiveness by ultraviolet irradiation.
  • the material of the plastic sealing layer 21 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate Diol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol, etc.
  • the plastic sealing layer 21 can also be various polymers, resins or polymer composite materials, such as resins with fillers or glass fibers, or other materials with similar properties.
  • the encapsulation can be performed by filling the liquid molding compound between the respective bare chips 1 , and then curing at a high temperature by a plastic encapsulation mold.
  • the plastic encapsulation layer 21 may also be formed by means of plastic material forming such as thermocompression forming and transfer forming.
  • the plastic encapsulation layer 21 may include opposite front surfaces 21a and back surfaces 21b.
  • the plastic encapsulation layer 21 can be thinned from the back surface 21b, and mechanical grinding, such as grinding with a grinding wheel, can be used to reduce the thickness of the chip package structure.
  • through holes 211 are formed in the plastic sealing layer 21 by using a laser drilling method to expose the copper layer 113 .
  • a laser with a higher energy is generally selected, but the higher energy will break down the aluminum pads. 112 , resulting in poor electrical connection reliability of the aluminum pads 112 .
  • a copper layer 113 is disposed on the aluminum pad 112, and the copper layer 113 can prevent the laser energy from penetrating the aluminum pad 112 too much; on the other hand, the copper layer 113 can also prevent the surface of the aluminum pad 112 from being oxidized. Oxidation increases the resistance of the aluminum pads 112 .
  • the thickness of the copper layer 113 may range from 2 ⁇ m to 5 ⁇ m to ensure that the aluminum pad 112 will not be broken down during the laser drilling process.
  • the size of the bottom of the via hole 211 is smaller than that of the copper layer 113 .
  • the bottom dimension of the through hole 211 is smaller than the top dimension.
  • the size of the bottom of the through hole 211 is generally greater than 75% of the size of the top, and generally not less than 60% of the size of the top.
  • leads 22 are formed on the plastic sealing layer 21 and the copper layer 113 .
  • forming the pins 22 includes the following steps S71-S74.
  • Step S71 forming a photoresist layer on the copper layer 113 and the back surface 21 b of the plastic sealing layer 21 .
  • the formed photoresist layer may be a photosensitive film.
  • the photosensitive film can be peeled off from the tape and attached to the copper layer 113 and the back surface 21 b of the plastic sealing layer 21 .
  • the photoresist layer can also be formed by first coating a liquid photoresist and then heating and curing.
  • Step S72 exposing and developing the photoresist layer, retaining the photoresist layer in the first predetermined area, and the first predetermined area is complementary to the area where the lead 22 to be formed is located.
  • the photoresist layer is patterned.
  • other easily removable sacrificial materials can also be used in place of the photoresist layer.
  • Step S73 filling a metal layer in the complementary region of the first predetermined region to form the lead 22 .
  • This step S73 may be completed by an electroplating process.
  • electroplating copper or aluminum.
  • a seed layer may be formed on the copper layer 113 and the back surface 21b of the plastic sealing layer 21 by physical vapor deposition or chemical vapor deposition.
  • the seed layer can be used as a power supply layer for electroplating copper or aluminum.
  • Electroplating may include electrolytic plating or electroless plating.
  • Electrolytic plating is to use the part to be plated as a cathode, and electrolyze the electrolyte to form a layer of metal on the part to be plated.
  • Electroless plating is the reduction and precipitation of metal ions in the solution to form a metal layer on the part to be plated.
  • the lead 22 may also be formed by sputtering first and then etching.
  • Step S74 removing the remaining photoresist layer in the first predetermined region by ashing.
  • the seed layer in the first predetermined region is removed by dry etching or wet etching.
  • step S8 in FIG. 6 the chip package structure 3 is formed by cutting.
  • the carrier plate 2 is removed.
  • the removal method of the carrier plate 2 may be laser lift-off, UV irradiation or the like.
  • each chip package structure 3 includes one die 1 after dicing.
  • the chip packaging structure 3 in this embodiment includes: a bare chip 1 ; a plastic sealing layer 21 covering the bare chip 1 ; pins 22 , which are located on the plastic sealing layer 21 , and the pins 22 are filled in the plastic sealing layer 21 .
  • the through holes 211 are connected to the copper layer 113 .
  • FIG. 13 is a schematic cross-sectional structural diagram of a chip package structure according to a third embodiment of the present disclosure.
  • the chip packaging structure 4 in this embodiment is substantially the same as the chip packaging structure 3 in FIG. 12 , and the only difference is that the chip packaging structure 4 shown in FIG. 13 further includes a rewiring layer 23 , a rewiring layer 23 is located on the plastic encapsulation layer 21 , and the redistribution layer 23 fills the through holes 211 in the plastic encapsulation layer 21 to be electrically connected with the copper layer 113 ; the pins 22 are located on the redistribution layer 23 .
  • the redistribution layer 23 can be selectively electrically interconnected with a part of the number of aluminum pads 112 through the copper layer 113, and a more complicated circuit layout can be realized.
  • the redistribution layer 23 and the pins 22 may be covered with a dielectric layer 24 , and the pins 22 are exposed from the dielectric layer 24 .
  • the redistribution layer 23 may also include two or more layers.
  • FIG. 14 is a schematic cross-sectional structure diagram of a control chip package structure. It should be noted that, when the bare chip 1 in the chip package structure 4 includes a high-frequency device, the current has a skin effect at a high frequency. If the upper surface of the aluminum bonding pad 112 is a rough surface with unevenness, and the copper layer 113 is directly formed on the aluminum bonding pad 112, the upper surface of the copper layer 113 is also a rough surface with unevenness. Further, the rewiring layer 23 corresponds to The area of the copper layer 113 is also a rough surface with unevenness. Therefore, the current I flowing through the above-mentioned rough surface of the redistribution layer 23 increases power consumption.
  • the upper surface of the copper layer 113 is also a flat surface.
  • the rewiring layer 23 corresponds to the copper layer 113 The area is also a flat surface. Therefore, the current I flowing through the above-mentioned flat surface of the redistribution layer 23 reduces power consumption.
  • the above repair method can refer to the b) scheme in the electroless electroplating process, and use the zinc layer to repair.
  • the difference between the present embodiment and the manufacturing method of the chip package structure in FIG. 6 is only that: before the step of forming the lead 22 in step S7, the rewiring layer 23 is formed on the plastic sealing layer 21 and the copper layer 113; The pins 22 are formed on the rewiring layer 23 .
  • the process of forming the redistribution layer 23 may refer to the process of forming the pin 22 .
  • FIG. 15 is a schematic cross-sectional structural diagram of a chip package structure according to a fourth embodiment of the present disclosure.
  • the chip packaging structure 6 in this embodiment is substantially the same as the chip packaging structure 4 in FIG. 13 , the only difference being that the die 5 in the chip packaging structure 6 is different from the die in the chip packaging structure 4 1.
  • the plurality of aluminum bonding pads 112 in the die 5 include a first aluminum bonding pad 112a near the edge of the die 5 and a second aluminum bonding pad 112b away from the edge of the die 5; the first aluminum bonding pad 112a is covered with The first edge of the copper layer 113 is flush with the first edge of the first aluminum pad 112a, and the first edge of the copper layer 113 covered on the first aluminum pad 112a is away from the edge of the second aluminum pad 112b.
  • the first edge of an aluminum bonding pad 112a is away from the edge of the second aluminum bonding pad 112b.
  • the method for fabricating the bare chip may further include: exposing the first opening of the first aluminum pad 112a, and exposing the second opening of the second solder pad 112b. Wherein, the first sidewall of the first opening is flush with the first edge of the first aluminum pad 112a, and the first sidewall of the first opening is a sidewall away from the second opening.
  • the die 5 may be fabricated or sold separately.
  • the chip package structure 6 may omit the redistribution layer 23 .
  • the spacing between the pins 22 can be increased.

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Abstract

本公开提供了一种裸片及其制作方法、以及芯片封装结构及其制作方法，裸片包括：铝焊垫、钝化层以及铜层；铝焊垫与钝化层位于裸片的活性面，钝化层具有开口，开口暴露铝焊垫的部分区域；铜层填充于钝化层的开口内，且覆盖于铝焊垫的表面。在铝焊垫上形成铜层，且铜层填充于钝化层的开口内，使得一方面，铜层能防止铝焊垫表面氧化，降低铝焊垫的电阻；第二方面，采用激光开孔法在塑封层内形成开孔时，铜层可避免激光能量过大击穿铝焊垫；第三方面，铜层完全位于钝化层的开口内，相对于铜层部分区域位于钝化层上的方案，可避免铜层与钝化层的结合性能差导致铜层从钝化层上剥离，从而提升封装结构的良率。

Description

裸片及其制作方法、芯片封装结构及其制作方法 技术领域
本公开涉及芯片封装技术领域，尤其涉及一种裸片及其制作方法、芯片封装结构及其制作方法。
背景技术
近年来，随着电路集成技术的不断发展，电子产品越来越向小型化、智能化、高集成度、高性能以及高可靠性方向发展。封装技术不但制约产品的小型化，而且还影响产品的性能。
有鉴于此，本公开提供一种新的裸片及其制作方法、芯片封装结构及其制作方法，以提升封装结构的良率。
发明内容
本公开的公开目的是提供一种裸片及其制作方法、芯片封装结构及其制作方法，以提升封装结构的良率。
为实现上述目的，本公开的第一方面提供一种裸片，包括：铝焊垫与钝化层，位于所述裸片的活性面上，所述钝化层具有开口，所述开口暴露所述铝焊垫的部分区域；铜层，填充于所述钝化层的开口内，且覆盖于所述铝焊垫的表面。
本公开的第二方面提供一种裸片的制作方法，包括：提供晶圆，所述晶圆包括钝化层与多个铝焊垫，所述钝化层与所述多个铝焊垫位于所述晶圆的活性面上，所述钝化层具有多个开口，所述开口暴露所述铝焊垫的部分区域；去除所述铝焊垫上的氧化层；
在所述铝焊垫上形成铜层，所述铜层填充于所述开口内；切割所述晶圆形成多个裸片。
本公开的第三方面提供一种芯片封装结构，包括：上述第一方面所述的裸片；包覆所述裸片的塑封层；引脚，位于所述塑封层上，所述引脚填充位于所述塑封层内的通孔以与所述铜层连接。
本公开的第四方面提供一种芯片封装结构的制作方法，包括：提供根据上述第二方面所述的制作方法制作的裸片，形成包覆所述裸片的塑封层；采用激光开孔法在所述塑封层内形成通孔，以暴露所述铜层；在所述塑封层与所述铜层上形成引脚；切割形成芯 片封装结构。
在铝焊垫上形成铜层，且铜层填充于钝化层的开口内，使得一方面，铜层能防止铝焊垫表面氧化，降低铝焊垫的电阻；第二方面，采用激光开孔法在塑封层内形成开孔时，一般激光工艺需过打孔以确保铜层完全露出避免开路，铜层可避免激光能量过大击穿铝焊垫；第三方面，铜层完全位于钝化层的开口内，相对于铜层部分区域位于钝化层上的方案，可避免铜层与钝化层的结合性能差导致铜层从钝化层上剥离，从而提升工艺窗口及封装结构的良率。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
图1是本公开第一实施例的裸片的制作方法的流程图；
图2至图4是图1中的流程对应的中间结构示意图；
图5是本公开第一实施例的裸片的截面结构示意图；
图6是本公开第二实施例的芯片封装结构的制作方法的流程图；
图7至图11是图6中的流程对应的中间结构示意图；
图12是本公开第二实施例的芯片封装结构的截面结构示意图；
图13是本公开第三实施例的芯片封装结构的截面结构示意图；
图14是对照芯片封装结构的截面结构示意图；
图15是本公开第四实施例的芯片封装结构的截面结构示意图。
为方便理解本公开，以下列出本公开中出现的所有附图标记：
晶圆11                              钝化层111
铝焊垫112                           晶圆的活性面11a
开口111a                            晶圆的背面11b
裸片1、5                            铜层113
塑封层21                            裸片的活性面1a
塑封层背面21b                       塑封层正面21a
通孔211                             载板2
再布线层23                           引脚22
第一铝焊垫112a                       介电层24
芯片封装结构3、4、6                  第二铝焊垫112b
具体实施方式
为使本公开的上述目的、特征和优点能够更为明显易懂，下面结合附图对本公开的具体实施例做详细的说明。
图1是本公开第一实施例的裸片的制作方法的流程图。图2至图4是图1中的流程对应的中间结构示意图；图5是本公开第一实施例的裸片的截面结构示意图。
首先，参照图1中的步骤S1、图2与图3所示，图2是晶圆的俯视图，图3是沿着图2中的AA线的剖视图，提供晶圆11，晶圆11包括钝化层111与多个铝焊垫112，钝化层111与多个铝焊垫112位于晶圆11的活性面11a上，钝化层111具有多个开口111a，开口111a暴露铝焊垫112的部分区域。
参照图2所示，晶圆11可以包括阵列式排布的多个区域，每个区域内可以包含形成于半导体衬底上的多种器件，以及与各个器件电连接的电互连结构。铝焊垫112与电互连结构连接，用于将各个器件的电信号输入/输出。
铝焊垫112的厚度可以小于3μm，例如，可以小于1μm。
钝化层111的材料可以为氮化硅等致密材料，以隔绝外界水汽、氧气等进入半导体衬底上的器件。
钝化层111内的开口111a可以通过干法刻蚀法或湿法刻蚀法形成。
接着，参照图1中的步骤S2与图3所示，去除铝焊垫112上的氧化层。
干法刻蚀法或湿法刻蚀法形成开口111a后，铝焊垫112暴露在环境中，有可能被环境中的氧气氧化生成氧化铝层。氧化铝层的电阻远大于铝的电阻，因而会增加铝焊垫112的电阻。
去除铝焊垫112上的氧化层可避免增加铝焊垫112的电阻。
具体地，可以通过氩气等离子轰击法或通过微蚀法实现去除铝焊垫112上的氧化层。由于钝化层111为无机材料，因而氩气等离子轰击时，不会影响钝化层111的性能。微蚀法可以采用酸性腐蚀液与氧化层发生反应实现去除氧化层，酸性溶液例如为硫酸、盐 酸、或硝酸等。
之后，参照图1中的步骤S3与图4所示，在铝焊垫112上形成铜层113，铜层113填充于开口111a内。
铜层113可以通过电镀法形成。
电镀法可以包括电解电镀法或无极电镀法。电解电镀法是将待电镀件作为阴极，对电解液进行电解，从而在待电镀件上形成一层金属。无极电镀法是将溶液中的金属离子还原析出在待电镀件上形成金属层。
电解电镀工艺中，先在铝焊垫112与钝化层111上形成一层籽晶层(Seed Layer)；之后，在籽晶层上形成图形化的掩膜层，图形化的掩膜层具有暴露待电镀区域的开口，该开口尺寸与钝化层111的开口111a的尺寸及位置完全相同。籽晶层作为电镀铜的供电层。图形化的掩膜层的材料可以为光刻胶。电镀完后，去除图形化的掩膜层，暴露籽晶层，再去除暴露的籽晶层。
无极电镀工艺中，a)将去除氧化层后的晶圆11置于铜离子溶液中，铝与铜离子发生置换反应，在铝焊垫112上析出铜层113。或b)将去除氧化层后的晶圆11先置于锌离子溶液中，铝与锌离子发生置换反应，在铝焊垫112上析出锌层；再将析出锌层后的晶圆11置于铜离子溶液中，锌与铜离子发生置换反应，在铝焊垫112上析出铜层113。相对于a)方案，b)方案的好处至少在于：锌层可修复铝焊垫112的粗糙表面，从而可形成平整度更高的铜层113。
铜层113的上表面低于钝化层111的上表面。考虑到后续激光开孔工艺中的激光能量，铜层113的厚度范围可以为：2μm～5μm。
需要说明的是，本实施例中的范围包括端点值。
铜层113完全位于钝化层111的开口111a内，相对于铜层113部分区域位于钝化层111上的方案，可避免铜层113与钝化层111的结合性能差导致铜层113从钝化层111上剥离。
再接着，参照图1中的步骤S4、图4与图5所示，切割晶圆11形成多个裸片1。
晶圆11在切割前可以自晶圆的背面11b减薄厚度，以降低裸片1的厚度。
参照图5所示，本实施例中的裸片1包括：铝焊垫112与钝化层111，位于裸片1的活性面1a，钝化层111具有开口111a，开口111a暴露铝焊垫112的部分区域；铜层 113，填充于钝化层111的开口111a内，且覆盖于铝焊垫112的表面。
图6是本公开第二实施例的芯片封装结构的制作方法的流程图。图7至图11是图6中的流程对应的中间结构示意图；图12是本公开第二实施例的芯片封装结构的截面结构示意图。
首先，参照图6中的步骤S5、图7与图8所示，提供参照图1中的步骤S1～S4制作的裸片1，形成包覆裸片1的塑封层21。
为提高封装效率，本步骤可以提供多个裸片1。各个裸片1的功能可以相同，也可以不同。
裸片1可以为电力裸片(POWER DIE)、存储裸片(MEMORY DIE)、传感裸片(SENSOR DIE)、或射频裸片(RADIO FREQUENCE DIE)等，本实施例不限定裸片1的功能。
具体地，形成包覆裸片1的塑封层21步骤可以包括：参照图7所示，将多个裸片1固定于载板2，裸片1的活性面1a远离载板2；在载板2的表面形成包埋各个裸片1的塑封层21。
载板2为硬质板件，可以包括玻璃板、陶瓷板、金属板等。
裸片1与载板2之间可以设置粘结层，以此实现两者之间的固定。具体地，可以在载板2表面涂布一整面粘结层，将多个裸片1置于该粘结层上。粘结层可以采用易剥离的材料，以便将载板2剥离下来，例如可以采用通过加热能够使其失去粘性的热分离材料或通过紫外照射能够使其失去粘性的UV分离材料。
塑封层21的材料可以为环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、乙烯-醋酸乙烯共聚物或聚乙烯醇等。塑封层21还可以为各种聚合物、树脂或聚合物复合材料，例如具有填充物或玻璃纤维布(glass fiber)的树脂，或者其它具有类似特性的材料。对应地，封装可以采用在各个裸片1之间填充液态塑封料、后经塑封模具高温固化进行。一些实施例中，塑封层21也可以采用热压成型、传递成型等塑性材料成型的方式成型。
塑封层21可以包括相对的正面21a与背面21b。
参照图8所示，可以自背面21b减薄塑封层21，可采用机械研磨例如采用砂轮研磨， 以减小芯片封装结构的厚度。
之后，参照图6中的步骤S6与图9所示，采用激光开孔法在塑封层21内形成通孔211，以暴露铜层113。
相关激光开孔工艺中，为确保铝焊垫112完全露出，避免铝焊垫112上的塑封层21残留导致开路，一般选择能量较大的激光，但能量较大，又会击穿铝焊垫112，造成铝焊垫112的电连接可靠性变差。本实施例中，铝焊垫112上设置铜层113，铜层113可避免激光能量过大击穿铝焊垫112；另一方面，铜层113还能防止铝焊垫112的表面氧化，上述氧化会增大铝焊垫112的电阻。
铜层113的厚度范围可以为：2μm～5μm，确保激光开孔工艺中不会击穿铝焊垫112。
通孔211的底部尺寸小于铜层113的尺寸。通孔211的底部尺寸小于顶部尺寸。实际工艺中，通孔211的底部尺寸一般大于顶部尺寸的75％，一般不小于顶部尺寸的60％。
再接着，参照图6中的步骤S7与图10所示，在塑封层21与铜层113上形成引脚22。
本实施例中，形成引脚22包括如下步骤S71～S74。
步骤S71：在铜层113与塑封层21的背面21b上形成光刻胶层。
本步骤S71中，一个可选方案中，形成的光刻胶层可为感光膜。感光膜可以从胶带上撕下，贴敷在铜层113与塑封层21的背面21b上。其它可选方案中，光刻胶层也可以采用先涂布液体光刻胶，后加热固化形成。
步骤S72：曝光显影光刻胶层，保留第一预定区域的光刻胶层，第一预定区域与待形成的引脚22所在区域互补。
本步骤S72对光刻胶层进行了图案化处理。其它可选方案中，也可以使用其它易去除的牺牲材料代替光刻胶层。
步骤S73：在第一预定区域的互补区域填充金属层以形成引脚22。
本步骤S73可以采用电镀工艺完成。例如，电镀铜或铝。
具体地，步骤S71形成光刻胶层之前，可以先通过物理气相沉积法或化学气相沉积法在铜层113与塑封层21的背面21b上形成一层籽晶层(Seed Layer)。籽晶层可以作为电镀铜或铝的供电层。
电镀可以包括电解电镀或无极电镀。电解电镀是将待电镀件作为阴极，对电解液进行电解，从而在待电镀件上形成一层金属。无极电镀是将溶液中的金属离子还原析出在待电镀件上形成金属层。一些实施例中，还可以采用先溅射、后刻蚀的方法形成引脚22。
步骤S74：灰化去除第一预定区域剩余的光刻胶层。
灰化完后，通过干法刻蚀或湿法刻蚀去除第一预定区域的籽晶层。
之后，参照图6中的步骤S8、图11与图12所示，切割形成芯片封装结构3。
参照图11所示，切割前，先去除载板2。
载板2的去除方式可以为激光剥离、UV照射等方式。
参照图12所示，当塑封层21包覆多个裸片1时，切割后，每个芯片封装结构3中包含一个裸片1。
参照图12所示，本实施例中的芯片封装结构3包括：裸片1；包覆裸片1的塑封层21；引脚22，位于塑封层21上，引脚22填充位于塑封层21内的通孔211以与铜层113连接。
图13是本公开第三实施例的芯片封装结构的截面结构示意图。参照图13所示，本实施例中的芯片封装结构4与图12中的芯片封装结构3大致相同，区别仅在于：图13示出的芯片封装结构4还包括再布线层23，再布线层23位于塑封层21上，再布线层23填充位于塑封层21内的通孔211以与铜层113电连接；引脚22位于再布线层23上。
再布线层23通过铜层113可与部分数目的铝焊垫112选择性电互连，可实现更复杂的电路布局。
再布线层23与引脚22可以包覆有介电层24，引脚22从介电层24露出。
一些实施例中，再布线层23还可以包括两层及以上。
图14是对照芯片封装结构的截面结构示意图。需要说明的是，当芯片封装结构4中的裸片1包含高频器件时，高频下，电流具有趋肤效应。若铝焊垫112的上表面为凹凸不平的粗糙表面，直接在铝焊垫112上形成铜层113时，则铜层113的上表面也为凹凸不平的粗糙表面，进一步，再布线层23对应铜层113的区域也为凹凸不平的粗糙表面。因此，电流I流经再布线层23的上述粗糙表面会增加能耗。
参照图13所示，形成铜层113前，若对铝焊垫112的粗糙表面进行修复，形成平坦表面，则铜层113的上表面也为平坦表面，进一步，再布线层23对应铜层113区域也 为平坦表面。因此，电流I流经再布线层23的上述平坦表面会降低能耗。
上述修复方法可参照无极电镀工艺中的b)方案，使用锌层修复。
相应地，对于制作方法，本实施例与图6中的芯片封装结构的制作方法的区别仅在于：步骤S7形成引脚22步骤前，在塑封层21与铜层113上形成再布线层23；引脚22形成在再布线层23上。
形成再布线层23的工艺可以参照引脚22的形成工艺。
图15是本公开第四实施例的芯片封装结构的截面结构示意图。参照图15所示，本实施例中的芯片封装结构6与图13中的芯片封装结构4大致相同，区别仅在于：芯片封装结构6中的裸片5不同于芯片封装结构4中的裸片1。例如，裸片5中的多个铝焊垫112包括靠近裸片5的边缘的第一铝焊垫112a与远离裸片5的边缘的第二铝焊垫112b；第一铝焊垫112a上覆盖的铜层113的第一边缘与第一铝焊垫112a的第一边缘齐平，第一铝焊垫112a上覆盖的铜层113的第一边缘为远离第二铝焊垫112b的边缘，第一铝焊垫112a的第一边缘为远离第二铝焊垫112b的边缘。这样，可以加大再布线层23之间的间距L，降低对再布线层23的宽度尺寸的精细程度的要求。
参照图15所示，裸片的制作方法还可以包括：暴露第一铝焊垫112a的第一开口，以及暴露第二焊垫112b的第二开口。其中，第一开口的第一侧壁与第一铝焊垫112a的第一边缘齐平，第一开口的第一侧壁为远离第二开口的侧壁。
一些实施例中，裸片5可以单独制作或销售。
一些实施例中，芯片封装结构6可以省略再布线层23。在第一铝焊垫112a上覆盖的铜层113的第一边缘与第一铝焊垫112a的第一边缘齐平时，可以加大引脚22之间的间距。
虽然本公开披露如上，但本公开并非限定于此。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各种更动与修改，因此本公开的保护范围应当以权利要求所限定的范围为准。

Claims (13)

  1. 一种裸片，包括：
    铝焊垫与钝化层，位于所述裸片的活性面上，所述钝化层具有开口，所述开口暴露所述铝焊垫的部分区域；
    铜层，填充于所述钝化层的开口内，且覆盖于所述铝焊垫的表面。
  2. 根据权利要求1所述的裸片，其特征在于，所述铜层的厚度范围为：2μm～5μm。
  3. 根据权利要求1所述的裸片，其特征在于，所述铝焊垫具有多个，所述多个铝焊垫包括靠近所述裸片的边缘的第一铝焊垫与远离所述裸片的边缘的第二铝焊垫；所述第一铝焊垫上覆盖的所述铜层的第一边缘与所述第一铝焊垫的第一边缘齐平，所述第一铝焊垫上覆盖的所述铜层的第一边缘为远离所述第二铝焊垫的边缘，所述第一铝焊垫的第一边缘为远离所述第二铝焊垫的边缘。
  4. 一种裸片的制作方法，包括：
    提供晶圆，所述晶圆包括钝化层与多个铝焊垫，所述钝化层与所述多个铝焊垫位于所述晶圆的活性面上，所述钝化层具有多个开口，所述开口暴露所述铝焊垫的部分区域；
    去除所述铝焊垫上的氧化层；
    在所述铝焊垫上形成铜层，所述铜层填充于所述开口内；
    切割所述晶圆形成多个裸片。
  5. 根据权利要求4所述的裸片的制作方法，其特征在于，去除所述铝焊垫上的氧化层通过氩气等离子轰击法或通过微蚀法实现。
  6. 根据权利要求4所述的裸片的制作方法，其特征在于，通过无极电镀法在所述铝焊垫上形成铜层，所述无极电镀法包括：先在所述铝焊垫上无极电镀锌层，所述锌层置换铜离子溶液中的铜，形成铜层。
  7. 一种芯片封装结构，包括：
    权利要求1至3任一项所述的裸片；
    包覆所述裸片的塑封层；
    引脚，位于所述塑封层上，所述引脚填充位于所述塑封层内的通孔以与所述铜层连接。
  8. 根据权利要求7所述的芯片封装结构，其特征在于，还包括：再布线层，位于所述塑封层上，所述再布线层填充位于所述塑封层内的通孔以与所述铜层连接；所述引脚位于所述再布线层上。
  9. 根据权利要求7所述的芯片封装结构，其特征在于，所述通孔的底部尺寸小于 所述铜层的尺寸，所述通孔的底部尺寸小于所述通孔的顶部尺寸。
  10. 一种芯片封装结构的制作方法，包括：
    提供根据权利要求4至6任一项所述的制作方法制作的裸片，形成包覆所述裸片的塑封层；
    采用激光开孔法在所述塑封层内形成通孔，以暴露所述铜层；
    在所述塑封层与所述铜层上形成引脚；
    切割形成芯片封装结构。
  11. 根据权利要求10所述的芯片封装结构的制作方法，其特征在于，形成所述塑封层步骤中，所述塑封层包覆多个所述裸片；切割步骤中，每个所述芯片封装结构包括一个所述裸片。
  12. 根据权利要求10所述的芯片封装结构的制作方法，其特征在于，形成所述引脚步骤前，在所述塑封层与所述铜层上形成再布线层；所述引脚形成在所述再布线层上。
  13. 根据权利要求10所述的芯片封装结构的制作方法，其特征在于，所述通孔的底部尺寸小于所述铜层的尺寸，所述通孔的底部尺寸小于所述通孔的顶部尺寸。
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Citations (3)

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CN102468186A (zh) * 2010-11-15 2012-05-23 无锡江南计算技术研究所 基板的制作方法及半导体芯片的封装方法
US20160126166A1 (en) * 2014-10-31 2016-05-05 Nantong Fujitsu Microelectronics Co., Ltd. Flip-chip on leadframe semiconductor packaging structure and fabrication method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101928947A (zh) * 2009-06-26 2010-12-29 中芯国际集成电路制造(上海)有限公司 清洗试剂以及铝焊盘的制作工艺
CN102468186A (zh) * 2010-11-15 2012-05-23 无锡江南计算技术研究所 基板的制作方法及半导体芯片的封装方法
US20160126166A1 (en) * 2014-10-31 2016-05-05 Nantong Fujitsu Microelectronics Co., Ltd. Flip-chip on leadframe semiconductor packaging structure and fabrication method thereof

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