WO2023272990A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2023272990A1
WO2023272990A1 PCT/CN2021/121617 CN2021121617W WO2023272990A1 WO 2023272990 A1 WO2023272990 A1 WO 2023272990A1 CN 2021121617 W CN2021121617 W CN 2021121617W WO 2023272990 A1 WO2023272990 A1 WO 2023272990A1
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layer
initial
dielectric layer
doped region
sidewall
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PCT/CN2021/121617
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English (en)
French (fr)
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韩清华
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长鑫存储技术有限公司
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Priority to EP21870544.0A priority Critical patent/EP4135036A1/en
Priority to KR1020237018424A priority patent/KR20230093335A/ko
Priority to JP2023532840A priority patent/JP2023551332A/ja
Priority to US17/648,732 priority patent/US11600726B2/en
Publication of WO2023272990A1 publication Critical patent/WO2023272990A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors

Definitions

  • the present disclosure includes, but is not limited to, a semiconductor structure and method of making the same.
  • a vertical GAA (Gate-All-Around) transistor structure When a vertical GAA (Gate-All-Around) transistor structure is used as a dynamic memory selection transistor (access transistor), its occupied area can reach 4F2 (F: the smallest pattern obtainable under a given process condition size), higher density efficiency can be achieved in principle, but at some sizes, the bit line buried at the bottom of the transistor has a higher resistance due to the main component being silicon.
  • F the smallest pattern obtainable under a given process condition size
  • An embodiment of the present disclosure provides a semiconductor structure, including: a substrate; a bit line located on the substrate, and the material of the bit line includes a metal semiconductor compound; a semiconductor channel located on the surface of the bit line, along the The base points to the direction of the bit line, the semiconductor channel includes a first doped region, a channel region and a second doped region arranged in sequence, and the first doped region is in contact with the bit line; A dielectric layer covering the sidewall surface of the first doped region, and having a first interval between the first dielectric layer adjacent to the sidewall of the first doped region on the same bit line; an insulating layer , covering the sidewall surface of the channel region; the word line, covering the sidewall surface of the insulating layer away from the channel region, and there is a second interval between adjacent word lines; the second dielectric layer, covering The sidewall surface of the second doped region, and there is a third interval between the second dielectric layer adjacent to the sidewall of the second doped region; the third dielectric layer is located at
  • the semiconductor structure further includes: a metal contact layer located on the top surface of the second doped region away from the substrate, and the metal semiconductor compound and the metal contact layer have the same metal element.
  • the orthographic projection of the metal contact layer on the substrate covers the orthographic projection of the second doped region on the substrate.
  • the semiconductor structure further includes: a transition layer located between the second doped region and the metal contact layer, and the metal contact layer wraps the transition layer, and the transition layer and the second doped region are doped with the same type doping ions, and the doping concentration of the doping ions in the transition layer is greater than that in the second doping region, and the doping ions are one of N-type ions or P-type ions.
  • the substrate, the bit line and the semiconductor channel have the same semiconductor element.
  • the first doping region, the channel region and the second doping region are doped with the same type of doping ions, and the doping concentration of the doping ions in the first doping region is the same as that in the The doping concentrations in the channel region and the second doping region are consistent, and the doping ions are one of N-type ions or P-type ions.
  • the orthographic projection of the channel region on the substrate is smaller than the orthographic projection of the second doped region on the substrate, and smaller than the orthographic projection of the first doped region on the substrate.
  • the insulating layer and the second dielectric layer have the same film layer structure.
  • the orthographic projection of the periphery of the insulating layer on the substrate is smaller than the orthographic projection of the periphery of the second dielectric layer on the substrate.
  • the first dielectric layer includes a fourth dielectric layer and a fifth dielectric layer
  • the fourth dielectric layer is located in the interval between adjacent bit lines, and the adjacent first doped layers located on adjacent bit lines In the interval between regions;
  • the fifth dielectric layer is located on the sidewall of the adjacent first doped region on the same bit line, and is located on the sidewall of the fourth dielectric layer.
  • an embodiment of the present disclosure also provides a method for fabricating a semiconductor structure, including: providing a substrate; forming an initial bit line on the substrate, and forming a semiconductor channel on a surface where the initial bit line is away from the substrate; In the direction of the semiconductor channel, the semiconductor channel includes the first doped region, the channel region and the second doped region arranged in sequence; the first dielectric layer covering the sidewall surface of the first doped region is formed, and the same initial bit line is adjacent There is a first interval between the first dielectric layer on the sidewall of the first doped region; an insulating layer covering the surface of the sidewall of the channel region is formed; a word line covering the surface of the sidewall of the insulating layer away from the channel region is formed, and adjacent There is a second interval between the word lines; a second dielectric layer covering the sidewall surface of the second doped region is formed, and there is a third interval between the second dielectric layer adjacent to the sidewall of the second doped region, the first The spacer, the second
  • the word line and before forming the second dielectric layer further comprising: using an epitaxial growth process to form an initial transition layer on the top surface of the second doped region away from the substrate, the initial transition layer and the The second doping region is doped with the same type of doping ions, the doping concentration of the doping ions in the initial transition layer is greater than that in the second doping region, and the doping ions are N-type ions or P-type One of the ions, and the orthographic projection of the initial transition layer on the substrate covers the orthographic projection of the second doped region on the substrate.
  • the step of performing metallization on the initial bit line further includes: performing metallization on the initial transition layer.
  • the step of forming the first dielectric layer includes:
  • the initial first dielectric layer surrounds the sidewall of the semiconductor channel, and there is a fourth interval between the initial first dielectric layer on the sidewall of the adjacent semiconductor channel on the same initial bit line;
  • the first isolation layer fills the fourth gap, and the material of the first isolation layer is different from the material of the initial first dielectric layer;
  • the second isolation layer surrounds the sidewall of the second doped region and is located on the sidewall of the first isolation layer, the second isolation layer located on the sidewall of the second doped region and the first isolation layer located on the sidewall of the first isolation layer
  • the two isolation layers together form a through hole, the bottom of the through hole exposes the initial first dielectric layer, and the material of the second isolation layer is different from that of the initial first dielectric layer;
  • the initial first dielectric layer located on the sidewall of the channel region exposed by the through hole is removed, and the initial first dielectric layer remains as the first dielectric layer.
  • the step of forming the insulating layer includes:
  • Thermal oxidation treatment is performed on the exposed sidewall of the channel region to form an insulating layer, and the insulating layer covers the sidewall surface of the remaining channel region, and there is a fifth space between the insulating layer and the first isolation layer.
  • the step of forming the word line includes:
  • the initial word line is filled with the fifth interval and the through hole, and the initial word line is also located between the insulating layers of the sidewalls of the channel region adjacent to the initial bit line;
  • the initial word lines located in the through holes are removed, and the remaining initial word lines are used as word lines.
  • the step of forming the first dielectric layer includes:
  • the initial first dielectric layer surrounds the sidewall of the semiconductor channel, and there is a fourth interval between the initial first dielectric layer on the sidewall of the adjacent semiconductor channel on the same initial bit line;
  • the first isolation layer fills the fourth gap, and the material of the first isolation layer is different from the material of the initial first dielectric layer;
  • the step of forming the insulating layer and the second dielectric layer includes:
  • the protective layer of the sidewall of the channel region is an insulating layer, covering the second doped region
  • the protection layer on the sidewall of the impurity region is the second dielectric layer.
  • the step of forming the word line includes:
  • the initial word line fills the sixth interval, and the initial word line is also located between the protective layer on the sidewall of the semiconductor channel part adjacent to the initial bit line;
  • Part of the initial word line is removed, and the remaining initial word line is used as the word line, and the word line only surrounds the side wall of the insulating layer located on the side wall of the channel region.
  • 1 to 35 are schematic diagrams of semiconductor structures corresponding to each step in the method for forming a semiconductor structure provided by an embodiment of the present disclosure.
  • the implementation of the present disclosure provides a semiconductor structure and a manufacturing method thereof.
  • the semiconductor structure there is a vertical GAA transistor on the substrate, and the bit line is located between the substrate and the GAA transistor, so that a 3D stacked semiconductor structure can be formed, which is conducive to improving the semiconductor structure. integration density.
  • the material of the bit line includes a metal-semiconductor compound, it is beneficial to reduce the resistance of the bit line to improve the electrical performance of the semiconductor structure.
  • FIG. 1 is a schematic structural view of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of the structure shown in FIG. 1 along the first cross-sectional direction AA1
  • FIG. 3 is a schematic cross-sectional view of the structure shown in FIG.
  • FIG. 4 is a schematic cross-sectional view of the structure shown in FIG. 1 along a second cross-sectional direction BB1
  • FIG. 5 is another schematic structural view of a semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure includes: a substrate 11; a bit line 104, located on the substrate 11, and the material of the bit line 104 includes a metal semiconductor compound; a semiconductor channel 105, located on the surface of the bit line 104, directed along the base 11 In the direction Z of the bit line 104, the semiconductor channel 105 includes a first doped region I, a channel region II, and a second doped region III arranged in sequence, and the first doped region I is in contact with the bit line 104; the first dielectric Layer 113, covering the surface of the sidewall of the first doped region I, and having a first interval between the first dielectric layer 113 adjacent to the sidewall of the first doped region I on the same bit line 104; the insulating layer 106, covering the channel Area II side wall surface; word line 107, covering the side wall surface of the insulating layer 106 away from the channel area II, and there is a second interval between adjacent word lines 107; second dielectric layer 123, covering the second doped area II
  • the semiconductor structure includes vertical GAA transistors, and the bit line 104 is located between the substrate 11 and the GAA transistors, a 3D stacked storage device can be formed, which is beneficial to increase the integration density of the semiconductor structure.
  • the semiconductor structure will be described in more detail below with reference to FIG. 1 to FIG. 5 .
  • the material type of the substrate 11 may be an elemental semiconductor material or a crystalline inorganic compound semiconductor material.
  • the elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide or gallium indium.
  • the substrate 11 is doped with first type ions.
  • the substrate 11, the bit line 104 and the semiconductor channel 105 have the same semiconductor element, then the semiconductor channel 105 and the bit line 104 can be formed using the same film layer structure, the film layer structure is composed of semiconductor elements, The semiconductor channel 105 and the bit line 104 are integrated, thereby improving the interface state defects between the semiconductor channel 105 and the bit line 104 and improving the performance of the semiconductor structure.
  • the semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium.
  • both the bit line 104 and the semiconductor channel 105 include silicon.
  • the bit line and the semiconductor channel both include germanium, or both the bit line and the semiconductor channel include silicon and germanium, or both the bit line and the semiconductor channel include silicon and carbon, or the bit line Both the bit line and the semiconductor channel include arsenic and gallium elements, or both the bit line and the semiconductor channel include gallium and indium elements.
  • the material of the bit line 104 includes a metal-semiconductor compound 114, which has a relatively low resistivity compared to an unmetallized semiconductor material, and therefore, compared to the semiconductor channel 105, the The lower resistivity is beneficial to reduce the resistance of the bit line 104 and the contact resistance between the bit line 104 and the first doped region I, further improving the electrical performance of the semiconductor structure.
  • the resistivity of the bit line 104 is also smaller than the resistivity of the substrate 11 .
  • the material of the region of the bit line 104 directly below the first doped region I is a semiconductor material, and the material of a part of the region of the bit line 104 not covered by the first doped region I is a metal-semiconductor compound.
  • the material of a part of the bit line 104 directly below the first doped region I is a semiconductor material, and the material of the bit line 104 directly below the first doped region I
  • the material of the remaining regions may also be a metal-semiconductor compound, and the "remaining regions" here are located at the periphery of the "partial regions".
  • the plurality of metal-semiconductor compounds 114 in the same bit line 104 are spaced from each other; in yet another example, referring to FIG. 3 , the plurality of metal-semiconductor compounds 114 in the same bit line 104 are are connected to each other.
  • FIG. 3 only exemplifies the situation that the edges between adjacent metal-semiconductor compounds 114 are just in contact with each other to communicate. In actual situations, the area of mutual contact between adjacent metal-semiconductor compounds 114 can be larger. In this embodiment There is no limitation on the size of the area where adjacent metal-semiconductor compounds 114 are in contact with each other.
  • the material of the entire bit line can be metal-semiconductor compound.
  • the metal-semiconductor compound 114 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide or platinum silicide.
  • a plurality of bit lines 104 arranged at intervals can be formed on the substrate 11, and each bit line 104 can be in contact with at least one first doped region I. Spaced bit lines 104, and each bit line 104 is in contact with four first doped regions I.
  • the number of bit lines 104 and the number of bit lines 104 in contact with each bit line 104 can be reasonably set according to actual electrical requirements. - the number of doped regions I.
  • the bit line 104 is doped with the second type of ions
  • the substrate 11 is doped with the first type of ions
  • the second type of ions are different from the first type of ions
  • both the first type of ions and the second type of ions are N-type ions or one of P-type ions.
  • the bit line 104 and the substrate 11 form a PN junction, and the PN junction is beneficial to prevent the leakage of the bit line 104 and further improve the electrical performance of the semiconductor structure.
  • the substrate 11 may not be doped with the first type of ions.
  • N-type ions are at least one of arsenic ions, phosphorus ions or antimony ions;
  • P-type ions are at least one of boron ions, indium ions or gallium ions
  • the first doped region I, the channel region II and the second doped region III in the semiconductor channel 105 are doped with the same type of doping ions, that is, the second type of ions, and the doping
  • the doping concentration of ions in the first doped region I is the same as that in the channel region II and the second doped region III.
  • the device formed by the semiconductor channel 105 is a junctionless transistor (Junctionless Transistor), that is, the types of dopant ions in the first doped region I, the channel region II and the second doped region III are the same, for example, the doped ions are homogeneous For N-type ions, the dopant ions in the first doped region I, the channel region II and the second doped region III may be the same.
  • Junctionless transistor Junctionless Transistor
  • no junction here refers to no PN junction, that is, there is no PN junction in the transistor formed by the semiconductor channel 105, that is, the doped regions in the first doped region I, the channel region II and the second doped region III
  • the doping concentration of hetero ions is the same, and such benefits include: on the one hand, there is no need to perform additional doping on the first doped region I and the second doped region III, thereby avoiding the need for doping the first doped region I and the second doped region III
  • the doping process of the doped region III is difficult to control, especially as the size of the transistor is further reduced, if the first doped region I and the second doped region III are additionally doped, the doping concentration is more difficult to control;
  • the device is a junction-free transistor, it is beneficial to avoid the ultra-steep source-drain concentration gradient doping process and the phenomenon of making an ultra-steep PN junction in the nanoscale range, thus avoiding the threshold voltage drift and Problems such as
  • the doping concentration of the second type ions in the semiconductor channel 105 is 1 ⁇ 10 19 atom/cm 3 to 1 ⁇ 10 20 atom/cm 3 , and the direction Z along the substrate 11 to the bit line 104 , the height of the semiconductor channel 105 is 100nm-150nm, and the heights of the first doped region I, the channel region II and the second doped region III are all 30nm-50nm.
  • the orthographic projection of the channel region II on the substrate 11 is smaller than the orthographic projection of the second doped region III on the substrate 11, and smaller than the orthographic projection of the first doped region I on the substrate 11.
  • the cross-section of the bit line 104 pointing to the direction Z of the semiconductor channel 105 it is beneficial to form the channel region II with a smaller cross-sectional area, and it is beneficial to improve the control ability of the subsequently formed word line on the channel region II, so that it is easier to control the GAA transistor. on or off.
  • the orthographic projections of the first doped region, the channel region, and the second doped region on the substrate can be equal; or, the orthographic projections of the channel region and the second doped region on the substrate are smaller than the first doped region. Orthographic projection of a doped region on a substrate.
  • both the width W of the channel region II and the length L of the channel region II are not higher than 10 nm, which is beneficial to ensure that the subsequently formed word line has a good effect on the channel region II. control ability.
  • the first dielectric layer 113 may include a fourth dielectric layer 143 and a fifth dielectric layer 153, the fourth dielectric layer 143 is located in the interval between the adjacent bit lines 104, and is located in the adjacent first doped regions on the adjacent bit lines 104 In the interval of I; the fifth dielectric layer 153 is located on the sidewall of the adjacent first doped region I on the same bit line 104, and is located on the sidewall of the fourth dielectric layer 143.
  • the first dielectric layer 113 is used to realize electrical insulation between adjacent semiconductor channels 105 and adjacent bit lines 104 .
  • the material of the fourth dielectric layer 143 and the material of the fifth dielectric layer 153 are the same, and the material of the fourth dielectric layer 143 and the material of the fifth dielectric layer 153 may both be silicon oxide. In other embodiments, the material of the fourth dielectric layer and the material of the fifth dielectric layer may also be different, as long as the material of the fourth dielectric layer and the material of the fifth dielectric layer are materials with good insulation effect.
  • the orthographic projection of the periphery of the insulating layer 106 on the substrate 11 is smaller than the orthographic projection of the periphery of the second dielectric layer 123 on the substrate 11, that is, with reference to FIGS. 2 and 4, the insulating layer 106 is far away from the outer wall of the semiconductor channel 105 Compared with the second dielectric layer 123 , it is farther away from the outer wall of the semiconductor channel 105 and is closer to the semiconductor channel 105 . In addition, the insulating layer 106 is farther away from the outer wall of the semiconductor channel 105 than the first dielectric layer 113 is farther away from the outer wall of the semiconductor channel 105 , and is also closer to the semiconductor channel 105 . Wherein, the material of the insulating layer 106 is silicon oxide.
  • the insulating layer and the second dielectric layer may have the same film structure, that is, the insulating layer and the second dielectric layer may be formed through the same process step.
  • the material of the insulating layer and the material of the second dielectric layer include at least one of silicon oxide or silicon nitride.
  • the first compartment, the second compartment and the third compartment are connected to each other.
  • the orthographic projections of the first interval and the second interval on the substrate 11 coincide, the third dielectric layer 133 fills the first interval, the second interval and the third interval, and the third The top surface of the dielectric layer 133 away from the base 11 is higher than the top surface of the second doped region III away from the base 11 .
  • gaps 109 in the third dielectric layer 133 located in the second interval that is, there are gaps 109 besides the third dielectric layer 133 between adjacent word lines 107, which is beneficial to reduce the The capacitance generated between adjacent word lines 107 is used to improve the electrical characteristics of the semiconductor structure.
  • voids may exist not only in the third dielectric layer located in the second space, but also in the third dielectric layer located in the first space, or in the third dielectric layer located in the third space. layer.
  • the semiconductor structure may further include: a metal contact layer 108 located on the top surface of the second doped region III away from the substrate 11 , and the metal semiconductor compound 114 and the metal contact layer 108 have the same metal element.
  • the metal element includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum.
  • the metal contact layer 108 Since there are metal elements in the metal contact layer 108, when the lower electrode of the capacitive structure is subsequently formed on the metal contact layer 108, the metal contact layer 108 forms an ohmic contact with the lower electrode, avoiding the direct contact between the lower electrode and the semiconductor material to form a Schottky potential
  • the barrier contact and the ohmic contact are beneficial to reduce the contact resistance between the second doped region III and the lower electrode, thereby reducing the energy consumption of the semiconductor structure during operation, and improving the RC delay effect to improve the electrical performance of the semiconductor structure.
  • the metal contact layer 108 and the metal-semiconductor compound 114 have the same metal element, which is beneficial to form the metal contact layer 108 and the metal-semiconductor compound 114 in the bit line 104 in one process step. .
  • the orthographic projection of the metal contact layer 108 on the substrate 11 covers the orthographic projection of the second doped region III on the substrate 11, which is beneficial to increase the contact between the metal contact layer 108 and the lower electrode. area, thereby reducing the contact resistance between the metal contact layer 108 and the bottom electrode, so as to improve the electrical performance of the semiconductor structure.
  • the semiconductor structure may further include: a transition layer 118, located between the second doped region III and the metal contact layer 108, and the transition layer 118 is located on a part of the top surface of the second doped region III, and the metal contact layer 108 wraps the transition layer 118
  • the transition layer 118 and the second doped region III are doped with the same type of dopant ions, and the doping concentration of the dopant ions in the transition layer 118 is greater than that in the second doped region III, Then the resistance of the transition layer 118 is smaller than the resistance of the second doped region III, which is beneficial to further reduce the transmission resistance between the second doped region III and the bottom electrode.
  • the semiconductor structure may not include a transition layer, and the top surface of the second doped region only has a metal contact layer.
  • the semiconductor structure may further include: a capacitor structure (not shown in the figure), and the capacitor structure is located on the surface jointly formed by the metal contact layer 108 and the third dielectric layer 133 .
  • the bit line 104 is located between the substrate 11 and the GAA transistors, so a 3D stacked semiconductor structure can be formed, which is beneficial to increase the integration density of the semiconductor structure.
  • the material of the bit line 104 includes metal-semiconductor compound 114, which is beneficial to reduce the resistance of the bit line 104, so as to reduce the contact resistance between the bit line 104 and the first doped region I, and further improve the electrical performance of the semiconductor structure.
  • the device formed by the semiconductor channel 105 is a junctionless transistor, which is beneficial to avoid the use of an ultra-steep source-drain concentration gradient doping process, so that problems such as threshold voltage drift and leakage current increase caused by doping mutations can be avoided, and it is also beneficial to suppress The short channel effect further improves the integration density and electrical performance of the semiconductor structure.
  • another embodiment of the present disclosure also provides a method for fabricating a semiconductor structure, which can be used to form the above-mentioned semiconductor structure.
  • FIGS. 1 to 35 are schematic cross-sectional structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.
  • the method for manufacturing a semiconductor structure provided by this embodiment will be described in detail below in conjunction with the accompanying drawings.
  • the parts that are the same as or corresponding to the examples will not be described in detail below.
  • a substrate 11 is provided; an initial bit line 124 is formed on the substrate 11, and a semiconductor channel 105 is formed on a surface of the initial bit line 124 away from the substrate 11;
  • the semiconductor channel 105 includes a first doped region I, a channel region II and a second doped region III arranged in sequence.
  • Providing the substrate 11 and forming the initial bit line 124 on the substrate 11 surrounding the semiconductor channel 105 includes the following steps:
  • a substrate 110 is provided, and the material type of the substrate 110 may be an elemental semiconductor material or a crystalline inorganic compound semiconductor material.
  • the elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide or gallium indium.
  • the substrate 110 includes: a base 11 doped with first type ions; and an initial semiconductor layer 10 disposed on the base 11 .
  • the initial semiconductor layer 10 is doped with the second type of ions for subsequent etching of the initial semiconductor layer 10 to form the initial bit line 124 and the semiconductor channel 105, and the second
  • the type ions are different from the first type ions, and both the first type ions and the second type ions are either N-type ions or P-type ions.
  • the doping treatment may adopt high-temperature diffusion or ion implantation, and after the initial semiconductor layer 10 is doped by ion implantation, the annealing temperature of the annealing treatment is 800°C-1000°C.
  • the doping concentration of the second-type ions in the initial semiconductor layer 10 is 1 ⁇ 10 19 atom/cm 3 to 1 ⁇ 10 20 atom/cm 3 , and the direction in which the initial semiconductor layer 10 points to the substrate 11
  • the doping depth of the second type ions in the initial semiconductor layer 10 is 150nm-250nm.
  • the first type of ions are P-type ions
  • the second type of ions are N-type ions.
  • the first type of ions may be N-type ions
  • the second type of ions may be P-type ions.
  • a buffer layer 120 and a barrier layer 130 are sequentially stacked on the side of the initial semiconductor layer 10 away from the substrate 11 .
  • the buffer layer 120 and the barrier layer 130 can be formed by a deposition process
  • the material of the buffer layer 120 is silicon oxide
  • the material of the barrier layer 130 is silicon nitride.
  • silicon nitride can be deposited by a chemical vapor deposition process to form the barrier layer 130.
  • the oxidation speed of the silicon nitride film layer is very slow, which is beneficial to protect the substrate 100 located under the silicon nitride film layer. , to prevent the substrate 100 from being oxidized.
  • the substrate 110 is a silicon substrate. Since the lattice constant and thermal expansion coefficient of silicon nitride have a large mismatch rate with the lattice constant and thermal expansion coefficient of the silicon substrate, if the silicon substrate Silicon nitride is directly formed, and the interface between silicon nitride and silicon has a high defect density, which is easy to become a carrier trap and recombination center, affecting the carrier mobility of silicon, thereby affecting the performance and working life of the semiconductor structure. Moreover, the stress of the silicon nitride film is relatively high, and it is easy to crack when it is directly deposited on the silicon substrate. Therefore, forming silicon oxide as the buffer layer 120 before depositing silicon nitride on the silicon substrate is beneficial to improve the performance and working life of the semiconductor structure.
  • the first mask layer 102 is formed on the barrier layer 130, the first mask layer 102 has a plurality of mutually separated first openings b, and along the extending direction X of the first openings b, the first openings
  • the length of b is the same as the length of the subsequently formed bit line.
  • the barrier layer 130 , the buffer layer 120 and the initial semiconductor layer 10 are etched using the first mask layer 102 as a mask to form a plurality of first trenches a, and the first mask layer 102 is removed.
  • the depth of the first trench a is 250-300 nm. Since the depth of the first trench a is greater than the doping depth of the second type of ions in the initial semiconductor layer 10, it is beneficial to ensure that the initial semiconductor layer 10 doped with the second type of ions is all etched, which facilitates the subsequent formation of the second type of ions Highly doped semiconductor channels and bit lines.
  • a fourth dielectric layer 143 is formed in the first trench a.
  • the fourth dielectric layer 143 can be formed by the following process steps: performing a deposition process to form a fourth dielectric film covering the top surface of the barrier layer 130 and filling the first trench a; planarization until the top surface of the barrier layer 130 is exposed, leaving the fourth dielectric film as the fourth dielectric layer 143 .
  • the material of the fourth dielectric film includes silicon oxide.
  • the second mask layer 112 is formed on the top surface of the fourth dielectric layer 143 and the remaining substrate 110, and the second mask layer 112 has a plurality of mutually separated second openings c , in the extending direction Y along the second opening c, the length of the second opening c is consistent with the length of the subsequently formed word line.
  • the extension direction X of the first opening b is perpendicular to the extension direction Y of the second opening c, so that the finally formed semiconductor channels 105 present a 4F2 arrangement, which is beneficial to further improve Integration density of semiconductor structures.
  • the extension direction of the first opening intersects with the extension direction of the second opening, and the angle between them may not be 90°.
  • the ratio of the opening width of the first opening b along the direction Y to the opening width of the second opening c along the direction X is 2-1, so as to ensure that the exposed surrounding channel region II can be formed subsequently.
  • the through hole of the first dielectric layer on the sidewall is beneficial to the subsequent formation of the first gap for manufacturing the word line.
  • the opening width of the first opening b along the direction Y is equal to the opening width of the second opening c along the direction X
  • the distance between adjacent first openings b is equal to the distance between adjacent second openings c
  • the methods for forming the first mask layer 102 and the second mask layer 112 both include self-aligned multiple exposure technique (SAQP, Self-Aligned Quadruple Patterning) or self-aligned multiple imaging technique (SADP, Self-Aligned Quadruple Patterning). -Aligned Double Patterning).
  • SAQP Self-Aligned Quadruple Patterning
  • SADP Self-Aligned Quadruple Patterning
  • -Aligned Double Patterning -Aligned Double Patterning
  • the initial semiconductor layer 10 (refer to FIG. 6) and the fourth dielectric layer 143 are etched using the second mask layer 112 as a mask to form a plurality of second trenches d, initial bit lines 124 and semiconductor channels 105, And in the direction Z perpendicular to the surface of the substrate 11, the depth of the second trench d is smaller than the depth of the first trench a, which is conducive to forming the initial bit line 124 and at the side of the initial bit line 124 away from the substrate 11 A plurality of semiconductor channels 105 separated from each other are formed, and the initial bit line 124 is in contact with the first doped region I of the semiconductor channels 105; the second mask layer 112 is removed.
  • the depth of the second trench d is 100nm-150nm, since the doping depth of the second-type ions in the initial semiconductor layer 10 is 150nm-250nm, it is beneficial to make most or all of the second-type ions doped.
  • the initial semiconductor layer 10 is transformed into a semiconductor channel 105 after two times of etching.
  • the material of the substrate 110 is silicon
  • the material of the fourth dielectric layer 143 is silicon oxide.
  • etching The etch rate of silicon oxide is greater than that of silicon, so part of the sidewall of initial bit line 124 will be exposed.
  • the remaining fourth dielectric layer 143 is also in the space between adjacent initial bit lines 124 , and in the space between adjacent semiconductor channels 105 .
  • the doping ions in the first doping region I, the channel region II and the second doping region III are of the same type, for example, the doping ions are all N-type ions, and the first doping region I, the channel region II and the second doping region
  • the doping concentration of the doping ions in the second doping region III is the same, that is, the device formed by the semiconductor channel 105 is a junctionless transistor.
  • Doping ions in the first doped region I, the channel region II and the second doped region III may be the same.
  • the channel effect can still work in the scale of several nanometers, thus helping to further improve the integration density and electrical performance of semiconductor structures.
  • the additional doping here refers to the doping performed to make the doping ion types of the first doping region I and the second doping region III different from the doping ion type of the channel region II.
  • forming a GAA transistor whose semiconductor channel 105 is perpendicular to the initial bit line 124 and away from the top surface of the substrate 11 can constitute a 3D stacked semiconductor structure, which is beneficial to the premise of not adversely affecting the electrical performance of the GAA transistor.
  • GAA transistors with smaller size features are designed to increase the integration density of semiconductor structures.
  • the initial bit line 124 and the semiconductor channel 105 are formed simultaneously through two etching processes.
  • the size of the second opening c regulates the size of the semiconductor channel 105, and forms a semiconductor channel 105 with high dimensional accuracy;
  • the line 124 and the semiconductor channel 105 are formed using the same film layer structure, so that the initial bit line 124 and the semiconductor channel 105 are integrated, thereby improving the interface state defects between the initial bit line 124 and the semiconductor channel 105 and improving the performance of the semiconductor structure.
  • a fourth dielectric layer 143 is also formed in the first trench a, which is used for the subsequent sidewalls of the channel region II and the first isolation Gaps are formed between the layers for preliminary preparations, which facilitates the subsequent formation of the first gaps for preparing word lines.
  • the first dielectric layer 113 covering the surface of the sidewall of the first doped region I is formed, and the first dielectric layer 113 on the sidewall of the adjacent first doped region I on the same initial bit line 124 Have a first interval; form an insulating layer 106 covering the sidewall surface of the channel region II; form a word line 107 covering the insulating layer 106 away from the sidewall surface of the channel region II, and have a second interval between adjacent word lines 107 ; form the second dielectric layer 123 covering the sidewall surface of the second doped region III, and have a third interval between the second dielectric layer 123 adjacent to the sidewall of the second doped region III, the first interval, the second The spacer is connected to the third spacer and exposes a part of the initial bit line 124 ; the exposed initial bit line 124 is metallized to form the bit line 104 , and the material of the bit line 104 includes the metal semiconductor compound 114 .
  • FIG. 12 is a schematic cross-sectional view of the structure shown in FIG. 11 along the first cross-sectional direction AA1
  • FIG. 13 is a schematic cross-sectional view of the structure shown in FIG. 11 along the second cross-sectional direction BB1.
  • one or both of the schematic cross-sectional view along the first cross-sectional direction AA1 and the schematic cross-sectional view along the second cross-sectional direction BB1 will be set according to the needs of the expression.
  • the drawing is along the first cross-sectional direction AA1
  • the drawing is first a schematic cross-sectional view along the first cross-sectional direction AA1, and secondly a schematic cross-sectional view along the second cross-sectional direction BB1.
  • forming the first dielectric layer 113, the insulating layer 106, the word line 107 and the second dielectric layer 123 includes the following steps:
  • an initial first dielectric layer 113a is formed, the initial first dielectric layer 113a surrounds the sidewall of the semiconductor channel 105, and the initial first dielectric layer 113a located on the sidewall of the adjacent semiconductor channel 105 on the same initial bit line 124 There is a fourth interval e between them.
  • a fifth dielectric film 103 is formed, and the fifth dielectric film 103 conformally covers the sidewall and bottom of the second trench d (refer to FIG. 9), and is also located on the top surface of the barrier layer 130 and the fourth dielectric layer 143 .
  • a maskless dry etching process is performed on the fifth dielectric film 103 until the barrier layer 130 is exposed, and different regions of the fifth dielectric film 103 are etched by the etching process within the same etching time. have the same thickness to form the fifth dielectric layer 153 .
  • the fourth dielectric layer 143 is located on the sidewall of the second trench d (refer to FIG. 9), the fourth dielectric layer 143 is located in the interval between adjacent semiconductor channels 105, the fourth dielectric layer 143 and the The five dielectric layers 153 together form the initial first dielectric layer 113a, and there is a fourth interval e between the fifth dielectric layers 153 located on the sidewall of the second trench d.
  • the material of the fourth dielectric layer 143 is the same as that of the fifth dielectric layer 153, so that the fourth dielectric layer 143 and the fifth dielectric layer 153 corresponding to the sidewall of the channel region II can be removed together by subsequent etching process, so that A gap is formed between the sidewall of the channel region II and the subsequently formed first isolation layer, thereby facilitating the subsequent formation of a gap for preparing a word line.
  • the material of the fourth dielectric layer 143 and the material of the fifth dielectric layer 153 are silicon oxide.
  • the material of the fourth dielectric layer and the material of the fifth dielectric layer can also be different, as long as the material of the fourth dielectric layer and the material of the fifth dielectric layer are materials with good insulation effect, then the The fourth dielectric layer and the fifth dielectric layer corresponding to the sidewall of the channel region are removed step by step.
  • a first isolation layer 163 is formed, the first isolation layer 163 fills the fourth space e, and the material of the first isolation layer 163 is different from that of the initial first dielectric layer 113a.
  • the first isolation layer 163 can be formed by the following process steps: performing a deposition process to form a first isolation film covering the top surface of the barrier layer 130 and filling the fourth space e; for the first isolation film, barrier layer 130, buffer layer 120 and The initial first dielectric layer 113 a is chemically mechanically planarized to expose the top surface of the second doped region III, leaving the first isolation film as the first isolation layer 163 .
  • the material of the first isolation film includes silicon nitride.
  • a portion of the initial first dielectric layer 113 a is etched to expose the sidewall of the second doped region III.
  • FIG. 17 is a schematic top view of FIG. 16
  • FIG. 18 is a schematic cross-sectional view along the third cross-sectional direction CC1
  • FIG. 19 is a schematic cross-sectional view along the second cross-sectional direction BB1 .
  • the second isolation layer 173 surrounds the sidewall of the second doped region III and is located on the sidewall of the first isolation layer 163, the second isolation layer 173 located on the sidewall of the second doped region III and is located on the first The second isolation layer 173 on the sidewall of the isolation layer 163 together forms a through hole f, and the bottom of the through hole f exposes the initial first dielectric layer 113a, and the material of the second isolation layer 173 is different from that of the initial first dielectric layer 113a.
  • the second isolation layer 173 covers the top surface of the fifth dielectric layer 153 and part of the top surface of the fourth dielectric layer 143 while surrounding the sidewall of the second doped region III.
  • the through hole f exposes part of the top surface of the fourth dielectric layer 143 .
  • the following process steps can be used to form the second isolation layer 173: performing a deposition process to form a second isolation layer that conformally covers the surface composed of the semiconductor channel 105, the initial first dielectric layer 113a, and the first isolation layer 163. film; perform a maskless dry etching process on the second isolation film until the top surface of the second doped region III is exposed, and use the same etching time to etch different regions of the second isolation film to have the same thickness , forming the second isolation layer 173 exposing the first isolation layer 163 .
  • the material of the second isolation layer 173 includes silicon nitride.
  • the ratio of the opening width of the first opening b along the direction Y to the opening width of the second opening c along the direction X is 2-1,
  • the gaps between the channels 105 are filled, so as to ensure the formation of a through hole f exposing part of the top surface of the fourth dielectric layer 143 , which facilitates subsequent removal of part of the initial first dielectric layer 113a by using the through hole f.
  • the initial first dielectric layer 113 a located on the sidewall of the channel region II exposed by the through hole f is removed, and the initial first dielectric layer 113 a remains as the first dielectric layer 113 .
  • the etching can be injected into the through hole f. liquid, remove the first dielectric layer 113 located on the sidewall of the channel region II by wet etching process, and retain the first dielectric layer 113 located on the sidewall of the first doped region I.
  • the first isolation layer 163 and the second isolation layer 173 together form a supporting frame, the supporting frame is in contact with the second doped region III, and part of the supporting frame is embedded in the first dielectric layer 113 .
  • the support frame has the function of supporting and fixing the semiconductor channel 105, and when the etching liquid flows, it generates a squeezing force on the semiconductor channel 105, which is beneficial to avoid the semiconductor channel 105 from being damaged.
  • the extrusion is tilted or shifted to improve the stability of the semiconductor structure; on the other hand, the supporting frame wraps the sidewall of the second doped region III, which is beneficial to avoid the etching solution from damaging the second doped region III.
  • a second gap g is formed between the channel region II and the first isolation layer 163, and the through hole f and the second gap g together form a cave structure h.
  • the exposed channel region II sidewall is thermally oxidized to form an insulating layer 106, and the insulating layer 106 covers the sidewall surface of the remaining channel region II, and the insulating layer 106 and the first isolation layer 163 with a fifth interval i between them.
  • the fifth interval i is also located between the insulating layer 106 of the sidewall of the adjacent semiconductor channel 105 adjacent to the initial bit line 124 .
  • the top surface of the second doped region III is also exposed, and a part of the second doped region III near the top surface and a part of the channel region II are transformed into an insulating layer 106,
  • Making the orthographic projection of the channel region II on the substrate 11 smaller than the orthographic projection of the second doped region III on the substrate 11, and smaller than the orthographic projection of the first doped region I on the substrate 11, is conducive to Under the premise of the process, the channel region II with a smaller cross-sectional area is formed in the cross section perpendicular to the direction Z of the initial bit line 124 pointing to the semiconductor channel 105, which is beneficial to improve the ability of the subsequently formed word line to control the channel region II , so that it is easier to control the turn-on or turn-off of the GAA transistor.
  • the material of the insulating layer 106 is silicon oxide.
  • the insulating layer covering the surface of the sidewall of the channel region may also be formed by a deposition process.
  • the insulating layer 106 located on the top surface of the remaining second doped region III is removed in subsequent process steps.
  • the insulating layer located on the top surface of the remaining second doped region may be removed after the thermal oxidation treatment, and only the insulating layer covering the sidewall surface of the remaining channel region remains.
  • the orthographic projection of the periphery of the insulating layer 106 on the substrate 11 is smaller than the orthographic projection of the periphery of the second isolation layer 173 on the substrate 11, that is, the insulating layer 106 is farther away from the outer wall of the semiconductor channel 105 than the outer wall of the second isolation layer 173.
  • the second isolation layer 173 is far away from the outer wall of the semiconductor channel 105, and is closer to the semiconductor channel 105, thereby ensuring that there is a fifth interval i between the insulating layer 106 and the first isolation layer 163, so that the subsequent word line can surround the insulating layer positioned at the side wall of the channel region II.
  • Layer 106 is farther away from the outer wall of the semiconductor channel 105 than the first dielectric layer 113 (refer to FIG. 20 ), and may be closer to the semiconductor channel 105 .
  • an initial word line is formed, the initial word line fills the fifth interval i and the via f, and the initial word line is also located on the insulating layer 106 of the sidewall of the channel region II on the adjacent initial bit line 124 Between; the initial word line located in the through hole f is removed, and the remaining initial word line is used as the word line 107 .
  • the initial word line may be formed by a deposition process, and the material of the initial word line includes at least one of polysilicon, titanium nitride, tantalum nitride, copper or tungsten.
  • the initial word line is self-aligned and filled with the cavity structure h (refer to FIG. 20 ). After removing the initial word line in the through hole f, it is beneficial to self-align to form the word line 107 with precise size, without the need of etching process. Designing the size of the word line 107 is beneficial to simplify the steps of forming the word line 107, and by adjusting the size of the fifth interval i, a small-sized word line 107 can be obtained.
  • a third isolation layer 183 is further formed, and the third isolation layer 183 fills the via hole f (refer to FIG. 26).
  • the following process steps can be used to form the third isolation layer 183: performing a deposition process to form a third isolation film covering the top surface of the insulating layer 106 located on the top surface of the second doped region III and filling the through hole f Perform chemical mechanical planarization on the third isolation film until the top surface of the insulating layer 106 is exposed, leaving the third isolation film as the third isolation layer 183 ;
  • the material of the third isolation film is the same as that of the first isolation layer and the second isolation layer, including silicon nitride.
  • chemical mechanical planarization can also be performed on the third isolation film to expose the top surface of the second doped region, that is, the insulating layer on the top surface of the second doped region is removed simultaneously, and the third isolation film remains as third isolation layer.
  • the insulating layer 106 located on the top surface of the second doped region III is removed, and an initial transition layer 128 is formed on the top surface of the second doped region III by using an epitaxial growth process, and the initial transition layer 128 on the substrate 11
  • the orthographic projection covers the orthographic projection of the second doped region III on the substrate 11 .
  • the initial transition layer 128 is also doped with the same type of dopant ions as in the second doped region III, and the doping concentration of the dopant ions in the initial transition layer 128 is higher than that in the If the doping concentration in the second doped region III is lower, the resistance of the initial transition layer 128 is smaller than the resistance of the second doped region III.
  • using the epitaxial growth process is beneficial to improve the continuity between the second doped region III and the initial transition layer 128, reduce contact defects caused by different lattice properties or lattice dislocations, and reduce contact defects caused by contact defects. resistance, improve the transport capability and moving speed of carriers, and then improve the conductivity between the second doped region III and the initial transition layer 128, and reduce the heat generation during the operation of the semiconductor structure; on the other hand, the epitaxial growth process is adopted It is beneficial to increase the orthographic projection of the initial transition layer 128 on the substrate 11, and it is beneficial to make the orthographic projection area of the initial transition layer 128 on the substrate 11 larger than the orthographic projection area of the second doped region III on the substrate 11, which can be used as mask to prevent the second dielectric layer surrounding the sidewall of the second doped region III from being etched to expose the second doped region III, so as to ensure good protection of the second doped region III by the subsequently formed second dielectric layer Effect.
  • the orthographic projection of the initial transition layer 128 on the substrate 11 covers the orthographic projection of the second doped region III on the substrate 11 , which is beneficial to avoid etching damage to the semiconductor channel 105 in this step.
  • a second dielectric film is formed to conformally cover the surface of the initial transition layer 128, the sidewall of the second doped region III, the top surface of the word line 107, and the top surface of the first isolation layer 163 (referring to FIG. 29); for the second
  • the dielectric film is chemically mechanically planarized until the surface of the initial transition layer 128 is exposed, and the remaining second dielectric layer 123 is etched with the initial transition layer 128 as a mask.
  • the area of the orthographic projection of the doped region III on the substrate 11 helps to remove the second dielectric film positioned on the surface of the initial transition layer 128, the top surface of the first isolation layer 163, and the top surface of the part of the word line 107, while avoiding the difference with the initial transition layer.
  • the second dielectric film facing the orthographic projection of layer 128 on the substrate 11 is etched, thereby forming the second dielectric layer 123 surrounding the sidewall of the second doped region III, to ensure that the second dielectric layer 123 is doped to the second Zone III good protective effect.
  • a deposition process may be used to form the second dielectric film.
  • the remaining first isolation layer 163 is removed to expose the top surface of the initial bit line 124 .
  • the first isolation layer, the second isolation layer, and the third isolation layer are etched using the initial transition layer as a mask to expose the initial bit line and the sidewall of the second doped region; and then the exposed The sidewall of the second doped region is thermally oxidized to form a second dielectric layer.
  • the exposed initial bit line 124 and the initial transition layer 128 are metallized to form the bit line 104 , and the material of the bit line 104 includes the metal-semiconductor compound 114 .
  • a metal layer is formed on the surface of the initial transition layer 128 and the top surface of the initial bit line 124, and the metal layer provides metal elements for the subsequent formation of the bit line; surface.
  • the material of the metal layer includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum.
  • Annealing is performed to convert a portion of the thickness of the initial transition layer 128 into the metal contact layer 108 and a portion of the thickness of the initial bit line 124 (see FIG. 30 ) into the bit line 104 .
  • bit line 104 After forming the bit line 104, the remaining metal layer is removed.
  • the metal layer reacts with the initial transition layer 128 and the initial bit line 124, and part of the thickness of the initial transition layer 128 is converted into the metal contact layer 108, and part of the thickness of the initial bit line 124 is converted into bit line 104 .
  • the plurality of metal-semiconductor compounds 114 in the same bit line 104 are spaced from each other; in yet another example, referring to FIG. 3 , the plurality of metal-semiconductor compounds 114 in the same bit line 104 are interconnected.
  • the full thickness of the initial transition layer may be converted to a metal contact layer, and the full thickness of the initial bit line may be converted to bits.
  • the insulating layer located on the top surface of the second doped region is not removed first, and only the initial bit line is subsequently metallized to form a bit line Afterwards, the insulating layer located on the top surface of the second doped region is removed.
  • a third dielectric layer 133 is formed, and the third dielectric layer 133 fills the first interval between adjacent first dielectric layers 113 and the second interval between adjacent word lines 107 And the third interval between adjacent second dielectric layers 123 is used to realize electrical insulation between adjacent semiconductor channels 105 and adjacent word lines 107 .
  • the third dielectric layer 133 located in the second space may further have a void.
  • forming the first dielectric layer 113, the insulating layer 106, the word line 107 and the second dielectric layer 123 includes the following steps:
  • an initial first dielectric layer 113a is formed, the initial first dielectric layer 113a surrounds the sidewall of the semiconductor channel 105, and the initial first dielectric layer 113a located on the sidewall of the adjacent semiconductor channel 105 on the same initial bit line 124 There is a fourth interval e between them; the first isolation layer 163 is formed, the first isolation layer 163 fills the fourth interval e, and the material of the first isolation layer 163 is different from that of the initial first dielectric layer 113a.
  • the steps of forming the initial first dielectric layer 113a and the first isolation layer 163 are the same as the above example, and will not be repeated here.
  • a portion of the initial first dielectric layer 113 a (refer to FIG. 14 ) is etched to expose the sidewalls of the second doped region III and the channel region II, leaving the initial first dielectric layer 113 a as the first dielectric layer 113 .
  • a protective layer 116 covering the sidewalls of the second doped region III and the sidewalls of the channel region II is formed, and there is a sixth interval k between the protective layer 116 and the first isolation layer 163, and the channel region
  • the protective layer 116 on the sidewall of II is the insulating layer 106
  • the protective layer 116 covering the sidewall of the second doped region III is the second dielectric layer 123 .
  • the sixth space k is also located between the protection layers 116 of the sidewalls of the adjacent semiconductor channels 105 adjacent to the initial bit lines 124 .
  • the material of the semiconductor channel 105 is silicon
  • the forming step of the protective layer 116 includes: thermally oxidizing the exposed sidewalls of the channel region II and the sidewalls and top surfaces of the second doped region III, so as to protect The layer 116 covers the sidewall surfaces of the remaining channel region II and the remaining second doped region III, and covers the top surface of the remaining second doped region III.
  • the protection layer covering the sidewalls of the channel region and the sidewalls and top surface of the second doped region may also be formed by a deposition process.
  • the partial regions of the channel region II and the second doped region III are converted into the protective layer 116, so that the channel region II and the second doped region III
  • the orthographic projections of the second doped region III on the substrate 11 are all smaller than the orthographic projections of the first doped region I on the substrate 11, which is conducive to forming a region perpendicular to the initial bit line 124 under the premise of not using an etching process.
  • the channel region II and the second doped region III with a smaller cross-sectional area are conducive to improving the ability of the subsequently formed word line to control the channel region II, thereby making it easier to control the GAA transistor on or off.
  • the protection layer 116 located on the top surface of the remaining second doped region III is removed in subsequent process steps.
  • the protective layer on the top surface of the remaining second doped region may be removed after the thermal oxidation treatment, leaving only the protective layer covering the remaining channel region and the sidewall surface of the remaining second doped region.
  • an initial word line is formed, the initial word line fills the sixth interval k, and the initial word line is also located between the protective layer 116 on the sidewall of the semiconductor channel 105 on the adjacent initial bit line 124; A part of the initial word line, the rest of the initial word line is used as the word line 107, and the word line 107 only surrounds the sidewall of the insulating layer 106 located on the sidewall of the channel region II.
  • the initial word line may be formed by a deposition process, and the material of the initial word line includes at least one of polysilicon, titanium nitride, tantalum nitride, copper or tungsten.
  • the initial word line fills the sixth space k in a self-aligned manner, which is conducive to forming word lines 107 with precise dimensions in a self-aligned manner.
  • the steps of forming the third isolation layer, forming the initial transition layer, metallizing the initial transition layer and the initial bit line to form the metal contact layer and the bit line, and forming the third dielectric layer are the same as the above example , which will not be described here.
  • a capacitor structure (not shown in the figure) is formed on the surface jointly formed by the metal contact layer 108 and the third dielectric layer 133 .
  • the metal contact layer may not be formed, and after removing the insulating layer located on the top surface of the second doped region, the capacitor structure is directly formed on the surface jointly formed by the second doped region and the third dielectric layer.
  • the first dielectric layer 113 is etched using the second dielectric layer 123 as a mask to form a cavity structure of a specific shape; using a deposition process, Forming word lines 107 with precise dimensions in the cavity structure by self-alignment does not require an etching process to design the size of the word lines 107, which is conducive to simplifying the formation steps of the word lines 107, and by adjusting the size of the cavity structure, it can be obtained Small-sized word lines 107 .
  • performing metallization treatment on the initial bit line 124 and the initial transition layer 128 is beneficial to reduce the resistance of the finally formed bit line 104 and the metal contact layer 108, so that an ohmic contact is formed between the metal contact layer 108 and the capacitance structure, avoiding capacitance.
  • the structure is in direct contact with the semiconductor material to form a Schottky barrier contact, which is beneficial to reduce the contact resistance between the second doped region III and the capacitor structure, thereby reducing the energy consumption of the semiconductor structure during operation, so as to improve the electrical performance of the semiconductor structure .
  • the bit line is located between the substrate and the GAA transistors, so a 3D stacked semiconductor structure can be formed, which is beneficial to improve the integration density of the semiconductor structure.
  • the material of the bit line includes a metal-semiconductor compound, it is beneficial to reduce the resistance of the bit line to improve the electrical performance of the semiconductor structure.

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Abstract

本公开实施例提供一种半导体结构及其制作方法，其中，半导体结构包括：基底；位线，位于基底上，且位线的材料包括金属半导体化合物；半导体通道，包括依次排列的第一掺杂区、沟道区以及第二掺杂区，第一掺杂区与位线相接触；第一介质层，覆盖第一掺杂区侧壁表面，且同一位线上相邻第一掺杂区侧壁的第一介质层之间具有第一间隔；绝缘层，覆盖沟道区侧壁表面；字线，覆盖绝缘层远离沟道区的侧壁表面，且相邻字线之间具有第二间隔；第二介质层，覆盖第二掺杂区侧壁表面，且位于相邻第二掺杂区侧壁的第二介质层之间具有第三间隔；第三介质层，位于第一间隔、第二间隔和第三间隔中。

Description

半导体结构及其制作方法
本公开要求在2021年07月01日提交中国专利局、申请号为202110746050.4、发明名称为“半导体结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开包括但不限于一种半导体结构及其制作方法。
背景技术
随着动态存储器的集成密度朝着更高的方向发展，在对动态存储器阵列结构中晶体管的排布方式以及如何缩小动态存储器阵列结构中单个功能器件的尺寸进行研究的同时，也需要提高小尺寸的功能器件的电学性能。
利用垂直的全环绕栅极(GAA，Gate-All-Around)晶体管结构作为动态存储器选择晶体管(access transistor)时，其占据的面积可以达到4F2(F：在给定工艺条件下可获得的最小图案尺寸)，原则上可以实现更高的密度效率，但是在部分尺寸下，埋藏于晶体管底部的位线因主要成分为硅导致电阻较大。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
公开本公开实施例提供一种半导体结构，包括：基底；位线，位于所述基底上，且所述位线的材料包括金属半导体化合物；半导体通道，位于所述位线表面，在沿所述基底指向所述位线的方向上，所述半导体通道包括依次排列的第一掺杂区、沟道区以及第二掺杂区，所述第一掺杂区与所述位线相接触；第一介质层，覆盖所述第一掺杂区侧壁表面，且同一所述位线上相邻所述第一掺杂区侧壁的所述第一介质层之间具有第一间隔；绝缘层，覆盖所述沟道区侧壁表面；字线，覆盖所述绝缘层远离所述沟道区的侧壁表面，且 相邻所述字线之间具有第二间隔；第二介质层，覆盖所述第二掺杂区侧壁表面，且位于相邻所述第二掺杂区侧壁的所述第二介质层之间具有第三间隔；第三介质层，位于所述第一间隔、所述第二间隔和所述第三间隔中。
本公开的一些实施例中，半导体结构还包括：金属接触层，位于第二掺杂区远离基底的顶面，且金属半导体化合物和金属接触层中具有相同的金属元素。
本公开的一些实施例中，金属接触层在基底上的正投影覆盖第二掺杂区在基底上的正投影。
本公开的一些实施例中，半导体结构还包括：过渡层，位于第二掺杂区和金属接触层之间，且金属接触层包裹过渡层，过渡层和第二掺杂区掺杂有相同类型的掺杂离子，且掺杂离子在过渡层中的掺杂浓度大于在第二掺杂区中的掺杂浓度，掺杂离子为N型离子或P型离子中的一者。
本公开的一些实施例中，基底、位线和半导体通道具有相同的半导体元素。
本公开的一些实施例中，第一掺杂区、沟道区和第二掺杂区掺杂有相同类型的掺杂离子，且掺杂离子在第一掺杂区中的掺杂浓度与在沟道区和第二掺杂区中的掺杂浓度一致，掺杂离子为N型离子或P型离子中的一者。
本公开的一些实施例中，沟道区在基底上的正投影小于第二掺杂区在基底上的正投影，且小于第一掺杂区在基底上的正投影。
本公开的一些实施例中，绝缘层和第二介质层为同一膜层结构。
本公开的一些实施例中，绝缘层的外围在基底上的正投影小于第二介质层的外围在基底上的正投影。
本公开的一些实施例中，第一介质层包括第四介质层和第五介质层，第四介质层位于相邻位线的间隔中，且位于相邻位线上的相邻第一掺杂区的间隔中；第五介质层位于同一位线上相邻第一掺杂区的侧壁，且位于第四介质层的侧壁。
本公开的一些实施例中，位于第二间隔中的第三介质层中具有空隙。
相应地，本公开实施例还提供一种半导体结构的制作方法，包括：提供基底；在基底上形成初始位线，以及在初始位线远离基底的表面形成半导体通道，在沿基底指向初始位线的方向上，半导体通道包括依次排列的第一掺 杂区、沟道区以及第二掺杂区；形成覆盖第一掺杂区侧壁表面的第一介质层，且同一初始位线上相邻第一掺杂区侧壁的第一介质层之间具有第一间隔；形成覆盖沟道区侧壁表面的绝缘层；形成覆盖绝缘层远离沟道区的侧壁表面的字线，且相邻字线之间具有第二间隔；形成覆盖第二掺杂区侧壁表面的第二介质层，且位于相邻第二掺杂区侧壁的第二介质层之间具有第三间隔，第一间隔、第二间隔和第三间隔相连通并暴露出部分初始位线；对暴露出的初始位线进行金属化处理，以形成位线，位线的材料包括金属半导体化合物。
本公开的一些实施例中，在形成字线之后，在形成第二介质层之前，还包括：采用外延生长工艺，在第二掺杂区远离基底的顶面形成初始过渡层，初始过渡层和第二掺杂区掺杂有相同类型的掺杂离子，掺杂离子在初始过渡层中的掺杂浓度大于在第二掺杂区中的掺杂浓度，掺杂离子为N型离子或P型离子中的一者，且初始过渡层在基底上的正投影覆盖第二掺杂区在基底上的正投影。
本公开的一些实施例中，在对初始位线进行金属化处理的步骤中，还包括：对初始过渡层进行金属化处理。
本公开的一些实施例中，形成第一介质层的步骤包括：
形成初始第一介质层，初始第一介质层环绕半导体通道侧壁，且位于同一初始位线上相邻半导体通道侧壁的初始第一介质层之间具有第四间隔；
形成第一隔离层，第一隔离层填充满第四间隔，且第一隔离层的材料和初始第一介质层的材料不同；
刻蚀部分初始第一介质层至露出第二掺杂区侧壁；
形成第二隔离层，第二隔离层环绕第二掺杂区侧壁和位于第一隔离层侧壁，位于第二掺杂区侧壁的第二隔离层和位于第一隔离层侧壁的第二隔离层共同围成通孔，通孔底部露出初始第一介质层，且第二隔离层的材料和初始第一介质层的材料不同；
去除通孔露出的位于沟道区侧壁的初始第一介质层，剩余初始第一介质层作为第一介质层。
本公开的一些实施例中，形成绝缘层的步骤包括：
对露出的沟道区侧壁进行热氧化处理，以形成绝缘层，且绝缘层覆盖剩 余沟道区的侧壁表面，绝缘层和第一隔离层之间具有第五间隔。
本公开的一些实施例中，形成字线的步骤包括：
形成初始字线，初始字线填充满第五间隔和通孔，且初始字线还位于相邻初始位线上的沟道区侧壁的绝缘层之间；
去除位于通孔中的初始字线，剩余初始字线作为字线。
本公开的一些实施例中，形成第一介质层的步骤包括：
形成初始第一介质层，初始第一介质层环绕半导体通道侧壁，且位于同一初始位线上相邻半导体通道侧壁的初始第一介质层之间具有第四间隔；
形成第一隔离层，第一隔离层填充满第四间隔，且第一隔离层的材料和初始第一介质层的材料不同；
刻蚀部分初始第一介质层至露出第二掺杂区侧壁和沟道区侧壁，剩余初始第一介质层作为第一介质层。
本公开的一些实施例中，形成绝缘层和第二介质层的步骤包括：
形成覆盖第二掺杂区侧壁和沟道区侧壁的保护层，且保护层和第一隔离层之间具有第六间隔，沟道区侧壁的保护层为绝缘层，覆盖第二掺杂区侧壁的保护层为第二介质层。
本公开的一些实施例中，形成字线的步骤包括：
形成初始字线，初始字线填充满第六间隔，且初始字线还位于相邻初始位线上的半导体通道部分侧壁的保护层之间；
去除部分初始字线，剩余初始字线作为字线，字线仅环绕位于沟道区侧壁的绝缘层侧壁。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些 示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1至35为本公开实施例提供的半导体结构的形成方法中各步骤对应的半导体结构的示意图。
具体实施方式
由背景技术可知，目前需要在提高半导体结构的集成密度的同时，需要提高半导体结构中小尺寸的功能器件的电学性能。
本公开实施提供一种半导体结构及其制作方法，半导体结构中，基底上具有垂直的GAA晶体管，且位线位于基底与GAA晶体管之间，因而可以构成3D堆叠的半导体结构，有利于提高半导体结构的集成密度。此外，由于位线的材料包括金属半导体化合物，有利于降低位线的电阻，以提高半导体结构的电学性能。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
本公开一实施例提供一种半导体结构，以下将结合附图对本公开一实施例提供的半导体结构进行详细说明。图1至图5为本公开一实施例提供的半导体结构对应的结构示意图。其中，图1为本公开一实施例提供的半导体结构的一种结构示意图，图2为图1所示结构沿第一截面方向AA1的一种剖面示意图，图3为图1所示结构沿第一截面方向AA1的又一种剖面示意图，图4为图1所示结构沿第二截面方向BB1的剖面示意图，图5为本公开一实施例提供的半导体结构的又一种结构示意图。
结合参考图1至图5，半导体结构包括：基底11；位线104，位于基底11上，且位线104的材料包括金属半导体化合物；半导体通道105，位于位线104表面，在沿基底11指向位线104的方向Z上，半导体通道105包括依次排列的第一掺杂区I、沟道区II以及第二掺杂区III，第一掺杂区I与位线104相接触；第一介质层113，覆盖第一掺杂区I侧壁表面，且同一位线104上相邻第一掺杂区I侧壁的第一介质层113之间具有第一间隔；绝缘层106，覆盖沟道区II侧壁表面；字线107，覆盖绝缘层106远离沟道区II的侧壁表 面，且相邻字线107之间具有第二间隔；第二介质层123，覆盖第二掺杂区II侧壁表面，且位于相邻第二掺杂区II侧壁的第二介质层123之间具有第三间隔；第三介质层133，位于第一间隔、第二间隔和第三间隔中。
由于半导体结构包括垂直的GAA晶体管，且位线104位于基底11与GAA晶体管之间，因而能够构成3D堆叠的存储器件，有利于提高半导体结构的集成密度。
以下将结合图1至图5对半导体结构进行更为详细的说明。
本实施例中，基底11的材料类型可以为元素半导体材料或者晶态无机化合物半导体材料。元素半导体材料可以硅或者锗；晶态无机化合物半导体材料可以为碳化硅、锗化硅、砷化镓或者镓化铟等。此外，基底11内掺杂有第一类型离子。
在本公开的一些实施例中，基底11、位线104和半导体通道105具有相同的半导体元素，则半导体通道105与位线104可以利用同一膜层结构形成，该膜层结构由半导体元素构成，使得半导体通道105与位线104为一体结构，从而改善半导体通道105与位线104之间的界面态缺陷，改善半导体结构的性能。
其中，半导体元素可以包括硅、碳、锗、砷、镓、铟中的至少一种。在一个例子中，位线104与半导体通道105均包括硅元素。在其他例子中，位线与半导体通道可以均包括锗元素，或者，位线与半导体通道均包括硅元素和锗元素，或者，位线与半导体通道均包括硅元素和碳元素，或者，位线与半导体通道均包括砷元素和镓元素，或者，位线与半导体通道均包括镓元素和铟元素。
位线104的材料包括金属半导体化合物114，金属半导体化合物114相较于未金属化的半导体材料而言，具有相对较小的电阻率，因此，相较于半导体通道105而言，位线104的电阻率更小，从而有利于降低位线104的电阻，且降低位线104与第一掺杂区I之间的接触电阻，进一步改善半导体结构的电学性能。此外，位线104的电阻率还小于基底11的电阻率。
在一些例子中，位于第一掺杂区I正下方的位线104的区域的材料为半导体材料，且未被第一掺杂区I覆盖的位线104的部分区域的材料为金属半导体化合物。随着器件尺寸的不断缩小或者制造工艺参数的调整，位于第一 掺杂区I正下方的位线104的部分区域的材料为半导体材料，位于第一掺杂区I正下方的位线104的其余区域的材料也可以为金属半导体化合物，此处的“其余区域”的位置位于“部分区域”的外围。
在一个例子中，参考图2，同一位线104中的多个金属半导体化合物114之间相互间隔；在又一个例子中，参考图3，同一位线104中的多个金属半导体化合物114之间相互连通，图3仅示例出来了相邻金属半导体化合物114之间边缘处刚好相互接触以连通的情况，实际情况中，相邻金属半导体化合物114之间相互接触的区域可以更大，本实施例对相邻金属半导体化合物114之间相互接触的区域的大小不做限制。
在其他例子中，整个位线的材料可以均为金属半导体化合物。
以半导体元素为硅为例，金属半导体化合物114包括硅化钴、硅化镍、硅化钼、硅化钛、硅化钨、硅化钽或者硅化铂中的至少一种。
本实施例中，在基底11上可以形成多个间隔排布的位线104，以及每一位线104可与至少一个第一掺杂区I相接触，图1至图4中以4个相互间隔的位线104，以及每一位线104与4个第一掺杂区I相接触作为示例，可根据实际电学需求，合理设置位线104的数量以及与每一位线104相接触的第一掺杂区I的数量。
其中，位线104中掺杂有第二类型离子，基底11中掺杂有第一类型离子，第二类型离子与第一类型离子不同，且第一类型离子与第二类型离子均为N型离子或P型离子中的一者。如此，位线104与基底11构成PN结，该PN结有利于防止位线104漏电，进一步改善半导体结构的电学性能。在其他实施例中，基底11也可以不掺杂第一类型离子。
N型离子为砷离子、磷离子或者锑离子中的至少一种；P型离子为硼离子、铟离子或者镓离子中的至少一种
在本公开的一些实施例中，半导体通道105中第一掺杂区I、沟道区II和第二掺杂区III掺杂有相同类型的掺杂离子，即第二类型离子，且掺杂离子在第一掺杂区I中的掺杂浓度与在沟道区II和第二掺杂区III中的掺杂浓度一致。
因而，半导体通道105构成的器件为无结晶体管(Junctionless Transistor)，即第一掺杂区I、沟道区II和第二掺杂区III中的掺杂离子的类 型相同，例如掺杂离子均为N型离子，第一掺杂区I、沟道区II和第二掺杂区III中的掺杂离子可以相同。其中，此处的“无结”指的是无PN结，即半导体通道105构成的晶体管中没有PN结，即第一掺杂区I、沟道区II和第二掺杂区III中的掺杂离子的掺杂浓度相同，这样的好处包括：一方面，无需对第一掺杂区I和第二掺杂区III进行额外的掺杂，从而避免了对第一掺杂区I和第二掺杂区III的掺杂工艺难以控制的问题，尤其是随着晶体管尺寸进一步缩小，若额外对第一掺杂区I和第二掺杂区III进行掺杂，掺杂浓度更加难以控制；另一方面，由于器件为无结晶体管，有利于避免采用超陡峭源漏浓度梯度掺杂工艺，在纳米尺度范围内制作超陡峭PN结的现象，因而可以避免掺杂突变所产生的阈值电压漂移和漏电流增加等问题，还有利于抑制短沟道效应，在几纳米的尺度范围内仍然可以工作，因而有助于进一步提高半导体结构的集成密度和电学性能。此处额外的掺杂指的是，为了让第一掺杂区I和第二掺杂区III的掺杂离子类型与沟道区II的掺杂离子类型不同而进行的掺杂。
在一些例子中，第二类型离子在半导体通道105内的掺杂浓度为1×10 19atom/cm 3～1×10 20atom/cm 3，且在沿基底11指向位线104的方向Z上，半导体通道105的高度为100nm～150nm，第一掺杂区I、沟道区II和第二掺杂区III的高度均为30nm～50nm。
本实施例中，沟道区II在基底11上的正投影小于第二掺杂区III在基底11上的正投影，且小于第一掺杂区I在基底11上的正投影，在垂直于位线104指向半导体通道105的方向Z的截面中，有利于形成截面面积更加小的沟道区II，有利于提高后续形成的字线对沟道区II的控制能力，从而更容易控制GAA晶体管的导通或者关断。在其他实施例中，第一掺杂区、沟道区以及第二掺杂区在基底上的正投影可以相等；或者，沟道区和第二掺杂区在基底上的正投影均小于第一掺杂区在基底上的正投影。
在一些例子中，在垂直于方向Z的截面中，沟道区II的宽度W和沟道区II的长度L均不高于10nm，有利于保证后续形成的字线对沟道区II有良好的控制能力。
第一介质层113可以包括第四介质层143和第五介质层153，第四介质层143位于相邻位线104的间隔中，且位于相邻位线104上的相邻第一掺杂 区I的间隔中；第五介质层153位于同一位线104上相邻第一掺杂区I的侧壁，且位于第四介质层143的侧壁。第一介质层113用于实现相邻半导体通道105和相邻位线104之间的电绝缘。
在一些例子中，第四介质层143的材料和第五介质层153的材料相同，，第四介质层143的材料和第五介质层153的材料可以均为氧化硅。在其他实施例中，第四介质层的材料和第五介质层的材料也可以不同，只需满足第四介质层的材料和第五介质层的材料为绝缘效果良好的材料。
本实施例中，绝缘层106的外围在基底11上的正投影小于第二介质层123的外围在基底11上的正投影，即参考图2和图4，绝缘层106远离半导体通道105的外壁相较于第二介质层123远离半导体通道105外壁，更靠近半导体通道105。此外，绝缘层106远离半导体通道105的外壁相较于第一介质层113远离半导体通道105外壁，也更靠近半导体通道105。其中，绝缘层106的材料为氧化硅。
在其他实施例中，绝缘层和第二介质层可以为同一膜层结构，即绝缘层和第二介质层可以通过同一工艺步骤形成。其中，绝缘层的材料和第二介质层的材料包括氧化硅或者氮化硅中的至少一种。
第一间隔、第二间隔和第三间隔之间相连通。
在一些例子中，参考图2至图4，第一间隔和第二间隔在基底11上的正投影重合，第三介质层133填充满第一间隔、第二间隔和第三间隔，且第三介质层133远离基底11的顶面高于第二掺杂区III远离基底11的顶面。
在又一些例子中，参考图5，位于第二间隔中的第三介质层133中具有空隙109，即相邻字线107之间除了具有第三介质层133，还具有空隙109，有利于降低相邻字线107之间产生的电容，以提高半导体结构的电学特性。在其他例子这，空隙不仅可以存在于位于第二间隔中的第三介质层中，还可以存在于位于第一间隔中的第三介质层中，或者存在于位于第三间隔中的第三介质层中。
半导体结构还可以包括：金属接触层108，位于第二掺杂区III远离基底11的顶面，且金属半导体化合物114和金属接触层108中具有相同的金属元素。其中，金属元素包括钴、镍、钼、钛、钨、钽或者铂中的至少一种。
由于金属接触层108中具有金属元素，后续在金属接触层108上形成电 容结构的下电极时，金属接触层108与下电极构成欧姆接触，避免下电极与半导体材料直接接触而形成肖特基势垒接触，欧姆接触有利于降低第二掺杂区III与下电极之间的接触电阻，从而降低半导体结构工作时的能耗，且改善RC延迟效应，以提高半导体结构的电学性能。此外，从制作工艺的角度而言，金属接触层108和金属半导体化合物114中具有相同的金属元素，有利于在一个工艺步骤中，形成金属接触层108和在位线104中形成金属半导体化合物114。
在本公开的一些实施例中，金属接触层108在基底11上的正投影覆盖第二掺杂区III在基底11上的正投影，有利于增大金属接触层108与下电极之间的接触面积，从而降低金属接触层108与下电极之间的接触电阻，以提高半导体结构的电学性能。
半导体结构还可以包括：过渡层118，位于第二掺杂区III和金属接触层108之间，且过渡层118位于第二掺杂区III的部分顶面，金属接触层108包裹过渡层118的其余表面，过渡层118和第二掺杂区III掺杂有相同类型的掺杂离子，且掺杂离子在过渡层118中的掺杂浓度大于在第二掺杂区III中的掺杂浓度，则过渡层118的电阻小于第二掺杂区III的电阻，有利于进一步降低第二掺杂区III与下电极之间的传输电阻。
在其他实施例中，半导体结构也可不包括过渡层，第二掺杂区顶面仅具有金属接触层。
半导体结构还可以包括：电容结构(图中未示出)，电容结构位于金属接触层108和第三介质层133共同构成的表面。
综上所述，基底11上具有垂直的GAA晶体管，且位线104位于基底11与GAA晶体管之间，因而可以构成3D堆叠的半导体结构，有利于提高半导体结构的集成密度。同时，位线104的材料包括金属半导体化合物114，有利于降低位线104的电阻，以降低位线104与第一掺杂区I之间的接触电阻，进一步改善半导体结构的电学性能。此外，半导体通道105构成的器件为无结晶体管，有利于避免采用超陡峭源漏浓度梯度掺杂工艺，因而可以避免掺杂突变所产生的阈值电压漂移和漏电流增加等问题，还有利于抑制短沟道效应，从而进一步提高半导体结构的集成密度和电学性能。
相应地，本公开又一实施例还提供一种半导体结构的制作方法，可用于 形成上述半导体结构。
图1至图35为本公开又一实施例提供的半导体结构的制造方法中各步骤对应的剖面结构示意图，以下将结合附图对本实施例提供的半导体结构的制造方法进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
参考图6至图9，提供基底11；在基底11上形成初始位线124，以及在初始位线124远离基底11的表面形成半导体通道105，在沿基底11指向初始位线124的方向上，半导体通道105包括依次排列的第一掺杂区I、沟道区II以及第二掺杂区III。
提供基底11，并在基底11上形成初始位线124环绕半导体通道105包括如下步骤：
参考图6，提供衬底110，衬底110的材料类型可以为元素半导体材料或者晶态无机化合物半导体材料。元素半导体材料可以为硅或者锗；晶态无机化合物半导体材料可以为碳化硅、锗化硅、砷化镓或者镓化铟等。
衬底110包括：基底11，基底11内掺杂有第一类型离子；初始半导体层10，设置于基底11上。
对初始半导体层10进行掺杂处理以及退火处理，使得初始半导体层10内掺杂有第二类型离子，用于后续刻蚀初始半导体层10以形成初始位线124和半导体通道105，且第二类型离子与第一类型离子不同，第一类型离子与第二类型离子均为N型离子或P型离子中的一者。
其中，掺杂处理可以采用高温扩散或者离子注入的方法，当采用离子注入的方式对初始半导体层10进行掺杂处理后，退火处理的退火温度为800℃～1000℃。
本实施例中，第二类型离子在初始半导体层10内的掺杂浓度为1×10 19atom/cm 3～1×10 20atom/cm 3，且在初始半导体层10指向基底11的方向上，初始半导体层10内第二类型离子的掺杂深度为150nm～250nm。此外，第一类型离子为P型离子，第二类型离子为N型离子。在其他实施例中，第一类型离子可以为N型离子，第二类型离子可以为P型离子。
在初始半导体层10远离基底11的一侧依次堆叠形成缓冲层120和阻挡层130。在一些例子中，可采用沉积工艺形成缓冲层120和阻挡层130，缓冲层120的材料为氧化硅，阻挡层130的材料为氮化硅。
在本公开的一些实施例中，可以采用化学气相沉积工艺沉积氮化硅以形成阻挡层130，氮化硅膜层的氧化速度非常慢，有利于保护位于氮化硅膜层下方的衬底100，避免衬底100被氧化。
在一些例子中，衬底110为硅衬底，由于氮化硅的晶格常数和热膨胀系数与硅衬底的晶格常数和热膨胀系数的失配率都很大，因而若在硅衬底上直接形成氮化硅，氮化硅和硅的界面处缺陷密度大，容易成为载流子陷阱和复合中心，影响硅的载流子迁移率，从而影响半导体结构的性能和工作寿命。而且，氮化硅薄膜应力较大，直接沉积在硅衬底上易出现龟裂现象。因而，在硅衬底上沉积氮化硅之前先形成氧化硅作为缓冲层120，有利于提高半导体结构的性能和工作寿命。
继续参考图6，在阻挡层130上形成第一掩膜层102，第一掩膜层102具有多个相互分立的第一开口b，在沿第一开口b的延伸方向X上，第一开口b的长度与后续形成的位线的长度一致。
参考图7，以第一掩膜层102为掩膜刻蚀阻挡层130、缓冲层120以及初始半导体层10，形成多个第一沟槽a，并去除第一掩膜层102。
本实施例中，沿垂直于基底11表面的方向Z，第一沟槽a的深度为250～300nm。由于第一沟槽a的深度大于初始半导体层10内第二类型离子的掺杂深度，有利于保证掺杂有第二类型离子的初始半导体层10均被刻蚀，便于后续形成第二类型离子掺杂浓度高的半导体通道和位线。
参考图8，在第一沟槽a中形成第四介质层143。
本实施例中，可采用以下工艺步骤形成第四介质层143：进行沉积工艺，形成覆盖阻挡层130顶面以及填充满第一沟槽a的第四介质膜；对第四介质膜进行化学机械平坦化处理至露出阻挡层130顶面，剩余第四介质膜作为第四介质层143。其中，第四介质膜的材料包括氧化硅。
在本公开的一些实施例中，在第四介质层143和剩余衬底110共同构成的顶面上形成第二掩膜层112，第二掩膜层112具有多个相互分立的第二开口c，在沿第二开口c的延伸方向Y上，第二开口c的长度与后续形成的字线的长度一致。
本实施例中，结合参考图6和图8，第一开口b的延伸方向X垂直于第二开口c的延伸方向Y，使得最终形成的半导体通道105呈现4F2的排布方 式，有利于进一步提高半导体结构的集成密度。在其他实施例中，第一开口的延伸方向与第二开口的延伸方向相交，两者之间的夹角可以不为90°。
在本公开的一些实施例中，第一开口b沿方向Y上的开口宽度与第二开口c沿方向X上的开口宽度的比值为2～1，以保证后续能形成露出环绕沟道区II侧壁的第一介质层的通孔，从而有利于后续形成用于制造字线的第一间隙。在一些例子中，第一开口b沿方向Y上的开口宽度等于第二开口c沿方向X上的开口宽度，且相邻第一开口b之间的间距等于相邻第二开口c之间的间距，一方面，使得后续形成的多个半导体通道排列规整，进一步提高半导体结构的集成密度；另一方面，可以采用同一掩膜版形成第一掩膜层102和形成第二掩膜层112，有利于降低半导体结构的制备成本。
本实施例中，形成第一掩膜层102和形成第二掩膜层112的方法均包括自对准多重曝光技术(SAQP，Self-Aligned Quadruple Patterning)或者自对准多重成像技术(SADP，Self-Aligned Double Patterning)。
参考图9，以第二掩膜层112为掩膜刻蚀初始半导体层10(参考图6)和第四介质层143，形成多个第二沟槽d、初始位线124和半导体通道105，且在垂直于基底11表面的方向Z上，第二沟槽d的深度小于第一沟槽a的深度，有利于在形成初始位线124的同时，在初始位线124远离基底11的一侧形成多个相互分立的半导体通道105，且初始位线124与半导体通道105的第一掺杂区I相接触；去除第二掩膜层112。
在一些例子中，第二沟槽d的深度为100nm～150nm，由于初始半导体层10内第二类型离子的掺杂深度为150nm～250nm，有利于使得大部分或者全部掺杂有第二类型离子的初始半导体层10经过两次刻蚀转变为半导体通道105。
此外，衬底110的材料为硅，第四介质层143的材料为氧化硅，在以第二掩膜层112为掩膜刻蚀初始半导体层10和第四介质层143的步骤中，刻蚀工艺对氧化硅的刻蚀速率大于对硅的刻蚀速率，因而初始位线124的部分侧壁会暴露出来。
为了实现相邻初始位线124和相邻半导体通道105之间的电绝缘，以第二掩膜层112为掩膜刻蚀初始半导体层10和第四介质层143之后，剩余第四介质层143还位于相邻初始位线124的间隔中，以及位于相邻半导体通道105 的间隔中。
第一掺杂区I、沟道区II和第二掺杂区III中的掺杂离子的类型相同，例如掺杂离子均为N型离子，且第一掺杂区I、沟道区II和第二掺杂区III中的掺杂离子的掺杂浓度相同，即半导体通道105构成的器件为无结晶体管。第一掺杂区I、沟道区II和第二掺杂区III中的掺杂离子可以相同。如此，一方面，无需对第一掺杂区I和第二掺杂区III进行额外的掺杂，从而避免了对第一掺杂区I和第二掺杂区III的掺杂工艺难以控制的问题，尤其是随着晶体管尺寸进一步缩小，若额外对第一掺杂区I和第二掺杂区III进行掺杂，掺杂浓度更加难以控制；另一方面，由于器件为无结晶体管，有利于避免采用超陡峭源漏浓度梯度掺杂工艺，在纳米尺度范围内制作超陡峭PN结的现象，因而可以避免掺杂突变所产生的阈值电压漂移和漏电流增加等问题，还有利于抑制短沟道效应，在几纳米的尺度范围内仍然可以工作，因而有助于进一步提高半导体结构的集成密度和电学性能。此处额外的掺杂指的是，为了让第一掺杂区I和第二掺杂区III的掺杂离子类型与沟道区II的掺杂离子类型不同而进行的掺杂。
在本公开的一些实施例中，形成半导体通道105垂直于初始位线124远离基底11顶面的GAA晶体管，可以构成3D堆叠的半导体结构，有利于在不对GAA晶体管的电学性能造成不利影响的前提下，设计尺寸特征更小的GAA晶体管，以提高半导体结构的集成密度。
本实施例中，利用第一掩膜层102和第二掩膜层112，通过两次刻蚀工艺同时形成初始位线124和半导体通道105，一方面，有利于通过调控第一开口b和第二开口c的尺寸调控半导体通道105的尺寸，且形成尺寸精度较高的半导体通道105；另一方面，初始位线124和半导体通道105均是通过刻蚀初始半导体层10形成的，即初始位线124和半导体通道105利用同一膜层结构形成，使得初始位线124和半导体通道105为一体结构，从而改善初始位线124和半导体通道105之间的界面态缺陷，改善半导体结构的性能。此外，在以第一掩膜层102为掩膜刻蚀初始半导体层10之后，在第一沟槽a中还形成有第四介质层143，为后续在沟道区II侧壁和第一隔离层之间形成间隙做前期准备，从而有利于后续形成制备字线的第一间隙。
参考图10至图35，形成覆盖第一掺杂区I侧壁表面的第一介质层113， 且同一初始位线124上相邻第一掺杂区I侧壁的第一介质层113之间具有第一间隔；形成覆盖沟道区II侧壁表面的绝缘层106；形成覆盖绝缘层106远离沟道区II的侧壁表面的字线107，且相邻字线107之间具有第二间隔；形成覆盖第二掺杂区III侧壁表面的第二介质层123，且位于相邻第二掺杂区III侧壁的第二介质层123之间具有第三间隔，第一间隔、第二间隔和第三间隔相连通并暴露出部分初始位线124；对暴露出的初始位线124进行金属化处理，以形成位线104，位线104的材料包括金属半导体化合物114。
其中，图12为图11所示结构沿第一截面方向AA1的剖面示意图，图13为图11所示结构沿第二截面方向BB1的剖面示意图。后续将根据表述需要设置沿第一截面方向AA1的剖面示意图以及沿第二截面方向BB1的剖面示意图中的一者或者两者，当仅参考一个附图时，附图为沿第一截面方向AA1的剖面示意图；当同时参考两个附图时，附图首先为沿第一截面方向AA1的剖面示意图，其次为沿第二截面方向BB1的剖面示意图。
在一些例子中，参考图10至图27，形成第一介质层113、绝缘层106、字线107以及第二介质层123包括如下步骤：
参考图10至图11，形成初始第一介质层113a，初始第一介质层113a环绕半导体通道105侧壁，且位于同一初始位线124上相邻半导体通道105侧壁的初始第一介质层113a之间具有第四间隔e。
参考图10，形成第五介质膜103，第五介质膜103保形覆盖第二沟槽d(参考图9)的侧壁和底部，且还位于阻挡层130和第四介质层143的顶面。
结合参考图10和图11，对第五介质膜103进行无掩膜干法刻蚀工艺，直至露出阻挡层130，利用相同的刻蚀时间内，刻蚀工艺刻蚀第五介质膜103不同区域的厚度相同，形成第五介质层153。
结合参考图11至图13，第四介质层143位于第二沟槽d(参考图9)的侧壁，第四介质层143位于相邻半导体通道105的间隔中，第四介质层143和第五介质层153共同组成初始第一介质层113a，且位于第二沟槽d侧壁的第五介质层153之间具有第四间隔e。
其中，第四介质层143的材料与第五介质层153的材料相同，便于后续通过刻蚀工艺一同去除与沟道区II侧壁对应的第四介质层143和第五介质层153，从而在沟道区II侧壁和后续形成的第一隔离层之间形成空隙，从而有 利于后续形成制备字线的间隙。第四介质层143的材料与第五介质层153的材料均为氧化硅。
在其他实施例中，第四介质层的材料和第五介质层的材料也可以不同，只需满足第四介质层的材料和第五介质层的材料为绝缘效果良好的材料即可，然后可以分步去除与沟道区侧壁对应的第四介质层和第五介质层。
参考图14，形成第一隔离层163，第一隔离层163填充满第四间隔e，且第一隔离层163的材料和初始第一介质层113a的材料不同。
可采用以下工艺步骤形成第一隔离层163：进行沉积工艺，形成覆盖阻挡层130顶面以及填充满第四间隔e的第一隔离膜；对第一隔离膜、阻挡层130、缓冲层120以及初始第一介质层113a进行化学机械平坦化处理至露出第二掺杂区III顶面，剩余第一隔离膜作为第一隔离层163。其中，第一隔离膜的材料包括氮化硅。
参考图15，刻蚀部分初始第一介质层113a至露出第二掺杂区III侧壁。
参考图16至图19，其中，图17为图16的俯视示意图，图18为沿第三截面方向CC1的剖面示意图，图19为沿第二截面方向BB1的剖面示意图。
形成第二隔离层173，第二隔离层173环绕第二掺杂区III侧壁和位于第一隔离层163侧壁，位于第二掺杂区III侧壁的第二隔离层173和位于第一隔离层163侧壁的第二隔离层173共同围成通孔f，通孔f底部露出初始第一介质层113a，且第二隔离层173的材料和初始第一介质层113a的材料不同。
在本公开的一些实施例中，参考图18和图19，第二隔离层173在环绕第二掺杂区III侧壁的同时，覆盖第五介质层153顶面和部分第四介质层143顶面，通孔f露出的是第四介质层143的部分顶面。
本实施例中，可采用以下工艺步骤形成第二隔离层173：进行沉积工艺，形成保形覆盖由半导体通道105、初始第一介质层113a以及第一隔离层163共同构成的表面的第二隔离膜；对第二隔离膜进行无掩膜干法刻蚀工艺，直至露出第二掺杂区III顶面，利用相同的刻蚀时间内，刻蚀工艺刻蚀第二隔离膜不同区域的厚度相同，形成露出第一隔离层163的第二隔离层173。其中，第二隔离层173的材料包括氮化硅。
此外，在前述的第一掩膜层102和第二掩膜层112中，第一开口b沿方向Y上的开口宽度与第二开口c沿方向X上的开口宽度的比值为2～1，在形 成第二隔离层173时，有利于保证第二隔离层173填充满同一初始位线124上相邻半导体通道105之间的间隔的同时，不会将相邻初始位线124上相邻半导体通道105之间的间隙填满，从而保证形成露出第四介质层143的部分顶面的通孔f，便于后续利用通孔f去除部分初始第一介质层113a。
结合图20至图22，去除通孔f露出的位于沟道区II侧壁的初始第一介质层113a，剩余所述初始第一介质层113a作为第一介质层113。
由于通孔f露出第一介质层113的部分顶面，第一介质层113的材料与第二介质层123和第三介质层133的材料均不相同，则可以向通孔f中注入刻蚀液，通过湿法刻蚀工艺去除位于沟道区II侧壁的第一介质层113，保留位于第一掺杂区I侧壁的第一介质层113。
此外，第一隔离层163和第二隔离层173共同组成支撑骨架，支撑骨架与第二掺杂区III相接触连接，且部分支撑骨架嵌入第一介质层113中。在进行湿法刻蚀工艺的步骤中，一方面，支撑骨架有对半导体通道105起支撑固定的作用，当刻蚀液流动时产生对半导体通道105的挤压力，有利于避免半导体通道105受挤压发生倾斜或者偏移，以提高半导体结构的稳定性；另一方面，支撑骨架包裹着第二掺杂区III侧壁，有利于避免刻蚀液对第二掺杂区III造成损伤。
去除位于沟道区II侧壁的初始第一介质层113a之后，沟道区II与第一隔离层163之间形成第二间隙g，通孔f和第二间隙g共同组成洞穴结构h。
参考图23和图24，对露出的沟道区II侧壁进行热氧化处理，以形成绝缘层106，且绝缘层106覆盖剩余沟道区II的侧壁表面，绝缘层106和第一隔离层163之间具有第五间隔i。
在本公开的一些实施例中，参考图24，第五间隔i还位于相邻初始位线124的相邻半导体通道105侧壁的绝缘层106之间。
热氧化处理的过程中，第二掺杂区III的顶面也暴露在外，则第二掺杂区III的靠近顶面的部分区域和沟道区II的部分区域均被转化为绝缘层106，使得沟道区II在基底11上的正投影小于第二掺杂区III在基底11上的正投影，且小于第一掺杂区I在基底11上的正投影，有利于在不采用刻蚀工艺的前提下，形成在垂直于初始位线124指向半导体通道105的方向Z的截面中，截面面积更加小的沟道区II，有利于提高后续形成的字线对沟道区II的 控制能力，从而更容易控制GAA晶体管的导通或者关断。其中，绝缘层106的材料为氧化硅。在其他实施例中，也可以通过沉积工艺形成覆盖沟道区侧壁表面的绝缘层。
本实施例中，在后续的工艺步骤中去除位于剩余第二掺杂区III顶面的绝缘层106。在其他实施例中，可以在热氧化处理之后，就去除位于剩余第二掺杂区顶面的绝缘层，仅保留覆盖剩余沟道区的侧壁表面的绝缘层。
继续参考图23和图24，绝缘层106的外围在基底11上的正投影小于第二隔离层173的外围在基底11上的正投影，即绝缘层106远离半导体通道105的外壁相较于第二隔离层173远离半导体通道105外壁，更靠近半导体通道105，从而保证绝缘层106与第一隔离层163之间具有第五间隔i，使得后续字线能环绕位于沟道区II侧壁的绝缘层106。此外，绝缘层106远离半导体通道105的外壁相较于第一介质层113(参考图20)远离半导体通道105外壁，也可以更靠近半导体通道105。
参考图25至图27，形成初始字线，初始字线填充满第五间隔i和通孔f，且初始字线还位于相邻初始位线124上的沟道区II侧壁的绝缘层106之间；去除位于通孔f中的初始字线，剩余初始字线作为字线107。其中，可通过沉积工艺形成初始字线，初始字线的材料包括多晶硅、氮化钛、氮化钽、铜或者钨中的至少一种。
初始字线自对准地填充满洞穴结构h(参考图20)，去除位于通孔f中的初始字线之后，有利于自对准地形成尺寸精确的字线107，无需通过刻蚀工艺来设计字线107的尺寸，有利于简化字线107的形成步骤，且通过调控第五间隔i的尺寸，即可获得小尺寸的字线107。
参考图28，形成字线107之后，还形成第三隔离层183，第三隔离层183填充满通孔f(参考图26)。
本实施例中，可采用以下工艺步骤形成第三隔离层183：进行沉积工艺，形成覆盖位于第二掺杂区III顶面的绝缘层106的顶面以及填充满通孔f的第三隔离膜；对第三隔离膜进行化学机械平坦化处理至露出绝缘层106顶面，剩余第三隔离膜作为第三隔离层183。其中，第三隔离膜与第一隔离层和第二隔离层的材料相同，均包括氮化硅。在其他实施例中，也可以对第三隔离膜进行化学机械平坦化处理至露出第二掺杂区顶面，即同步去除位于第 二掺杂区顶面的绝缘层，剩余第三隔离膜作为第三隔离层。
继续参考图28，去除位于第二掺杂区III顶面的绝缘层106，采用外延生长工艺，在第二掺杂区III顶面形成初始过渡层128，且初始过渡层128在基底11上的正投影覆盖第二掺杂区III在基底11上的正投影。
此外，在外延生长的工艺步骤中，在初始过渡层128还掺杂有与第二掺杂区III中相同类型的掺杂离子，且掺杂离子在初始过渡层128中的掺杂浓度大于在第二掺杂区III中的掺杂浓度，则初始过渡层128的电阻小于第二掺杂区III的电阻。
一方面，采用外延生长工艺有利于提升第二掺杂区III和初始过渡层128之间的连续性，减少因晶格特性不同或者晶格错位导致的接触缺陷，减小因接触缺陷导致的接触电阻，提升载流子的传输能力和移动速度，进而提高第二掺杂区III和初始过渡层128之间的导电性能，以及降低半导体结构运行过程中的发热；另一方面，采用外延生长工艺有利于增大初始过渡层128在基底11上的正投影，有利于使得初始过渡层128在基底11上的正投影面积大于第二掺杂区III在基底11上的正投影面积，后续可以作为掩膜，避免形成环绕第二掺杂区III侧壁的第二介质层被刻蚀至露出第二掺杂区III，以保证后续形成的第二介质层对第二掺杂区III良好的保护效果。
结合参考图28和图29，以初始过渡层128为掩膜，刻蚀第一隔离层163、第二隔离层173以及第三隔离层183，以露出第二掺杂区III侧壁，剩余第一隔离层163顶面不高于字线107顶面。其中，初始过渡层128在基底11上的正投影覆盖第二掺杂区III在基底11上的正投影，有利于避免半导体通道105在该步骤中受到刻蚀损伤。
参考图30，形成保形覆盖初始过渡层128表面、第二掺杂区III侧壁、字线107顶面以及第一隔离层163(参考图29)顶面的第二介质膜；对第二介质膜进行化学机械平坦化处理至露出初始过渡层128表面，以初始过渡层128为掩膜刻蚀剩余的第二介质层123，由于初始过渡层128在基底11上的正投影面积大于第二掺杂区III在基底11上的正投影面积，有利于在去除位于初始过渡层128表面、第一隔离层163顶面以及部分字线107顶面的第二介质膜的同时，避免与初始过渡层128在基底11上的正投影正对的第二介质膜被刻蚀，从而形成环绕第二掺杂区III侧壁的第二介质层123，以保证第二 介质层123对第二掺杂区III良好的保护效果。其中，可以采用沉积工艺形成第二介质膜。
在本公开的一些实施例中，参考图30，去除剩余的第一隔离层163，以露出初始位线124顶面。
在其他实施例中，以初始过渡层为掩膜，刻蚀第一隔离层、第二隔离层以及第三隔离层，以露出初始位线以及露出第二掺杂区侧壁；然后对露出的第二掺杂区侧壁进行热氧化处理，以形成第二介质层。
参考图1至图4，对暴露出的初始位线124和初始过渡层128进行金属化处理，以形成位线104，位线104的材料包括金属半导体化合物114。
在初始过渡层128表面和初始位线124顶面形成金属层，金属层为后续形成位线提供金属元素；金属层还位于第二介质层123、字线107以及第一介质层113暴露出的表面。其中，金属层的材料包括钴、镍、钼、钛、钨、钽或者铂中的至少一种。
进行退火处理，以将部分厚度的初始过渡层128转化为金属接触层108，将部分厚度的初始位线124(参考图30)转化为位线104。
在形成位线104之后，去除剩余的金属层。
在一些实施例中，在退火处理过程中，金属层与初始过渡层128和初始位线124发生反应，部分厚度的初始过渡层128转化为金属接触层108，部分厚度的初始位线124转化为位线104。在一个例子中，参考图2，同一位线104中的多个金属半导体化合物114之间相互间隔；在又一个例子中，参考图3，同一位线104中的多个金属半导体化合物114之间相互连通。
在其他实施例中，全部厚度的初始过渡层可以转化为金属接触层，全部厚度的初始位线可以转化为位。
在其他实施例中，在第二掺杂区顶面没有形成初始过渡层时，先不去除位于第二掺杂区顶面的绝缘层，后续仅对初始位线进行金属化处理，形成位线之后，再去除位于第二掺杂区顶面的绝缘层。结合参考图30和图1至图4，形成第三介质层133，第三介质层133填充相邻第一介质层113之间的第一间隔、相邻在字线107之间的第二间隔以及相邻第二介质层123之间的第三间隔，用于实现相邻半导体通道105以及相邻字线107之间的电绝缘。在一些例子中，参考图5，在形成第三介质层133时，位于第二间隔中的第三 介质层133中还可以具有空隙。
在又一些例子中，结合参考图10至图14和图31至图35，形成第一介质层113、绝缘层106、字线107以及第二介质层123包括如下步骤：
参考图10至图14，形成初始第一介质层113a，初始第一介质层113a环绕半导体通道105侧壁，且位于同一初始位线124上相邻半导体通道105侧壁的初始第一介质层113a之间具有第四间隔e；形成第一隔离层163，第一隔离层163填充满第四间隔e，且第一隔离层163的材料和初始第一介质层113a的材料不同。
形成初始第一介质层113a和第一隔离层163的步骤与上述例子相同，在此不做赘述。
参考图31，刻蚀部分初始第一介质层113a(参考图14)至露出第二掺杂区III侧壁和沟道区II侧壁，剩余初始第一介质层113a作为第一介质层113。
参考图32至图33，形成覆盖第二掺杂区III侧壁和沟道区II侧壁的保护层116，且保护层116和第一隔离层163之间具有第六间隔k，沟道区II侧壁的保护层116为绝缘层106，覆盖第二掺杂区III侧壁的保护层116为第二介质层123。
在本公开的一些实施例中，参考图33，第六间隔k还位于相邻初始位线124的相邻半导体通道105侧壁的保护层116之间。
本实施例中，半导体通道105的材料为硅，保护层116的形成步骤包括：对露出的沟道区II侧壁和第二掺杂区III的侧壁和顶面进行热氧化处理，则保护层116覆盖剩余沟道区II和剩余第二掺杂区III的侧壁表面，且覆盖剩余第二掺杂区III顶面。在其他实施例中，也可以通过沉积工艺形成覆盖沟道区侧壁和第二掺杂区的侧壁和顶面表面的保护层。
由于对露出的沟道区II和第二掺杂区III侧壁进行热氧化处理，则沟道区II和第二掺杂区III的部分区域被转化为保护层116，使得沟道区II和第二掺杂区III在基底11上的正投影均小于第一掺杂区I在基底11上的正投影，有利于在不采用刻蚀工艺的前提下，形成在垂直于初始位线124指向半导体通道105的方向Z的截面中，截面面积更加小的沟道区II和第二掺杂区III，有利于提高后续形成的字线对沟道区II的控制能力，从而更容易控制GAA晶体管的导通或者关断。
本实施例中，在后续的工艺步骤中去除位于剩余第二掺杂区III顶面的保护层116。在其他实施例中，可以在热氧化处理之后，就去除位于剩余第二掺杂区顶面的保护层，仅保留覆盖剩余沟道区以及剩余第二掺杂区的侧壁表面的保护层。
参考图34至图35，形成初始字线，初始字线填充满第六间隔k，且初始字线还位于相邻初始位线124上的半导体通道105部分侧壁的保护层116之间；去除部分初始字线，剩余初始字线作为字线107，字线107仅环绕位于沟道区II侧壁的绝缘层106侧壁。其中，可通过沉积工艺形成初始字线，初始字线的材料包括多晶硅、氮化钛、氮化钽、铜或者钨中的至少一种。
初始字线自对准地填充满第六间隔k，有利于自对准地形成尺寸精确的字线107。
在形成字线107之后，形成第三隔离层、形成初始过渡层、对初始过渡层和初始位线进行金属化处理以形成金属接触层和位线以及形成第三介质层的步骤与上述例子相同，在此不做赘述。
在本公开的一些实施例中，在金属接触层108和第三介质层133共同构成的表面形成电容结构(图中未示出)。在其他实施例中，还可以不形成金属接触层，在去除位于第二掺杂区顶面的绝缘层之后，直接在第二掺杂区和第三介质层共同构成的表面形成电容结构。
综上所述，通过形成第一介质层113和第二介质层123，以第二介质层123为掩膜对第一介质层113进行刻蚀，以形成特定形状的空洞结构；采用沉积工艺，在空洞结构中自对准地形成尺寸精确的字线107，无需通过刻蚀工艺来设计字线107的尺寸，有利于简化字线107的形成步骤，且通过调控空洞结构的尺寸，即可获得小尺寸的字线107。此外，对初始位线124和初始过渡层128进行金属化处理，有利于降低最终形成的位线104和金属接触层108的电阻，使得金属接触层108与电容结构之间构成欧姆接触，避免电容结构与半导体材料直接接触而形成肖特基势垒接触，有利于降低第二掺杂区III与电容结构之间的接触电阻，从而降低半导体结构工作时的能耗，以提高半导体结构的电学性能。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或 示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构及其制作方法，基底上具有垂直的GAA晶体管，且位线位于基底与GAA晶体管之间，因而可以构成3D堆叠的半导体结构，有利于提高半导体结构的集成密度。此外，由于位线的材料包括金属半导体化合物，有利于降低位线的电阻，以提高半导体结构的电学性能。

Claims (20)

  1. 一种半导体结构，所述半导体结构包括：
    基底；
    位线，位于所述基底上，且所述位线的材料包括金属半导体化合物；
    半导体通道，位于所述位线表面，在沿所述基底指向所述位线的方向上，所述半导体通道包括依次排列的第一掺杂区、沟道区以及第二掺杂区，所述第一掺杂区与所述位线相接触；
    第一介质层，覆盖所述第一掺杂区侧壁表面，且同一所述位线上相邻所述第一掺杂区侧壁的所述第一介质层之间具有第一间隔；
    绝缘层，覆盖所述沟道区侧壁表面；
    字线，覆盖所述绝缘层远离所述沟道区的侧壁表面，且相邻所述字线之间具有第二间隔；
    第二介质层，覆盖所述第二掺杂区侧壁表面，且位于相邻所述第二掺杂区侧壁的所述第二介质层之间具有第三间隔；
    第三介质层，位于所述第一间隔、所述第二间隔和所述第三间隔中。
  2. 如权利要求1所述的半导体结构，其中，所述半导体结构还包括：金属接触层，位于所述第二掺杂区远离所述基底的顶面，且所述金属半导体化合物和所述金属接触层中具有相同的金属元素。
  3. 如权利要求2所述的半导体结构，其中，所述金属接触层在所述基底上的正投影覆盖所述第二掺杂区在所述基底上的正投影。
  4. 如权利要求2所述的半导体结构，其中，所述半导体结构还包括：过渡层，位于所述第二掺杂区和所述金属接触层之间，且所述金属接触层包裹所述过渡层，所述过渡层和所述第二掺杂区掺杂有相同类型的掺杂离子，且所述掺杂离子在所述过渡层中的掺杂浓度大于在所述第二掺杂区中的掺杂浓度，所述掺杂离子为N型离子或P型离子中的一者。
  5. 如权利要求1所述的半导体结构，其中，所述基底、所述位线和所述半导体通道具有相同的半导体元素。
  6. 如权利要求1所述的半导体结构，其中，所述第一掺杂区、所述沟道区和所述第二掺杂区掺杂有相同类型的掺杂离子，且所述掺杂离子在所述第一掺杂区中的掺杂浓度与在所述沟道区和所述第二掺杂区中的掺杂浓度一致，所述 掺杂离子为N型离子或P型离子中的一者。
  7. 如权利要求1所述的半导体结构，其中，所述沟道区在所述基底上的正投影小于所述第二掺杂区在所述基底上的正投影，且小于所述第一掺杂区在所述基底上的正投影。
  8. 如权利要求1所述的半导体结构，其中，所述绝缘层和所述第二介质层为同一膜层结构。
  9. 如权利要求1所述的半导体结构，其中，所述绝缘层的外围在所述基底上的正投影小于所述第二介质层的外围在所述基底上的正投影。
  10. 如权利要求1所述的半导体结构，其中，所述第一介质层包括第四介质层和第五介质层，所述第四介质层位于相邻所述位线的间隔中，且位于相邻所述位线上的相邻所述第一掺杂区的间隔中；所述第五介质层位于同一所述位线上相邻所述第一掺杂区的侧壁，且位于所述第四介质层的侧壁。
  11. 如权利要求1所述的半导体结构，其中，位于所述第二间隔中的所述第三介质层中具有空隙。
  12. 一种半导体结构的制作方法，所述制作方法包括：
    提供基底；
    在所述基底上形成初始位线，以及在所述初始位线远离所述基底的表面形成半导体通道，在沿所述基底指向所述初始位线的方向上，所述半导体通道包括依次排列的第一掺杂区、沟道区以及第二掺杂区；
    形成覆盖所述第一掺杂区侧壁表面的第一介质层，且同一所述初始位线上相邻所述第一掺杂区侧壁的所述第一介质层之间具有第一间隔；
    形成覆盖所述沟道区侧壁表面的绝缘层；
    形成覆盖所述绝缘层远离所述沟道区的侧壁表面的字线，且相邻所述字线之间具有第二间隔；
    形成覆盖所述第二掺杂区侧壁表面的第二介质层，且位于相邻所述第二掺杂区侧壁的所述第二介质层之间具有第三间隔，所述第一间隔、所述第二间隔和所述第三间隔相连通并暴露出部分所述初始位线；
    对暴露出的所述初始位线进行金属化处理，以形成位线，所述位线的材料包括金属半导体化合物。
  13. 如权利要求12所述的半导体结构的制作方法，其中，在形成所述字线 之后，在形成所述第二介质层之前，所述制作方法还包括：
    采用外延生长工艺，在所述第二掺杂区远离所述基底的顶面形成初始过渡层，所述初始过渡层和所述第二掺杂区掺杂有相同类型的掺杂离子，所述掺杂离子在所述初始过渡层中的掺杂浓度大于在所述第二掺杂区中的掺杂浓度，所述掺杂离子为N型离子或P型离子中的一者，且所述初始过渡层在所述基底上的正投影覆盖所述第二掺杂区在所述基底上的正投影。
  14. 如权利要求13所述的半导体结构的制作方法，其中，在对所述初始位线进行所述金属化处理的步骤中，所述制作方法还包括：对所述初始过渡层进行金属化处理。
  15. 如权利要求12所述的半导体结构的制作方法，其中，形成所述第一介质层的步骤包括：
    形成初始第一介质层，所述初始第一介质层环绕所述半导体通道侧壁，且位于同一所述初始位线上相邻所述半导体通道侧壁的所述初始第一介质层之间具有第四间隔；
    形成第一隔离层，所述第一隔离层填充满所述第四间隔，且所述第一隔离层的材料和所述初始第一介质层的材料不同；
    刻蚀部分所述初始第一介质层至露出所述第二掺杂区侧壁；
    形成第二隔离层，所述第二隔离层环绕所述第二掺杂区侧壁和位于所述第一隔离层侧壁，位于所述第二掺杂区侧壁的所述第二隔离层和位于所述第一隔离层侧壁的所述第二隔离层共同围成通孔，所述通孔底部露出所述初始第一介质层，且所述第二隔离层的材料和所述初始第一介质层的材料不同；
    去除所述通孔露出的位于所述沟道区侧壁的所述初始第一介质层，剩余所述初始第一介质层作为所述第一介质层。
  16. 如权利要求15所述的半导体结构的制作方法，其中，形成所述绝缘层的步骤包括：
    对露出的所述沟道区侧壁进行热氧化处理，以形成所述绝缘层，且所述绝缘层覆盖剩余所述沟道区的侧壁表面，所述绝缘层和所述第一隔离层之间具有第五间隔。
  17. 如权利要求16所述的半导体结构的制作方法，其中，形成所述字线的步骤包括：
    形成初始字线，所述初始字线填充满所述第五间隔和所述通孔，且所述初始字线还位于相邻所述初始位线上的所述沟道区侧壁的所述绝缘层之间；
    去除位于所述通孔中的所述初始字线，剩余所述初始字线作为所述字线。
  18. 如权利要求12所述的半导体结构的制作方法，其中，形成所述第一介质层的步骤包括：
    形成初始第一介质层，所述初始第一介质层环绕所述半导体通道侧壁，且位于同一所述初始位线上相邻所述半导体通道侧壁的所述初始第一介质层之间具有第四间隔；
    形成第一隔离层，所述第一隔离层填充满所述第四间隔，且所述第一隔离层的材料和所述初始第一介质层的材料不同；
    刻蚀部分所述初始第一介质层至露出所述第二掺杂区侧壁和所述沟道区侧壁，剩余所述初始第一介质层作为所述第一介质层。
  19. 如权利要求18所述的半导体结构的制作方法，其中，形成所述绝缘层和所述第二介质层的步骤包括：
    形成覆盖所述第二掺杂区侧壁和所述沟道区侧壁的保护层，且所述保护层和所述第一隔离层之间具有第六间隔，所述沟道区侧壁的所述保护层为所述绝缘层，覆盖所述第二掺杂区侧壁的所述保护层为所述第二介质层。
  20. 如权利要求19所述的半导体结构的制作方法，其中，形成所述字线的步骤包括：
    形成初始字线，所述初始字线填充满所述第六间隔，且所述初始字线还位于相邻所述初始位线上的所述半导体通道部分侧壁的所述保护层之间；
    去除部分所述初始字线，剩余所述初始字线作为所述字线，所述字线仅环绕位于所述沟道区侧壁的所述绝缘层侧壁。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101572258A (zh) * 2008-05-02 2009-11-04 海力士半导体有限公司 半导体器件及其制造方法
CN108461496A (zh) * 2018-05-09 2018-08-28 睿力集成电路有限公司 集成电路存储器及其形成方法、半导体集成电路器件
CN208127209U (zh) * 2018-05-09 2018-11-20 长鑫存储技术有限公司 集成电路存储器及半导体集成电路器件
CN208655642U (zh) * 2018-09-05 2019-03-26 长鑫存储技术有限公司 半导体存储器

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3745392B2 (ja) * 1994-05-26 2006-02-15 株式会社ルネサステクノロジ 半導体装置
US5990509A (en) 1997-01-22 1999-11-23 International Business Machines Corporation 2F-square memory cell for gigabit memory applications
US7355230B2 (en) 2004-11-30 2008-04-08 Infineon Technologies Ag Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array
KR100673012B1 (ko) 2005-09-02 2007-01-24 삼성전자주식회사 이중 게이트형 수직 채널 트랜지스터들을 구비하는다이내믹 랜덤 억세스 메모리 장치 및 그 제조 방법
KR20070047572A (ko) * 2005-11-02 2007-05-07 삼성전자주식회사 반도체 장치 및 그 형성 방법
KR100985883B1 (ko) 2008-06-20 2010-10-08 주식회사 하이닉스반도체 4ｆ2 트랜지스터를 갖는 반도체 소자 및 그 제조방법
TWI368315B (en) * 2008-08-27 2012-07-11 Nanya Technology Corp Transistor structure, dynamic random access memory containing the transistor structure, and method of making the same
US7968876B2 (en) 2009-05-22 2011-06-28 Macronix International Co., Ltd. Phase change memory cell having vertical channel access transistor
KR101778287B1 (ko) * 2010-08-30 2017-09-14 삼성전자주식회사 반도체 메모리 소자 및 그 제조방법
KR101133701B1 (ko) 2010-09-10 2012-04-06 주식회사 하이닉스반도체 매립비트라인을 구비한 반도체장치 제조 방법
US20120080725A1 (en) 2010-09-30 2012-04-05 Seagate Technology Llc Vertical transistor memory array
KR101820022B1 (ko) 2010-11-11 2018-01-19 삼성전자주식회사 수직 채널 트랜지스터를 갖는 반도체 소자 및 그 제조방법
KR101802220B1 (ko) 2010-12-20 2017-11-29 삼성전자주식회사 수직형 채널 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법
US8530312B2 (en) * 2011-08-08 2013-09-10 Micron Technology, Inc. Vertical devices and methods of forming
TW201322255A (zh) * 2011-11-21 2013-06-01 Inotera Memories Inc 動態隨機存取記憶體結構及其製作方法
KR20130075348A (ko) 2011-12-27 2013-07-05 에스케이하이닉스 주식회사 매립비트라인을 구비한 반도체장치 및 그 제조 방법
KR20130103942A (ko) * 2012-03-12 2013-09-25 에스케이하이닉스 주식회사 무접합 수직 게이트 트랜지스터를 갖는 반도체 소자 및 그 제조 방법
US9023723B2 (en) * 2012-05-31 2015-05-05 Applied Materials, Inc. Method of fabricating a gate-all-around word line for a vertical channel DRAM
KR20160006466A (ko) * 2014-07-09 2016-01-19 에스케이하이닉스 주식회사 수직 채널을 갖는 반도체 집적 회로 장치 및 그 제조방법
US9646973B2 (en) * 2015-03-27 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-port SRAM cell structure with vertical devices
EP3435413A1 (en) * 2017-07-28 2019-01-30 IMEC vzw A semiconductor device and a method for forming a semiconductor device
CN109461756B (zh) * 2017-09-06 2021-05-14 中国科学院微电子研究所 Mram及其制造方法及包括mram的电子设备
CN109461738B (zh) 2017-09-06 2021-03-26 中国科学院微电子研究所 半导体存储设备及其制造方法及包括存储设备的电子设备
TWI653712B (zh) 2017-11-07 2019-03-11 華邦電子股份有限公司 半導體結構及其製造方法
CN108493188B (zh) 2018-05-09 2023-10-13 长鑫存储技术有限公司 集成电路存储器及其形成方法、半导体集成电路器件
CN110957319A (zh) 2018-09-27 2020-04-03 长鑫存储技术有限公司 集成电路存储器及其形成方法、半导体集成电路器件
CN111354738A (zh) 2018-12-21 2020-06-30 芯恩（青岛）集成电路有限公司 一种三维有结半导体存储器件及其制造方法
US10629615B1 (en) 2019-01-04 2020-04-21 Macronix International Co., Ltd. Semiconductor structure having doped active pillars in trenches
KR20210012710A (ko) 2019-07-26 2021-02-03 에스케이하이닉스 주식회사 수직형 메모리 장치 및 수직형 메모리 장치 제조 방법
US11315936B2 (en) 2019-08-29 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device and manufacturing method thereof
CN211719592U (zh) 2020-04-27 2020-10-20 长鑫存储技术有限公司 半导体结构和存储器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101572258A (zh) * 2008-05-02 2009-11-04 海力士半导体有限公司 半导体器件及其制造方法
CN108461496A (zh) * 2018-05-09 2018-08-28 睿力集成电路有限公司 集成电路存储器及其形成方法、半导体集成电路器件
CN208127209U (zh) * 2018-05-09 2018-11-20 长鑫存储技术有限公司 集成电路存储器及半导体集成电路器件
CN208655642U (zh) * 2018-09-05 2019-03-26 长鑫存储技术有限公司 半导体存储器

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