WO2023189513A1 - 配線基板 - Google Patents

配線基板 Download PDF

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Publication number
WO2023189513A1
WO2023189513A1 PCT/JP2023/009735 JP2023009735W WO2023189513A1 WO 2023189513 A1 WO2023189513 A1 WO 2023189513A1 JP 2023009735 W JP2023009735 W JP 2023009735W WO 2023189513 A1 WO2023189513 A1 WO 2023189513A1
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WO
WIPO (PCT)
Prior art keywords
conductor layer
silica particles
wiring board
conductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/009735
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
裕明 佐野
登志文 東
晃 井本
貴史 山口
泉太郎 山元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to CN202380028008.6A priority Critical patent/CN118947228A/zh
Priority to EP23779533.1A priority patent/EP4503867A1/en
Priority to JP2024511717A priority patent/JPWO2023189513A1/ja
Priority to US18/851,565 priority patent/US20250185162A1/en
Publication of WO2023189513A1 publication Critical patent/WO2023189513A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1283—After-treatment of the printed patterns, e.g. sintering or curing methods
    • H05K3/1291—Firing or sintering at relative high temperatures for patterns on inorganic boards, e.g. co-firing of circuits on green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0175—Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0242—Shape of an individual particle
    • H05K2201/0257—Nanoparticles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1126—Firing, i.e. heating a powder or paste above the melting temperature of at least one of its constituents

Definitions

  • the disclosed embodiments relate to a wiring board.
  • wiring boards that have an insulating layer mainly composed of ceramics and a conductor layer mainly composed of metal.
  • Such a wiring board can be obtained, for example, by simultaneously firing a conductive material made of copper powder to which a metal oxide is added and glass ceramics as an insulating layer material (for example, see Patent Document 1).
  • the wiring board of the present disclosure includes an insulating layer made of ceramic, and a conductor layer extending in a planar direction inside the insulating layer.
  • the conductor layer is composed of a sintered body of a plurality of crystallites whose main component is metal.
  • FIG. 1 is an enlarged sectional view showing an example of the configuration of a wiring board according to an embodiment.
  • FIG. 2 is an enlarged view of area A shown in FIG.
  • FIG. 3 is a diagram showing a SEM observation photograph of the conductor layer according to Example 1.
  • wiring boards that have an insulating layer mainly composed of ceramics and a conductor layer mainly composed of metal.
  • Such a wiring board is obtained, for example, by simultaneously firing a conductive material made of copper powder to which a metal oxide is added and glass ceramics as an insulating layer material.
  • FIG. 1 is an enlarged sectional view showing an example of the wiring board 1 according to the embodiment
  • FIG. 2 is an enlarged view of area A shown in FIG. 1.
  • the wiring board 1 according to the embodiment includes an insulating layer 10 and a conductor layer 20.
  • the insulating layer 10 can be made of, for example, a glass ceramic sintered body.
  • the glass ceramic sintered body may contain ceramics such as aluminum oxide, aluminum nitride, silicon carbide, silicon nitride, or mullite as a filler.
  • the insulating layer 10 may be made of glass ceramics, for example.
  • the wiring board 1 can be manufactured by simultaneously firing the green sheet, which is the raw material for the insulating layer 10, and the conductive paste, which is the raw material for the conductor layer 20. Therefore, according to the embodiment, the manufacturing cost of the wiring board 1 can be reduced.
  • the insulating layer 10 may include a first layer 11 and a second layer 12 facing each other with the conductor layer 20 in between.
  • the first layer 11 and the second layer 12 are located, for example, so as to sandwich both sides of the conductor layer 20 in the thickness direction.
  • the conductor layer 20 is electrically conductive and extends in the planar direction (lateral direction in FIG. 1) inside the insulating layer 10.
  • the conductor layer 20 is arranged, for example, between the first layer 11 and the second layer 12 in a predetermined pattern shape. Note that in the present disclosure, the conductor layer 20 may be exposed and located on the surface of the wiring board 1.
  • the conductor layer 20 is composed of a sintered body of a plurality of crystallites 21.
  • the crystallite 21 is made of a metal material such as copper, silver, palladium, gold, platinum-tungsten, molybdenum, or manganese, or an alloy material or mixed material containing these metal materials as main components.
  • the term "mainly composed of a metal material or a metal (for example, copper)” refers to a case where the metal occupies 70 (%) or more by volume in the conductor layer 20. If the conductor layer 20 includes voids, the volume ratio of the metal excluding the voids may be set to 80(%) or more. The upper limit of the volume ratio of metal (for example, copper) contained in the conductor layer 20 may be 99(%).
  • the upper limit of the volume ratio of the metal (for example, copper) contained in the conductor layer 20 is set to 99 (%) is that the wiring board 1 of the present disclosure is formed by co-firing a ceramic insulating layer and a metal. Therefore, it is taken into consideration that elements contained in the insulating layer inevitably enter the conductive layer 20 from the insulating layer 10.
  • the volume ratio of metal in the conductor layer 20 is determined, for example, by the following method.
  • the area ratio of the metal determined by the following method is defined as the volume ratio.
  • the wiring board 1 is cut or crushed to expose its internal cross section.
  • one conductor layer 20 seen in the exposed cross section of the wiring board 1 is selected. At this time, if the length of the conductor layer 20 is long enough to correspond to the width of the wiring board 1, a specific length is specified.
  • the specified length may be within a range where the portion of the conductor layer 20 to be evaluated can fit in one photograph or screen when observed and photographed using a scanning electron microscope (SEM), which will be described later. As for the length, it is better that the size is larger than the thickness of the conductor layer 20.
  • a good guideline for the length is 1 ( ⁇ m) or more and 100 ( ⁇ m) or less.
  • the target range of the conductor layer 20 is preferably a range that can be seen as an outline when observed using a scanning electron microscope, for example.
  • the outline of the conductor layer 20 is preferably determined from a backscattered electron image, which is one of the analysis methods using a scanning electron microscope, but it may also be determined by mapping analysis using an elemental analyzer attached to a scanning electron microscope. .
  • an electron back scattered diffraction (EBSD) method may be used to measure the volume fraction of metal.
  • EBSD electron back scattered diffraction
  • the area of all voids included in the observation range may be removed from the area of the conductor layer 20 in advance.
  • the size of the void to be counted as a void is based on a void having a maximum diameter of 0.1 ( ⁇ m) or more.
  • a specific range (for example, area A) of the conductor layer 20 is specified in a cross-sectional view, the straight line length in the plane direction (horizontal direction in FIG. 2) is set as L0, and the outline 20a of the conductor layer 20 is When the length (that is, the length of the interface between the conductor layer 20 and the insulating layer 10) is L1, L1/L0 is in the range of 1.04 to 1.40.
  • the specific range is a range in which the width of the conductor layer 20 in the longitudinal direction is greater than or equal to 10 ( ⁇ m) and less than or equal to 100 ( ⁇ m).
  • the width in the longitudinal direction in this specific range can be selected from a range of 10 ⁇ m (or more) and 100 ( ⁇ m) or less.
  • Such an arbitrary width is determined in consideration of the thickness of the conductor layer 20, the size of the crystallites 21 contained in the conductor layer 20, and the like.
  • the specific range may be a range where one conductor layer 20 is sandwiched between upper and lower insulating layers 10.
  • the specific range multiple locations in the photographed photograph may be designated.
  • the interfacial conductivity of the conductor layer 20 can be increased.
  • the sintered body constituting the conductor layer 20 includes nano-sized silica particles 22 (see FIG. 3), and the silica particles 22 may be located on the surface of the crystallites 21.
  • silica may exist in the form of particles on the surface of the conductor layer 20.
  • the surface of the conductor layer 20 refers to the vicinity of the interface between the insulating layer 10 and the conductor layer 20 when the conductor layer 20 is formed on the surface of the insulating layer 10.
  • This "near the interface” includes a small width range from the surface of the conductor layer 20 to the inside of the conductor layer 20.
  • This "slight width” is, for example, a range within 1 ( ⁇ m) from the surface of the conductor layer 20.
  • the conductor layer 20 When the silica particles 22 are present on the surface of the conductor layer 20, the conductor layer 20 has a distance from the silica particles 22 of 1 ( ⁇ m) or less and a range of 1 ( ⁇ m) or less from the surface of the conductor layer 20. In this case, there are no voids in some parts. In this case, the void refers to a space whose size is equal to or larger than the maximum diameter of the silica particles 22.
  • the conductive layer 20 has such a dense region around the silica particles 22 is that the silica particles 22 exist at the interface with the insulating layer 10, so that components from the insulating layer 10 are absorbed. This is thought to be because the sintering behavior of the copper powder is controlled by reducing diffusion into the copper powder, resulting in gradual sintering.
  • the presence of the silica particles 22 near the interface with the insulating layer 10 partially reduces the diffusion of glass components from the glass-ceramic insulating layer 10. In this way, since the surface of the insulating layer 10 can maintain a gentle shape during firing, the shape of the surface of the conductor layer 20 can be maintained flat. The silica particles 22 are unlikely to cause excessive reaction with the insulating layer 10.
  • the conductor layer 20 has a microstructure formed by fine copper crystallites 21.
  • the plurality of crystallites 21 include those having a polygonal shape including linear sides, and are in contact with the sides as grain boundaries.
  • the longest diameter of the crystallite 21 is preferably 1 ( ⁇ m) or more and 10 ⁇ m (or less).
  • the plurality of crystallites 21 preferably have a number ratio of 70 (%) or more of crystallites having two or more sides.
  • the presence of silica particles 22 on the surface of the conductor layer 20 can improve the adhesion between the conductor layer 20 and the insulating layer 10.
  • the silica particles 22 may be present over the entire surface of the conductor layer 20 facing the insulating layer 10, or may be present only on a part of the surface of the conductor layer 20. When a plurality of silica particles 22 are present on the surface of the conductor layer 20, these silica particles 22 may be isolated from each other.
  • the shrinkage behavior of the metal material (for example, copper) used during firing is similar to the shrinkage behavior of the silica particles 22.
  • the reason why the shrinkage behavior of the metal material used for the conductor layer 20 during firing and the shrinkage behavior of the silica particles 22 are similar is considered to be that the size of the silica particles 22 is minute (nano size). .
  • silica particles 22 larger than nano-sized are used, the particle size distribution will expand based on the size, and the heat capacity will increase due to the size. These factors become factors that change the sintering behavior and adhesion.
  • the temperature range in which the glass powder reaches a molten state is different from that of the nano-sized silica particles 22. It is wider than in the case of silica particles 22.
  • the melting temperature of glass powder may start at a lower temperature than that of nano-sized silica particles 22.
  • glass powder often has a wide particle size distribution. When glass powder having these properties is used, the glass powder tends to aggregate or move during sintering within the printed pattern that becomes the conductor layer 20.
  • nano-sized silica particles 22 when they have a single composition, the temperature range in which they reach a molten state is narrower than when using glass powder. As a result, the conductor layer 20 becomes dense, and gently shaped recesses are likely to be formed on the surface along the insulating layer 10.
  • the particle size of the silica particles 22 according to the embodiment is preferably 1 (nm) to 50 (nm).
  • the particle size refers to the diameter.
  • the diameter refers to the maximum diameter obtained when observing the silica particles 22.
  • the silica particles 22 preferably have an average particle diameter of 20 (nm). Further, it is preferable that the cumulative amount of the silica particles 22 has a lower limit of 10 (nm) and an upper limit of 30 (nm) of 70 (%) or more.
  • the area ratio of the silica particles 22 in the conductor layer 20 may be 0.002 (%) to 0.067 (%). Thereby, the interfacial conductivity of the conductor layer 20 can be increased. Note that how to determine the area ratio of the silica particles 22 in the conductor layer 20 will be described later.
  • the content rate of the silica particles 22 in the conductor layer 20 may be 0.099 (wt%) to 2.912 (wt%).
  • the interfacial conductivity of the conductor layer 20 can be increased.
  • the content rate of the silica particles 22 is the ratio obtained by dividing the amount of the silica particles 22 added by the total amount of the copper powder and the silica particles 22.
  • the crystallite 21 may be composed of copper as a main component, and the copper content in the conductor layer 20 may be 80 (wt%) to 99 (wt%). Thereby, the interfacial conductivity of the conductor layer 20 can be further increased.
  • the crystallites 21 may have a polygonal shape. This makes it possible to reduce the decrease in the interfacial conductivity in a high frequency region (for example, 1 (GHz) to 49 (GHz)), thereby increasing the interfacial conductivity of the conductor layer 20 in the high frequency region.
  • a high frequency region for example, 1 (GHz) to 49 (GHz)
  • a mixture of 40 (wt%) alumina particles and 60 (wt%) borosilicate glass was prepared as a material for the insulating layer.
  • Such a mixture is a raw material for glass ceramics with a firing temperature of 900 (°C) to 1000 (°C).
  • copper powder purity 99.9 (wt%)
  • silica particles with an average particle size of 20 (nm) were prepared.
  • the amount of silica particles added was 0.1 (parts by mass) with respect to 100 (parts by mass) of copper powder.
  • a mixed solvent of isobutyl methacrylate resin, butyl carbitol acetate, and dibutyl phthalate was used as the organic binder. Then, isobutyl methacrylate resin is added at a ratio of 5 (parts by mass) to 100 (parts by mass) of copper powder, and a mixed solvent of butyl carbitol acetate and dibutyl phthalate is further added to contain copper powder and silica particles. A conductive paste was prepared.
  • a conductive paste was printed on both surfaces of the produced green sheet in a predetermined area and fired.
  • the firing was performed in a reducing atmosphere using a hydrogen-nitrogen mixed gas at a maximum temperature of 930 (° C.) and a holding time of 2 hours.
  • a plurality of green sheets were stacked to have a thickness of 500 ( ⁇ m). Thereby, the wiring board 1 of Example 1 was obtained.
  • Examples 2 to 7 Wiring substrates 1 of Examples 2 to 7 were obtained using the same method and conditions as in Example 1 above, except for the amount of silica particles added in the conductor paste manufacturing process.
  • Examples 2 to 7 in the process of manufacturing the conductive paste, 0.3 (parts by mass), 0.5 (parts by mass), 1 (parts by mass), and 1.5 (parts by mass), 2 (parts by mass), and 3 (parts by mass).
  • Example 8 The wiring board 1 of Example 8 was obtained using the same method and conditions as in Example 1 described above except for the process of manufacturing the conductive paste.
  • copper powder purity 99.9 (wt%)
  • borosilicate glass powder with an average particle size of 2 ( ⁇ m) were prepared as raw materials for the conductor layer. did.
  • the amount of glass powder added was 6 (parts by mass) per 100 (parts by mass) of copper powder.
  • a mixed solvent of isobutyl methacrylate resin, butyl carbitol acetate, and dibutyl phthalate was used as the organic binder.
  • a conductor containing copper powder and glass powder by adding isobutyl methacrylate resin at a ratio of 5 (parts by mass) to 100 (parts by mass) of copper powder, and further adding a mixed solvent of butyl carbitol acetate and dibutyl phthalate.
  • a paste was prepared.
  • FIG. 3 is a diagram showing a SEM observation photograph of the conductor layer 20 according to Example 1.
  • silica particles 22 were observed between adjacent copper crystallites 21 (that is, on the surfaces of crystallites 21).
  • the volume ratio of metal (copper) contained in the conductor layer 20 of the manufactured wiring board 1 was 90 (%) or more and 98 (%) or less in all samples, excluding the void portion.
  • point A and point B are attached to both ends of one outline 20a for the conductor layer 20 shown in the cross-sectional photograph, and a straight line is drawn between the points A and B.
  • the length of this straight line was defined as L0.
  • the length of the contour 20a from point A to point B was determined, and this length was defined as L1.
  • L1/L0 was determined as the ratio of both lengths.
  • the area ratios of the silica particles 22 in Examples 1 to 8 were measured. Specifically, first, a plurality of square ranges with a length of 1/10 to 1/2 of the thickness of the conductor layer 20 shown in the cross-sectional photograph were specified. For example, 8 to 10 such square ranges are specified so that they are arranged continuously in the direction in which the conductor layer 20 extends (planar direction).
  • the area of the metal portion (corresponding to the crystallites 21) in the area divided by the squares was set as A0. Further, the area of the black portion (corresponding to the silica particles 22) shown in FIG. 3 was defined as A1.
  • the ratio A1/A0 of both areas was taken as the area ratio of the silica particles 22 in one square area.
  • the average value of the area proportions of the silica particles 22 in a plurality of square areas was taken as the area proportion of the silica particles 22 of this sample.
  • the interfacial conductivity of each of the wiring boards 1 of Examples 1 to 8 obtained above was measured.
  • the interfacial conductivity was measured by the dielectric cylindrical resonator method described below. Further, as a sample for measurement, one having a diameter of 50 (mm) and having a conductor layer 20 formed over almost the entire surface of both surfaces was used.
  • a method for measuring interfacial conductivity using the dielectric cylinder resonator method is to form the above-mentioned conductor inside on both end faces or one end face of a dielectric cylinder made of a dielectric material whose relative dielectric constant and dielectric loss are known. This method measures the conductivity at the interface between a conductor and an insulating layer, that is, at the conductor interface, by attaching insulating layers in a predetermined relationship to form a dielectric resonator.
  • the principle of this measurement method is that a conductor plate (usually the diameter of the dielectric cylinder
  • a conductor plate usually the diameter of the dielectric cylinder
  • conductor plates having a diameter D approximately three times as large as That is, this is due to the fact that it is distributed only on the opposing surfaces of the dielectric and the conductor.
  • a high frequency current flowing through a conductor in TEomn mode flows through the dielectric material in contact with the conductor and the dielectric cylinder.
  • the interfacial conductivity was measured at a frequency of 10 (GHz).
  • the sample for evaluation was cut at a position approximately 1/2 the length in one direction, and both the interface between the insulating layer 10 and the conductor layer 20 in the cross section was observed. . If a peeled portion was observed at even one location, it was determined that there was "peeling", and if no peeled portion was found at any interface, it was determined that there was "no peeling".
  • the state of "peeling” is defined as a case where the length of the region where the distance between the insulating layer 10 and the conductor layer 20 is 0.1 (mm) or more is 1 (mm) or more. .
  • the amount of silica particles and glass powder added in the conductor layer 20 the value of L1/L0 in the conductor layer 20, the area ratio of the silica particles in the conductor layer 20, and the frequency 10 (GHz Table 1 shows the measurement results of the interfacial conductivity in ) and the evaluation results of the presence or absence of conductor peeling. Note that the measurement results of the interfacial conductivity at a frequency of 10 (GHz) are relative values when the interfacial conductivity at direct current is 100 (%).
  • the interfacial conductivity of the conductor layer 20 can be increased by setting the value of L1/L0 in the conductor layer 20 in the range of 1.04 to 1.40. Furthermore, it can be seen that by setting the value of L1/L0 in the conductor layer 20 in the range of 1.04 to 1.18, the interfacial conductivity of the conductor layer 20 can be made higher.
  • the interfacial conductivity of the conductor layer 20 can be further increased. Furthermore, it can be seen that by setting the value of L1/L0 in the conductor layer 20 in the range of 1.04 to 1.11, the interfacial conductivity of the conductor layer 20 can be further increased.
  • the value of L1/L0 in the conductor layer ends up being 2 or more. Further, in this printed circuit board, since the contour of the conductor layer has large irregularities, the interfacial conductivity of the conductor layer decreases.
  • samples (Example 2 to Implementation It can be seen that in Example 5), the interfacial conductivity of the conductor layer 20 can be further increased, and the peeling of the conductor of the conductor layer 20 can be reduced.
  • the interfacial conductivity of the conductor layer 20 can be increased. I understand. Furthermore, it is found that peeling of the conductor in the conductor layer 20 can be reduced by setting the area ratio of the silica particles 22 in the conductor layer 20 to a range of 0.005 (%) to 0.067 (%).
  • the interfacial conductivity of the conductor layer 20 can be made higher, and the It can be seen that conductor peeling can be reduced.
  • the interfacial conductivity of the conductor layer 20 can be further increased. It can be seen that conductor peeling can be reduced.
  • fine ceramic powder other than silica for example, fine alumina powder, etc.
  • fine alumina powder for example, fine alumina powder, etc.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
PCT/JP2023/009735 2022-03-30 2023-03-13 配線基板 Ceased WO2023189513A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202380028008.6A CN118947228A (zh) 2022-03-30 2023-03-13 布线基板
EP23779533.1A EP4503867A1 (en) 2022-03-30 2023-03-13 Wiring board
JP2024511717A JPWO2023189513A1 (https=) 2022-03-30 2023-03-13
US18/851,565 US20250185162A1 (en) 2022-03-30 2023-03-13 Wiring board

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Application Number Priority Date Filing Date Title
JP2022-056142 2022-03-30
JP2022056142 2022-03-30

Publications (1)

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WO2023189513A1 true WO2023189513A1 (ja) 2023-10-05

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US (1) US20250185162A1 (https=)
EP (1) EP4503867A1 (https=)
JP (1) JPWO2023189513A1 (https=)
CN (1) CN118947228A (https=)
WO (1) WO2023189513A1 (https=)

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JP2003277852A (ja) 2002-03-25 2003-10-02 Kyocera Corp 銅メタライズ組成物およびセラミック配線基板
JP2004134378A (ja) * 2002-07-17 2004-04-30 Ngk Spark Plug Co Ltd 銅ペーストとそれを用いた配線基板
JP2008159726A (ja) * 2006-12-22 2008-07-10 Kyocera Corp 多層配線基板
WO2015118982A1 (ja) * 2014-02-04 2015-08-13 株式会社村田製作所 電子部品モジュール、および電子部品モジュールの製造方法

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JP2004006624A (ja) * 2002-03-27 2004-01-08 Kyocera Corp 配線基板及びその製造方法
JP4703212B2 (ja) * 2005-02-21 2011-06-15 京セラ株式会社 配線基板及びその製造方法
JP4781189B2 (ja) * 2006-07-27 2011-09-28 京セラ株式会社 配線基板
JP6129738B2 (ja) * 2011-07-14 2017-05-17 株式会社東芝 セラミックス回路基板
JP6260731B1 (ja) * 2017-02-15 2018-01-17 Tdk株式会社 ガラスセラミックス焼結体およびコイル電子部品

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003123537A (ja) * 2001-08-07 2003-04-25 Mitsui Mining & Smelting Co Ltd 混合銅粉、その混合銅粉の製造方法、その混合銅粉を用いた銅ペースト及びその銅ペーストを用いたプリント配線板
JP2003277852A (ja) 2002-03-25 2003-10-02 Kyocera Corp 銅メタライズ組成物およびセラミック配線基板
JP2004134378A (ja) * 2002-07-17 2004-04-30 Ngk Spark Plug Co Ltd 銅ペーストとそれを用いた配線基板
JP2008159726A (ja) * 2006-12-22 2008-07-10 Kyocera Corp 多層配線基板
WO2015118982A1 (ja) * 2014-02-04 2015-08-13 株式会社村田製作所 電子部品モジュール、および電子部品モジュールの製造方法

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