Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
  • H01J37/32082—Radio frequency generated discharge
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
  • H01J37/32082—Radio frequency generated discharge
  • H01J37/32128—Radio frequency generated discharge using particular waveforms, e.g. polarised waves
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
  • H01J37/32082—Radio frequency generated discharge
  • H01J37/32137—Radio frequency generated discharge controlling of the discharge by modulation of energy
  • H01J37/32146—Amplitude modulation, includes pulsing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
  • H01J37/32082—Radio frequency generated discharge
  • H01J37/32174—Circuits specially adapted for controlling the RF discharge
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32431—Constructional details of the reactor
  • H01J37/32697—Electrostatic control
  • H01J37/32706—Polarising the substrate
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of DC power input into DC power output
  • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
  • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
  • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
  • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
  • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
  • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
  • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
  • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
  • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
  • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
  • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
  • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
  • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
  • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
  • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
  • H02M7/539—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
  • H02M7/5395—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/53—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback
  • H03K3/57—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback the switching device being a semiconductor device

Definitions

• the present invention relates generally to power supplies, and more specifically to power supplies for applying a voltage for plasma processing.
• the substrate is a dielectric, however, a non-varying voltage is ineffective to place a voltage across the surface of the substrate.
• an alternating current (AC) voltage e.g., high frequency AC or radio frequency (RF)
• AC alternating current
• RF radio frequency
• the surface of the substrate will be charged negatively, which causes ions to be attracted toward the negatively-charged surface during the negative portion of the AC cycle.
• the impact dislodges material from the surface of the substrate — effectuating the etching.
• An aspect may be characterized as a bias supply to apply a periodic voltage.
• the bias supply comprises a switch network and at least one power supply coupled to an output node and a return node.
• the switch network and the at least one power supply are configured, in combination, to apply an asymmetric periodic voltage waveform and a corresponding current waveform at the output node relative to the return node.
• a timing parameter estimator is configured to receive a digital representation of a full cycle of the asymmetric periodic voltage waveform and the current waveform and to generate a pulse width control signal based on a first crossing time that the current waveform crosses a threshold current value after falling from a positive peak current value.
• a gate drive signal generator is configured to, responsive to the pulse width control signal received from the timing parameter estimator, provide a gate drive signal to at least one switch of the switch network to control application of the asymmetric periodic voltage waveform and the current waveform to the output node relative to the return node.
• Yet another aspect may be characterized as a method for applying a periodic voltage.
• the method comprises applying an asymmetric periodic voltage waveform and providing a corresponding current waveform at an output node relative to a return node of a bias supply.
• Digital representations of the asymmetric periodic voltage waveform and the current waveform are received, and a pulse width control signal is generated based on a first crossing time that the current waveform crosses a threshold current value after falling from a positive peak current value.
• a gate drive signal is provided, responsive to the pulse width control signal, to at least one switch of a switch network to control application of the asymmetric periodic voltage waveform.
• bias supply to apply a periodic voltage comprising an output node, a return node, and means for applying an asymmetric periodic voltage waveform and a corresponding current waveform at the output node relative to the return node.
• the bias supply also comprises a processor and non-volatile memory, the nonvolatile memory comprising non- transient, processor executable instructions, the instructions comprising instructions to receive a digital representation of a full cycle of the asymmetric periodic voltage waveform and the current waveform and generate a pulse width control signal based on a first crossing time that the current waveform crosses a threshold current value after falling from a positive peak current value.
• the bias supply comprises a gate drive signal generator configured to, responsive to the pulse width control signal received from the timing parameter estimator, provide a gate drive signal to at least one switch of the switch network to control application of the asymmetric periodic voltage waveform and the current waveform to the output node relative to the return node.
• FIG. 1 is a block diagram depicting an exemplary plasma processing environment in which bias supplies disclosed herein may be utilized
• FIG. 2 is a schematic diagram depicting an exemplary bias supply
• FIG. 3 is a schematic diagram electrically representing aspects of a plasma processing chamber
• FIG. 4 is a block diagram depicting aspects of sampling, readback, and control of a bias supply
• FIG. 5 is a block diagram depicting a control system for a bias supply with two power supplies
• FIG. 6 is a block diagram depicting a control system for a bias supply with one power supply
• FIG. 7A is a schematic diagram depicting an example of a one-switch network that may be implemented in a bias supply having a one power supply configuration
• FIG. 7B is a schematic diagram depicting another example of a one-switch network that may be implemented in a bias supply having a one power supply configuration
• FIG. 8 is a schematic diagram depicting an example of a one-switch network that may be implemented in a bias supply having a two-power supply configuration
• FIG. 9 depicts graphs and a timing diagram illustrating aspects of a bias supply that comprises a single switch
• FIG. 10 depicts complete digital representations of one cycle of the asymmetrical periodic output voltage and current waveforms associated with implementations of bias supplies having one switch;
• FIG. 11 is a flowchart depicting a method for setting the gate drive pulse width and reset time that may be performed in conjunction with bias supplies having a one- switch network and either one or two power supplies;
• FIG. 12 is a flowchart depicting another method for setting the gate drive pulse width and reset time that may be performed in conjunction with bias supplies having a one-switch network and either one or two power supplies;
• FIG. 13 is a flowchart depicting a method for setting the gate drive pulse width and reset time that may be performed in conjunction with bias supplies having a one- switch network and one power supply;
• FIG. 14 is a flowchart depicting a method for computing the threshold current value in conjunction with bias supplies having a one-switch network
• FIG. 15 is a flowchart depicting a method for computing the threshold voltage value in conjunction with bias supplies having a one switch, one power supply configuration
• FIG. 16 is a flowchart depicting a method for computing the threshold voltage value in conjunction with bias supplies having a one switch, two power supply configuration
• FIG. 17 is a schematic diagram depicting an example of a two-switch network that may be implemented in a bias supply having a one power supply configuration
• FIG. 18 is a schematic diagram depicting an example of a two-switch network that may be implemented in a bias supply having a two power supply configuration
• FIG. 19 depicts graphs and a timing diagram illustrating aspects of a bias supply that comprises two switches
• FIG. 20 depicts complete digital representations of one cycle of the asymmetrical periodic output voltage and current waveforms associated with implementations of bias supplies having two switches;
• FIG. 21 is a flowchart depicting a method for setting gate drive pulse widths and reset time that may be performed in conjunction with bias supplies having a two-switch network;
• FIG. 22 is a flowchart depicting a method for computing threshold current values in conjunction with bias supplies having a two-switch network
• FIG. 23 is a block diagram depicting components that may be utilized to implement control aspects disclosed herein.
• source generators are those whose energy is primarily directed to generating and sustaining the plasma
• bias supplies are those whose energy is primarily directed to generating a surface potential for attracting ions and electrons from the plasma.
• bias supplies that may be used to apply a periodic voltage function to a substrate support in a plasma processing chamber.
• the plasma processing environment may include many pieces of equipment coupled directly and indirectly to a plasma processing chamber 101, within which a volume containing a plasma 102 and workpiece 103 (e.g., a wafer) and electrodes 104 (which may be embedded in a substrate support) are contained.
• the equipment may include vacuum handling and gas delivery equipment (not shown), one or more bias supplies 108, one or more source generators 112, and one or more source matching networks 113.
• the source generator 112 may be a higher frequency RF generator (e.g., 13.56 MHz to 120 MHz).
• the electrode 105 generically represents what may be implemented with an inductively coupled plasma (ICP) source, a dual capacitively-coupled plasma source (CCP) having a secondary top electrode biased at another RF frequency, a helicon plasma source, a microwave plasma source, a magnetron, or some other independently operated source of plasma energy.
• ICP inductively coupled plasma
• CCP dual capacitively-coupled plasma source
• the source generator 112 and source matching network 113 may be replaced by, or augmented with, a remote plasma source.
• Other variations of the system may include only a single bias supply 108.
• many other variations of the plasma processing environment depicted in FIG. 1 may be utilized.
• implementations can include any substrate processing within a plasma chamber.
• objects other than a substrate can be processed using the systems, methods, and apparatus herein disclosed.
• this disclosure applies to plasma processing of any object within a sub-atmospheric plasma processing chamber to affect a surface change, subsurface change, deposition, or removal by physical or chemical means.
• the bias supply 208 includes an output 210 (also referred to as an output node 210), a return node 212, a switch network 220, and a series combination of an inductance 214 and a first power supply 216 (also referred to herein as Vsuppiy) that is coupled between the output node 210 and the return node 212.
• the bias supply 208 functions to apply an asymmetric periodic voltage function V ou t between the output node 210 and the return node 212.
• Current delivered to a load through the output node 210 is returned to the bias supply 208 through the return node 212 that may be common with the load.
• the bias supply 208 may be coupled to a controller and/or include a controller that is coupled to the switch network 220.
• Variations of the switch network 220 are disclosed further herein, but first, it is helpful to understand aspects of a plasma load.
• the plasma processing chamber 101 may be represented by a chuck capacitance Cch (that includes a capacitance of a chuck and workpiece 103) that is positioned between an input 310 (also referred to as an input node 310) to the plasma processing chamber 101 and a node representing a sheath voltage V s at a surface of the workpiece 103 (also referred to as a wafer substrate 103). Therefore, references to the sheath voltage V s are also referred to herein as a voltage at a surface of the wafer or substrate.
• a return node 312 (which may be a connection to ground) is depicted.
• the plasma 102 in the processing chamber is represented by a parallel combination of a sheath capacitance Cs, a diode, and a current source.
• the diode represents the non-linear, diode-like nature of the plasma sheath that results in rectification of the applied AC field, such that a direct-current (DC) voltage drop, appears between the workpiece 103 and the plasma 102.
• DC direct-current
• FIG. 4 shown is a block diagram depicting general aspects of metrology, readback and control. Shown are the bias supply 208, a metrology section 620 and a digital control section 622.
• the metrology section 620 receives signals indicative of power-related parameter values and provides a digital representation of the power-related parameter values to the digital control section 622.
• the power related parameters may be the output current i ou t provided to the output node 210 and the voltage Vout between the output node 210 and the return node 212.
• the return node may be a ground connection.
• the metrology section 620 may receive signals from one or more bias supply signal lines 624.
• the bias supply signal lines 624 may convey signals indicative of bias supply parameters such as the compensation current I CO mp, temperature, and other parameters within the bias supply 208.
• a current signal line 626 may provide analog signals from a current transducer that are indicative of current provided to the output node 210, and a voltage line 628 may provide analog signals that are indicative of the voltage Vout at the output of the bias supply.
• the metrology section 620 samples and digitizes the power-related signals. For example, the metrology section 620 may provide complete digital representations of the asymmetrical periodic voltage waveform V ou t, the output current waveform i ou t, and/or the compensation current I CO mp.
• An aspect of many variations of the metrology section 620 is that the complete voltage and current waveforms are captured, which provides enhanced visibility of the output of the bias supply and enables improved control aspects disclosed further herein.
• the metrology section 620 may be realized in part by a field programmable gate array, and the digital control section 622 may be realized by one or more processors that execute code stored in non-transitory media (to effectuate the functions of the digital control section 622).
• Other combinations of hardware, software, and firmware may be used to realize the metrology section 620 and the digital control section 622.
• the digital representations of the asymmetrical periodic voltage waveform V ou t, the output current waveform i ou t, and/or i CO mp may be provided to a data reporting component 631, which may be a user interface (e.g., a touchscreen display).
• a data reporting component 631 may be a user interface (e.g., a touchscreen display).
• the digital representations of the asymmetrical periodic voltage waveform V ou t, the output current i ou t and/or the compensation current i CO mp are provided to a data processing module 630, which may further process the digital representations of the asymmetrical periodic voltage waveform V ou t, the output current waveform i ou t and/or the compensation current icomp to provide readback of one or more of sheath voltage v s , and one or more other parameter values such as Ei on , V s te P , AEi on , output voltage slope (e.g., the slope of the third portion of the asymmetrical periodic voltage waveform), and/or a slope deviation factor, Ks.
• a data processing module 630 may further process the digital representations of the asymmetrical periodic voltage waveform V ou t, the output current waveform i ou t and/or the compensation current icomp to provide readback of one or more of sheath voltage v s , and one or more other parameter values such as
• the slope deviation factor, Ks may be calculated as: where slope w is the slope from t3 to t4 of the wafer/sheath voltage.
• the slope deviation factor may be calculated to satisfy the following equation:
• the slope deviation factor, Ks provides a convenient representation of a level of compensation current I CO mp relative to the ion current Ii on .
• the compensation current is providing a full compensation; when Ks 0, Icomp is overcompensating for the ion current, and when Ks ⁇ 0, the compensation current I CO mp is undercompensating for the ion current Ii on .
• the readback values may also be used as part of feedback control.
• a first comparator 638 may calculate a difference between a first setpoint, setpointl, and a first readback value, readbackl, to produce a first error signal, errorl .
• a second comparator 640 may calculate a difference between a second setpoint, setpoint2, and a second readack value, readback2, to produce a second error signal error2.
• the error signals (errorl and error 2) may be fed to one or more compensators 632, and the one or more compensators 632 may provide control signals (Ctrl_knobl and Ctrl_knob2) to the bias supply 208 as described further herein.
• Timing parameter estimator 634 may receive the digital representations of the output voltage waveform V ou t and the output current waveform i ou t and produce a pulse width control signal.
• the timing parameter estimator 634 detects when there is zero current through switches of the bias supply and sets the pulse width to cause the switches to open (turn off) at or after that time, in order to reduce switching-related losses; thus, the on time for the switches is also controlled.
• the timing parameter estimator 634 may also determine treset (shown in FIGS. 4 and 5), and the value for t re set may be reported via the data reporting component 631 and provided to the data processing module 630.
• Timing parameter estimator 634 may be realized by one or more processors that execute code stored in non- transitory media, and/or other combinations of hardware, software, and firmware.
• the digital control section 622 also comprises a gate drive signal generator 636 that is configured to provide gate drive signals to the switches SI and S2 of the bias supply 208 (to control the time the switches SI and S2 are on and off) responsive to the pulse width control signal 637 from the timing parameter estimator 634 and/or responsive to a control signal 639 output by the one or more compensators 632 (in a one-supply configuration).
• a gate drive signal generator 636 that is configured to provide gate drive signals to the switches SI and S2 of the bias supply 208 (to control the time the switches SI and S2 are on and off) responsive to the pulse width control signal 637 from the timing parameter estimator 634 and/or responsive to a control signal 639 output by the one or more compensators 632 (in a one-supply configuration).
• the gate drive signal generator 636 may provide optical signals.
• FIG. 5 shown is a block diagram depicting a control system for the bias supply 208 of FIG. 2, where the bias supply 208 includes the first power supply (V SU ppiy) 216 and the second power supply (V ra ii supply) 218 in a two-supply configuration.
• the switch network 220 may comprise a variety of different topologies including one or two switches, as will be described below.
• the control system may comprise two control “knobs” to control the DC voltages of V SU ppiy and Vraii.
• This approach is in contrast to prior approaches that control compensation current I CO mp (to control a width of a distribution of ion energies) and control Vraii to achieve a desirable ion energy, eV.
• the voltages of the first power supply 216 (V supply) and the voltage of the second power supply (V ra ii) may be controlled based on a general relationship:
• K 2 2 — - 2Tsw , where Tsw is the switching period (from U-to).
• a first setpoint may be an ion energy setpoint, Ei O n_set, and a second setpoint may be for a spread (also referred to as a distribution) of ion energies, AEion set (both Eion set and AEion_set are shown in FIG. 5).
• the data processing module 630 may calculate Ei on and AEion based upon the digital representations of the output current waveform i ou t and the voltage waveform Vout received from the metrology section 620.
• the first comparator 638 may produce the first error signal, error 1, based upon the difference between the first setpoint, Ei on _set, and the calculated value of Ei on
• the second comparator 640 may produce a second error signal, error2, based upon the difference between the second setpoint, AEion_set, and the calculated value of AEion.
• the first setpoint (to set ion energy) may be a Vstep setpoint and the second setpoint (to set the spread of ion energies) may be a slope setpoint (to set the slope, of the fourth portion (between times t3 and t4) of the asymmetric periodic voltage waveform) or the second setpoint may be a slope-deviation-factor setpoint (to set the slope deviation factor, Ks).
• the data processing module 630 may calculate Vstep and the slope or the slope deviation factor, Ks based upon the digital representations of i ou t and V ou t received from the metrology section 620.
• the first comparator 638 may produce the first error signal, errorl, based upon the difference between the first setpoint (e.g., a Vstep setpoint) and the calculated value of Vstep, and the second comparator 640 may produce a second error signal, error2, based upon the difference between the second setpoint (either a slope setpoint or a slope-deviation-factor setpoint) and the calculated value of the slope or the calculate value of the slope deviation factor, Ks.
• the first setpoint e.g., a Vstep setpoint
• the second comparator 640 may produce a second error signal, error2 based upon the difference between the second setpoint (either a slope setpoint or a slope-deviation-factor setpoint) and the calculated value of the slope or the calculate value of the slope deviation factor, Ks.
• the control system may comprise two compensators: a first compensator 1132A and a second compensator 1132B.
• the first compensator 1132A may receive the first error signal, errorl, and produce a signal, V S up P iy_set, to control the first power supply 216.
• the second compensator 1132B may receive the second error signal, error2, and produce a signal, Vraii_set, to control the second power supply 218.
• the gate drive signal generator 636 may be set with fixed switching times for the first switch (and the second switch in a two-switch bias supply) of the bias supply 208.
• the timing parameter estimator 634 may provide a pulse width signal so that the gate drive signal generator 636 may open (turn off) the switches of the bias supply 208 (thus, controlling the on time of the switches of the bias supply 208) to provide zero current switching.
• Each of the compensators 1132A, 1132B may be realized by a proportional- integral-derivative (PID) controller, and in some variations, a bandwidth of the first compensator 1132A is set to be different from the bandwidth of the second compensator 1132B, which enables control loops associated with each of the compensators 1132A, 1132B to be decoupled. For example, a sampling rate of each control loop may be set to a different rate to result in the different bandwidths. [0057] Referring next to FIG.
• FIG. 6 shown is a block diagram depicting a control system for the bias supply 208 of FIG. 2, where the bias supply 208 includes only the first power supply 216 (Vsuppiy) in a one-supply configuration.
• the switch network 220 may comprise a variety of different topologies including one or two switches, as will be described below.
• the control system of FIG. 6 for a one-supply configuration is virtually the same as the control system of FIG. 5 for a two-supply configuration except that the second compensator 1132B provides a frequency setpoint signal f sw _set to control a frequency of the switching of the bias supply 208 (rather than providing a signal, V r aii_set, to control the second power supply 218, as in FIG.
• one MIMO compensator 632 can be used with multiple inputs (shown generally as errorl and error2 in FIG. 6) and multiple outputs where Ctrl_knobl and Ctrl_knob2 in FIG. 6 may be Vsuppiy _set and Vrail_set, respectively.
• FIGS. 7A, 7B and 8 shown are examples of switch networks having one-switch configurations that may be implemented in switch network 220 of bias supply 208 (FIG. 2).
• FIGS. 7 A and 7B depict one-switch configurations that may be implemented in one-supply configurations, that is, where the bias supply 208 includes only the first power supply 216 and is controlled by an associated one-supply control system such as that of FIG. 6.
• FIG. 8 depicts a one-switch configuration that may be implemented in a two-supply configuration, that is, where the bias supply 208 includes the first power supply 216 and the second power supply 218 and is controlled by an associated two- supply control system such as that of FIG. 5.
• the switches disclosed herein are realized by field-effect switches such as metal-oxide semiconductor field-effect transistors (MOSFETS), and in some implementations, the switches are realized by silicon carbide metal-oxide semiconductor field-effect transistors (SiC MOSFETs) or gallium nitride metal-oxide semiconductor field-effect transistors (GaN MOSFETs). As another example, the switches may be realized by an insulated gate bipolar transistor (IGBT).
• the gate drive signal generator 636 may comprise an electrical driver known in the art that is configured to apply electrical drive signals to the switches responsive to signals from the timing parameter estimator 634 and/or the one or more compensators 632. It is also contemplated that the drive signals may be sent via optical lines to convey optical switching signals. And the switches may switch in response to the optical signal and/or optical signals that are converted to an electrical drive signal.
• each of the switches depicted herein generally represents one or more switches that are capable of closing and opening to connect and disconnect, respectively, a current pathway.
• each of the switches may be realized by a plurality of switches arranged is series (for enhanced voltage capability), may be realized by a plurality of switches arranged is parallel (for enhanced current capability), or each of the switches may be comprised of a plurality of switches arranged in a series-parallel combination (for enhanced voltage and or current capability).
• each switch may be synchronously driven by a corresponding drive signal.
• any of the diodes depicted herein may be realized by a plurality of diodes.
• any diode may be realized by a plurality of series- connected diodes (to enhance voltage capability), may be realized by a plurality of diodes arranged in parallel (to enhance current capability), or may be comprised of a plurality of diodes arranged in a series-parallel combination (for enhanced voltage and or current capability).
• FIG. 7 A shown is a schematic drawing depicting a switch network 1820B that is an example of a switching section 220 having a single switch SI, and that may be deployed in conjunction with a one-supply configuration in which the bias supply 208 includes only the first power supply 216 and is controlled by an associated one-supply control system such as that of FIG. 6.
• a first inductor LI is coupled between a node 1870 and the output node 210.
• the switch S 1 is coupled between the node 1870 and the return node 212.
• a diode DI is coupled in parallel with the switch SI between the node 1870 and the return node 212.
• FIG. 7B shown is a schematic drawing depicting a switch network 1820C that is another example of a switching section 220 having a single switch SI, and that may be deployed in conjunction with a one-supply configuration in which the bias supply 208 includes only the first power supply 216 and is controlled by an associated one supply control system such as that of FIG. 6.
• the switch network 1820C comprises a first current pathway (for current iSl), between the return node 212 and node 1872.
• the first current pathway comprises a series combination of the switch SI a diode DI and an inductor LI.
• the switch network 1820C comprises second current pathway (for current iD2), (between the node 1872 and the return node 212), which comprises a second diode D2 and an inductive element L2. As shown, a cathode of diode D2 is coupled to the return node 212, and a third inductor L3 is positioned between the node 1872 and the output node 210.
• FIG. 8 shown is a schematic drawing depicting a switch network 1420B that is an example of a switching section 220 having a single switch SI, and that may be deployed in conjunction with a two-supply configuration in which the bias supply 208 includes the first power supply 216 and the second power supply 218 and is controlled by an associated two-supply control system such as that of FIG. 5.
• the switch network 1420B comprises a first current pathway (for current iSl), between the node 1050 and the output node 210.
• the first current pathway comprises a series combination of a switch SI, a diode DI and an inductor LI.
• the switch network 1420B also comprises second current pathway (for current iD2), between the output node 210 and the return node 212, which comprises a second diode D2 and an inductor L2.
• FIG. 9 shown are graphs and a timing diagram illustrating aspects of bias supplies that comprise switching networks having a single switch, such as the switching networks of FIGS. 7A, 7B and 8.
• the switch SI is closed (turned on) and then opened (turned off) for the time duration of the gate drive pulse width signal in order to produce the output current waveform i ou t, the asymmetric periodic output voltage waveform Vout, and the sheath voltage waveform V s .
• a full cycle of the asymmetric periodic current and voltage waveforms of FIG. 9 extends from time to to U.
• a second portion of the output voltage waveform Vout falls from the positive peak voltage level by an amount Vstep to a third (negative) voltage level at time t3.
• the switch SI is opened (turned off) at or before the time t3.
• a third (negative ramping) portion of the asymmetrical periodic voltage V ou t ramps down in a steadily and negatively until the switch S 1 is closed (turned on) again at time U.
• a first portion of the output current waveform i ou t rises at time to, when switch S 1 is closed (turned on), from a threshold current value to a positive peak current value.
• the switch S 1 is opened (turned off) at or after the time of the first crossing of the threshold current value.
• a third portion of the output current waveform i ou t then rises from the negative peak current value to reach the threshold current value again at time t3.
• a fourth portion of the output current waveform i ou t flattens out and eventually reaches -I o .
• the voltage waveform V ou t produces a sheath voltage waveform V s that is generally negative in order to attract ions to impact a surface of the workpiece to enable etching of the workpiece 103.
• the first portion of the asymmetric periodic voltage waveform V ou t causes the sheath voltage V s to approach a positive voltage to repel positive charges that accumulate on the surface of the workpiece while the surface of the workpiece is held at a negative voltage.
• V ou t falls by an amount V s te P and causes the sheath voltage V s to become a desired negative voltage (or range of voltages) to achieve an ion flux that achieves a desired ion energy.
• V s te P corresponds to a sheath voltage at t3 that produces ions at any energy level, -Ei on .
• the sheath voltage may become more negative so that at t4, ions at an energy level of -(Ei on +AEion) are produced.
• times t re set (between times to and t3) and t r am P (between times t3 and ).
• treset covers a time that includes both the first and second portions of the asymmetric periodic voltage waveform V ou t
• t r am P includes the third ramping portion of the voltage waveform V ou t.
• the compensation current I C om P may be provided throughout the application of the asymmetric periodic voltage function V ou t, and I ou t may or may not equal I C om P during the third portion of the asymmetric periodic voltage waveform V ou t (during t ra mp).
• the compensation current I C om P may compensate for ion current in the plasma chamber 101. Without the compensation current I C om P , the sheath voltage V s may gradually change to become more positive during the third portion of the asymmetric periodic voltage, which creates a broader distribution of ion energies, which may be undesirable.
• the compensation current I CO mp may intentionally be set to overcompensate or undercompensate for ion current in the plasma chamber 101 to create a broader distribution of ion energies.
• the compensation current I CO mp provides a sheath voltage V s that negatively ramps in correspondence with the third (negative ramping) portion of the voltage waveform V ou t.
• the fundamental period (from to to U) of the asymmetric periodic voltage waveform V ou t may be adjusted to adjust a spread of ion energies.
• a full current cycle occurs between times to and t3 during the first and second portions of the asymmetric periodic voltage waveform V ou t.
• the time between full current cycles is the time, tramp, between t3 and U.
• An aspect of the present disclosure addresses the problem of how to adjust the output current, I ou t, to compensate for the ion current Ii on .
• Another aspect of the present disclosure addresses the problem of how to adjust a level of ion energies and distribution of the ion energies in the plasma chamber.
• the timing parameter estimator 634 may detect when the output current i ou t reverses (crosses the threshold current value) and may generate a pulse width signal to the gate drive signal generator 636 to cause the switch S 1 to close (turn on) at time to and then open (turn off) at or after the time that the current crosses the threshold current value.
• switch SI stays closed (turned on) for the duration of the gate drive pulse width and opens (turns off) when the pulse width signal ends. Once the current reverses direction, current is no longer flowing through switch SI, and switch SI may thereafter be opened (turned off) to reduce losses.
• FIGS. 10-16 address computing the gate pulse width and reset time treset.
• FIG. 10 shown are graphs depicting complete digital representations of one cycle of the asymmetrical periodic output voltage and output current waveforms V ou t and iout associated with implementations of bias supplies 208 that have one switch.
• FIG. 10 illustrates various timing parameters used by timing parameter estimator 634 to calculate the gate drive pulse width provided to gate drive signal generator 636, and to calculate the reset time t reS et provided to data processing module 630.
• the times to-U correspond to the times to-U of the timing diagram of FIG. 9.
• Timing parameter estimator 634 receives the complete digital representations of the asymmetrical periodic voltage waveform Vout, the output current waveform i ou t and/or the compensation current I CO mp from metrology section 620. From these waveforms, timing parameter estimator 634 can accurately compute the gate drive pulse width that is provided to gate drive signal generator 636 so that switch SI is opened (turned off) at an appropriate time with minimal losses. Timing parameters estimator 634 also computes the reset time t re set that is provided to data processing module 630. The reset time t re set is used to find the starting point of the ramp (third) portion of the voltage waveform V ou t, and is the time by which the switch S 1 must be opened (turned off)
• the output voltage waveform V ou t rises during a first portion from a beginning negative voltage at time to, when switch S 1 is closed (turned on), to a positive peak voltage value at time ti, then falls during a second portion to an intermediate (third) negative voltage at time t3, and then ramps down steadily and gradually during a third portion to an ending negative voltage at time U. Since time U is the end of the cycle and the beginning of a new cycle, the ending negative voltage should be approximately equal to the beginning negative voltage. While falling between times ti and t2, the voltage crosses the threshold voltage value Vthreshoid at voltage threshold crossing time t v -cross. The threshold voltage value Vthreshoid is typically at or near zero volts.
• the output current waveform i ou t rises beginning at time to, when the switch S 1 is closed (turned on) during a first portion from a threshold current value ithreshoid to a positive peak current current value.
• a second portion of the output current waveform i ou t falls from the positive peak current value to a negative peak current value.
• the output current waveform i ou t crosses a threshold current value ithreshoid for a first time at first threshold current crossing time h-crossi. It is at this time that a window for opening (turning off) the switch S 1 begins.
• a third portion of the output current waveform i ou t rises from the negative peak current value to cross the threshold current value Ithreshoid for a second time at second threshold current crossing time tj- C ross2. It is at this time that the window for opening (turning off) the switch SI ends.
• a fourth portion of the output current waveform i ou t then gradually flattens out to a slightly negative compensation current value -I CO mp.
• Method 1100 may be performed in conjunction with either the one-switch, one-supply configuration of FIG. 7B or the one-switch, two-supply configuration of FIG. 8.
• Method 1100 of FIG. 11 sets the maximum gate drive pulse width using the output current waveform i ou t.
• An alternate method 1200 that sets the maximum gate drive pulse width using the voltage waveform V ou t is discussed with reference to FIG. 12.
• timing parameter estimator 634 loads a default threshold current value threshold, a default gate drive pulse width, and a default reset time treset.
• timing parameter estimator 634 captures the output current waveform i ou t of one fundamental cycle. In one example, for instance, estimator 634 captures one cycle of the complete digital representation of asymmetric periodic current waveform i ou t that is provided by metrology section 620, as is depicted in FIG. 10.
• timing parameter estimator 634 searches the output current waveform i ou t for the first threshold current crossing time ti-crossi and the second threshold current crossing time tj. C ross2.
• step 1108 if the threshold current crossing times tj. C rossi and tj. C ross2 are not found in step 1106, the method proceeds to step 1110 to set the gate drive pulse width as the default pulse width value or the previously computed pulse width, and to set the reset time t re set as the default reset time or the previously computed reset time.
• step 1112 the threshold current value threshold is computed as described with reference to FIG. 14, and the threshold current value threshold is updated with this computed value in step 1 1 14.
• the method 1100 then loops back to step 1104 to capture the next cycle of the asymmetric periodic current waveform i ou t that is provided by metrology section 620, and the method repeats from there.
• step 1108 if the threshold current crossing times ti- cr ossi and tj- C ross2 are found in step 1106, the method proceeds to step 1116.
• the reset time treset is set to be the total time that it takes the output current waveform i ou t to rise to its positive peak current value, fall to its negative peak current value (crossing the threshold current value threshold for a first time), and then rise again to reach the threshold current value threshold for a second time.
• the pulse width may be set within a range between maximum and minimum pulse widths.
• the minimum pulse width tpuise min is set to be the total time from time to that it takes the output current waveform i ou t to rise to its positive peak current value and then fall to reach the threshold current value threshold for the first time.
• the maximum pulse width t pu ise_max is set to be midway between the first time that the output current waveform i ou t crosses the threshold current value threshold and the second time that the output current waveform i ou t crosses the threshold current value threshold, i.e., t pu ise_ max — 0.5(ti-crossl"l"ti-cross2 .
• Step 1120 determines whether the current pulse width is within the range between the minimum pulse width t pu ise-min and the maximum pulse width t pu ise_max within a predefined margin, which is a design choice value. If the current pulse width is within this range, the current pulse width is kept as the pulse width (step 1122), and the method 1100 then loops back to step 1104 to capture the next cycle of the asymmetric periodic current waveform iout that is provided by metrology section 620, and the method repeats from there.
• step 1120 if the current pulse width is not within the range between the minimum pulse width tpuise-min and the maximum pulse width t pu ise_max with the predefined margin, then the pulse width is recalculated in step 1124.
• the pulse width is set to be somewhere between the minimum pulse width t pu ise_min and the maximum pulse width t pu ise_max.
• the method 1100 loops back to step 1104 to capture the next cycle of the asymmetric periodic current waveform i ou t that is provided by metrology section 620, and the method repeats from there.
• FIG. 12 shown is a flowchart depicting an alternate method 1200 that may be performed by timing parameters estimator 634, associated with implementations of bias supplies 208 that have one switch, for setting the gate drive pulse width and reset time beset.
• Method 1200 uses the voltage waveform Vout to set the maximum gate drive pulse width, in contrast to method 1100 of FIG. 11 which uses the output current waveform i ou tto set the maximum gate drive pulse width.
• method 1200 may be performed in conjunction with either the one-switch, one-supply configuration of FIG. 7B or the one-switch, two-supply configuration of FIG. 8.
• timing parameter estimator 634 loads a default gate drive pulse width and a default reset time t re set.
• timing parameter estimator 634 captures the output current waveform i ou t and the voltage waveform V ou t of one fundamental cycle. In one example, for instance, estimator 634 captures one cycle of the complete digital representations of asymmetric periodic current waveform i ou t and asymmetric periodic voltage waveform Vout that are provided by metrology section 620, as are depicted in FIG. 10.
• timing parameter estimator 634 searches the output current waveform i ou t for the first threshold current crossing time ti. C rossi and the second threshold current crossing time ti-cross2 «
• step 1208 if the threshold current crossing times ti- C rossi and ti- C ross2 are not found in step 1206, the method proceeds to step 1210 to set the gate drive pulse width as the default pulse width or the previously computed pulse width, and to set the reset time t re set as the default reset time or the previously computed reset time.
• step 1212 the threshold current value Ithreshoid is computed as described with reference to FIG. 14, and the threshold current value Ithreshoid is updated with this computed value in step 1214.
• the method 1200 then loops back to step 1204 to capture the next cycle of the asymmetric periodic current and voltage waveforms i ou t and V ou t that are provided by metrology section 620, and the method repeats from there.
• step 1208 if the threshold current crossing times tj. C rossi and tj. C ross2 are found in step 1206, the method proceeds to step 1216.
• the reset time t re set is set to be the total time that it takes the output current waveform i ou t to rise to its positive peak current value, fall to its negative peak current value (crossing the threshold current Ithreshoid for a first time), and then rise again to reach the threshold current value Ithreshoid for a second time.
• the minimum pulse width is set to be the first threshold current crossing time (t pu ise_ min — ti-crossi).
• the minimum pulse width tpuise min is set to be the total time that it takes the output current waveform i ou t to rise to its positive peak current value and then fall to reach the threshold current value Ithreshoid for the first time.
• step 1218 the threshold voltage value Vthreshoid (see FIG. 10) is computed.
• the threshold voltage value Vthreshoid is computed as shown in FIG. 15.
• the threshold voltage value Vthreshoid is computed as shown in FIG. 16.
• timing parameter estimator 634 searches the voltage waveform V ou t for the voltage threshold crossing time tv-cross, and in step 1222, the maximum pulse width is set to be voltage threshold crossing time tv-cross (tpuise max— tv-cross)* In other words, the maximum pulse width is set to be the total time that it takes the voltage waveform Vout to rise to its positive peak voltage value and then fall to reach the threshold voltage value Vthreshoid*
• Step 1224 determines whether the current pulse width is within the range between the minimum pulse width t pu ise-min and the maximum pulse width t pu ise_max with a predefined margin, which is a design choice value. If the current pulse width is within this range, the current pulse width is kept as the pulse width (step 1226), the method 1200 loops back to step 1204 to capture the next cycle of the asymmetric periodic current and voltage waveforms i ou t and V ou t that are provided by metrology section 620, and the method repeats from there.
• step 1224 if the current pulse width is not within the range between the minimum pulse width t P uise-min and the maximum pulse width t pu ise_max with the predefined margin, then the pulse width is recalculated in step 1228.
• the pulse width is set to be somewhere between the minimum pulse width t pu ise_min and the maximum pulse width t pu ise_max*
• the method 1200 loops back to step 1204 to capture the next cycle of the asymmetric periodic current and voltage waveforms i ou t and V ou t that are provided by metrology section 620, and the method repeats from there.
• FIG. 13 is a flowchart depicting a method 1300 performed by timing parameter estimator 634, associated with implementations of bias supplies 208 that have one switch and one supply, for setting the gate drive pulse width and reset time treset.
• Method 1300 may be performed, for example, in conjunction with the one-switch, one-supply configuration of FIG. 7A.
• timing parameter estimator 634 loads a default threshold current value Threshold, a default gate drive pulse width, and a default reset time treset*
• timing parameter estimator 634 captures the output current waveform iout of one fundamental cycle. In one example, for instance, estimator 634 captures one cycle of the complete digital representation of asymmetric periodic current waveform i ou t that is provided by metrology section 620, as is depicted in FIG. 10.
• timing parameter estimator 634 searches the output current waveform i ou t for the first threshold current crossing time ti- cr ossi and the second threshold current crossing time ti- cr oss2.
• step 1308 if the threshold current crossing times ti- cr ossi and ti- cr oss2 are not found in step 1306, the method proceeds to step 1310 to set the gate drive pulse width as the default pulse width or the previously computed pulse width, and to set the reset time t re set as the default reset time or the previously computed reset time. Then, in step 1312, the threshold current value threshold is computed as described with reference to FIG. 14, and the threshold current Ithreshoid is updated with this computation in step 1314. The method 1300 then loops back to step 1304 to capture the next cycle of the asymmetric periodic current waveform i ou t that is provided by metrology section 620, and the method repeats from there.
• step 1308 if the threshold current crossing times ti-crossi and ti- cr oss2 are found in step 1306, the method proceeds to step 1316.
• the reset time t re set is set to be the total time that it takes the output current waveform i ou t to rise to its positive peak current value, fall to its negative peak current value (crossing the threshold current Ithreshoid for a first time), and then rise again to reach the threshold current Ithreshoid for a second time.
• the minimum pulse width is set to be the first threshold current crossing time (tpuise min— ti-crossi).
• the minimum pulse width t pu ise_min is set to be the total time that it takes the output current waveform i ou t to rise to its positive peak current value and then fall to reach the threshold current value Ithreshoid for the first time.
• the maximum pulse width is set to be the second threshold current crossing time (tpuise max— ti-cross2) . In other words, the maximum pulse width t pu ise_max is set to be the same as the reset time treset.
• Step 1320 determines whether the current pulse width is within the range between the minimum pulse width tpuise min and the maximum pulse width t pu ise_max with a predefined margin. If the current pulse width is within this range, the current pulse width is kept as the pulse width (step 1322), and the method 1300 then loops back to step 1304 to capture the next cycle of the asymmetric periodic current waveform i ou t that is provided by metrology section 620, and the method repeats from there.
• step 1320 if the current pulse width is not within the range between the minimum pulse width tpuise min and the maximum pulse width t pu ise_max with a predefined margin, which is a design choice value, then the pulse width is recalculated in step 1324.
• the pulse width is set to be somewhere between the minimum pulse width and the maximum pulse width.
• the method 1300 loops back to step 1304 to capture the next cycle of the asymmetric periodic current waveform i ou t that is provided by metrology section 620, and the method repeats from there.
• FIGS. 11-13 depict three different methods for computing the gate drive pulse width and the reset time t re set in one-switch configurations, and these methods differ primarily in how the maximum gate drive pulse width is computed.
• the maximum gate drive pulse width is computed by using the output Current waveform iout, where t p ulse_max— ti-cross2— treset.
• FIG. 14 shown is a flowchart depicting a method 1400 for computing the threshold current value Ithreshoid in step 1112 of FIG. 11, step 1212 of FIG. 12, and step 1312 of FIG. 13.
• FIG. 14 is used to compute the threshold current Ithreshoid value in any of the methods used in conjunction with the one-switch configurations of FIGS. 7A, 7B and 8.
• Step 1402 of method 1400 determines whether the compensation current value I C om P is directly available.
• I C om P -k* (average of i ou t from t re set to end of period), where k is a designer choice value between 0 and 1.
• Step 1502 determines whether the output voltage waveform V ou t data is DC-coupled or AC-coupled. If the output voltage waveform V ou t data is AC-coupled, the threshold voltage value Vthreshoid is set in step 1504 to be equal to Vsuppiy (the first power supply voltage 216). If the output voltage waveform Vout data is DC-coupled, the threshold voltage value Vthreshoid is set in step 1506 to be zero.
• Step 1602 determines whether the output voltage waveform V ou t data is DC-coupled or AC-coupled. If the output voltage waveform V ou t data is AC-coupled, the threshold voltage value Vthreshoid is set in step 1604 to be equal to be the sum of Vsuppiy (the first power supply voltage 216) and V ra ii (the second power supply voltage 218). If the output voltage waveform V ou t data is DC-coupled, the threshold voltage value Vthreshoid is set in step 1606 to be Vraii (the second power supply voltage 218).
• FIGS. 17 and 18 shown are examples of switch networks having two- switch configurations that may be implemented in switch network 220 of bias supply 208 (FIG. 2).
• FIG. 17 depicts a two-switch configuration that may be implemented in a one- supply configuration, that is, where the bias supply 208 includes only the first power supply 216 and is controlled by an associated one-supply control system such as that of FIG. 6.
• FIG. 18 depicts a two-switch configuration that may be implemented in a two- supply configuration, that is, where the bias supply 208 includes the first power supply 216 and the second power supply 218 and is controlled by an associated two-supply control system such as that of FIG. 5.
• FIG. 17 shown is a schematic drawing depicting a switch network 1820A that is an example of a switch network 220 having two switches SI and S2, and that may be deployed in conjunction with a one-supply configuration in which the bias supply 208 includes only the first power supply 216 and is controlled by an associated one-supply control system such as that of FIG. 6.
• a series combination of the first switch SI and the first diode DI is arranged between the return node 212 of the bias supply 208 and node 1862.
• a series combination of the second switch S2 and the second diode D2 is arranged between the node 1862 and the return node 212 of the bias supply 208.
• FIG. 17 shown is a schematic drawing depicting a switch network 1820A that is an example of a switch network 220 having two switches SI and S2, and that may be deployed in conjunction with a one-supply configuration in which the bias supply 208 includes only the first power supply 216 and is controlled by an associated one-supply control system such as that of FIG.
• the first diode DI is arranged between the first switch SI and the node 1862 with its anode coupled to the first switch SI and its cathode coupled to the node 1862.
• the second diode D2 is arranged between the second switch S2 and the node 1862 with its cathode coupled to the second switch S2 and its anode coupled to the node 1862.
• the cathode of the first diode DI is coupled to the anode of the second diode D2 at the node 1862.
• FIG. 18 shown is a schematic drawing depicting a switch network 1420A that is an example of a switch network 220 having two switches SI and S2, and that may be deployed in conjunction with a two-supply configuration in which the bias supply 208 includes the first power supply 216 and the second power supply 218 and is controlled by an associated two-supply control system such as that of FIG. 5.
• Switch network 1420A couples to the bias supply 208 at node 1050, the return node 212, and the output node 210.
• node 1460 Also shown for reference in the switch network 1420A is node 1460.
• the switch network 1420A comprises a first switch SI arranged in series with a first diode DI between node 1050 and node 1460.
• a cathode of the diode DI is coupled to the node 1460 and an anode of the diode DI is coupled to the switch SI.
• the switch network 1420A also comprises a second switch S2 arranged in series with a second diode D2 between the return node 212 and node 1460.
• An anode of the diode D2 is coupled to the node 1460 and a cathode of the diode D2 is coupled to the switch S2.
• an inductor LI is positioned between the node 1460 and the output node 210.
• FIG. 19 shown are graphs and a timing diagram illustrating aspects of bias supplies that comprise switching networks having two switches SI and S2, such as the switching networks of FIGS. 17 and 18.
• the switches SI and S2 are operated to create the asymmetric periodic voltage and current waveforms V ou t and i ou t depicted in FIG. 19.
• first diode DI conducts when the first switch SI is closed (turned on)
• a second diode D2 conducts when the second switch D2 is closed (turned on).
• the output current waveform i ou t rises at time to (when switch SI is closed) from a first threshold current value (which may or may not be equal to I o ) to a positive peak current value.
• the output current waveform i ou t then falls from the positive peak current value to reach the first threshold current level and flattens out.
• switch S2 is closed (turned on) and the output current waveform i ou t falls to a negative peak current value.
• the output current waveform iout then rises from the negative peak current value to reach a second threshold current value (which may or may not be equal to I o ).
• the output current waveform i ou t then gradually flattens out to a slightly negative compensation current -I o until at time U when the cycle ends and SI is closed again (turned on).
• the bias supplies 208 disclosed herein operate to apply an asymmetric periodic voltage waveform V ou t from time to to U between the output node 210 and the return node 212.
• the asymmetric periodic voltage waveform V ou t includes a first portion from time to to ti that begins at time to with a first negative voltage value and rises to a positive peak voltage value at time ti.
• the voltage waveform V ou t has a transition ramp portion during the deadtime from ti to t2 and then at time t2, falls by an amount V s te P to a third (negative) voltage value at time t3.
• a third portion of the voltage waveform V ou t (from time t3 to U) includes a voltage ramp between the third voltage level and a fourth, negative voltage level (at time U)
• the asymmetric periodic voltage waveform comprises a voltage step Vstep between times t2 and t3, and V s te P corresponds to a sheath voltage at t3 that produces ions at any energy level, -Ei on .
• the sheath voltage may become more negative so that at time , ions at an energy level of -(Ei O n+AEion) are produced.
• treset covers a time that includes both the first and second portions of the asymmetric periodic voltage waveform Vout, and tramp includes the third portion of the Vout waveform.
• the compensation current I C om P referenced in FIG. 2.
• the compensation current I C om P may be provided throughout the application of the asymmetric periodic voltage function, and i ou t may or may not equal I C om P during the third portion of the asymmetric periodic voltage waveform (during tramp).
• the fundamental period (from to to ) of the asymmetric periodic voltage waveform may be adjusted to adjust a spread of ion energies. As shown in FIG. 19, a full current cycle occurs between times to and t3 during the first and second portions of the asymmetric periodic voltage waveform. The time between full current cycles is the time tramp between t3 and t4.
• switches SI and S2 may be controlled with an adjustable deadtime, which is the time from ti to t2 (after the switch SI is opened from a closed position and before the switch S2 is closed).
• the first portion of the voltage waveform V ou t may transition (during the deadtime between time ti to t2) in a ramp profile to the second portion of the asymmetric periodic voltage waveform.
• Control of the deadtime enables control over the reset time t re set and adjusting a ratio of the reset time t re set to the ramp time tramp adjusts average power.
• Control over t re set enables the fundamental switching frequency to be controlled (e.g., to remain below a level that affects plasma density in the plasma processing chamber 101).
• ion current compensation Another aspect of control that may be achieved with the bias supply 208 disclosed herein is ion current compensation. More specifically, the length of the deadtime, the length of tramp, and/or the period of the periodic voltage function (between to and t4) may be controlled to control a level of ion current compensation. In FIG.
• the frequency of the periodic voltage waveform may be fixed if desired, but it is also possible to vary the deadtime, tramp, and the frequency of the periodic voltage waveform. It is also contemplated that the deadtime may be shortened while shortening or lengthening tramp.
• two gate drive pulse width signals are required: a first pulse width signal to close (turn on) and open (turn off) the first switch SI, and a second pulse width signal to open (turn on) and close (turn off) the second switch S2.
• the timing parameter estimator 634 may detect when the output current i ou t reverses (crosses the threshold current value) for a first time and for a second time, and may generate respective pulse width signals to the gate drive signal generator 636 to cause switches SI and S2 to open (turn off) at or after these times. Once the current reverses direction, current is no longer flowing through the active switch, and it may be safely opened (turned off).
• the second switch S2 must be opened (turned off) before the reset time beset so that the voltage output waveform V ou t takes on the downward ramp profile during time tramp. Therefore, as in the single-switch configuration, there is a range of pulse widths that the pulse widths may fall within.
• the time t2 at which the second switch S2 is closed (turned on) must be computed. There is no need for a computation as to when the first switch SI is closed (turned on), since it automatically closes (turns on) at time to (as in the one-switch configuration).
• FIGS. 20- 22, described below, address computing the gate pulse widths for the first and second switches, the reset time t re set, and the close (turn on) time for the second switch.
• FIG. 20 is a timing diagram associated with implementations of bias supplies 208 that have two switches and illustrates various timing parameters used by timing parameter estimator 634 in the calculation of the gate drive pulse widths t pu isei and t pu ise2, the time t2 for turning on the second switch, and the reset time t reS et.
• FIG. 20 depicts one cycle of the complete digital representation of the asymmetrical periodic output voltage waveform Vout, and one cycle of the complete digital representation of asymmetric periodic current waveform i ou t.
• Timing parameter estimator 634 may receive these representations of the voltage and current waveforms, for example, from metrology section 620. In the following description of FIG. 20, times to-U are as indicated in the timing diagram of FIG. 19.
• the output current waveform i ou t rises at time to (when switch SI is closed) from a first threshold current value Ithreshoiai to a positive peak current value.
• the output current waveform i ou t then falls from the positive peak current value to cross the first threshold current Ithreshoiai at first threshold current crossing time h-crossi.
• switch S2 is closed (turned on) and the output current waveform i ou t falls to a negative peak current value.
• the output current waveform iout then rises from the negative peak current value to cross the second threshold current Ithreshoid2 at second threshold current crossing time ti_ C ross2.
• the output current waveform iout then gradually flattens out to a slightly negative compensation current -Icomp.
• the asymmetric periodic voltage waveform Vout of FIG. 20 includes a first portion from time to to ti that begins at time to with a first negative voltage value and rises to a positive peak voltage value at time ti.
• the voltage waveform Vout has a transition ramp portion during the deadtime from ti to t2 and then at time t2, falls by an amount Vstep to a third (negative) voltage value at time t3.
• a third portion of the voltage waveform V ou t (from time t3 to U) ramps steadily and negatively between the third voltage level and a fourth, negative voltage level (at time U).
• FIG. 21 is a flowchart depicting a method 2100 performed by timing parameter estimator 634, in conjunction with implementations of bias supplies 208 that have two switches, for computing the gate drive pulse widths t pu isei and t pu ise2, the time t2 for closing (turning on) the second switch S2, and the reset time t re set.
• Method 2100 may be performed in conjunction with a two-switch, single-supply configuration, such as the configuration of FIG. 17, or in conjunction with a two-switch, two-supply configuration, such as that shown in FIG. 18.
• timing parameter estimator 634 loads default first and second threshold current values Ithreshoidi and Ithreshoid2, default gate drive pulse widths tpuisei and t P uise2, and a default reset time t re set.
• timing parameter estimator 634 captures the output current waveform i ou t of one fundamental cycle. In one example, for instance, estimator 634 captures one cycle of the complete digital representation of asymmetric periodic current waveform i ou t that is provided by metrology section 620, as is depicted in FIG. 20.
• first and second threshold current values Ithreshoidi and Ithreshoid2 are computed as shown in FIG. 22.
• step 2106 Following computation of the threshold current values in step 2106, method 2100 proceeds with steps 2108-2126 to compute the first pulse width tpuisei and the time t2 for the start of the second gate drive pulse, and with steps 2128-2140 to comput the second pulse width t pu ise2. Steps 2108-2126 for computing the first pulse width and the time for turning on the second switch S2 are described first. [00128] In step 2108, timing parameter estimator 634 searches the output current i ou t waveform from time to to time t2 for the time ti- cr ossi that the output current i ou t waveform crosses the first threshold current value Ithreshoidi.
• step 2110 if the first threshold current crossing time h-crossi is not found, the method proceeds to step 2112 to set the first gate drive pulse width tpuisei as the default pulse width or the previously computed pulse width, and to set the time t2 for start of the second pulse (closing of switch 2) as the default or previously computed time t2.
• the method 2100 then loops back to step 2104 to capture the next cycle of the asymmetric periodic current waveform i ou t that is provided by metrology section 620, and the method repeats from there.
• step 2110 if the first threshold current crossing time ti-crossi is found, the method proceeds to step 2114.
• the minimum width of the first pulse (time during which S 1 is closed or turned on) is set to be the total time from to that it takes the output current waveform i ou t to rise to its positive peak current and then fall to the point at which it crosses the first threshold current value threshold for the first time.
• step 2116 if the current first pulse width t pu isei is greater than the minimum first pulse width tpuiseLmin plus a margin (a design choice value), then the first pulse width t pu isei and time t2 are kept at their current values in step 2118.
• the method 2100 then loops back to step 2104 to capture the next cycle of the asymmetric periodic current waveform i ou t that is provided by metrology section 620, and the method repeats from there.
• step 2122 if the time t2 (time for the start of the second pulse to close (turn on) S2) is greater than the first pulse width t pu isei plus the margin, then t2 is kept the same in step 2124.
• the method 2100 then loops back to step 2104 to capture the next cycle of the asymmetric periodic current waveform i ou t that is provided by metrology section 620, and the method repeats from there.
• the method 2100 then loops back to step 2104 to capture the next cycle of the asymmetric periodic current waveform i ou t that is provided by metrology section 620, and the method repeats from there.
• step 2128 following computation of the first and second threshold current values Lhreshoidi and Ithreshoid2 in step 2106, timing parameter estimator 634 searches the output current i ou t waveform, starting from time t2, for the time ti- C ross2 that the output current i ou t waveform crosses the second threshold current value Lhreshom. In step 2130, if the second threshold current crossing time ti.
• step 2132 the method proceeds to step 2132 to set the second gate drive pulse width t pu ise2 as the default second pulse width or the previously computed second pulse width, and to set the reset time t re set as the default reset time or previously computed reset time.
• the method 2100 then loops back to step 2104 to capture the next cycle of the asymmetric periodic current waveform i ou t that is provided by metrology section 620, and the method repeats from there.
• the minimum width of the second pulse (time during which S2 is closed or turned on) is set to be the total time from t2 that it takes the output current waveform i ou t to fall to its negative peak current value and then rise to the point at which it crosses the second threshold current value Ithreshom.
• step 2136 if the current second pulse width t pu ise2 is greater than the minimum second pulse width t pu ise2_min with the margin, then the second pulse width t pu ise2 is kept at its current value in step 2138.
• the method 2100 then loops back to step 2104 to capture the next cycle of the asymmetric periodic current waveform i ou t that is provided by metrology section 620, and the method repeats from there.
• the method 2100 then loops back to step 2104 to capture the next cycle of the asymmetric periodic current waveform i ou t that is provided by metrology section 620, and the method repeats from there.
• FIG. 22 is a flowchart depicting a method 2200 for computing the first and second threshold current values Ithreshoidi and Threshold! in step 2106 of FIG. 21, that is, for computing the first and second threshold current values in conjunction with the two- switch configurations of FIGS. 17 and 18.
• Step 2202 determines whether the compensation current I CO mp is directly available, such as by being directly sensed.
• the compensation current Lomp is computed in step 2204, it is used in step 2206 as described above to compute the threshold current Threshold.
• FIG. 23 shown is a block diagram depicting physical components that may be utilized to realize control aspects disclosed herein.
• a display 2312 and nonvolatile memory 2320 are coupled to a bus 2322 that is also coupled to random access memory (“RAM”) 2324, a processing portion (which includes N processing components) 2326, a field programmable gate array (FPGA) 2327, and a transceiver component 2328 that includes N transceivers.
• RAM random access memory
• FPGA field programmable gate array
• transceiver component 2328 that includes N transceivers.
• This display 2312 generally operates to provide a user interface for a user, and in several implementations, the display is realized by a touchscreen display.
• the nonvolatile memory 2320 is non-transitory memory that functions to store (e.g., persistently store) data and processor-executable code (including executable code that is associated with effectuating the methods described herein).
• the nonvolatile memory 2320 includes bootloader code, operating system code, file system code, and non-transitory processor-executable code to facilitate the execution of a method of controlling a switch network of a bias supply.
• the timing parameter estimator 634 may be realized (at least in part) by a processor executing instructions that may be stored as processor-executable code in the nonvolatile memory 2330.
• the nonvolatile memory 2320 is realized by flash memory (e.g., NAND or ONENAND memory), but it is contemplated that other memory types may be utilized as well. Although it may be possible to execute the code from the nonvolatile memory 2320, the executable code in the nonvolatile memory is typically loaded into RAM 2324 and executed by one or more of the N processing components in the processing portion 2326.
• flash memory e.g., NAND or ONENAND memory
• the N processing components in connection with RAM 2324 generally operate to execute the instructions stored in nonvolatile memory 2320 to enable execution of the algorithms and functions disclosed herein. It should be recognized that several algorithms are disclosed herein, but some of these algorithms are not represented in flowcharts. Processor-executable code to effectuate methods described herein may be persistently stored in nonvolatile memory 2320 and executed by the N processing components in connection with RAM 2324.
• the processing portion 2326 may include a video processor, digital signal processor (DSP), micro-controller, graphics processing unit (GPU), or other hardware processing components or combinations of hardware and software processing components (e.g., an FPGA or an FPGA including digital logic processing portions).
• non-transitory FPGA-configuration- instructions may be persistently stored in nonvolatile memory 2320 and accessed (e.g., during boot up) to configure a field programmable gate array (FPGA) to implement the algorithms disclosed herein.
• the input component 2330 may receive signals (e.g., signals indicative of current and voltage obtained at the output of the disclosed bias supplies).
• the input component 2330 may receive phase information and/or a synchronization signal between bias supplies 108 and source generator 112 that are indicative of one or more aspects of an environment within a plasma processing chamber 101 and/or synchronized control between a source generator and the single switch bias supply.
• the signals received at the input component may include, for example, synchronization signals, power control signals to the various generators and power supply units, or control signals from a user interface.
• synchronization signals for example, synchronization signals, power control signals to the various generators and power supply units, or control signals from a user interface.
• sensors such as, without limitation, directional couplers and voltage-current (VI) sensors, may be used to sample power parameters, such as voltage and current, and that the signals indicative of the power parameters may be generated in the analog domain and converted to the digital domain.
• the output component may operates to provide one or more analog or digital signals to effectuate (at least in part) the opening and closing of the switches SI and S2.
• the output component may also control of the voltage sources described herein.
• the depicted transceiver component 2328 includes N transceiver chains, which may be used for communicating with external devices via wireless or wireline networks.
• Each of the N transceiver chains may represent a transceiver associated with a particular communication scheme (e.g., WiFi, Ethernet, Profibus, etc.).
• aspects of the present disclosure may be embodied as a system, method or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

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