WO2023115791A1 - 晶体管单元及其阵列、集成电路 - Google Patents

晶体管单元及其阵列、集成电路 Download PDF

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Publication number
WO2023115791A1
WO2023115791A1 PCT/CN2022/092382 CN2022092382W WO2023115791A1 WO 2023115791 A1 WO2023115791 A1 WO 2023115791A1 CN 2022092382 W CN2022092382 W CN 2022092382W WO 2023115791 A1 WO2023115791 A1 WO 2023115791A1
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Prior art keywords
source
drain
substrate
conductive plugs
metal layer
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PCT/CN2022/092382
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English (en)
French (fr)
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王宇哲
李新
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长鑫存储技术有限公司
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Priority to US17/954,573 priority Critical patent/US20230013672A1/en
Publication of WO2023115791A1 publication Critical patent/WO2023115791A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to the technical field of semiconductors, in particular to a transistor unit, an array thereof, and an integrated circuit.
  • an ESD protection element is generally provided between an input/output interface (I/O) of an integrated circuit and an internal core circuit.
  • I/O input/output interface
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the transistor element used for ESD protection has the problems of limited discharge capability and low integration level.
  • Embodiments of the present disclosure provide a transistor unit, an array thereof, and an integrated circuit.
  • An embodiment of the present disclosure provides a transistor unit, including:
  • N gates are all located on the substrate; the projection of the N gates on the substrate surface forms a closed shape; N is a positive integer greater than 2;
  • the first source region is located in the substrate and the projection on the substrate surface is located in the closed shape; the first source region is shared by the N gates;
  • N drain regions are located in the substrate; each of the N drain regions and the first source region are located on both sides of a corresponding gate in the N gates;
  • first source terminal conductive plugs located on the first source region and in electrical contact with the first source region
  • Each of the drain regions is provided with a plurality of conductive plugs at the drain end, and the conductive plugs at the drain end are in electrical contact with the drain region;
  • the first source metal layer is located on the first source conductive plug and is in electrical contact with all the first source conductive plugs;
  • the drain metal layer is located on the drain conductive plugs and is in electrical contact with all the drain conductive plugs.
  • the transistor unit also includes:
  • the N second source regions are located in the substrate; the projection of each of the N second source regions on the substrate surface is located outside the closed shape and is distinguished from the drain on both sides of the corresponding grid;
  • a plurality of the second source conductive plugs are disposed on each of the second source regions, and the second source conductive plugs are in electrical contact with the second source regions;
  • Each of the N second source terminal metal layers is located on a corresponding second source region in the N second source regions, and is in electrical contact with all the second source terminal conductive plugs on the corresponding second source region.
  • said N is 3, 4, 5 or 6.
  • the closed shape formed by the projection of the N gates on the surface of the substrate is a square.
  • the sum of the areas of the N second source regions is equal to the area of the first source regions.
  • the conductive plugs at the first source end are aligned and arranged at intervals along a direction parallel to any one of the N gates, forming M conductive plugs at the first source end parallel to any gate.
  • a plurality of second source terminal conductive plugs are aligned and arranged at intervals along a direction parallel to the corresponding gate, forming K parallel to the corresponding gate.
  • drain-end conductive plugs are aligned and arranged at intervals along a direction parallel to the corresponding gate, forming P rows of drain-end conductive plugs parallel to the corresponding gate;
  • M, K, and P are all positive integers.
  • the total number of the first source conductive plugs on the first source region is the same as the total number of the second source conductive plugs on the N second source regions.
  • the first source conductive plug, the second source conductive plug, and the drain conductive plug have the same shape and size.
  • the orthographic projections of the first source conductive plug, the second source conductive plug, and the drain conductive plug on the substrate surface are all elongated.
  • the transistor further includes a plurality of source contacts, which are respectively located on the first source metal layer and the second source metal layer and are respectively in electrical contact with the first source metal layer or the electrical contact with the second source metal layer;
  • the transistor also includes a drain contact on and in electrical contact with the drain metal layer.
  • the projections of the source contact and the drain contact on the surface of the substrate are distributed in a point shape.
  • the orthographic projection of the first source region on the plane of the substrate covers the orthographic projection of the first source metal layer on the plane of the substrate;
  • the orthographic projection of the metal layer at the drain end on the plane where the substrate is located surrounds the orthographic projection of the metal layer at the first source end on the plane where the substrate is located.
  • An embodiment of the present disclosure further provides a transistor unit array, including a plurality of the transistor units provided in the embodiments of the present disclosure; the plurality of transistor units are arranged in an array.
  • the drain regions of two adjacent transistor units are electrically connected; the second source regions of two adjacent transistor units are electrically connected.
  • the embodiment of the present disclosure further provides an integrated circuit, including the transistor cell array provided by the embodiment of the present disclosure.
  • the transistor unit includes: a substrate; N gates, all located on the substrate; the projection of the N gates on the surface of the substrate forms a closed shape; N is a positive integer greater than 2; the first source region , located in the substrate and the projection on the substrate surface is located in the closed shape; the first source region is shared by the N gates; N drain regions are located in the substrate; N drain regions Each of them and the first source region are located on both sides of the corresponding gate in the N gates; a plurality of first source terminal conductive plugs are located on the first source region and connected to the first The source region is in electrical contact; each of the drain regions is provided with a plurality of drain-end conductive plugs and the drain-end conductive plugs are in electrical contact with the drain region; the first source-end metal layer is located at the first source-end conductive The plug is in electrical contact with all the first source conductive plugs; the drain metal layer is located on the drain conductive
  • the sources of multiple transistors are connected together and the gates of the multiple transistors are connected to form a closed standard unit. It can be understood that the sharing of the source makes the occupied area of the transistor unit provided by the embodiment of the present disclosure smaller; at the same time, the shared source region can provide a larger area for setting more conductive plugs at the source end, and more The conductive plug at the source end makes the transistor unit provided by the embodiments of the present disclosure have a stronger discharge current capability.
  • FIG. 1 is a partial schematic diagram of an ESD layout in the related art
  • FIG. 2 is a schematic structural diagram of a transistor unit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a transistor unit array provided by an embodiment of the present disclosure.
  • spatially relative terms such as “below”, “under”, “under”, “under”, “on”, “above”, etc. are used herein Descriptive convenience may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “beneath” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • FIG. 1 shows a partial schematic diagram of an ESD layout in the related art.
  • a plurality of gates 11 parallel to each other are arranged on the ESD layout; a source 12 and a drain 13 located on both sides of the gate 11;
  • the source end conductive plug 14 in electrical contact with the pole 12; the drain end conductive plug 15 located on the drain 13 and in electrical contact with the drain 13; the drain end conductive plug 15 located on the source end conductive plug 14 and in contact with the
  • the source metal layer 16 electrically contacted by the source conductive plug 14 ; the drain metal layer 17 located on the drain conductive plug 15 and in electrical contact with the drain conductive plug 15 .
  • the material of the gate 11 can be polysilicon; the positions of the source 12 and the drain 13 on both sides of the gate can be exchanged.
  • the ESD layout in the related art needs to meet the ESD rules, and the distance between the source, the drain and the gate is very large, which will waste a lot of area, resulting in an excessively occupied area of the overall layout. big.
  • the number of conductive plugs at the source end and the number of conductive plugs at the drain end are small, and the ability of the transistor element in the ESD layout to discharge current is limited.
  • the sources of multiple transistors are connected together and the gates of the multiple transistors are connected to form a closed standard unit. It can be understood that the sharing of the source makes the occupied area of the transistor unit provided by the embodiment of the present disclosure smaller; at the same time, the shared source region can provide a larger area for setting more conductive plugs at the source end, and more The conductive plug at the source end makes the transistor unit provided by the embodiments of the present disclosure have a stronger discharge current capability.
  • An embodiment of the present disclosure provides a transistor unit, including:
  • N gates are all located on the substrate; the projection of the N gates on the substrate surface forms a closed shape; N is a positive integer greater than 2;
  • the first source region is located in the substrate and the projection on the substrate surface is located in the closed shape; the first source region is shared by the N gates;
  • N drain regions are located in the substrate; each of the N drain regions and the first source region are located on both sides of a corresponding gate in the N gates;
  • first source terminal conductive plugs located on the first source region and in electrical contact with the first source region
  • Each drain region is provided with a plurality of drain-end conductive plugs, and the plurality of drain-end conductive plugs are in electrical contact with the corresponding drain region;
  • the first source metal layer is located on the first source conductive plug and is in electrical contact with all the first source conductive plugs;
  • the metal layer at the drain end is located on the conductive plugs at the drain end and is in electrical contact with all the conductive plugs at the drain end.
  • the transistor unit provided in the embodiment of the present disclosure may be an NMOS element or a PMOS element.
  • the substrate can be any substrate known to those skilled in the art for making transistors, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon on insulator (SOI, Silicon On Insulator ) or germanium on insulator (GOI, Germanium On Insulator), etc.
  • the material of the substrate includes silicon.
  • the substrate may have a shallow trench isolation structure for defining an active region, and the shape of the active region may be rectangular or other shapes.
  • the bottom of the gate can be isolated from the substrate by a gate dielectric layer, the top surface of the gate can be covered with a gate isolation layer, side walls of the gate can be formed with sidewalls, the gate isolation layer and The side walls are used to protect the grid.
  • the gate can be a metal gate structure, or a polysilicon gate structure, and when the gate is a metal gate structure, it can be fabricated by a replacement gate process.
  • the number (or number) of the gates is a positive integer greater than 2, and the closed shape may include various regular or irregular shapes.
  • the N is 3, 4, 5 or 6.
  • the number of the gates is 4, and the closed shape includes a square;
  • the number of the gates is 5, and the closed shape includes a pentagon;
  • the The number of gates is 6, and the closed shape includes a hexagon.
  • the projections of the plurality of grids on the surface of the substrate may just form a closed shape, or may form more shapes than the closed shape.
  • the number of grids is four, and the projections of the four grids on the substrate surface can just form a square; in other specific examples, the projections of the four grids on the substrate surface can also form
  • the figure of Jiugongge includes a square in the middle of the figure of Jiugongge.
  • the transistor unit in this embodiment includes at least one first source region shared by the N gates and N drain regions; wherein, the first source region is located in the active region of the substrate and in the substrate The projection of the bottom surface is located in the closed shape; the N drain regions are located in the active region of the substrate and each of the N drain regions is located in the N gates with the first source region on both sides of the corresponding grid. It should be noted that the number of drain regions may be the same as the number of gates.
  • the transistor unit may also include more source regions.
  • the transistor unit further includes: N second source regions, second source conductive plugs, and N second source metal layers; wherein,
  • the N second source regions are located in the substrate; the projection of each of the N second source regions on the surface of the substrate is located outside the closed shape, and is separated from one of the N drain regions by the corresponding gate. sides.
  • the N second source regions are located in the active region of the substrate.
  • ions of corresponding conductivity types are doped in the drain region and source region of transistor elements of different conductivity types, for example, when the transistor element is an N-type transistor, the drain region, the first source region and the second source region
  • the doping ions are N-type doping ions, and the N-type doping ions are, for example, phosphorus (P) ions, arsenic (As) ions, antimony (Sb) ions, etc.; when the transistor element is a P-type transistor, then
  • the dopant ions in the drain region, the first source region and the second source region are P-type dopant ions, such as boron (B) ions, boron fluoride (BF 2 ) ions, gallium ( Ga) ions, indium (In) ions, etc.
  • a plurality of second source conductive plugs are disposed on each second source region, and the plurality of second source conductive plugs are in electrical contact with the corresponding second source region.
  • electrical contact can be understood as physical contact and electrical connection.
  • the plurality of first source conductive plugs are arranged in an array.
  • each conductive plug at the first source end has the same shape, for example, a strip shape.
  • the material of each of the conductive plugs at the first source end is the same, for example, titanium (Ti), tungsten (W), cobalt (Co), nickel (Ni), zirconium (Zr), molybdenum (Mo), tantalum (Ta), copper (Cu), aluminum (Al), etc.
  • each second source region when there are N second source regions, there are correspondingly a plurality of second source terminal conductive plugs on each second source region, and the plurality of second source terminal conductive plugs are located on the second on the source region and in electrical contact with the second source region.
  • the material of each conductive plug at the second source end may be the same as that of the first conductive plug at the source end.
  • the plurality of drain-side conductive plugs are arranged in an array.
  • each of the conductive plugs at the drain end has the same shape, for example, a strip shape.
  • the material of each of the conductive plugs at the drain end is the same, for example, titanium (Ti), tungsten (W), cobalt (Co), nickel (Ni), zirconium (Zr), molybdenum (Mo ), tantalum (Ta), copper (Cu), aluminum (Al), etc. It should be noted that the shape and material of the conductive plug at the first source end may be the same as that of the conductive plug at the drain end.
  • first source-end conductive plug, the second source-end conductive plug, and the drain-end conductive plug are all a conductive contact structure, which can be expressed as Licon in English.
  • the design of a plurality of first source conductive plugs, a plurality of second source conductive plugs and a plurality of drain conductive plugs is different from that of a source conductive plug and a drain conductive plug.
  • the design of the plug can establish a wider and more uniform current discharge path, so as to improve the current distribution and discharge uniformity during electrostatic discharge discharge, thereby improving the ESD protection capability.
  • the first source metal layer is formed on the first source conductive plugs and is in electrical contact with all the first source conductive plugs.
  • the shape of the first source metal layer can be adapted to the closed shape formed by the aforementioned gate.
  • the closed shape is a square
  • the shape of the first source-end metal layer is a square with an area slightly smaller than the square where the closed shape is a square.
  • the material of the first source metal layer can be the same as that of the first source conductive plug, that is, the material of the first source metal layer can also include titanium (Ti), tungsten (W), cobalt (Co), nickel (Ni), zirconium (Zr), molybdenum (Mo), tantalum (Ta), copper (Cu), aluminum (Al), etc.
  • each of the N second source end metal layers is located in the N second source regions respectively. on the corresponding second source region in the source region, and be in electrical contact with all the second source terminal conductive plugs on the corresponding second source region.
  • the shape of the second source metal layer can be adapted to the closed shape formed by the aforementioned gate.
  • the closed shape is a square
  • the shape of the first source-end metal layer is a square.
  • the material of each second source metal layer may be the same as that of the first source conductive plug.
  • the drain metal layer is formed on the drain conductive plugs and is in electrical contact with all the drain conductive plugs.
  • the shape of the metal layer at the drain end can be adapted to the closed shape formed by the aforementioned gate.
  • the closed shape is a square
  • the shape of the metal layer at the drain end is a zigzag shape with an area slightly larger than the square where the closed shape is the square, that is, the orthographic projection of the metal layer at the drain end on the plane where the substrate is located surrounds
  • the first source metal layer is orthographically projected on the plane where the substrate is located.
  • the shape of the metal layer at the drain end may also be independently set corresponding to the N drain regions.
  • N drain regions share the same drain metal layer, it is more conducive to the miniaturization of the transistor unit area provided by the embodiment of the present disclosure; at the same time, sharing the same drain metal layer can provide a larger More conductive plugs at the drain end are arranged according to the area, and the more conductive plugs at the drain end make the transistor unit provided by the embodiments of the present disclosure more capable of discharging current.
  • the material of the metal layer at the drain end may be the same as that of the conductive plug at the drain end, that is, the material of the metal layer at the drain end may also include titanium (Ti), tungsten (W), cobalt (Co), nickel ( Ni), zirconium (Zr), molybdenum (Mo), tantalum (Ta), copper (Cu), aluminum (Al), etc.
  • the orthographic projection of the first source region on the plane of the substrate covers the orthographic projection of the first source metal layer on the plane of the substrate;
  • the orthographic projection of the metal layer at the drain end on the plane where the substrate is located surrounds the orthographic projection of the metal layer at the first source end on the plane where the substrate is located.
  • the orthographic projection can be understood as the projection formed on the projection surface when the outer contour of the object to be projected is perpendicular to the projection surface.
  • N gates share the first source region, when the orthographic projection of the drain metal layer on the plane of the substrate surrounds the first source metal layer on the plane of the substrate When projecting, this sharing can be better realized.
  • the geometric centerlines of the first source metal layer and the drain metal layer coincide.
  • the drain region is connected to the I/O interface or the power port through the conductive plug at the drain end and the metal layer at the drain end, and the first source region is connected to the I/O interface or the power port through the first source region.
  • the first source conductive plug and the first source metal layer are grounded, the second source region is grounded through the second source conductive plug and the second source metal layer, and the drain region is used as the input end of the ESD discharge current.
  • a source area is used as the discharge end of the ESD discharge current. Under the ESD discharge current, the NMOS element is turned on, and the channel of the NMOS is first opened.
  • Plug, drain region, channel/substrate, source region, all the first source conductive plugs and the first source metal layer are discharged; at the same time, the second source conductive plugs and the drain conductive plugs are correspondingly grounded Establish a current release path to discharge the ESD current.
  • the drain region is grounded through the conductive plug at the drain end and the metal layer at the drain end, and the first source region is grounded through the conductive plug at the first source end and the metal layer at the drain end.
  • the first source metal layer is connected to the I/O interface or the power port, the gate is connected to the power port, the first source area is used as the input end of the ESD discharge current, and the drain area is used as the discharge end of the ESD discharge current.
  • the PMOS element Under the ESD discharge current , the PMOS element is turned on, the channel of the PMOS is turned on first, and the ESD discharge current enters from the first source metal layer, and passes through all the first source conductive plugs, the first source region, the channel/substrate, and the drain in turn. area, drain-side conductive plug, all drain-side conductive plugs, and drain-side metal layers.
  • the second source-end conductive plug and the drain-end conductive plug correspondingly establish a current release path to discharge the ESD current.
  • An embodiment of the present disclosure discloses a transistor unit, including: a substrate; N gates, all located on the substrate; projections of the N gates on the surface of the substrate form a closed shape; N is a positive integer greater than 2; The first source region is located in the substrate and the projection on the substrate surface is located in the closed shape; the first source region is shared by the N gates; N drain regions are located in the substrate; N Each of the drain regions and the first source region are located on both sides of the corresponding gate in the N gates; a plurality of first source terminal conductive plugs are located on the first source region and connected to the first source region.
  • the first source region is in electrical contact; each drain region is provided with a plurality of drain-end conductive plugs, and the plurality of drain-end conductive plugs are in electrical contact with the corresponding drain region; the first source-end metal layer is located at the second A source-side conductive plug is in electrical contact with all the first source-side conductive plugs; a drain-side metal layer is located on the drain-side conductive plug and is in electrical contact with all the drain-side conductive plugs.
  • the sources of multiple transistors are connected together and the gates of the multiple transistors are connected to form a closed standard unit.
  • the sharing of the source makes the occupied area of the transistor unit provided by the embodiment of the present disclosure smaller; at the same time, the shared source region can provide a larger area for setting more conductive plugs at the source end, and more The conductive plug at the source terminal makes the transistor unit provided by the embodiments of the present disclosure have a stronger discharge current capability.
  • FIG. 2 is a schematic structural diagram of a transistor unit with four gates provided by an embodiment of the present disclosure. As shown in FIG. 2, the transistor unit 200 includes:
  • the four grids 21 are all located on the substrate; the projections of the four grids 21 on the surface of the substrate form a square;
  • the first source region 22 is located in the active region 20 of the substrate and the projection on the substrate surface is located in the square; the first source region 22 is shared by the four gates 21;
  • the four second source regions 23 are located in the active region 20 of the substrate; the projection of each of the four second source regions 23 on the surface of the substrate is located outside the square, and is in line with the four one of the drain regions 24 is located on both sides of the corresponding gate;
  • each of the four drain regions 24 and the first source region 22 are separated from two of the corresponding gates in the four gates 21 side;
  • first source terminal conductive plugs 25 located on the first source region 22 and in electrical contact with the first source region 22;
  • Each second source region 23 is provided with a plurality of second source conductive plugs 26, and the plurality of second source conductive plugs 26 are in electrical contact with the corresponding second source region 23;
  • Each drain region 24 is provided with a plurality of drain end conductive plugs 27, and the plurality of drain end conductive plugs 27 are in electrical contact with the corresponding drain region 24;
  • the first source metal layer 28 is located on the first source conductive plug 25 and is in electrical contact with all the first source conductive plugs 25;
  • each of the four second source-end metal layers is respectively located on the corresponding second source region in the four second source regions 23, and is connected to the corresponding second source region 23 All the second source end conductive plugs 26 are in electrical contact;
  • the drain metal layer 30 is located on the drain conductive plugs 27 and is in electrical contact with all the drain conductive plugs 27 .
  • the middle and four corners of the transistor unit 200 are sources, and the four sides are drains.
  • the four grids 21 can form any closed quadrilateral, such as a rectangle, a rhombus, and the like. It can be understood that when the four gates 21 form a square, the transistor unit can have a more reasonable symmetrical arrangement of source and drain terminals, and a simpler manufacturing process.
  • the projection of the N grids 21 on the surface of the substrate forms a first square.
  • the first source metal layer 28, the second source metal layer 29, and the drain metal layer 30 are all adapted to the closed shape formed by the gate 21.
  • the first The projection of the source terminal metal layer 28 on the substrate surface forms a second square, and the second square is located in the first square; the projection of the second source terminal metal layer 29 on the substrate surface forms a third square, and the third square is located in the first square. Outside the first square; the projection of the drain metal layer 30 on the surface of the substrate forms a zigzag shape, and the first square is located in the zigzag shape.
  • the geometric centerlines of the first square, the second square and the zigzag coincide.
  • the sum of the areas of the N second source regions is equal to the area of the first source regions.
  • the area of the four second source regions 23 in FIG. 2 is equal to the area of the first source region 22 . It can be understood that when the sum of the areas of the N second source regions is equal to the area of the first source region, it is more convenient to splice multiple transistor units.
  • the spliced area of the 4 second source regions in the middle of the corresponding 4 first source regions in the 4 transistor units is the same as that of each of the 4 first source regions.
  • the area of a source region is equal. In this way, it can be ensured that the electrostatic discharge channel of the structure obtained by splicing a plurality of transistor units is uniform, so that the discharge current of the transistor units is more stable.
  • the corners of the second square and the back shape can be rounded or chamfered to prevent discharge phenomenon.
  • the corners of the second square and the back shape are both rounded or chamfered.
  • FIG. 2 What is shown in FIG. 2 is the situation that the corners of the second square and the back shape are all chamfered.
  • the first source conductive plugs 25 are aligned and arranged at intervals along a direction parallel to any gate of the N gates 21, forming M first gates parallel to any gate. Conductive plug row at the source end;
  • a plurality of second source terminal conductive plugs 26 on each second source region 23 are aligned in rows along a direction parallel to the corresponding gate at intervals. cloth, forming K second source-end conductive plug rows parallel to the corresponding gates;
  • drain-end conductive plugs 27 on each drain region 24 are aligned and arranged at intervals along a direction parallel to the corresponding gate, forming a structure parallel to the corresponding gate.
  • M, K, and P are all positive integers.
  • the shapes and materials of the first source conductive plug 25 , the second source conductive plug 26 and the drain conductive plug 27 may be the same.
  • M the values of M, K, and P can be adjusted according to the actual situation.
  • the total number of first source conductive plugs 25 on the first source region 22 is the same as the total number of second source conductive plugs 26 on the N second source regions 23.
  • the total number of the first source conductive plugs 25 on the first source region 22 is the same as the total number of the second source conductive plugs 26 on the N second source regions 23. for 24.
  • the sum of the total numbers of the first source-side conductive plugs 25 and the second source-side conductive plugs 26 is the same as the total number of the drain-side conductive plugs 27 .
  • the first source conductive plug 25 , the second source conductive plug 26 and the drain conductive plug 27 have the same shape and size.
  • projections of the first source conductive plug 25 , the second source conductive plug 26 and the drain conductive plug 27 on the surface of the substrate are all strip-shaped.
  • the projections of the first source conductive plug 25 , the second source conductive plug 26 and the drain conductive plug 27 on the substrate surface are all strip-shaped.
  • the transistor further includes a plurality of source contacts 31 respectively located on the first source metal layer 28 and the second source metal layer 29 and connected to the first source metal layer respectively.
  • Layer 28 is in electrical contact or the second source metal layer 29 is in electrical contact;
  • the transistor also includes a drain contact 32 located on the drain metal layer 30 and in electrical contact with the drain metal layer 30 .
  • the source contacts 31 are respectively used to electrically lead out the corresponding first source metal layer 28 and the second source metal layer 29 so as to be connected to a power interface or ground according to actual needs.
  • the drain contact 32 is used to electrically lead the drain metal layer 30 to be connected to a ground or a power interface according to actual needs.
  • source contact 31 and the drain contact 32 are both a conductive contact structure, which can be expressed as Contact in English.
  • the projections of the source contacts 31 and the drain contacts 32 on the surface of the substrate are distributed in a point shape.
  • FIG. 2 What is shown in FIG. 2 is the situation that the projections of the source contacts 31 and the drain contacts 32 on the surface of the substrate are distributed in dots.
  • an embodiment of the present disclosure further provides a transistor unit array, including a plurality of transistor units provided in the embodiments of the present disclosure; the plurality of transistor units are arranged in an array.
  • the drain regions of two adjacent transistor units are electrically connected; the second source regions of two adjacent transistor units are electrically connected.
  • the transistor unit array provided by the present disclosure has one or more transistor units described in the present disclosure, and the transistor elements are NMOS elements or PMOS elements.
  • the transistor unit array has a plurality of transistor elements of the same type, the plurality of transistor elements are connected in parallel, and are laid out in a way of sharing source and drain.
  • the transistor unit array 300 of an embodiment of the present disclosure is mainly composed of four parallel transistor units described in the present disclosure (four transistor units 200-1, 200-2, 200- 3 and 200-4), the four transistor elements are formed in the same active region, and the adjacent transistor elements have a common source or a common drain.
  • the transistor cell array of the above embodiment has 4 transistor cells of the present disclosure, but the technical solution of the present disclosure is not limited thereto, the number of transistor elements of the present disclosure in the transistor cell array of other embodiments of the present disclosure can be It is multiple, such as 2, 3 or 4, and can also be greater than 4, and when the number of transistor elements of the present disclosure is greater than or equal to 2, the adjacent two shown in Figure 3 can be used
  • the parallel connection of two adjacent transistor elements is realized by the common source and common drain parallel connection of the transistor elements.
  • the structures of the transistor elements of the present disclosure in the transistor cell arrays of various embodiments of the present disclosure may be completely the same, or may be partially completely the same.
  • the transistor cell array includes at least one A PMOS element and at least one NMOS element of the present disclosure.
  • the transistor unit array of the present disclosure has a simple structure and relatively high protection performance.
  • the transistor unit array of the present disclosure can be used as an independent device installed on the corresponding equipment circuit, or it can be integrated into the corresponding integrated circuit. in the circuit.
  • the source and drain can be shared at the same time, which will greatly reduce the wasted area caused by the source and drain being too far away from the gate, thereby reducing the entire ESD The area of the array layout.
  • the total width of the transistor unit array is the number of horizontal gates times the length of the horizontal gate+the number of vertical gates multiplied by the length of the vertical gate.
  • the ESD array layout provided by the embodiment of the present disclosure has a smaller area under the condition of the same total width; at the same time, the number of Licons increases and the current discharge capability is stronger.
  • the overall shape of the ESD array layout provided by the embodiments of the present disclosure can be adjusted by splicing.
  • an embodiment of the present disclosure further provides an integrated circuit, including multiple transistor cell arrays provided in the embodiments of the present disclosure.
  • the integrated circuit includes the transistor unit array, the input/output interface and the internal circuit described in the present disclosure; wherein the transistor unit array is connected between the input/output interface and the internal circuit.
  • the transistor unit array includes an NMOS unit and/or a PMOS unit, the drain region of the NMOS element is connected between the input/output interface and the internal circuit, and the source region and the gate of the NMOS element are grounded; Or the source area of the PMOS element is connected between the input/output interface and the internal circuit, the gate of the PMOS element is connected to the power port, and the drain area of the PMOS element is grounded.
  • the sources of multiple transistors are connected together and the gates of the multiple transistors are connected to form a closed standard unit. It can be understood that the sharing of the source makes the occupied area of the transistor unit provided by the embodiment of the present disclosure smaller; at the same time, the shared source region can provide a larger area for setting more conductive plugs at the source end, and more The conductive plug at the source end makes the transistor unit provided by the embodiments of the present disclosure have a stronger discharge current capability.

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Abstract

本公开实施例公开了一种晶体管单元及其阵列、集成电路。其中，晶体管单元包括：衬底；N条栅极，均位于衬底上；N条栅极在衬底表面的投影形成封闭的形状；N为大于2的正整数；第一源区；位于衬底中，且第一源区在衬底表面的投影位于封闭的形状中；第一源区被N条栅极共用；N个漏区；位于衬底中，且N个漏区中的每个漏区均和源区分居N条栅极中相应栅极的两侧；多个第一源端导电插栓，位于第一源区上，并与第一源区电接触；每个漏区设置有多个漏端导电插栓，且多个漏端导电插栓与漏区电接触；第一源端金属层，位于第一源端导电插栓上，并与所有的第一源端导电插栓电接触；漏端金属层，位于漏端导电插栓上，并与所有的漏端导电插栓电接触。

Description

晶体管单元及其阵列、集成电路
相关申请的交叉引用
本公开基于申请号为202111602790.7、申请日为2021年12月24日、发明名称为“晶体管单元及其阵列、集成电路”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种晶体管单元及其阵列、集成电路。
背景技术
当静电放电(ESD，Electro Static Discharge)产生的放电电流在集成电路内流过时，会产生局部发热或电场集中的情况，由此会破坏集成电路，导致集成电路失效。因此，为了防止ESD造成的破坏，一般在集成电路的输入/输出接口(I/O)与内部核心电路之间设置ESD保护元件。其中，金属氧化物半导体场效应晶体管(MOSFET，Metal Oxide Semiconductor Field Effect Transistor)元件通常用于集成电路中的ESD保护，能够将相应的ESD放电电流泄放至地，避免损坏所涉及的集成电路中的半导体器件和/或金属互连。
然而，相关技术中，用于ESD保护的晶体管元件存在放电能力有限，集成度较低的问题。
发明内容
本公开实施例提出一种晶体管单元及其阵列、集成电路。
本公开实施例提供了一种晶体管单元，包括：
衬底；
N条栅极，均位于衬底上；N条栅极在衬底表面的投影形成封闭的形状；N为大于2的正整数；
第一源区，位于衬底中且在衬底表面的投影位于所述封闭的形状中；所述第一源区被所述N条栅极共用；
N个漏区，位于衬底中；N个漏区中的每个均和所述第一源区分居所述N条栅极中相应栅极的两侧；
多个第一源端导电插栓，位于所述第一源区上并与所述第一源区电接触；
每个所述漏区上设置有多个漏端导电插栓且所述漏端导电插栓与所述漏区电接触；
第一源端金属层，位于所述第一源端导电插栓上并与所有的所述第一源端导电插栓电接触；
漏端金属层，位于所述漏端导电插栓上并与所有的所述漏端导电插栓电接触。
上述方案中，所述晶体管单元还包括：
N个第二源区、第二源端导电插栓，以及N个第二源端金属层；其中，
所述N个第二源区位于所述衬底中；所述N个第二源区中的每个在所述衬底表面的投影均位于所述封闭的形状外，且与所述漏区分居相应栅极的两侧；
位于每个所述第二源区上设置有多个所述第二源端导电插栓且所述第二源端导电插栓与所述第二源区电接触；
所述N个第二源端金属层中的每个分别位于N个第二源区中相应第二源区上，并与相应第二源区上的所有第二源端导电插栓电接触。
上述方案中，所述N为3、4、5或者6。
上述方案中，N＝4。
上述方案中，所述N条栅极在衬底表面的投影形成的封闭形状为正方形。
上述方案中，所述N个第二源区的面积之和等于所述第一源区的面积。
上述方案中，所述第一源端导电插栓沿平行于N条栅极中任一栅极的方向相互间隔地对齐排布，构成平行于任一栅极的M个第一源端导电插栓排；
针对所述N个第二源区中的每个第二源区，多个第二源端导电插栓沿平行于相应栅极方向相互间隔地对齐排布，构成平行于相应栅极的K个第二源端导电插栓排；
针对所述N个漏区每个漏区，多个漏端导电插栓沿平行于相应栅极方向相互间隔地对齐排布，构成平行于相应栅极的P个漏端导电插栓排；
其中，M、K、P均为正整数。
上述方案中，所述第一源区上第一源端导电插栓的总数量与所述N个第二源区上第二源端导电插栓的总数量相同。
上述方案中，所述第一源端导电插栓、所述第二源端导电插栓及所述漏端导电插栓的形状、尺寸均相同。
上述方案中，所述第一源端导电插栓、所述第二源端导电插栓及所述漏端导电插栓在衬底表面的正投影均为长条状。
上述方案中，所述晶体管还包括多个源端接触，分别位于所述第一源端金属层和所述第二源端金属层上并分别与所述第一源端金属层电接触或所述第二源端金属层电接触；
所述晶体管还包括漏端接触，位于所述漏端金属层上并与所述漏端金属层电接触。
上述方案中，所述源端接触和所述漏端接触在衬底表面的投影均呈点状分布。
上述方案中，所述第一源区在所述衬底所在平面上的正投影覆盖所述第一源端金属层在所述衬底所在平面上正投影；
漏端金属层在衬底所在平面上的正投影环绕所述第一源端金属层在所述衬底所在平面上正投影。
上述方案中，所述第一源端金属层和所述漏端金属层的几何中心线重合。
本公开实施例又提供了一种晶体管单元阵列，包括多个本公开实施例提供的所述的晶体管单元；多个所述晶体管单元呈阵列排布。
上述方案中，两个相邻所述晶体管单元的漏区电连接；两个相邻所述晶体管单元的第二源区电连接。
本公开实施例又提供了一种集成电路，包括本公开实施例提供的所述的晶体管单元阵列。
本公开实施例公开了一种晶体管单元及其阵列、集成电路。其中，所述晶体管单元，包括：衬底；N条栅极，均位于衬底上；N条栅极在衬底表面的投影形成封闭的形状；N为大于2的正整数；第一源区，位于衬底中且在衬底表面的投影位于所述封闭的形状中；所述第一源区被所述N条栅极共用；N个漏区，位于衬底中；N个漏区中的每个均和所述第一源区分居所述N条栅极中相应栅极的两侧；多个第一源端导电插栓，位于所述第一源区上并与所述第一源区电接触；每个所述漏区上设置有多个漏端导电插栓且所述漏端导电插栓与所述漏区电接触；第一源端金属层，位于第一源端导电插栓上并与所有的第一源端导电插栓电接触；漏端金属层，位于漏端导电插栓上并与所有的漏端导电插栓电接触。本公开实施例中，通过将多个晶体管的源极极连接在一起并将该多个晶体管的栅极接成一个封闭的形状的标准单元。可以理解的是，源极的共用使得本公开实施例提供的晶体管单元占用面积较小；同时，共用的源极区域可以提供较大的面积来设置较多的源端导电插栓，较多的源端导电插栓使得本公开实施例提供 的晶体管单元的泄放电流的能力较强。
附图说明
图1为相关技术中的ESD版图的局部示意图；
图2为本公开实施例提供的一种晶体管单元的结构示意图；
图3为本公开实施例提供的一种晶体管单元阵列的结构示意图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取 向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
需要说明的是：“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
为了能够更加详尽地了解本公开实施例的特点与技术内容，下面结合附图对本公开实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本公开实施例。
工业调查表明大约有40％的集成电路(IC，Integrated Circuit)的失效与ESD有关，为防止静电放电现象损坏电路，需要设计ESD版图。
图1示出了相关技术中的ESD版图的局部示意图。如图1所示，该ESD版图上设置有多条相互平行的栅极11；位于所述栅极11两侧的源极12和漏极13；位于所述源极12上且与所述源极12电接触的源端导电插栓14；位于所述漏极13上且与所述漏极13电接触的漏端导电插栓15；位于所述源端导电插栓14上且与所述源端导电插栓14电接触的源端金属层16；位于所述漏端导电插栓15上且与所述漏端导电插栓15电接触的漏端金属层17。实际应用中，所述栅极11的材料可以为多晶硅；所述源极12和漏极13在所述栅极两侧的位置可以调换。
从图1可以看出，相关技术中的ESD版图由于需要满足ESD规则，源 极和漏极与栅极之间的间距很大，这样会浪费较多的面积，导致整体版图的占用的面积过大。同时，源端导电插栓的数量和漏端导电插栓的数量较少，ESD版图中晶体管元件泄放电流的能力有限。
基于此，在本公开的各实施例中，通过将多个晶体管的源极连接在一起并将该多个晶体管的栅极接成一个封闭的形状的标准单元。可以理解的是，源极的共用使得本公开实施例提供的晶体管单元占用面积较小；同时，共用的源极区域可以提供较大的面积来设置较多的源端导电插栓，较多的源端导电插栓使得本公开实施例提供的晶体管单元的泄放电流的能力较强。
本公开实施例提供一种晶体管单元，包括：
衬底；
N条栅极，均位于衬底上；N条栅极在衬底表面的投影形成封闭的形状；N为大于2的正整数；
第一源区，位于衬底中且在衬底表面的投影位于所述封闭的形状中；所述第一源区被所述N条栅极共用；
N个漏区，位于衬底中；N个漏区中的每个均和所述第一源区分居所述N条栅极中相应栅极的两侧；
多个第一源端导电插栓，位于所述第一源区上并与所述第一源区电接触；
每个漏区上设置有多个漏端导电插栓，且多个漏端导电插栓与对应的漏区电接触；
第一源端金属层，位于第一源端导电插栓上并与所有的第一源端导电插栓电接触；
漏端金属层，位于漏端导电插栓上并与所有的漏端导电插栓电接触。
需要说明的是，本公开实施例提供的晶体管单元可以NMOS元件，也可以是PMOS元件。
其中，所述衬底可以是本领域技术人员熟知的任何用于制作晶体管的底材，例如硅(Si)、锗(Ge)、锗化硅(SiGe)、绝缘体上硅(SOI，Silicon On Insulator)或绝缘体上锗(GOI，Germanium On Insulator)等。在一些实施例中，所述衬底的材料包括硅。所述衬底中可以具有用于定义有源区的浅沟槽隔离结构，所述有源区的形状可以是矩形，也可以是其它形状。
这里，所述栅极底部可以通过栅介质层与衬底隔离，所述栅极的顶面上可以覆盖有栅极隔离层，栅极的侧壁上可以形成有侧墙，栅极隔离层和侧墙均用于保护栅极。栅极可以是金属栅极结构，也可以是多晶硅栅极结构，当栅极为金属栅极结构时，可以采用替代栅极工艺制作。
所述栅极的数量(或者条数)为大于2的正整数，所述封闭的形状可以包括各种规则或不规格的形状。在一些实施例中，所述N为3、4、5或者6。示例性地，所述栅极的数量为4，所述封闭的形状包括正方形；示例性地，所述栅极的数量为5，所述封闭的形状包括五边形；示例性地，所述栅极的数量为6，所述封闭的形状包括六边形。
需要说明的是，多条栅极在衬底表面的投影可以正好形成封闭的形状，也可以形成比封闭形状更多的形状。在一些具体示例中，所述栅极的数量为4，4条栅极在衬底表面的投影可以正好形成正方形；在另一些具体示例中，4条栅极在衬底表面的投影也可以形成九宫格的图形，在九宫格的图形的正中间包括一个正方形。
这里，本实施例中的晶体管单元包括至少一个被所述N条栅极共用的第一源区以及N个漏区；其中，所述第一源区位于衬底的有源区中且在衬底表面的投影位于所述封闭的形状中；所述N个漏区位于衬底的有源区中且N个漏区中的每个均和所述第一源区分居所述N条栅极中相应栅极的两侧。需要说明的是，这里漏区的数量可以与栅极的数量相同。
当多条栅极在衬底表面的投影形成比封闭形状更多的形状时，晶体管单元还可以包括更多的源区。
基于此，在一些实施例中，晶体管单元还包括：N个第二源区、第二源端导电插栓，以及N个第二源端金属层；其中，
N个第二源区位于衬底中；N个第二源区中的每个在衬底表面的投影均位于封闭的形状外，且与N个漏区中的一个漏区分居相应栅极的两侧。
这里，所述N个第二源区位于衬底的有源区中。
实际应用中，不同导电类型的晶体管元件的漏区和源区中掺杂相应导电类型的离子，例如所述晶体管元件为N型晶体管时，则漏区、第一源区及第二源区中的掺杂离子为N型掺杂离子，所述N型掺杂离子例如为磷(P)离子、砷(As)离子、锑(Sb)离子等；所述晶体管元件为P型晶体管时，则漏区、第一源区及第二源区中的掺杂离子为P型掺杂离子，所述P型掺杂离子例如为硼(B)离子、氟化硼(BF 2)离子、稼(Ga)离子、铟(In)离子等。
这里，每个第二源区上设置有多个第二源端导电插栓且多个第二源端导电插栓与对应的第二源区电接触。其中，电接触可以理解为，物理接触且电连接。在一些实施例中，多个第一源端导电插栓呈阵列排布。在一些实施例中，每个第一源端导电插栓的形状均相同，如，长条状。在一些实施例中，每个所述第一源端导电插栓的材料均相同，例如包括钛(Ti)、钨(W)、钴(Co)、镍(Ni)、锆(Zr)、钼(Mo)、钽(Ta)、铜(Cu)、铝(Al)等。
在一些实施例中，当存在N个第二源区时，每个第二源区上对应地还会存在多个第二源端导电插栓，多个第二源端导电插栓位于第二源区上并与第二源区电接触。实际应用中，每个第二源端导电插栓的材料可以与第一源端导电插栓的材料相同。
在一些实施例中，多个漏端导电插栓呈阵列排布。在一些实施例中，每个所述漏端导电插栓的形状均相同，如，长条状。在一些实施例中，每个所述漏端导电插栓的材料均相同，例如包括钛(Ti)、钨(W)、钴(Co)、 镍(Ni)、锆(Zr)、钼(Mo)、钽(Ta)、铜(Cu)、铝(Al)等。需要说明的是，第一源端导电插栓的形状和材料均可以与漏端导电插栓的形状和材料相同。
需要说明的是，所述第一源端导电插栓、第二源端导电插栓以及漏端导电插栓均为一种导电接触结构，英文可以表达为Licon。
可以理解的是，多个第一源端导电插栓、多个第二源端导电插栓及多个漏端导电插栓的设计，相较于一个源端导电插栓和一个漏端导电插栓的设计可以建立更宽且更加均匀的电流释放路径，从而能够改善静电放电泄流时的电流分布和泄流均匀性，从而提高ESD防护能力。
这里，所述第一源端金属层形成于所述第一源端导电插栓上且与所有的所述第一源端导电插栓电接触。实际应用中，第一源端金属层的形状可以与前述栅极形成的封闭形状适配。示例性地，所述封闭形状为正方形，所述第一源端金属层的形状为面积比封闭形状为正方形所在的正方形略小的正方形。
实际应用中，第一源端金属层的材料可以与第一源端导电插栓的材料相同，即所述第一源端金属层的材料同样可以包括钛(Ti)、钨(W)、钴(Co)、镍(Ni)、锆(Zr)、钼(Mo)、钽(Ta)、铜(Cu)、铝(Al)等。
在一些实施例中，当存在N个第二源区时，对应地还会存在N个第二源端金属层，所述N个第二源端金属层中的每个分别位于N个第二源区中相应第二源区上，并与相应第二源区上的所有第二源端导电插栓电接触。实际应用中，第二源端金属层的形状可以与前述栅极形成的封闭形状适配。示例性地，所述封闭形状为正方形，所述第一源端金属层的形状为正方形。实际应用中，每个第二源端金属层的材料可以与所述第一源端导电插栓的材料相同。
这里，所述漏端金属层形成于所述漏端导电插栓上且与所有的所述漏 端导电插栓电接触。实际应用中，漏端金属层的形状可以与前述栅极形成的封闭形状适配。示例性地，所述封闭形状为正方形，所述漏端金属层的形状为面积比封闭形状为正方形所在的正方形略大的回字形，即漏端金属层在衬底所在平面上的正投影环绕所述第一源端金属层在所述衬底所在平面上正投影。需要说明的是，漏端金属层的形状也可以对应N个漏区分别独立设置。可以理解的是，当所述N个漏区共用同一个漏端金属层时，更利于本公开实施例提供的晶体管单元面积的小型化；同时，共用同一个漏端金属层可以提供较大的面积来设置较多的漏端导电插栓，较多的漏端导电插栓使得本公开实施例提供的晶体管单元的泄放电流的能力更强。
实际应用中，漏端金属层的材料可以与漏端导电插栓的材料相同，即所述漏端金属层的材料同样可以包括钛(Ti)、钨(W)、钴(Co)、镍(Ni)、锆(Zr)、钼(Mo)、钽(Ta)、铜(Cu)、铝(Al)等。
在一些实施例中，所述第一源区在所述衬底所在平面上的正投影覆盖所述第一源端金属层在所述衬底所在平面上正投影；
漏端金属层在衬底所在平面上的正投影环绕所述第一源端金属层在所述衬底所在平面上正投影。
这里，所述正投影可以理解为待投影对象的外轮廓向投影面作垂线时在投影面形成的投影。在本申请实施例中，由于N个栅极共用第一源区，当漏端金属层在衬底所在平面上的正投影环绕所述第一源端金属层在所述衬底所在平面上正投影时，能够更好的实现该共用。
在一些实施例中，所述第一源端金属层和所述漏端金属层的几何中心线重合。
可以理解的是，当所述第一源端金属层和所述漏端金属层的几何中心线重合时，可以获得对称性良好的源、漏端排布，从而可以保证静电释放的通道均匀，不产生尺寸突变，即晶体管单元的泄放电流的更加平稳。
在一些实施例中，本实施例提供的晶体管单元为NMOS元件并用静电 保护时，漏区通过漏端导电插栓和漏端金属层连接到I/O接口或电源端口，第一源区通过第一源端导电插栓和第一源端金属层接地，第二源区通过第二源端导电插栓和第二源端金属层接地栅极接地，漏区作为ESD放电电流的输入端、第一源区作为ESD放电电流的泄放端，在ESD放电电流下，NMOS元件导通，所述NMOS的沟道率先开启，ESD放电电流从漏端金属层进入，依次经所有的漏端导电插栓、漏区、沟道/衬底、源区、所有第一源端导电插栓和第一源端金属层进行泄放；同时，第二源端导电插栓和漏端导电插栓对应地建立电流释放路径来泄放ESD电流。
在另一些实施例中，本实施例提供的晶体管单元为PMOS元件并用静电保护时，漏区通过漏端导电插栓和漏端金属层接地，第一源区通过第一源端导电插栓和第一源端金属层连接到I/O接口或电源端口，栅极接电源端口，第一源区作为ESD放电电流的输入端、漏区作为ESD放电电流的泄放端，在ESD放电电流下，PMOS元件导通，所述PMOS的沟道率先开启，ESD放电电流从第一源端金属层进入，依次经所有第一源端导电插栓、第一源区、沟道/衬底、漏区、漏端导电插栓、所有的漏端导电插栓和漏端金属层进行泄放。同时，第二源端导电插栓和漏端导电插栓对应地建立电流释放路径来泄放ESD电流。
本公开实施例公开了一种晶体管单元，包括：衬底；N条栅极，均位于衬底上；N条栅极在衬底表面的投影形成封闭的形状；N为大于2的正整数；第一源区，位于衬底中且在衬底表面的投影位于所述封闭的形状中；所述第一源区被所述N条栅极共用；N个漏区，位于衬底中；N个漏区中的每个均和所述第一源区分居所述N条栅极中相应栅极的两侧；多个第一源端导电插栓，位于所述第一源区上并与所述第一源区电接触；，每个漏区上设置有多个漏端导电插栓，且多个漏端导电插栓与对应的漏区电接触；第一源端金属层，位于第一源端导电插栓上并与所有的第一源端导电插栓电接触；漏端金属层，位于漏端导电插栓上并与所有的漏端导电插栓电接 触。本公开实施例中，通过将多个晶体管的源极连接在一起并将该多个晶体管的栅极接成一个封闭的形状的标准单元。可以理解的是，源极的共用使得本公开实施例提供的晶体管单元占用面积较小；同时，共用的源极区域可以提供较大的面积来设置较多的源端导电插栓，较多的源端导电插栓使得本公开实施例提供的晶体管单元的泄放电流的能力较强。
在一个应用场景中，N＝4。也就是说包括4条栅极。图2为本公开实施例提供的一种具有4条栅极的晶体管单元的结构示意图。如图2所示，所述晶体管单元200，包括：
衬底；
4条栅极21，均位于衬底上；4条栅极21在衬底表面的投影形成正方形；
第一源区22，位于衬底的有源区20中且在衬底表面的投影位于所述正方形中；所述第一源区22被所述4条栅极21共用；
4个第二源区23，位于衬底的有源区20中；所述4个第二源区23中的每个在所述衬底表面的投影均位于所述正方形外，且与4个漏区24中的一个漏区分居相应栅极的两侧；
4个漏区24，位于衬底的有源区20中；所述4个漏区24中的每个均和所述第一源区22分居所述4条栅极21中相应栅极的两侧；
多个第一源端导电插栓25，位于所述第一源区22上并与所述第一源区22电接触；
每个第二源区23上设置有多个第二源端导电插栓26，且多个第二源端导电插栓26与相应的第二源区23电接触；
每个漏区24上设置有多个漏端导电插栓27，且多个漏端导电插栓27与相应的漏区24电接触；
第一源端金属层28，位于第一源端导电插栓25上并与所有的第一源端导电插栓25电接触；
4个第二源端金属层29，所述4个第二源端金属层中的每个分别位于4个第二源区23中相应第二源区上，并与相应第二源区23上的所有第二源端导电插栓26电接触；
漏端金属层30，位于漏端导电插栓27上并与所有的漏端导电插栓27电接触。
这里，晶体管单元200的中间和四角是源极，四边是漏级。
实际应用中，4条栅极21可以形成任意封闭的四边形，如长方形、菱形等。可以理解的是当4条栅极21形成正方形时，晶体管单元可以具有更合理的源、漏端对称排布，更简洁的制造工艺。
基于此，在一些实施例中，所述N条栅极21在所述衬底表面的投影形成第一正方形。
前已述及，所述第一源端金属层28、第二源端金属层29、漏端金属层30均与栅极21形成的封闭形状适配，在一些实施例中，所述第一源端金属层28在衬底表面的投影形成第二正方形，第二正方形位于所述第一正方形中；第二源端金属层29在衬底表面的投影形成第三正方形，第三正方形位于所述第一正方形外；漏端金属层30在衬底表面的投影形成回字形，第一正方形位于所述回字形中。
在一些实施例中，所述第一正方形、所述第二正方形以及所述回字形的几何中心线重合。
可以理解的是，按照上述方式设置第一源端金属层28、第二源端金属层29、漏端金属层30的形状可以获得对称性良好的源、漏端排布，从而可以保证静电释放的通道均匀，不产生尺寸突变，即晶体管单元的泄放电流的更加平稳。
在一些实施例中，所述N个第二源区的面积之和等于所述第一源区的面积。
示例性地，图2中4个第二源区23的面积与第一源区22的面积相等。 可以理解的是，当N个第二源区的面积之和与所述第一源区的面积相等时，更方便多个晶体管单元进行拼接。示例性地，图3中4个晶体管单元进行拼接时，4个晶体管单元中对应的4个第一源区中间的4个第二源区拼接的面积与4个第一源区中每个第一源区的面积相等。如此，可以保证多个晶体管单元进行拼接得到的结构的静电释放的通道均匀，从而晶体管单元的泄放电流的更加平稳。
实际应用中，考虑到直角比较尖锐，容易产生放电现象，可以将所述第二正方形和所述回字形的角均为圆角或倒角，以防止放电现象的产生。
基于此，在一些实施例中，所述第二正方形和所述回字形的角均为圆角或倒角。
图2中示出的是所述第二正方形和所述回字形的角均为倒角的情况。
在一些实施例中，所述第一源端导电插栓25沿平行于N条栅极21中任一栅极的方向相互间隔地对齐排布，构成平行于任一栅极的M个第一源端导电插栓排；
针对所述N个第二源区中的每个第二源区23，每个第二源区23上的多个第二源端导电插栓26沿平行于相应栅极方向相互间隔地对齐排布，构成平行于相应栅极的K个第二源端导电插栓排；
针对所述N个漏区中的每个漏区24，每个漏区24上的多个漏端导电插栓27沿平行于相应栅极方向相互间隔地对齐排布，构成平行于相应栅极的P个漏端导电插栓排；
其中，M、K、P均为正整数。
实际应用中，所述第一源端导电插栓25、第二源端导电插栓26及漏端导电插栓27的形状和材料均可以相同。
实际应用中，所述M、K、P的数值可以根据实际情况进行调整，图2中示出的是M＝2，K＝1，P＝2的情况。
在一些实施例中，所述第一源区22上第一源端导电插栓25的总数量 与所述N个第二源区23上第二源端导电插栓26的总数量相同。
如图2所示，所述第一源区22上第一源端导电插栓25的总数量与所述N个第二源区23上第二源端导电插栓26的总数量相同，均为24个。
在另一些实施例中，所述第一源端导电插栓25和第二源端导电插栓26的总数量之和与所述漏端导电插栓27的总数量相同。
在一些实施例中，所述第一源端导电插栓25、所述第二源端导电插栓26及所述漏端导电插栓27的形状、尺寸均相同。
在一些实施例中，所述第一源端导电插栓25、所述第二源端导电插栓26及所述漏端导电插栓27在衬底表面的投影均为长条状。
图2中示出的是所述第一源端导电插栓25、所述第二源端导电插栓26及所述漏端导电插栓27在衬底表面的投影均为长条状。
在一些实施例中，所述晶体管还包括多个源端接触31，分别位于所述第一源端金属层28和所述第二源端金属层29上并分别与所述第一源端金属层28电接触或所述第二源端金属层29电接触；
所述晶体管还包括漏端接触32，位于所述漏端金属层30上并与所述漏端金属层30电接触。
实际应用中，所述源端接触31分别用于将相应的第一源端金属层28、所述第二源端金属层29电引出，以根据实际需求与电源接口或地连接。所述漏端接触32用于将漏端金属层30电引出，以根据实际需求与地或电源接口连接。
需要说明的是，所述源端接触31、漏端接触32均为一种导电接触结构，英文可以表达为Contact。
在一些实施例中，所述源端接触31和所述漏端接触32在衬底表面的投影均呈点状分布。
图2中示出的是所述源端接触31和所述漏端接触32在衬底表面的投影均呈点状分布的情况。
基于前述晶体管单元，本公开实施例还提供一种晶体管单元阵列，包括多个本公开实施例提供的晶体管单元；多个所述晶体管单元呈阵列排布。
在一些实施例中，两个相邻所述晶体管单元的漏区电连接；两个相邻所述晶体管单元的第二源区电连接。
本公开提供的晶体管单元阵列，具有一个或多个本公开所述的晶体管单元，所述晶体管元件为NMOS元件或PMOS元件。当所述晶体管单元阵列具有多个同类型的所述的晶体管元件时，多个所述的晶体管元件并联，并采用共用源漏共用方式进行布局。如图3所示，本公开的一实施例的晶体管单元阵列300主要由4个并联的本公开所述的晶体管单元(如图3中的4个晶体管单元200-1、200-2、200-3以及200-4)组成，4个所述晶体管元件形成于同一个有源区中，且相邻的所述晶体管元件共源或共漏。
上述实施例的晶体管单元阵列具有4个本公开的晶体管单元，但本公开的技术方案并不仅仅限定于此，本公开的其他实施例的晶体管单元阵列中具有的本公开的晶体管元件的数量可以为多个，例如2个、3个或4个，也可以大于4个，且当具有的本公开的晶体管元件的数量大于或等于2时，均可以采用图3中所示的相邻两个晶体管元件共源共漏的并联方式来实现相邻两个晶体管元件的并联。此外，本公开各实施例的晶体管单元阵列中的各个本公开的晶体管元件的结构可以完全相同，也可以是部分完全相同，例如在本公开其他实施例中，晶体管单元阵列包括至少一个本公开的PMOS元件和至少一个本公开的NMOS元件。
由上所述，本公开的晶体管单元阵列，结构简单，且防护性能较，本公开的晶体管单元阵列，可以作为一个独立器件安装到相应的设备电路上进行使用，也可以是集成到相应的集成电路中。
可以理解的是，通过将晶体管单元拼接在一起，形成晶体管单元阵列实现了源极、漏极同时共用，会大大减少由于源极、漏级距离栅极过远导致浪费的面积，从而缩小整个ESD阵列版图的面积。
由于充分的利用了衬底的有源区(Active area)，晶体管单元阵列的总宽度为横向栅极个数乘横向栅极长度+纵向栅极个数乘纵向栅极长度。相较于相关技术中提供的ESD版图，本公开实施例提供的ESD阵列版图在总宽度相同的条件下面积更小；同时Licon数目增多，电流泄放能力更强。此外，本公开实施例提供的ESD阵列版图的总形状可以通过拼接来调节。
基于前述晶体管单元阵列，本公开实施例还提供一种集成电路，包括多个本公开实施例提供的所述晶体管单元阵列。
实际应用中，所述集成电路包括本公开所述的晶体管单元阵列以及输入/输出接口和内部电路；其中，所述晶体管单元阵列连接在所述输入/输出接口和内部电路之间。具体地，所述晶体管单元阵列包括NMOS单元和/或PMOS单元，所述NMOS元件的漏区连接在所述输入/输出接口和内部电路之间，所述NMOS元件的源区和栅极接地；或者所述PMOS元件的源区连接在所述输入/输出接口和内部电路之间，所述PMOS元件的栅极连接电源端口，所述PMOS元件的漏区接地。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本公开的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可 轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例中，通过将多个晶体管的源极极连接在一起并将该多个晶体管的栅极接成一个封闭的形状的标准单元。可以理解的是，源极的共用使得本公开实施例提供的晶体管单元占用面积较小；同时，共用的源极区域可以提供较大的面积来设置较多的源端导电插栓，较多的源端导电插栓使得本公开实施例提供的晶体管单元的泄放电流的能力较强。

Claims (17)

  1. 一种晶体管单元，包括：
    衬底；
    N条栅极，均位于衬底上；所述N条栅极在衬底表面的投影形成封闭的形状；N为大于2的正整数；
    第一源区，位于衬底中且在衬底表面的投影位于所述封闭的形状中；所述第一源区被所述N条栅极共用；
    N个漏区，位于衬底中，所述N个漏区中的每个均和所述第一源区分居所述N条栅极中相应栅极的两侧；
    多个第一源端导电插栓，位于所述第一源区上并与所述第一源区电接触；
    每个所述漏区上设置有多个漏端导电插栓，且所述多个漏端导电插栓与所述漏区电接触；
    第一源端金属层，位于所述第一源端导电插栓上并与所有的所述第一源端导电插栓电接触；
    漏端金属层，位于所述漏端导电插栓上并与所有的所述漏端导电插栓电接触。
  2. 根据权利要求1所述的晶体管单元，其中，所述晶体管单元还包括：N个第二源区、第二源端导电插栓，以及N个第二源端金属层；其中，
    所述N个第二源区位于所述衬底中；所述N个第二源区中的每个在所述衬底表面的投影均位于所述封闭的形状外，且与所述漏区分居相应栅极的两侧；
    每个所述第二源区上设置有多个所述第二源端导电插栓，且所述多个第二源端导电插栓与所述第二源区电接触；
    所述N个第二源端金属层中的每个分别位于N个第二源区中相应第二 源区上，并与相应第二源区上的所有第二源端导电插栓电接触。
  3. 根据权利要求2所述的晶体管单元，其中，所述N为3、4、5或者6。
  4. 根据权利要求3所述的晶体管单元，其中，N＝4。
  5. 根据权利要求4所述的晶体管单元，其中，所述N条栅极在衬底表面的投影形成的封闭形状为正方形。
  6. 根据权利要求2-5任一项所述的晶体管单元，其中，所述N个第二源区的面积之和等于所述第一源区的面积。
  7. 根据权利要求2所述的晶体管单元，其中，
    所述多个第一源端导电插栓沿平行于所述N条栅极中任一栅极的延伸方向相互间隔地对齐排布，构成平行于任一栅极的M个第一源端导电插栓排；
    每个第二源区中的所述多个第二源端导电插栓沿平行于相应栅极方向相互间隔地对齐排布，构成平行于相应栅极的K个第二源端导电插栓排；
    每个漏区中的所述多个漏端导电插栓沿平行于相应栅极方向相互间隔地对齐排布，构成平行于相应栅极的P个漏端导电插栓排；
    其中，M、K、P均为正整数。
  8. 根据权利要求2所述的晶体管单元，其中，所述第一源区上第一源端导电插栓的总数量与所述N个第二源区上第二源端导电插栓的总数量相同。
  9. 根据权利要求2所述的晶体管单元，其中，所述第一源端导电插栓、所述第二源端导电插栓及所述漏端导电插栓的形状、尺寸均相同。
  10. 根据权利要求9所述的晶体管单元，其中，所述第一源端导电插栓、所述第二源端导电插栓及所述漏端导电插栓在衬底表面的正投影均为长条状。
  11. 根据权利要求2所述的晶体管单元，其中，
    所述晶体管还包括多个源端接触，分别位于所述第一源端金属层和所述第二源端金属层上并分别与所述第一源端金属层电接触或所述第二源端金属层电接触；
    所述晶体管还包括漏端接触，位于所述漏端金属层上并与所述漏端金属层电接触。
  12. 根据权利要求11所述的晶体管单元，其中，所述源端接触和所述漏端接触在衬底表面的投影呈点状分布。
  13. 根据权利要求1所述的晶体管单元，其中，所述第一源区在所述衬底所在平面上的正投影覆盖所述第一源端金属层在所述衬底所在平面上正投影；
    漏端金属层在衬底所在平面上的正投影环绕所述第一源端金属层在所述衬底所在平面上正投影。
  14. 根据权利要求1所述的晶体管单元，其中，所述第一源端金属层和所述漏端金属层的几何中心线重合。
  15. 一种晶体管单元阵列，包括多个权利要求1至14中任一项所述的晶体管单元；多个所述晶体管单元呈阵列排布。
  16. 根据权利要求15所述的晶体管单元阵列，其中，两个相邻所述晶体管单元的漏区电连接；两个相邻所述晶体管单元的第二源区电连接。
  17. 一种集成电路，包括权利要求15或16所述的晶体管单元阵列。
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