WO2023074661A1 - 配線基板およびその製造方法 - Google Patents

配線基板およびその製造方法 Download PDF

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Publication number
WO2023074661A1
WO2023074661A1 PCT/JP2022/039641 JP2022039641W WO2023074661A1 WO 2023074661 A1 WO2023074661 A1 WO 2023074661A1 JP 2022039641 W JP2022039641 W JP 2022039641W WO 2023074661 A1 WO2023074661 A1 WO 2023074661A1
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WIPO (PCT)
Prior art keywords
layer
wiring conductor
wiring
recess
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/039641
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English (en)
French (fr)
Japanese (ja)
Inventor
範征 清水
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Kyocera Corp
Original Assignee
Kyocera Corp
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Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2023556450A priority Critical patent/JP7660699B2/ja
Priority to KR1020247012742A priority patent/KR20240056637A/ko
Priority to CN202280070335.3A priority patent/CN118120341A/zh
Priority to US18/703,638 priority patent/US20240422900A1/en
Publication of WO2023074661A1 publication Critical patent/WO2023074661A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/064—Photoresists
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths

Definitions

  • the present invention relates to a wiring board and its manufacturing method.
  • the semi-additive method is a method of forming wiring conductors in the following procedure. First, a thin underlying metal layer is formed on the exposed surface of the insulating layer by electroless plating, sputtering, or the like. Next, a plating resist layer having openings corresponding to the pattern of the wiring conductor is formed on the base metal layer. Next, an electrolytic plated layer is formed on the base metal layer exposed in the opening of the plating resist layer. Next, the plating resist layer is peeled off, and finally, the base metal layer is removed by etching from the portion not covered with the electrolytic plating layer.
  • the miniaturization of wiring conductors is progressing. For example, there is a demand for wiring conductors with a width of 15 ⁇ m or less and a spacing between adjacent wiring conductors of 15 ⁇ m or less.
  • the wiring conductor has a narrow width of, for example, 15 ⁇ m or less, the bonding area between the insulating layer and the wiring conductor through the base metal layer becomes small, and the wiring conductor is easily separated from the insulating layer. Furthermore, electrical insulation reliability is lowered between wiring conductors adjacent to each other.
  • Patent Document 1 a method of forming a wiring conductor composed of an underlying metal layer and an electrolytic plating layer remaining in the groove has been proposed.
  • a groove corresponding to the pattern of the wiring conductor is formed on the surface of the insulating layer to a predetermined depth by laser processing.
  • a thin underlying metal layer is formed on the surface of the insulating layer including the inner wall of the groove by electroless plating, sputtering, or the like.
  • an electrolytic plated layer having a thickness that fills the grooves is formed on the underlying metal layer.
  • the underlying metal layer and the electroplated layer on the insulating layer are removed by chemical mechanical polishing.
  • grooves for wiring conductors with a relatively narrow width are satisfactorily filled with the electrolytic plating layer.
  • wiring conductor grooves having a relatively wide width are difficult to fill satisfactorily with an electrolytic plating layer.
  • the upper surface of the wiring conductor is greatly recessed, resulting in poor flatness. If the thickness of the electroplated layer is further increased to eliminate the recess, the stress generated during the formation of the electroplated layer increases. Therefore, a large stress acts on the inner wall of the groove for the wide wiring conductor through the base metal layer, and the wide wiring conductor is easily peeled off.
  • a wiring board includes an insulating layer, a groove located on the top surface of the insulating layer, a recess located on the top surface of the insulating layer and having a width wider than the groove, an inner surface of the groove, and a base located on the inner surface of the recess. a metal layer, a first wiring conductor positioned on the base metal layer to fill the trench, and a second wiring conductor positioned on the base metal layer to fill the recess and having a width wider than that of the first wiring conductor. and wiring conductors.
  • the second wiring conductor has a first portion and a second portion integrally positioned adjacent to the first portion. A plurality of voids are located at the boundary of the first portion and the second portion.
  • a method for manufacturing a wiring board according to the present disclosure includes a step of forming a groove and a recess having a wider width than the groove on an upper surface of an insulating layer; forming at least one plating resist having a width narrower than the width of the recess on the underlying metal layer in the recess; and a first electroplating layer on the underlying metal layer exposed from the plating resist.
  • a step of removing the plating resist from the base metal layer a step of forming a second electroplated layer on the first electroplated layer and on the base metal layer; a first electroplated layer, a second A first wiring made of a first electroplated metal derived from the first electroplated layer or a second electroplated metal derived from the second electroplated layer filling the groove by removing a portion of the electroplated layer and the underlying metal layer.
  • a second wiring conductor consisting of a conductor and a first electroplated metal filling the recess and a second electroplated metal derived from the second electroplated layer.
  • FIG. 1 is an explanatory diagram showing a cross section of a wiring board according to an embodiment of the present disclosure
  • FIG. 2 is an electron micrograph of region X shown in FIG. 1
  • FIG. 4 is an explanatory diagram showing steps of manufacturing the first wiring conductor and the second wiring conductor in the wiring board manufacturing method according to the embodiment of the present disclosure
  • FIG. 4 is an explanatory diagram showing steps of manufacturing the first wiring conductor and the second wiring conductor in the wiring board manufacturing method according to the embodiment of the present disclosure
  • FIG. 4 is an explanatory diagram showing steps of manufacturing the first wiring conductor and the second wiring conductor in the wiring board manufacturing method according to the embodiment of the present disclosure
  • FIG. 4 is an explanatory diagram showing steps of manufacturing the first wiring conductor and the second wiring conductor in the wiring board manufacturing method according to the embodiment of the present disclosure
  • FIG. 4 is an explanatory diagram showing steps of manufacturing the first wiring conductor and the second wiring conductor in the wiring board manufacturing method according to the embodiment of the present disclosure
  • FIG. 4 is an explanatory diagram showing steps of manufacturing the first wiring conductor and the second wiring conductor in the wiring board manufacturing method according to the embodiment of the present disclosure
  • FIG. 4 is an explanatory diagram showing steps of manufacturing the first wiring conductor and the second wiring conductor in the wiring board manufacturing method according to the embodiment of the present disclosure
  • FIG. 4 is an explanatory diagram showing steps of manufacturing the first wiring conductor and the second wiring conductor in the wiring board manufacturing method according to the embodiment of the present disclosure
  • FIG. 4 is an explanatory diagram showing steps of manufacturing the first wiring conductor and the second wiring conductor in the wiring board manufacturing method according to the embodiment of the present disclosure
  • FIG. 4 is an explanatory diagram showing steps of manufacturing the first wiring conductor and the second wiring conductor in the wiring board manufacturing method according to the embodiment of the present disclosure
  • FIG. 4 is an explanatory diagram showing steps of manufacturing the first wiring conductor and the second wiring conductor in the wiring board manufacturing method according to the embodiment of the present disclosure
  • FIG. 4 is an explanatory diagram showing steps of manufacturing the first wiring conductor and the second wiring conductor in the wiring board manufacturing method according to the embodiment of the present disclosure
  • the wide second wiring conductor has the first portion and the second portion that is integrally positioned adjacent to the first portion, and the first portion and A plurality of voids are located at the boundary of the second portion. Therefore, the stress generated between the second wiring conductor and the insulating layer and the stress generated within the second wiring conductor are dispersed and relaxed at the boundary between the first portion and the second portion where the gap is located. . As a result, the wiring board according to the present disclosure can reduce peeling of the second wiring conductor.
  • the stresses generated during the formation of the first electroplated layer and the second electroplated layer are dispersed by the above steps.
  • the method for manufacturing a wiring board according to the present disclosure it is possible to obtain a wiring board in which peeling of the second wiring conductor formed in the recess is reduced.
  • FIG. 1 is an explanatory diagram showing a cross section of a wiring board according to an embodiment of the present disclosure.
  • a wiring board 10 according to one embodiment includes insulating layers 1 ( 11 , 12 ), first wiring conductors 5 and second wiring conductors 6 .
  • the insulating layer 1 (11) corresponds to the core insulating layer 11
  • the insulating layer 1 (12) corresponds to the buildup insulating layer 12.
  • FIG. 1 In the wiring board 10 according to one embodiment, a form in which the first wiring conductor 5 and the second wiring conductor 6 are included in the build-up insulating layer 12 will be described.
  • the core insulating layer 11 is made of resin such as epoxy resin, bismaleimide-triazine resin, polyimide resin, polyphenylene ether resin, and liquid crystal polymer. These resins may be used alone or in combination of two or more.
  • the core insulating layer 11 may contain a reinforcing material such as glass cloth, and further may have insulating particles dispersed therein.
  • the insulating particles are not limited, and examples thereof include inorganic insulating fillers such as silica, alumina, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide.
  • the thickness of the core insulating layer 11 is not limited, and the thickness of the core insulating layer is, for example, 0.1 mm or more and 2.0 mm or less.
  • the core insulating layer 11 has through-hole conductors 11 a for electrically connecting the conductor layers 11 b on the upper and lower surfaces of the core insulating layer 11 .
  • the through-hole conductors 11a are located in through-holes penetrating through the upper and lower surfaces of the insulating layer 11 for core.
  • the through-hole conductor 11a is made of a conductor plated with a metal such as copper plating.
  • Through-hole conductors 11a are connected to conductor layers 11b on both sides of insulating layer 11 for core.
  • the through-hole conductor 11a may be formed only on the inner wall surface of the through-hole, or may be filled in the through-hole.
  • the build-up insulating layer 12 is also made of resin such as epoxy resin, bismaleimide-triazine resin, polyimide resin, polyphenylene ether resin, liquid crystal polymer. These resins may be used alone or in combination of two or more.
  • the core insulating layer 11 and the buildup insulating layer 12 may be made of the same resin or may be made of different resins.
  • the build-up insulating layer 12 may contain a reinforcing material such as glass cloth, and further may have insulating particles dispersed therein.
  • the insulating particles are not limited, and examples thereof include inorganic insulating fillers such as silica, alumina, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide.
  • the thickness of the build-up insulating layer 12 is not limited, and is, for example, 10 ⁇ m or more and 50 ⁇ m or less.
  • the buildup insulating layer 12 has via-hole conductors 12a for electrically connecting the conductor layers located on the upper and lower surfaces of the buildup insulating layer 12. As shown in FIG. The via-hole conductors 12a are located in via-holes penetrating the top and bottom surfaces of the buildup insulating layer 12 . The via-hole conductors 12a are formed at the same time as the first wiring conductors 5 and the second wiring conductors 6 are formed, for example. The via-hole conductor 12a may be formed only on the inner wall surface of the via-hole, or may be filled in the via-hole.
  • a groove 2 and a recess 3 are located on the upper surface of the build-up insulating layer 12 .
  • a base metal layer 4 is positioned on the inner surfaces of the grooves 2 and the recesses 3 .
  • the base metal layer 4 is a base portion of the first wiring conductor 5 and the second wiring conductor 6 .
  • the underlying metal layer 4 is made of metal such as copper.
  • the base metal layer 4 has a thickness of, for example, 0.1 ⁇ m or more and 0.5 ⁇ m or less. The presence of the base metal layer 4 improves the adherence of the first wiring conductor 5 and the second wiring conductor 6 .
  • the groove 2 is filled with the first wiring conductor 5 .
  • the width of the first wiring conductor 5 is relatively narrow, and may be, for example, 15 ⁇ m or less. Such a first wiring conductor 5 functions, for example, as a signal wiring conductor.
  • the width of the groove 2 is appropriately set according to the width of the first wiring conductor 5 .
  • the depth of the groove 2 is not limited as long as it does not penetrate the buildup insulating layer 12 .
  • the depth of the groove 2 is preferably 10% or more and 50% or less of the thickness of the buildup insulating layer 12, for example.
  • the fact that the groove 2 is filled with the first wiring conductor means, for example, a gap in the groove 2 due to entrainment of air during manufacturing, a gap due to non-adherence of the underlying metal layer 4 or the first wiring conductor to the narrow portion, and the like. including when there is
  • the arithmetic mean roughness Ra of the inner surface of the groove 2 is not limited, and may be, for example, 50 nm or more and 100 nm or less.
  • the arithmetic mean roughness Ra of the inner surface of the groove 2 is 50 nm or more and 100 nm or less, the base metal layer 4 is adhered more firmly, and peeling of the base metal layer 4 can be further reduced.
  • the arithmetic mean roughness Ra of the surface of the base metal layer 4 located in the groove 2 is not limited, and may be, for example, 50 nm or more and 100 nm or less.
  • the first wiring conductor 5 is firmly adhered to the base metal layer 4 and the first wiring conductor 5 can be further reduced from peeling off.
  • the first wiring conductor 5 may have a surface roughness with an arithmetic mean roughness Ra of 50 nm or more and 100 nm or less corresponding to the arithmetic mean roughness Ra of the surface of the base metal layer 4 . This roughness is smaller than the side surface roughness of the second wiring conductor 6, and transmission loss can be further reduced when a high-frequency signal is transmitted to the first wiring conductor 5.
  • the recess 3 has a wider width than the groove 2.
  • the recess 3 is filled with a second wiring conductor 6 .
  • the width of the second wiring conductor 6 is wider than the width of the first wiring conductor 5, and may be, for example, 150 ⁇ m or more.
  • Such a second wiring conductor 6 functions, for example, as a ground conductor layer.
  • the width of the recess 3 is appropriately set according to the width of the second wiring conductor 6 .
  • the depth of the recess 3 is not limited as long as it does not penetrate the buildup insulating layer 12 .
  • the depth of the concave portion 3 is preferably 10% or more and 50% or less of the thickness of the buildup insulating layer 12, for example.
  • the recess 3 is filled with the second wiring conductor means, for example, a gap in the recess 3 due to entrainment of air during manufacturing, a gap due to non-adherence of the underlying metal layer 4 or the second wiring conductor to the narrow portion, and the like. including when there is
  • the second wiring conductor 6 includes a first portion 61 and a second portion 62, the second portion 62 being adjacent to the first portion 61 and integrally positioned.
  • the first portion 61 is made of, for example, a first electroplating metal, such as copper.
  • the second portion 62 is made of, for example, a second electroplating metal, such as copper. Even if the first portion 61 and the second portion 62 are made of the same metal (for example, copper), they are treated as separate portions in this specification.
  • FIG. 1 a boundary 63 between the first portion 61 and the second portion 62 is shown for convenience. As shown, a plurality of voids 64 are located at the boundary 63 portion. A gap 64 separates the first portion 61 and the second portion 62 .
  • FIG. 2 is an electron micrograph of region X shown in FIG.
  • the second wiring conductor 6 has a first portion 61 and a second portion 62, and a plurality of gaps 64 are positioned at the boundary 63 between the first portion 61 and the second portion 62.
  • the stress generated between the second wiring conductor 6 and the insulating layer 1 and the stress generated in the second wiring conductor 6 are applied to the boundary 63 between the first portion 61 and the second portion 62 where the gap 64 is located. is dispersion-relaxed at As a result, the wiring board according to the embodiment can reduce peeling of the second wiring conductors 6 .
  • the size of the void 64 is not limited, and for example, the maximum length may be 50 nm or more and 1 ⁇ m or less. As used herein, the term “maximum length” means the length of the longest linear distance between the peripheral edges of the gap 64 . If the maximum length of the air gap 64 is 50 nm or more and 1 ⁇ m or less, the stress can be sufficiently dispersed and relaxed without affecting the bonding strength between the first portion 61 and the second portion 62 .
  • At least a portion of the first portion 61 and the second portion 62 located across the boundary 63 contains continuous crystals.
  • a continuous crystal means that the crystal orientations of the first electroplated metal forming the first portion 61 and the second electroplating metal forming the second portion are aligned across the boundary 63 .
  • the arithmetic mean roughness Ra of the inner surface of the recess 3 is not limited, and may be, for example, 50 nm or more and 100 nm or less. If the arithmetic mean roughness Ra of the inner surface of the concave portion 3 is 50 nm or more and 100 nm or less, the underlying metal layer 4 is more firmly adhered to the concave portion 3 and peeling of the underlying metal layer 4 can be further reduced.
  • the arithmetic mean roughness Ra of the surface of the underlying metal layer 4 located in the concave portion 3 is not limited, and may be, for example, 50 nm or more and 100 nm or less. If the arithmetic mean roughness Ra of the surface of the base metal layer 4 located in the recess 3 is 50 nm or more and 100 nm or less, the second wiring conductor 6 is firmly adhered to the base metal layer 4 and the second wiring conductor 6 can be further reduced from peeling off.
  • the second wiring conductor 6 may have a surface roughness with an arithmetic mean roughness Ra of 50 nm or more and 100 nm or less corresponding to the arithmetic mean roughness Ra of the surface of the base metal layer 4 .
  • the wiring board 10 may have the solder resist 7 positioned on the outermost layer.
  • the solder resist 7 is made of, for example, acrylic-modified epoxy resin.
  • the solder resist 7 has a function of protecting the conductor layers (the first wiring conductor 5 and the second wiring conductor 6) from solder, for example, when mounting an electronic component or connecting to a motherboard. .
  • An opening is formed in the solder resist 7 to expose a part of the first wiring conductor 5 or the second wiring conductor 6 positioned directly below. A part of the first wiring conductor 5 or the second wiring conductor 6 exposed from the opening functions as a pad when a semiconductor element or the like is mounted.
  • FIGS. 3 to 12 are explanatory diagrams showing steps of manufacturing the first wiring conductor and the second wiring conductor in the wiring board manufacturing method according to the embodiment of the present disclosure.
  • a wiring board manufacturing method according to the present disclosure includes the following steps (a) to (g).
  • an insulating layer 1 (core insulating layer 11) is prepared.
  • a conductor layer 11b is formed on the upper surface of the insulating layer 11 for core, and a through-hole conductor 11a is formed in the insulating layer 11 for core.
  • the through-hole conductor 11a is connected to part of the conductor layer 11b formed on the upper surface of the insulating layer 11 for core.
  • the core insulating layer 11, the through-hole conductor 11a, and the conductor layer 11b are as described above, and detailed description thereof will be omitted.
  • the drawing shown on the lower side in FIG. 3 is a cross-sectional view taken along the line AA shown in the drawing shown on the upper side. 4 to 12 below are cross-sectional views taken along line AA shown in the upper drawings.
  • the insulating layer 1 (build-up insulating layer 12) is laminated so as to cover the core insulating layer 11 and the conductor layer 11b.
  • the build-up insulating layer 12 is as described above, and detailed description thereof will be omitted.
  • a groove 2 and a recess 3 having a wider width than the groove 2 are formed on the upper surface of the insulating layer 1 (buildup insulating layer 12) (step (a)).
  • the grooves 2 may be formed at positions where the first wiring conductors 5 are formed.
  • the method of forming the grooves 2 is not limited, and they are formed by laser processing such as excimer laser, CO 2 laser, UV-YAG laser. An excimer laser is preferable because it facilitates the formation of grooves 2 of uniform depth. The depth of the groove 2 is as described above, and detailed description is omitted.
  • the arithmetic mean roughness Ra of the inner surface of the groove 2 is not limited. If necessary, the inner surface of the groove 2 may be roughened so that the arithmetic mean roughness Ra of the inner surface of the groove 2 is, for example, 50 nm or more and 100 nm or less. The detailed description is as described above, and will be omitted.
  • the recess 3 may be formed at a position where the second wiring conductor 6 is to be formed.
  • the method for forming the concave portion 3 is not limited, and is formed by laser processing such as an excimer laser, CO 2 laser, UV-YAG laser, or the like. It is preferable to employ an excimer laser because the concave portions 3 having a uniform depth can be easily formed.
  • the depth of the concave portion 3 is as described above, and detailed description is omitted.
  • the arithmetic mean roughness Ra of the inner surface of the recess 3 is not limited. If necessary, the inner surface of the recess 3 may be roughened so that the arithmetic mean roughness Ra of the inner surface of the recess 3 is, for example, 50 nm or more and 100 nm or less. The detailed description is as described above, and will be omitted.
  • via holes 12a' are formed in the buildup insulating layer 12.
  • the via hole 12a' is formed by laser processing such as excimer laser, CO 2 laser, UV-YAG laser.
  • a base metal layer 4 is formed on the upper surface of the insulating layer 1, the inner surfaces of the grooves 2, and the inner surfaces of the recesses 3 (step (b)).
  • the underlying metal layer 4 is formed, for example, by depositing a metal such as copper by electroless plating. Palladium may be used as a catalyst during electroless plating.
  • the base metal layer 4 has a thickness of, for example, 0.1 ⁇ m or more and 0.5 ⁇ m or less.
  • the arithmetic mean roughness Ra of the surface of the base metal layer 4 located in the groove 2 is not limited. If necessary, the surface of the underlying metal layer 4 located in the grooves 2 is roughened so that the arithmetic mean roughness Ra of the surface of the underlying metal layer 4 located in the grooves 2 is, for example, 50 nm to 100 nm. The following may be used. The detailed description is as described above, and will be omitted.
  • the arithmetic mean roughness Ra of the surface of the base metal layer 4 located in the recess 3 is not limited. If necessary, the surface of the underlying metal layer 4 located in the recess 3 is roughened so that the arithmetic mean roughness Ra of the surface of the underlying metal layer 4 located in the recess 3 is, for example, 50 nm or more and 100 nm. The following may be used. The detailed description is as described above, and will be omitted.
  • At least one plating resist 8 having a width W narrower than the width of the recess 3 is formed on the base metal layer 4 in the recess 3 (step (c)).
  • the width W of the plating resist 8 is not limited as long as it is narrower than the width of the recess 3, and may be, for example, 50 ⁇ m or more and 100 ⁇ m or less. As long as the plating resist 8 having a width W narrower than the width of the recess 3 is formed in the recess 3, the plating resist 8 may be formed so as to cover other portions such as the groove 2, for example. .
  • the plating resist 8 is made of, for example, resin such as acrylic resin or methacrylic resin.
  • a first electroplating layer P1 is formed on the base metal layer 4 exposed from the plating resist 8 (step (d)).
  • the first electrolytic plated layer P1 is formed, for example, by depositing a metal such as copper by electrolytic plating.
  • the plating resist 8 is removed from the base metal layer 4 (step (e)).
  • the base metal layer 4 is exposed in the concave portion 3 except for the portion where the first electrolytic plated layer P1 is located.
  • a second electroplated layer P2 is formed on the first electroplated layer P1 and on the underlying metal layer 4 (step (f)). Specifically, on the first electrolytic plated layer P1 formed in the recess 3, the second electrolytic plating is performed on the portion where the base metal layer 4 is exposed by removing the plating resist 8 in the groove 2 and the recess 3. Form layer P2.
  • the second electrolytic plated layer P2 is formed, for example, by depositing a metal such as copper by electrolytic plating.
  • the second electrolytic plated layer P2 is formed, for example, so that the concave portions 3 are filled with a metal such as copper.
  • the first electrolytic plated layer P1, the second electrolytic plated layer P2, and part of the base metal layer 4 are removed, and the second electrolytic plated layer P2 derived from the second electrolytic plated layer P2 filling the grooves 2 is removed.
  • a first wiring conductor 5 made of an electrolytic plated metal, and a second wiring conductor 5 made of a first electrolytic plated metal derived from the first electrolytic plated layer P1 filling the recess 3 and a second electrolytic plated metal derived from the second electrolytic plated layer P2. 2 wiring conductors 6 are formed (step (g)).
  • the first electroplated metal corresponds to the first portion 61 and the second electroplated metal corresponds to the second portion 62 .
  • the first portion 61 and the second portion 62 are clearly distinguished for convenience. However, in reality, there is no clear boundary between the first portion 61 and the second portion 62 as described above, and a plurality of gaps 64 are located at the boundary 63 as shown in FIG. ing. A gap 64 separates the first portion 61 and the second portion 62 .
  • the first wiring conductor 5 and the second wiring conductor 6 are formed on the insulating layer 1 such as the core insulating layer and the buildup insulating layer, and the wiring board according to the present disclosure is obtained.
  • the insulating layer 1 is a build-up insulating layer
  • the steps (a) to (g) are repeated to form a desired number of build-up layers.
  • the solder resist 7 may be located on the outermost layer. The solder resist 7 is as described above, and detailed description is omitted.
  • the plating resist 8 is formed on the base metal layer 4 in the recess 3 so as to form a lattice when viewed from above.
  • the plating resist 8 formed on the underlying metal layer 4 in the recesses 3 is not limited to a grid pattern.
  • the plating resist may be formed on the underlying metal layer in the recesses so that when viewed from above, the recesses are hollowed out in a circular shape instead of a square shape.
  • the plating resist By forming the plating resist so as to hollow out in a circular shape in this manner, the second wiring conductor 6a having the first portion 61a and the second portion 62a as shown in FIG. 13 is formed.
  • the plating resist when viewed from the top, may remain in the rectangular or circular cut-out portions and may have a structure in which the plating resist does not exist in the lattice portions (so-called sea-island structure). .
  • sea-island structure When the plating resist exists in a sea-island structure, the first portions 61, 61a and the second portions 62, 62a of the second wiring conductors 6, 6a are reversed in FIGS.
  • the plating resist does not need to intersect vertically and horizontally when viewed from above, and may be linear.
  • the second wiring conductor 6b having the first portion 61b and the second portion 62b as shown in FIG. 14 is formed.
  • the plating resist formed on the base metal layer in the recesses may have a polygonal line shape such as a mountain shape, or a curved shape such as a wave shape when viewed from the top, in addition to the linear shape.
  • the second wiring conductor 6c having the first portion 61c and the second portion 62c as shown in FIG. 15 is formed.
  • the second wiring conductor 6d having the first portion 61d and the second portion 62d as shown in FIG. 16 is formed.
  • the plating resist 8 is also formed in portions other than the recesses 3 in the above-described embodiment. Specifically, in FIG. 8, plating resist 8 is also formed to cover groove 2 . However, the plating resist 8 may be formed only in the concave portion 3 . In this case, the trench is filled with the first electroplated layer, and the first wiring conductor is formed of the first electroplated metal derived from the first electroplated layer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Structure Of Printed Boards (AREA)
PCT/JP2022/039641 2021-10-28 2022-10-25 配線基板およびその製造方法 Ceased WO2023074661A1 (ja)

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JP2023556450A JP7660699B2 (ja) 2021-10-28 2022-10-25 配線基板およびその製造方法
KR1020247012742A KR20240056637A (ko) 2021-10-28 2022-10-25 배선 기판 및 그 제조 방법
CN202280070335.3A CN118120341A (zh) 2021-10-28 2022-10-25 布线基板以及其制造方法
US18/703,638 US20240422900A1 (en) 2021-10-28 2022-10-25 Wiring board and manufacturing method for the same

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JP2021-176324 2021-10-28

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JP2001060589A (ja) * 1999-08-20 2001-03-06 Matsushita Electronics Industry Corp 半導体装置の製造方法

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JP2004149926A (ja) 2003-11-20 2004-05-27 Matsushita Electric Ind Co Ltd 埋め込み配線の形成方法
JP2005183452A (ja) 2003-12-16 2005-07-07 Fujikura Ltd 端子部の接合構造及び接合方法
JP4395388B2 (ja) 2004-02-20 2010-01-06 京セラ株式会社 配線基板およびその製造方法
JP6819599B2 (ja) * 2015-09-25 2021-01-27 大日本印刷株式会社 実装部品、配線基板、電子装置、およびその製造方法
JP6783614B2 (ja) * 2016-10-11 2020-11-11 株式会社ディスコ 配線基板の製造方法
JP7063101B2 (ja) 2018-05-11 2022-05-09 住友電気工業株式会社 プリント配線板及びプリント配線板の製造方法
CN112586098B (zh) * 2018-09-28 2021-09-21 三井金属矿业株式会社 多层布线板的制造方法

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JP2001060589A (ja) * 1999-08-20 2001-03-06 Matsushita Electronics Industry Corp 半導体装置の製造方法

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TW202333542A (zh) 2023-08-16
KR20240056637A (ko) 2024-04-30

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