WO2023065160A1 - 内埋电路板及其制作方法 - Google Patents

内埋电路板及其制作方法 Download PDF

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Publication number
WO2023065160A1
WO2023065160A1 PCT/CN2021/125048 CN2021125048W WO2023065160A1 WO 2023065160 A1 WO2023065160 A1 WO 2023065160A1 CN 2021125048 W CN2021125048 W CN 2021125048W WO 2023065160 A1 WO2023065160 A1 WO 2023065160A1
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WO
WIPO (PCT)
Prior art keywords
layer
groove
electronic component
circuit substrate
base layer
Prior art date
Application number
PCT/CN2021/125048
Other languages
English (en)
French (fr)
Inventor
钞兰婷
陈盈儒
焦政亭
Original Assignee
庆鼎精密电子（淮安）有限公司
鹏鼎控股(深圳)股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 庆鼎精密电子（淮安）有限公司, 鹏鼎控股(深圳)股份有限公司 filed Critical 庆鼎精密电子（淮安）有限公司
Priority to CN202180077586.XA priority Critical patent/CN116529878A/zh
Priority to PCT/CN2021/125048 priority patent/WO2023065160A1/zh
Priority to TW110139956A priority patent/TWI772212B/zh
Publication of WO2023065160A1 publication Critical patent/WO2023065160A1/zh
Priority to US18/200,785 priority patent/US20230292446A1/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/301—Assembling printed circuits with electric components, e.g. with resistor by means of a mounting structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0165—Holder for holding a Printed Circuit Board [PCB] during processing, e.g. during screen printing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469—Circuit made after mounting or encapsulation of the components

Definitions

  • the present application relates to the technical field of circuit boards, in particular to an embedded circuit board and a manufacturing method thereof.
  • circuit boards occupy a large space of electronic products, so the volume of circuit boards affects the volume of electronic products to a large extent.
  • electronic components such as resistors, capacitors, etc.
  • the interior of the circuit substrate is conducive to reducing the overall thickness of the circuit board, thereby reducing the thickness of electronic products.
  • the usual method of embedding electronic components is as follows: first, an inner circuit substrate is fabricated, and a groove is formed on the inner circuit substrate; then, the electronic component is placed in the groove, and then build-up is performed.
  • the electronic components are prone to irregular deviation, which increases the difficulty of precise alignment between the subsequent formation of blind holes and soldering terminals.
  • the first aspect of the present application provides a method for manufacturing an embedded circuit board, comprising the following steps:
  • the inner layer circuit substrate comprising a first surface and a second surface oppositely disposed
  • the through groove penetrates through the first surface and the second surface
  • the electronic component module includes a body, at least one electronic component, a first adhesive layer and a second adhesive layer, the body is provided with a groove, the at least one electronic component passes through the first The adhesive layer is fixed on the bottom wall of the groove, and the second adhesive layer is filled in the groove and covers the at least one electronic component together with the first adhesive layer;
  • first conductive circuit layer on the surface of the first base layer away from the first surface to obtain a first circuit substrate
  • second conductive circuit layer on the surface of the second base layer away from the second surface to obtain the second circuit substrate
  • the second aspect of the present application provides an embedded circuit board, including an inner circuit substrate, an electronic component module, a first circuit substrate, and a second circuit substrate, and the inner circuit substrate includes a first surface and a second surface oppositely arranged.
  • the surface is provided with a through groove penetrating the first surface and the second surface, the electronic component module is accommodated in the through groove, and the electronic component module includes a body, at least one electronic component, a first An adhesive layer and a second adhesive layer, the body is provided with a groove, the at least one electronic component is fixed on the bottom wall of the groove through the first adhesive layer, and the second adhesive layer is filled in the and cover the at least one electronic component together with the first adhesive layer, the first circuit substrate includes a first base layer and a first conductive circuit layer stacked, and the second circuit substrate includes a stacked A second base layer and a second conductive circuit layer are provided, the first base layer covers the first surface, the second base layer covers the second surface, and the first base layer and the second base layer fill the The through groove
  • the electronic component module is pre-adhesively positioned on the carrier board, which reduces the flow of dielectric materials caused by the subsequent pressing process of the base layer. Offset risk; and the electronic component is pre-fixed in the groove through the first glue layer, further reducing the offset risk caused by glue flow in the subsequent glue filling process.
  • the process flow can be simplified by integrating multiple electronic components into the electronic component module.
  • FIG. 1 is a schematic cross-sectional view of an inner circuit substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional view after opening a through groove on the inner circuit substrate shown in FIG. 1 .
  • FIG. 3 is a schematic cross-sectional view after attaching a carrier board to one surface of the inner circuit substrate shown in FIG. 1 .
  • Fig. 4 is a top view of an insulating board provided by an embodiment of the present application.
  • FIG. 5 is a schematic cross-sectional view of the body of the insulating board shown in FIG. 4 .
  • FIG. 6 is a schematic cross-sectional view of a groove formed on the body shown in FIG. 5 .
  • FIG. 7 is a schematic cross-sectional view after the electronic component is accommodated in the groove shown in FIG. 6 .
  • Fig. 8 is a schematic cross-sectional view after filling the groove shown in Fig. 7 with glue.
  • FIG. 9 is a schematic cross-sectional view after separating the insulation board shown in FIG. 8 to obtain a plurality of electronic component modules.
  • Fig. 10 is a schematic cross-sectional view of placing the electronic component module shown in Fig. 8 in the through groove shown in Fig. 3 .
  • FIG. 11 is a schematic cross-sectional view of the side of the inner layer circuit substrate shown in FIG. 10 away from the carrier board after lamination of the first base layer.
  • FIG. 12 is a schematic cross-sectional view after removing the bearing plate shown in FIG. 11 .
  • FIG. 13 is a schematic cross-sectional view of the inner layer circuit substrate shown in FIG. 12 after lamination of the second base layer on the side away from the first base layer.
  • FIG. 14 is a schematic cross-sectional view of blind holes formed on the structure shown in FIG. 13 .
  • FIG. 15 is a schematic cross-sectional view after the first conductive structure is formed in the blind hole shown in FIG. 14 .
  • FIG. 16 is a schematic cross-sectional view of a first conductive circuit layer and a second conductive circuit layer respectively formed on the first base layer and the second base layer shown in FIG. 15 .
  • FIG. 17 is a schematic cross-sectional view of a third circuit substrate and a fourth circuit substrate respectively formed on the first conductive circuit layer and the second conductive circuit layer shown in FIG. 16 .
  • the first adhesive layer 32 is the first adhesive layer 32
  • the first circuit substrate 40 is the first circuit substrate 40
  • An embodiment of the present application provides a method for manufacturing an embedded circuit board, which includes the following steps.
  • Step S1 please refer to FIG. 1, providing an inner layer circuit substrate 10.
  • the inner layer circuit substrate 10 includes a first surface 11 and a second surface 12 oppositely disposed.
  • the inner layer circuit substrate 10 is a circuit board formed with conductive lines.
  • the inner circuit substrate 10 includes at least one conductive circuit layer and at least one dielectric layer. Each dielectric layer is arranged between two adjacent conductive circuit layers. A first conductive structure is formed in each dielectric layer, and two adjacent conductive circuit layers are electrically connected to each other through the first conductive structure.
  • the material of the dielectric layer can be a rigid insulating material, such as FR-4 grade polyimide, polypropylene, liquid crystal polymer, polyether ether ketone, polyethylene terephthalate and polyethylene naphthalene One of ethylene glycol formate, etc.
  • the material of the dielectric layer can also be a flexible insulating material, such as polyimide, polypropylene, liquid crystal polymer, polyether ether ketone, polyethylene terephthalate and polyethylene naphthalate One of esters, etc.
  • the material of the conductive circuit layer may include but not limited to copper, gold, silver and the like.
  • the manufacturing method of the inner layer circuit substrate 10 may adopt the manufacturing method of the circuit board in the prior art.
  • the core substrate is manufactured first, and then the build-up is performed on both sides of the core substrate by means of build-up, so as to obtain the inner circuit substrate.
  • Step S2 please refer to FIG. 2 , forming a through groove 101 on the inner circuit substrate 10 .
  • the through groove 101 passes through the first surface 11 and the second surface 12 .
  • the through groove 101 can be formed by mechanical drilling or laser drilling.
  • Step S3 please refer to FIG. 3 , attaching a carrier board 20 on the second surface 12 of the inner circuit substrate 10 to seal one end of the through groove 101 .
  • the surface of the carrier board 20 in contact with the inner circuit substrate 10 is provided with an adhesive layer for adhering components to be embedded.
  • the carrier board 20 is an adhesive tape, and the adhesive tape is bonded to the surface of the inner circuit substrate 10 and covers one end of the through groove 101 .
  • Step S4 please refer to FIG. 4 and FIG. 5 , providing an insulating board 31 .
  • the insulating board 31 includes a plurality of bodies 311 arranged in a matrix. A plurality of bodies 311 are connected to each other to form the insulating board 31 .
  • the material of the body 311 has the properties of heat-resistant pressing and laser ablation.
  • the material of the body 311 can be, but not limited to, dielectric materials commonly used in the field, such as polyimide, epoxy resin, and the like.
  • Step S5 please refer to FIG. 6 , forming a groove 301 on each body 311 , and forming a first adhesive layer 32 at the bottom of the groove 301 .
  • the groove 301 runs through a surface of the body 311 .
  • the groove 301 can be formed by mechanical drilling or laser drilling.
  • the first adhesive layer 32 can be formed on the bottom wall of the groove 301 by but not limited to printing, coating or dispensing. In this embodiment, the first adhesive layer 32 completely covers the bottom wall of the groove 301 .
  • Step S6 please refer to FIG. 7 , install at least one electronic component 33 on the first adhesive layer 32 located in the groove 301 .
  • the at least one electronic component 33 is placed on the first adhesive layer 32 and bonded to the first adhesive layer 32 to position the at least one electronic component 33 .
  • the at least one electronic component 33 includes at least one of an active component and a passive component.
  • one active component and two passive components are accommodated in the groove 301 . It can be understood that the number of active components and passive components accommodated in the groove 301 can be adjusted according to actual needs.
  • Step S7 please refer to FIG. 8 , fill the groove 301 with glue to form the second glue layer 35 , and obtain the electronic component module 30 .
  • the second adhesive layer 35 covers the exposed surface of the electronic component 33 exposed to the first adhesive layer 32 and is connected to the first adhesive layer 32 .
  • the second adhesive layer 35 and the first adhesive layer 32 jointly cover the electronic component 33, so that the electronic component 33 is embedded in the second adhesive layer 35 and the first adhesive layer 32 to jointly form in the glue layer.
  • the surface of the second adhesive layer 35 exposed outside the groove 301 is flush with the surface of the body 311 provided with the groove 301 , that is, the second adhesive layer 35 and the body 311 have no The contour level of the step difference.
  • the material of the first adhesive layer 32 and the second adhesive layer 35 can be, but not limited to, room temperature curing adhesive.
  • Step S8 please refer to FIG. 9 , separate the plurality of electronic component modules 30 along the boundary lines between the plurality of bodies 311 .
  • the plurality of electronic component modules 30 can be separated by mechanical cutting or laser cutting.
  • Step S9 please refer to FIG. 10 , place the electronic component module 30 in the through groove 101 .
  • the electronic component module 30 is supported on the carrier board 20 and bonded to the carrier board 20 to position the electronic component module 30 .
  • the electronic component module 30 is turned upside down and placed in the through groove 101, so that the adhesive layer of the electronic component module 30 is bonded to the carrier plate 20, so as to improve the electronic component module. Adhesion firmness of the group 30 and the carrier board 20 .
  • the height of the electronic component module 30 is equal to the depth of the through groove 101 .
  • Step S10 press-bond the first base layer 41 on the first surface 11 of the inner circuit substrate 10 .
  • the first base layer 41 covers the first surface 11 of the inner circuit substrate 10 and the exposed surface of the electronic component module 30 , and fills the gap between the electronic component module 30 and the sidewall of the through groove 101 the gap between.
  • the material of the first base layer 41 can be a common dielectric material in the field, such as polyimide, epoxy resin and the like.
  • step S11 please refer to FIG. 12 , removing the carrier plate 20 to expose the second surface 12 of the inner circuit substrate 10 .
  • the carrying plate 20 can be removed by tearing off or the like.
  • Step S12 please refer to FIG. 13 , press-bond the second base layer 51 on the second surface 12 of the inner circuit substrate 10 .
  • the second base layer 51 covers the second surface 12 of the inner circuit substrate 10 and the surface of the electronic component module 30 exposed outside the first base layer 41 , and is connected to the first base layer 41 .
  • the first base layer 41 and the second base layer 51 cover the electronic component module 30 together, so that the electronic component module 30 is embedded in the first base layer 41 and the second base layer 51 to form a joint in the grassroots.
  • the material of the second base layer 51 can be a common dielectric material in the field, such as polyimide, epoxy resin and the like.
  • Step S13 please refer to FIG. 14 , forming a blind hole 110 exposing the soldering terminal of the electronic component 33 .
  • the position and quantity of the blind holes 110 can be adaptively changed according to the type and quantity of the electronic components 33 , which are not limited in this application.
  • a plurality of blind holes 110 corresponding to a plurality of electronic components 33 are formed, wherein some blind holes 110 pass through the second base layer 51 and the second adhesive layer 35, and the other part of blind holes 110 pass through the The first base layer 41 , the body 311 and the first adhesive layer 32 .
  • the blind hole 110 can be formed by mechanical drilling or laser drilling.
  • Step S14 please refer to FIG. 15 , forming a first metal layer 42 and a second metal layer 42 on the surface of the first base layer 41 facing away from the first surface 11 and the surface of the second base layer 51 facing away from the second surface 12, respectively.
  • metal layer 52 and form a first conductive structure 112 in the blind hole 110 .
  • the first metal layer 42 completely covers the surface of the first base layer 41 facing away from the first surface 11 of the inner circuit substrate 10, and the second metal layer 52 completely covers the second base layer 51 facing away from the inner layer circuit substrate. layer of the second surface 12 of the circuit substrate 10 .
  • the first metal layer 42 and the second metal layer 52 are respectively electrically connected to the soldering terminals of the corresponding electronic components 33 through the corresponding first conductive structures 112 .
  • the first conductive structure 112 may be a conductive hole or a conductive pillar.
  • the first metal layer 42 , the second metal layer 52 and the first conductive structure 112 can be formed by electroplating, printing and the like.
  • the first metal layer 42 , the second metal layer 52 and the first conductive structure 112 can be formed by electroplating, and the first conductive structure 112 is a conductive hole.
  • step S15 please refer to FIG. 16 , circuit fabrication is performed on the first metal layer and the second metal layer to form a first conductive circuit layer 43 and a second conductive circuit layer 53 respectively.
  • the first conductive circuit layer 43 and the second conductive circuit layer 53 can be formed by image transfer process and etching process.
  • the first conductive circuit layer 43 and the first base layer 41 together constitute the first circuit substrate 40 .
  • the second conductive circuit layer 53 and the second base layer 51 together constitute the second circuit substrate 50 .
  • the first conductive circuit layer 43 and the second conductive circuit layer 53 are respectively electrically connected to corresponding electronic components 33 through corresponding first conductive structures 112 .
  • Step S16 please refer to FIG. 17 , forming a third circuit substrate 60 and a fourth circuit substrate 70 on the surfaces of the first conductive circuit layer 43 and the second conductive circuit layer 53 respectively, so as to produce an embedded circuit board 100 .
  • the third circuit substrate 60 includes a third base layer 61 and a third conductive circuit layer 63 that are laminated.
  • the third base layer 61 covers the first conductive circuit layer 43 and fills the circuit gap of the first conductive circuit layer 43 so as to be connected with the first base layer 41 .
  • the third conductive circuit layer 63 is located on a side of the third base layer 61 away from the first conductive circuit layer 43 .
  • the fourth circuit substrate 70 includes a fourth base layer 71 and a fourth conductive circuit layer 73 that are laminated.
  • the fourth base layer 71 covers the second conductive circuit layer 53 and fills circuit gaps of the second conductive circuit layer 53 to be connected to the second base layer 51 .
  • the fourth conductive circuit layer 73 is located on a side of the fourth base layer 71 away from the second conductive circuit layer 53 .
  • the material of the third base layer 61 and the fourth base layer 71 can be a common dielectric material in the field, such as polyimide, epoxy resin and the like.
  • the embedded circuit board 100 further includes a plurality of second conductive structures 113 .
  • Part of the second conductive structure 113 is electrically connected to the first conductive circuit layer 43 and the third conductive circuit layer 63, and another part of the second conductive structure 113 is electrically connected to the second conductive circuit layer 53 and the fourth conductive circuit layer Layer 73.
  • the second conductive structure 113 may be a conductive hole or a conductive pillar.
  • the embodiment of the present application also provides an embedded circuit board 100, including an inner circuit substrate 10, an electronic component module 30, a first circuit substrate 40, a second circuit substrate 50, a third circuit substrate 60 and The fourth circuit substrate 70 .
  • the inner circuit substrate 10 includes a first surface 11 and a second surface 12 opposite to each other, and a through groove 101 penetrating through the first surface 11 and the second surface 12 is opened.
  • the electronic component module 30 is accommodated in the through groove 101 .
  • the first circuit substrate 40 includes a first base layer 41 and a first conductive circuit layer 43 that are laminated.
  • the second circuit substrate 50 includes a second base layer 51 and a second conductive circuit layer 53 that are stacked.
  • the first base layer 41 covers the first surface 11, the second base layer 51 covers the second surface, and the first base layer 41 and the second base layer 51 fill the through groove 101 to jointly enclose Cover the electronic component module 30 .
  • the electronic component module 30 includes a body 311 , at least one electronic component 33 , a first adhesive layer 32 and a second adhesive layer 35 .
  • the body 311 is provided with a groove 301, the at least one electronic component 33 is fixed on the bottom wall of the groove 301 through the first adhesive layer 32, and the second adhesive layer 35 is filled in the groove.
  • the slot 301 covers the at least one electronic component 33 together with the first adhesive layer 32 .
  • the electronic component module 30 is pre-adhesively positioned on the carrier board 20, which reduces the flow of dielectric materials in the subsequent lamination process.
  • the risk of offset caused; and the electronic component 33 is pre-fixed in the groove 301 through the first glue layer 32, which further reduces the offset caused by the flow of glue in the subsequent glue filling process risk.
  • the process flow can be simplified.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种内埋电路板的制作方法，包括以下步骤：提供内层电路基板，设有贯通槽；在内层电路基板上贴附一承载板以封住贯通槽的一端；提供一电子组件模组，电子组件模组包括本体、至少一个电子组件、第一胶层以及第二胶层，本体开设有凹槽，至少一个电子组件通过第一胶层固定于凹槽的底壁上，且第二胶层填充于凹槽中并和第一胶层共同包覆至少一个电子组件；将电子组件模组放置于贯通槽中；在内层电路基板一侧压合第一基层；去除承载板；在内层电路基板另一侧压合第二基层，其中，第一基层和第二基层填充贯通槽并共同包覆电子组件模组。本申请还提供采用上述方法制得的内埋电路板。

Description

内埋电路板及其制作方法 技术领域
本申请涉及电路板技术领域，尤其涉及一种内埋电路板及其制作方法。
背景技术
近年来，电子产品被广泛应用在日常工作和生活中，小型化、多功能化及高性能化的需求越来越高。电路板作为电子产品的主要部件，其占据了电子产品的较大空间，因此电路板的体积在很大程度上影响了电子产品的体积，通过将电子组件(如电阻、电容等)嵌埋在电路基板的内部有利于减少电路板的整体厚度，从而减少电子产品的厚度。
内埋电子组件的通常做法如下：首先，制作一个内层电路基板，并在所述内层电路基板上形成凹槽；然后，将电子组件放置于所述凹槽中，再进行增层。然而，在进行增层时，电子组件容易产生无规律的偏移的现象，进而增加了后续形成盲孔与焊接端子之间精准对位的难度。
发明内容
有鉴于此，有必要提供一种能够解决上述技术问题的内埋电路板及其制作方法。
本申请第一方面提供一种内埋电路板的制作方法，包括以下步骤：
提供内层电路基板，所述内层电路基板包括相对设置的第一表面和第二表面；
在所述内层电路基板上形成一贯通槽，所述贯通槽贯通所述第一表面和所述第二表面；
在所述第二表面上贴附一承载板以封住所述贯通槽的一端；
提供一电子组件模组，所述电子组件模组包括本体、至少一个电子组件、第一胶层以及第二胶层，所述本体开设有凹槽，所述至少一个电子组件通过所述第一胶层固定于所述凹槽的底壁上，且所述第二胶层填充于所述凹槽中并和所述第一胶层共同包覆所述至少一个电子组件；
将所述电子组件模组放置于所述贯通槽中，其中，所述电子组件模组与所述承载板相粘接；
在所述第一表面压合第一基层；
去除所述承载板；
在所述第二表面压合第二基层，其中，所述第一基层和所述第二基层填充所述贯通槽并共同包覆所述电子组件模组；
在所述第一基层背离所述第一表面的表面形成第一导电线路层以得到第一电路基板，并在所述第二基层背离所述第二表面的表面形成第二导电线路层以得到第二电路基板。
本申请第二方面提供一种内埋电路板，包括内层电路基板、电子组件模组、第一电路基板和第二电路基板，所述内层电路基板包括相对设置的第一表面和第二表面并开设有贯通所述第一表面和所述第二表面的贯通槽，所述电子组件模组收容于所述贯通槽中，所述电子组件模组包括本体、至少一个电子组件、第一胶层以及第二胶层，所述本体开设有凹槽，所述至少一个电子组件通过所述第一胶层固定于所述凹槽的底壁上，且所述第二胶层填充于所述凹槽中并和所述第一胶层共同包覆所述至少一个电子组件，所述第一电路基板包括层叠设置 的第一基层和第一导电线路层，所述第二电路基板包括层叠设置的第二基层和第二导电线路层，所述第一基层覆盖所述第一表面，所述第二基层覆盖所述第二表面，且所述第一基层和所述第二基层填充所述贯通槽以共同包覆所述电子组件模组。
本申请提供的内埋电路板及其制作方法中，将所述电子组件模组预先粘接定位于所述承载板上，减小了后续的压合基层工序中因介电材料流动而导致的偏移风险；且将所述电子组件预先通过所述第一胶层固定于所述凹槽中，进一步减小了后续的填胶工序中因胶水流动而导致的偏移风险。另外，通过将多个电子组件集成于电子组件模组中，可简化工艺流程。
附图说明
图1为本申请一实施方式提供的内层电路基板的截面示意图。
图2为在图1所示内层电路基板上开设一贯通槽后的截面示意图。
图3为在图1所示内层电路基板的一表面贴附承载板后的截面示意图。
图4为本申请一实施方式提供的绝缘板的俯视图。
图5为图4所示绝缘板的本体的截面示意图。
图6为在图5所示的本体上形成一凹槽后的截面示意图。
图7为将电子组件收容于图6所示的凹槽中后的截面示意图。
图8为在图7所示凹槽中填入胶水后的截面示意图。
图9为分离图8所示绝缘板得到多个电子组件模组后的截面示意图。
图10为将图8所示电子组件模组放置于图3所示贯通槽 中后的截面示意图。
图11为在图10所示内层电路基板远离所示承载板的一侧压合第一基层后的截面示意图。
图12为去除图11所示的承载板后的截面示意图。
图13为在图12所示的内层电路基板远离所述第一基层的一侧压合第二基层后的截面示意图。
图14为在图13所示结构上形成盲孔后的截面示意图。
图15为在图14所示盲孔中形成第一导电结构后的截面示意图。
图16为在图15所示第一基层和第二基层上分别形成第一导电线路层和第二导电线路层后的截面示意图。
图17为在图16所示第一导电线路层和第二导电线路层上分别形成第三电路基板和第四电路基板后的截面示意图。
主要元件符号说明
内层电路基板            10
第一表面                11
第二表面                12
贯通槽                  101
承载板                  20
绝缘板                  31
本体                    311
凹槽                    301
第一胶层                32
电子组件                33
第二胶层                35
电子组件模组            30
第一基层                41
第二基层               51
盲孔                   110
第一金属层             42
第二金属层             52
第一导电线路层         43
第二导电线路层         53
第一电路基板           40
第二电路基板           50
第三电路基板           60
第三基层               61
第三导电线路层         63
第四电路基板           70
第四基层               71
第四导电线路层         73
第二导电结构           113
内埋电路板             100
如下具体实施方式将结合上述附图进一步说明本申请。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
本申请一实施方式提供一种内埋电路板的制作方法，其包括以下步骤。
步骤S 1，请参阅图1，提供内层电路基板10。所述内层电 路基板10包括相对设置的第一表面11和第二表面12。
所述内层电路基板10为形成有导电线路的电路板。所述内层电路基板10包括至少一导电线路层和至少一介电层。每层介电层设置于相邻的两层导电线路层之间。每层介电层内形成有第一导电结构，相邻的两层导电线路层之间通过所述第一导电结构相互电导通。
所述介电层的材质可以为硬性绝缘材料，例如为FR-4等级的聚酰亚胺、聚丙烯、液晶聚合物、聚醚醚酮、聚对苯二甲酸乙二醇酯以及聚萘二甲酸乙二醇酯等中的一种。所述介电层的材质还可以为柔性绝缘材料，例如为聚酰亚胺、聚丙烯、液晶聚合物、聚醚醚酮、聚对苯二甲酸乙二醇酯以及聚萘二甲酸乙二醇酯等中的一种。所述导电线路层的材质可包含但不限于铜、金、银等。
所述内层电路基板10的制作方法可以采用现有技术中电路板的制作方法制成。如先进行芯层基板的制作，然后，采用增层的方式，在芯层基板的两侧进行增层，从而得到内层电路基板。
步骤S2，请参阅图2，在所述内层电路基板10上形成贯通槽101。
所述贯通槽101贯通所述第一表面11和所述第二表面12。所述贯通槽101可以通过机械钻孔或激光钻孔等方式形成。
步骤S3，请参阅图3，在所述内层电路基板10的第二表面12上贴附一承载板20以封住所述贯通槽101的一端。
所述承载板20与所述内层电路基板10相接触的表面设有粘接层，用于粘附待内埋的组件。本实施方式中，所述承载板20为胶带，所述胶带粘接于所述内层电路基板10的表面并封盖所述贯通槽101的一端。
步骤S4，请参阅图4和图5，提供一绝缘板31。所述绝缘板31包括呈矩阵排列的多个本体311。多个本体311相互连接构成所述绝缘板31。
所述本体311的材质具有耐热压合和可进行激光烧熔的性能。所述本体311的材质可以但不限于为本领域常用的介电材料，例如聚酰亚胺、环氧树脂等。
步骤S5，请参阅图6，在每个本体311上形成一凹槽301，并在所述凹槽301的底部形成一第一胶层32。
所述凹槽301贯通所述本体311的一个表面。所述凹槽301可以通过机械钻孔或激光钻孔等方式形成。
所述第一胶层32可以但不限于通过印刷、涂布或点胶等方式形成于所述凹槽301的底壁上。本实施方式中，所述第一胶层32完全覆盖所述凹槽301的底壁。
步骤S6，请参阅图7，将至少一个电子组件33安装于位于所述凹槽301中的第一胶层32上。
所述至少一个电子组件33放置于所述第一胶层32上并与所述第一胶层32相粘接以定位所述至少一个电子组件33。所述至少一个电子组件33包括主动组件和被动组件中的至少一种。本实施方式中，将一个主动组件和两个被动组件收容于所述凹槽301中。可以理解的是，收容于所述凹槽301中的主动组件和被动组件的数量可以依据实际需要进行调整。
步骤S7，请参阅图8，向所述凹槽301中填入胶水形成第二胶层35，得到电子组件模组30。
所述第二胶层35覆盖所述电子组件33暴露于所述第一胶层32外的暴露面，并与所述第一胶层32相连接。所述第二胶层35和所述第一胶层32共同包覆所述电子组件33，使得所述电子组件33内埋于所述第二胶层35和所述第一胶层32共 同形成的胶层中。
所述第二胶层35暴露于所述凹槽301外的表面与所述本体311设有所述凹槽301的表面相平齐，即所述第二胶层35与所述本体311具有无段差的等高水平面。
当胶水填入所述凹槽301中形成第二胶层35时，由于所述电子组件33已通过所述第一胶层32固定于所述凹槽301中，因此可降低因胶水流动而导致电子组件33发生偏移的风险。
所述第一胶层32和所述第二胶层35的材质可以但不限于为常温固化胶。
步骤S8，请参阅图9，沿着所述多个本体311之间的分界线分离多个电子组件模组30。可通过机械切割或激光切割等方式分离多个电子组件模组30。
步骤S9，请参阅图10，将所述电子组件模组30放置于所述贯通槽101中。
所述电子组件模组30支承于所述承载板20上，并与所述承载板20相粘接，以定位所述电子组件模组30。
本实施方式中，所述电子组件模组30翻转放置于所述贯通槽101中，使得所述电子组件模组30的胶层与所述承载板20相粘接，以提高所述电子组件模组30与所述承载板20的粘接牢固性。
本实施方式中，所述电子组件模组30的高度与所述贯通槽101的深度相等。
步骤S10，请参阅图11，在所述内层电路基板10的第一表面11上压合第一基层41。
所述第一基层41覆盖所述内层电路基板10的第一表面11以及所述电子组件模组30的暴露面，并填充所述电子组件模组30与所述贯通槽101的侧壁之间的缝隙。
所述第一基层41的材质可以为本领域常用的介电材料，例如聚酰亚胺、环氧树脂等。
步骤S11，请参阅图12，去除所述承载板20，以暴露所述内层电路基板10的第二表面12。
所述承载板20可通过撕除等方式去除。
步骤S12，请参阅图13，在所述内层电路基板10的第二表面12上压合第二基层51。
所述第二基层51覆盖所述内层电路基板10的第二表面12以及所述电子组件模组30暴露于所述第一基层41外的表面，并与所述第一基层41相连接。所述第一基层41和所述第二基层51共同包覆所述电子组件模组30，使得所述电子组件模组30内埋于所述第一基层41和所述第二基层51共同构成的基层中。
所述第二基层51的材质可以为本领域常用的介电材料，例如聚酰亚胺、环氧树脂等。
步骤S13，请参阅图14，形成暴露所述电子组件33的焊接端子的盲孔110。
所述盲孔110的位置和数量可根据所述电子组件33的类型、数量等进行适应性改变，本申请并不做限制。本实施方式中，形成了对应多个电子组件33的多个盲孔110，其中，部分盲孔110贯通所述第二基层51和所述第二胶层35，另一部分盲孔110贯通所述第一基层41、所述本体311和所述第一胶层32。
所述盲孔110可通过机械钻孔或激光钻孔等方式形成。
步骤S14，请参阅图15，在所述第一基层41背离所述第一表面11的表面和所述第二基层51背离所述第二表面12的表面分别形成第一金属层42和第二金属层52，并在所述盲孔110 中形成第一导电结构112。
所述第一金属层42完全覆盖所述第一基层41背离所述内层电路基板10的第一表面11的表面，所述第二金属层52完全覆盖所述第二基层51背离所述内层电路基板10的第二表面12的表面。所述第一金属层42和所述第二金属层52分别通过相应的第一导电结构112与相应的电子组件33的焊接端子电连接。所述第一导电结构112可以为导电孔或导电柱。
所述第一金属层42、所述第二金属层52以及所述第一导电结构112可通过电镀、印刷等方式形成。本实施方式中，所述第一金属层42、所述第二金属层52以及所述第一导电结构112可通过电镀方式形成，所述第一导电结构112为导电孔。
步骤S15，请参阅图16，在所述第一金属层和所述第二金属层上进行线路制作，分别形成第一导电线路层43和第二导电线路层53。
所述第一导电线路层43和所述第二导电线路层53可采用影像转移工艺和蚀刻工艺形成。
所述第一导电线路层43和所述第一基层41共同构成第一电路基板40。所述第二导电线路层53和所述第二基层51共同构成第二电路基板50。所述第一导电线路层43和所述第二导电线路层53分别通过相应的第一导电结构112与相应的电子组件33电连接。
步骤S16，请参阅图17，在所述第一导电线路层43以及所述第二导电线路层53的表面分别形成第三电路基板60和第四电路基板70，以制得内埋电路板100。
所述第三电路基板60包括层叠设置的第三基层61和第三导电线路层63。所述第三基层61覆盖所述第一导电线路层43，并填充所述第一导电线路层43的线路缝隙以与所述第一基层 41相连接。所述第三导电线路层63位于所述第三基层61背离所述第一导电线路层43的一侧。
所述第四电路基板70包括层叠设置的第四基层71和第四导电线路层73。所述第四基层71覆盖所述第二导电线路层53，并填充所述第二导电线路层53的线路缝隙以与所述第二基层51相连接。所述第四导电线路层73位于所述第四基层71背离所述第二导电线路层53的一侧。
所述第三基层61和所述第四基层71的材质可以为本领域常用的介电材料，例如聚酰亚胺、环氧树脂等。
所述内埋电路板100还包括多个第二导电结构113。部分第二导电结构113电连接所述第一导电线路层43和所述第三导电线路层63，另一部分第二导电结构113电连接所述第二导电线路层53和所述第四导电线路层73。所述第二导电结构113可以为导电孔或导电柱。
请参阅图17，本申请实施方式还提供一种内埋电路板100，包括内层电路基板10、电子组件模组30、第一电路基板40、第二电路基板50、第三电路基板60和第四电路基板70。
所述内层电路基板10包括相对设置的第一表面11和第二表面12，并开设有贯通所述第一表面11和所述第二表面12的贯通槽101。所述电子组件模组30收容于所述贯通槽101中。所述第一电路基板40包括层叠设置的第一基层41和第一导电线路层43。所述第二电路基板50包括层叠设置的第二基层51和第二导电线路层53。所述第一基层41覆盖所述第一表面11，所述第二基层51覆盖所述第二表面，且所述第一基层41和所述第二基层51填充所述贯通槽101以共同包覆所述电子组件模组30。
所述电子组件模组30包括本体311、至少一个电子组件33、 第一胶层32以及第二胶层35。所述本体311开设有凹槽301，所述至少一个电子组件33通过所述第一胶层32固定于所述凹槽301的底壁上，且所述第二胶层35填充于所述凹槽301中并和所述第一胶层32共同包覆所述至少一个电子组件33。
本申请提供的内埋电路板100及其制作方法中，将所述电子组件模组30预先粘接定位于所述承载板20上，减小了后续的压合基层工序中因介电材料流动而导致的偏移风险；且将所述电子组件33预先通过所述第一胶层32固定于所述凹槽301中，进一步减小了后续的填胶工序中因胶水流动而导致的偏移风险。另外，通过将多个电子组件33集成于电子组件模组30中，可简化工艺流程。
以上所揭露的仅为本申请较佳实施方式而已，当然不能以此来限定本申请，因此依本申请所作的等同变化，仍属本申请所涵盖的范围。

Claims (10)

  1. 一种内埋电路板的制作方法，其特征在于，包括以下步骤：
    提供内层电路基板，所述内层电路基板包括相对设置的第一表面和第二表面；
    在所述内层电路基板上形成一贯通槽，所述贯通槽贯通所述第一表面和所述第二表面；
    在所述第二表面上贴附一承载板以封住所述贯通槽的一端；
    提供一电子组件模组，所述电子组件模组包括本体、至少一个电子组件、第一胶层以及第二胶层，所述本体开设有凹槽，所述至少一个电子组件通过所述第一胶层固定于所述凹槽的底壁上，且所述第二胶层填充于所述凹槽中并和所述第一胶层共同包覆所述至少一个电子组件；
    将所述电子组件模组放置于所述贯通槽中，其中，所述电子组件模组与所述承载板相粘接；
    在所述第一表面压合第一基层；
    去除所述承载板；
    在所述第二表面压合第二基层，其中，所述第一基层和所述第二基层填充所述贯通槽并共同包覆所述电子组件模组；
    在所述第一基层背离所述第一表面的表面形成第一导电线路层以得到第一电路基板，并在所述第二基层背离所述第二表面的表面形成第二导电线路层以得到第二电路基板。
  2. 如权利要求1所述的内埋电路板的制作方法，其特征在于，“提供一电子组件模组”的步骤包括：
    提供一本体，并在所述本体上形成一凹槽；
    在所述凹槽的底部形成第一胶层；
    将至少一个电子组件安装于所述第一胶层上；
    向所述凹槽中填入胶水形成第二胶层，其中，所述第二胶层和所述第一胶层共同包覆所述至少一个电子组件。
  3. 如权利要求1所述的内埋电路板的制作方法，其特征在于，当所述电子组件模组放置于所述贯通槽中时，所述第二胶层与所述承载板相粘接。
  4. 如权利要求1所述的内埋电路板的制作方法，其特征在于，所述第二胶层暴露于所述凹槽外的表面与所述本体设有所述凹槽的表面相平齐。
  5. 如权利要求1所述的内埋电路板的制作方法，其特征在于，所述电子组件模组的高度与所述贯通槽的深度相等。
  6. 如权利要求1所述的内埋电路板的制作方法，其特征在于，还包括以下步骤：在所述第一导电线路层以及所述第二导电线路层的表面分别形成第三电路基板和第四电路基板。
  7. 如权利要求1所述的内埋电路板的制作方法，其特征在于，所述至少一个电子组件包括主动组件和被动组件中至少一种。
  8. 一种内埋电路板，其特征在于，包括内层电路基板、电子组件模组、第一电路基板和第二电路基板，所述内层电路基板包括相对设置的第一表面和第二表面并开设有贯通所述第一表面和所述第二表面的贯通槽，所述电子组件模组收容于所述贯通槽中，所述电子组件模组包括本体、至少一个电子组件、第一胶层以及第二胶层，所述本体开设有凹槽，所述至少一个电子组件通过所述第一胶层固定于所述凹槽的底壁上，且所述第二胶层填充于所述凹槽中并和所述第一胶层共同包覆所述至少一个电子组件，所述第一电路基板包括层叠设置的第一基层和第一导电线路层，所述第二电路基板包括层叠设置的 第二基层和第二导电线路层，所述第一基层覆盖所述第一表面，所述第二基层覆盖所述第二表面，且所述第一基层和所述第二基层填充所述贯通槽以共同包覆所述电子组件模组。
  9. 如权利要求8所述的内埋电路板，其特征在于，所述内埋电路板还包括分别设置于所述第一导电线路层和所述第二导电线路层的表面的第三电路基板和第四电路基板。
  10. 如权利要求8所述的内埋电路板，其特征在于，所述至少一个电子组件包括主动组件和被动组件中至少一种。
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