WO2023063412A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2023063412A1
WO2023063412A1 PCT/JP2022/038348 JP2022038348W WO2023063412A1 WO 2023063412 A1 WO2023063412 A1 WO 2023063412A1 JP 2022038348 W JP2022038348 W JP 2022038348W WO 2023063412 A1 WO2023063412 A1 WO 2023063412A1
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Prior art keywords
region
high resistance
doping concentration
semiconductor device
semiconductor substrate
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English (en)
French (fr)
Japanese (ja)
Inventor
洋輔 桜井
晴司 野口
大輔 尾崎
竜太郎 浜崎
拓弥 山田
巧裕 伊倉
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Priority to CN202280024178.2A priority Critical patent/CN117063293A/zh
Priority to DE112022000977.2T priority patent/DE112022000977T5/de
Priority to JP2023554643A priority patent/JP7670158B2/ja
Publication of WO2023063412A1 publication Critical patent/WO2023063412A1/ja
Priority to US18/469,541 priority patent/US20240006519A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.
  • Patent Document 1 JP 2019-91892 A
  • the breakdown voltage or withstand capacity of the semiconductor device does not decrease.
  • a semiconductor device may comprise a semiconductor substrate having a top surface and a bottom surface and including a drift region of a first conductivity type.
  • the semiconductor device may comprise a base region of the second conductivity type provided between the drift region and the top surface of the semiconductor substrate.
  • the semiconductor device may include a plurality of trench portions provided from the upper surface of the semiconductor substrate to below the base region.
  • the semiconductor device may include a second conductivity type lower end region provided in contact with the lower ends of the two or more trench portions.
  • the semiconductor device may include a well region of the second conductivity type arranged at a position different from the lower end region in top view, provided from the upper surface of the semiconductor substrate to below the base region, and having a doping concentration higher than that of the base region.
  • the semiconductor device may include a second-conductivity-type high-resistance region disposed between the lower end region and the well region in top view and having a lower doping concentration than the lower end region.
  • the high resistance region may connect the lower end region and the well region.
  • the length of the high resistance region in top view may be greater than the width of the high resistance region in the depth direction of the semiconductor substrate.
  • the high resistance region may be in contact with the lower ends of two or more trench portions.
  • the semiconductor device may include an active portion surrounded by a well region when viewed from above.
  • the high resistance region may be arranged at a position in contact with the well region in the active portion.
  • the high-resistance region may surround the active portion when viewed from above.
  • the high-resistance region may have a first high-resistance portion arranged at a corner portion of the active portion when viewed from above, and a second high-resistance portion having a lower doping concentration than the first high-resistance portion.
  • the high resistance region may have a lower doping concentration than the base region.
  • the doping concentration of the high resistance region may be 10% or less of the doping concentration of the lower end region.
  • the high-resistance region may have a doping concentration peak in the direction connecting the bottom region and the well region.
  • the peak doping concentration in the high resistance region may be 0.5 times or more and 1.5 times or less than the doping concentration in the lower end region.
  • the semiconductor device may include an emitter region of the first conductivity type provided between the base region and the upper surface of the semiconductor substrate and having a higher doping concentration than the drift region. A part of the emitter region and a part of the high resistance region may overlap when viewed from above.
  • the semiconductor device may include an emitter region of the first conductivity type provided between the base region and the upper surface of the semiconductor substrate and having a higher doping concentration than the drift region.
  • the emitter region and the high resistance region may be arranged apart from each other when viewed from above.
  • the plurality of trench portions may include one or more gate trench portions.
  • the high resistance region may be in contact with the lower end of at least one gate trench portion.
  • the high resistance region may have a lower end portion in contact with the lower end of the gate trench portion and a low concentration portion having a lower doping concentration than the lower end portion.
  • the semiconductor device may include an accumulation region provided between the base region and the drift region and having a higher doping concentration than the drift region. A portion of the accumulation region and a portion of the high resistance region may overlap when viewed from above.
  • the trench may have a long side in the first direction and a short side in the second direction when viewed from above.
  • the ratio of the first length of the high-resistance region connecting the bottom region and the well region in the first direction to the second length of the high-resistance region connecting the bottom region and the well region in the second direction is 0.9 or more; It may be 1.1 or less.
  • the doping concentration distribution in the first direction of the high resistance region may be flatter than the doping concentration distribution in the second direction of the high resistance region.
  • a second aspect of the present invention provides a method of manufacturing a semiconductor device.
  • a manufacturing method includes forming a second conductivity type base region provided between the drift region and the top surface of the semiconductor substrate in a semiconductor substrate having a top surface and a bottom surface and including a first conductivity type drift region. you can The manufacturing method may form a plurality of trench portions provided from the upper surface of the semiconductor substrate to below the base region. The manufacturing method may form a second conductivity type lower end region provided in contact with the lower ends of the two or more trench portions.
  • a well region of the second conductivity type is formed, which is arranged at a position different from the lower end region when viewed from above, is provided from the upper surface of the semiconductor substrate to below the base region, and has a doping concentration higher than that of the base region. good.
  • the manufacturing method may form a high-resistance region of the second conductivity type which is arranged between the lower end region and the well region in top view and has a lower doping concentration than the lower end region.
  • the dopant of the second conductivity type may be implanted into both the region where the high resistance region should be formed and the region where the lower end region should be formed.
  • the manufacturing method may further implant a dopant of the second conductivity type into the region where the bottom region is to be formed.
  • different concentrations of the second conductivity type dopant may be implanted into the region where the high resistance region is to be formed and the region where the lower end region is to be formed.
  • a dopant of the second conductivity type is implanted into a region away from the region where the lower end region is to be formed, among the regions where the high resistance region is to be formed, and heat treatment is performed to remove the dopant from the region where the lower end region is to be formed. may be diffused towards
  • FIG. 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention
  • FIG. 2 is an enlarged view of a region D in FIG. 1
  • FIG. 3 is a diagram showing an example of an ee cross section in FIG. 2
  • FIG. 3 is a diagram showing an example of arrangement of well regions 11 and lower end regions 202 in top view.
  • FIG. 5 is a diagram showing an example of the ff cross section in FIG. 4
  • FIG. 5B is a diagram showing an example of the net doping concentration distribution of the aa cross section and the bb cross section in FIG. 5A; It is a figure which shows an example of doping concentration distribution in an X-axis direction.
  • FIG. 5 is a diagram showing an example of the net doping concentration distribution of the aa cross section and the bb cross section in FIG. 5A
  • It is a figure which shows an example of doping concentration distribution in an X-axis direction.
  • FIG. 5 is a diagram showing an example of a gg cross section in FIG. 4; 3 shows the result of measuring the relationship between the doping concentration of the high-resistance region 204 and the withstand voltage of the portion where the high-resistance region 204 is formed.
  • FIG. 10 is a diagram showing another arrangement example of the high-resistance region 204 when viewed from above;
  • FIG. 10 is a diagram showing another arrangement example of the high-resistance region 204 when viewed from above;
  • 3A to 3C are diagrams showing a part of steps of a method of manufacturing the semiconductor device 100;
  • FIG. It is a figure explaining an example of 2nd area
  • FIG. 11 is a diagram illustrating another example of the second region forming step S1104;
  • FIG. 11 is a diagram illustrating another example of the second region forming step S1104;
  • FIG. 10 is a diagram showing another example of doping concentration distribution in the X-axis direction;
  • FIG. 10 is a diagram showing another example of doping concentration distribution in the X-axis direction;
  • FIG. 10 is a diagram showing another example of doping concentration distribution in the X-axis direction;
  • FIG. 10 is a diagram showing another example of doping concentration distribution in the X-axis direction;
  • FIG. 10 is a diagram showing another configuration example of the lower end region 202 and the high resistance region 204;
  • FIG. 4 is a diagram showing an example of doping concentration distribution in a high resistance region 204;
  • FIG. 10 is a diagram showing another arrangement example of the high-resistance regions 204 in the X-axis direction;
  • one side in the direction parallel to the depth direction of the semiconductor substrate is called “upper”, and the other side is called “lower”.
  • One of the two main surfaces of a substrate, layer or other member is called the upper surface and the other surface is called the lower surface.
  • the directions of “up” and “down” are not limited to the direction of gravity or the direction when the semiconductor device is mounted.
  • the Cartesian coordinate axes only specify the relative positions of the components and do not limit any particular orientation.
  • the Z axis does not limit the height direction with respect to the ground.
  • the +Z-axis direction and the ⁇ Z-axis direction are directions opposite to each other.
  • the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.
  • orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are defined as the X-axis and the Y-axis.
  • the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is defined as the Z-axis.
  • the Z-axis direction may be referred to as the depth direction.
  • a direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis may be referred to as a horizontal direction.
  • the region from the center of the semiconductor substrate in the depth direction to the upper surface of the semiconductor substrate may be referred to as the upper surface side.
  • the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.
  • the conductivity type of the doping region doped with impurities is described as P-type or N-type.
  • impurities may specifically refer to either N-type donors or P-type acceptors, and may also be referred to as dopants.
  • doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.
  • doping concentration means the concentration of donors or the concentration of acceptors at thermal equilibrium.
  • the net doping concentration means the net concentration including charge polarity, where the donor concentration is the positive ion concentration and the acceptor concentration is the negative ion concentration.
  • the donor concentration is N D and the acceptor concentration is N A , then the net net doping concentration at any location is N D ⁇ N A.
  • net doping concentration may be simply referred to as doping concentration.
  • a donor has the function of supplying electrons to a semiconductor.
  • the acceptor has the function of receiving electrons from the semiconductor.
  • Donors and acceptors are not limited to impurities per se.
  • VOH defects in which vacancies (V), oxygen (O), and hydrogen (H) are combined in semiconductors function as donors that supply electrons.
  • VOH defects are sometimes referred to herein as hydrogen donors.
  • the semiconductor substrate herein is distributed throughout with N-type bulk donors.
  • Bulk donors are donors from dopants that are substantially uniformly contained within the ingot during the manufacture of the ingot from which the semiconductor substrate is made.
  • the bulk donor in this example is an element other than hydrogen.
  • Bulk donor dopants include, but are not limited to, phosphorus, antimony, arsenic, selenium or sulfur.
  • the bulk donor in this example is phosphorus.
  • Bulk donors are also included in the P-type regions.
  • the semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by singulating the wafer.
  • Semiconductor ingots may be manufactured by any of the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), and the float zone method (FZ method).
  • the ingot in this example is manufactured by the MCZ method.
  • the oxygen concentration contained in the substrate manufactured by the MCZ method is 1 ⁇ 10 17 to 7 ⁇ 10 17 /cm 3 .
  • the oxygen concentration contained in the substrate manufactured by the FZ method is 1 ⁇ 10 15 to 5 ⁇ 10 16 /cm 3 .
  • a higher oxygen concentration tends to generate hydrogen donors more easily.
  • the bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate and may be between 90% and 100% of the chemical concentration.
  • a non-doped substrate that does not contain a dopant such as phosphorus may be used as the semiconductor substrate.
  • the bulk donor concentration (D0) of the non-doped substrate is, for example, 1 ⁇ 10 10 /cm 3 or more and 5 ⁇ 10 12 /cm 3 or less.
  • the bulk donor concentration (D0) of the non-doped substrate is preferably 1 ⁇ 10 11 /cm 3 or higher.
  • the bulk donor concentration (D0) of the non-doped substrate is preferably 5 ⁇ 10 12 /cm 3 or less.
  • Each concentration in the present invention may be a value at room temperature. As an example of the value at room temperature, a value at 300 K (Kelvin) (approximately 26.9° C.) may be used.
  • references herein to P-type or N-type refer to higher doping concentrations than P-type or N-type; references to P-type or N-type refer to higher doping than P-type or N-type. It means that the concentration is low.
  • P++ type or N++ type in this specification means that the doping concentration is higher than that of the P+ type or N+ type.
  • the unit system in this specification is the SI unit system unless otherwise specified. The unit of length is sometimes displayed in cm, but various calculations may be performed after converting to meters (m).
  • chemical concentration refers to the atomic density of impurities measured regardless of the state of electrical activation. Chemical concentrations can be measured, for example, by secondary ion mass spectroscopy (SIMS).
  • the net doping concentrations mentioned above can be measured by the voltage-capacitance method (CV method).
  • the carrier concentration measured by the spreading resistance measurement method (SR method) may be used as the net doping concentration.
  • the carrier concentration measured by the CV method or SR method may be a value in thermal equilibrium.
  • the donor concentration is sufficiently higher than the acceptor concentration in the N-type region, the carrier concentration in the region may be used as the donor concentration.
  • the carrier concentration in that region may be used as the acceptor concentration.
  • the doping concentration of the N-type regions is sometimes referred to herein as the donor concentration
  • the doping concentration of the P-type regions is sometimes referred to as the acceptor concentration.
  • the peak value may be taken as the concentration of donors, acceptors or net doping in the region.
  • the average value of the concentration of donors, acceptors or net doping in the region may be used as the concentration of donors, acceptors or net doping.
  • atoms/cm 3 or /cm 3 are used to express concentration per unit volume. This unit is used for donor or acceptor concentrations, or chemical concentrations, within a semiconductor substrate. The atoms notation may be omitted.
  • the carrier concentration measured by the SR method may be lower than the donor or acceptor concentration.
  • the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. A decrease in carrier mobility is caused by scattering of carriers due to disorder of the crystal structure due to lattice defects or the like.
  • the donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor.
  • the donor concentration of phosphorus or arsenic as a donor or the acceptor concentration of boron (boron) as an acceptor in a silicon semiconductor is about 99% of these chemical concentrations.
  • the donor concentration of hydrogen serving as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.
  • FIG. 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention.
  • FIG. 1 shows the positions of each member projected onto the upper surface of the semiconductor substrate 10 .
  • FIG. 1 only some members of the semiconductor device 100 are shown, and some members are omitted.
  • a semiconductor device 100 includes a semiconductor substrate 10 .
  • the semiconductor substrate 10 is a substrate made of a semiconductor material.
  • the semiconductor substrate 10 is a silicon substrate.
  • the semiconductor substrate 10 has an edge 162 when viewed from above. In this specification, simply referring to a top view means viewing from the top side of the semiconductor substrate 10 .
  • the semiconductor substrate 10 of this example has two sets of edges 162 facing each other when viewed from above. In FIG. 1 , the X-axis and Y-axis are parallel to one of the edges 162 . Also, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10 .
  • An active portion 160 is provided on the semiconductor substrate 10 .
  • the active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 operates.
  • An emitter electrode is provided above the active portion 160, but is omitted in FIG.
  • the active portion 160 may refer to a region that overlaps the emitter electrode when viewed from above. Also, the active portion 160 may include a region sandwiched between the active portions 160 when viewed from above.
  • the active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor).
  • the active portion 160 may further include a diode portion 80 including a diode element such as a freewheeling diode (FWD).
  • FWD freewheeling diode
  • the transistor portions 70 and the diode portions 80 are alternately arranged along a predetermined arrangement direction (X-axis direction in this example) on the upper surface of the semiconductor substrate 10 .
  • the semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT).
  • the region where the transistor section 70 is arranged is denoted by the symbol "I”
  • the region where the diode section 80 is arranged is denoted by the symbol "F”.
  • the direction perpendicular to the arrangement direction in top view may be referred to as the stretching direction (the Y-axis direction in FIG. 1).
  • the transistor section 70 and the diode section 80 may each have a length in the extending direction. That is, the length in the Y-axis direction of the transistor section 70 is greater than the width in the X-axis direction. Similarly, the length in the Y-axis direction of the diode section 80 is greater than the width in the X-axis direction.
  • the extending direction of the transistor portion 70 and the diode portion 80 may be the same as the longitudinal direction of each trench portion described later.
  • the diode section 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10 .
  • the region provided with the cathode region is referred to as the diode section 80 . That is, the diode portion 80 is a region that overlaps with the cathode region when viewed from above.
  • a P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in a region other than the cathode region.
  • the diode section 80 may also include an extension region 81 extending in the Y-axis direction from the diode section 80 to the gate wiring described later.
  • a collector region is provided on the lower surface of the extension region 81 .
  • the transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10 .
  • a gate structure having an N-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film is periodically arranged on the upper surface side of the semiconductor substrate 10 .
  • the semiconductor device 100 may have one or more pads above the semiconductor substrate 10 .
  • the semiconductor device 100 of this example has a gate pad 164 .
  • Semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current sensing pad. Each pad is arranged near the edge 162 .
  • the vicinity of the edge 162 refers to a region between the edge 162 and the emitter electrode in top view.
  • each pad may be connected to an external circuit via a wiring such as a wire.
  • a gate potential is applied to the gate pad 164 .
  • Gate pad 164 is electrically connected to the conductive portion of the gate trench portion of active portion 160 .
  • the semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with oblique lines.
  • the gate wiring of this example has a peripheral gate wiring 130 and an active side gate wiring 131 .
  • the peripheral gate wiring 130 is arranged between the active portion 160 and the edge 162 of the semiconductor substrate 10 when viewed from above.
  • the peripheral gate wiring 130 of this example surrounds the active portion 160 when viewed from above.
  • a region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160 .
  • a well region is formed below the gate wiring.
  • a well region is a P-type region having a higher concentration than a base region, which will be described later, and is formed from the upper surface of the semiconductor substrate 10 to a position deeper than the base region.
  • a region surrounded by the well region in top view may be the active portion 160 .
  • the peripheral gate wiring 130 is connected to the gate pad 164 .
  • the peripheral gate wiring 130 is arranged above the semiconductor substrate 10 .
  • the peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.
  • the active side gate wiring 131 is provided in the active portion 160 .
  • variations in wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10 .
  • the peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160 .
  • the peripheral gate wiring 130 and the active side gate wiring 131 are arranged above the semiconductor substrate 10 .
  • the peripheral gate wiring 130 and the active side gate wiring 131 may be wirings formed of a semiconductor such as polysilicon doped with impurities.
  • the active side gate wiring 131 may be connected to the peripheral gate wiring 130 .
  • the active-side gate wiring 131 of this example extends in the X-axis direction from one outer peripheral gate wiring 130 sandwiching the active portion 160 to the other outer peripheral gate wiring 130 so as to cross the active portion 160 at substantially the center in the Y-axis direction. is provided.
  • the transistor portions 70 and the diode portions 80 may be alternately arranged in the X-axis direction in each divided region.
  • the semiconductor device 100 also includes a temperature sensing portion (not shown), which is a PN junction diode made of polysilicon or the like, and a current detecting portion (not shown) that simulates the operation of the transistor portion provided in the active portion 160. good too.
  • a temperature sensing portion which is a PN junction diode made of polysilicon or the like
  • a current detecting portion (not shown) that simulates the operation of the transistor portion provided in the active portion 160. good too.
  • the semiconductor device 100 of this example includes an edge termination structure portion 90 between the active portion 160 and the edge 162 when viewed from above.
  • the edge termination structure 90 in this example is located between the peripheral gate line 130 and the edge 162 .
  • the edge termination structure 90 reduces electric field concentration on the upper surface side of the semiconductor substrate 10 .
  • Edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf annularly surrounding active portion 160 .
  • FIG. 2 is an enlarged view of area D in FIG. Region D is a region including transistor section 70 , diode section 80 , and active-side gate wiring 131 .
  • the semiconductor device 100 of this example includes a gate trench portion 40 , a dummy trench portion 30 , a well region 11 , an emitter region 12 , a base region 14 and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10 .
  • Each of the gate trench portion 40 and the dummy trench portion 30 is an example of the trench portion.
  • the semiconductor device 100 of this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10 . Emitter electrode 52 and active-side gate line 131 are provided separately from each other.
  • An interlayer insulating film is provided between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is omitted in FIG.
  • a contact hole 54 is provided through the interlayer insulating film of this example. In FIG. 2, each contact hole 54 is hatched with oblique lines.
  • the emitter electrode 52 is provided above the gate trench portion 40 , the dummy trench portion 30 , the well region 11 , the emitter region 12 , the base region 14 and the contact region 15 .
  • Emitter electrode 52 contacts emitter region 12 , contact region 15 and base region 14 on the upper surface of semiconductor substrate 10 through contact hole 54 .
  • the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film.
  • the emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction.
  • the active-side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film.
  • the active-side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction.
  • the active-side gate wiring 131 is not connected to the dummy conductive portion within the dummy trench portion 30 .
  • the emitter electrode 52 is made of a material containing metal.
  • FIG. 2 shows the range in which the emitter electrode 52 is provided.
  • the emitter electrode 52 is made of aluminum or a metal alloy such as an aluminum-silicon alloy such as AlSi, AlSiCu.
  • the emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like under the region made of aluminum or the like. Further, the contact hole may have a plug formed by embedding tungsten or the like so as to be in contact with the barrier metal and the aluminum or the like.
  • the well region 11 is provided so as to overlap with the active side gate wiring 131 .
  • the well region 11 is also provided extending with a predetermined width in a range not overlapping the active side gate wiring 131 .
  • the well region 11 of this example is provided away from the Y-axis direction end of the contact hole 54 on the active side gate wiring 131 side.
  • the well region 11 is a second conductivity type region having a higher doping concentration than the base region 14 .
  • the base region 14 in this example is of P ⁇ type and the well region 11 is of P+ type.
  • Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction.
  • one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction.
  • a plurality of dummy trench portions 30 are provided along the array direction in the diode portion 80 of this example.
  • the gate trench portion 40 is not provided in the diode portion 80 of this example.
  • the gate trench portion 40 of this example connects the two straight portions 39 extending along the extending direction perpendicular to the arrangement direction (the portion of the trench that is linear along the extending direction) and the two straight portions 39 . It may have a tip 41 .
  • the stretching direction in FIG. 2 is the Y-axis direction.
  • At least a portion of the tip portion 41 is preferably provided in a curved shape when viewed from above.
  • the dummy trench portions 30 are provided between the respective straight portions 39 of the gate trench portions 40 .
  • One dummy trench portion 30 may be provided between the straight portions 39, or a plurality of dummy trench portions 30 may be provided.
  • the dummy trench portion 30 may have a linear shape extending in the extending direction, and may have a linear portion 29 and a tip portion 31 like the gate trench portion 40 .
  • the semiconductor device 100 shown in FIG. 2 includes both linear dummy trench portions 30 without tip portions 31 and dummy trench portions 30 with tip portions 31 .
  • the diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30 .
  • Y-axis direction ends of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11 when viewed from above. That is, the bottom of each trench in the depth direction is covered with the well region 11 at the end of each trench in the Y-axis direction. As a result, electric field concentration at the bottom of each trench can be relaxed.
  • a mesa portion is provided between each trench portion in the arrangement direction.
  • the mesa portion refers to a region sandwiched between trench portions inside the semiconductor substrate 10 .
  • the upper end of the mesa portion is the upper surface of the semiconductor substrate 10 .
  • the depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion.
  • the mesa portion of this example extends in the extension direction (Y-axis direction) along the trench on the upper surface of the semiconductor substrate 10 .
  • the transistor section 70 is provided with a mesa section 60 and the diode section 80 is provided with a mesa section 61 .
  • simply referring to the mesa portion refers to the mesa portion 60 and the mesa portion 61 respectively.
  • a base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region arranged closest to the active-side gate wiring 131 is referred to as a base region 14-e.
  • FIG. 2 shows the base region 14-e arranged at one end in the extending direction of each mesa, the base region 14-e is also arranged at the other end of each mesa. It is In each mesa portion, at least one of the first conductivity type emitter region 12 and the second conductivity type contact region 15 may be provided in a region sandwiched between the base regions 14-e when viewed from above.
  • the emitter region 12 in this example is of N+ type and the contact region 15 is of P+ type. Emitter region 12 and contact region 15 may be provided between base region 14 and the upper surface of semiconductor substrate 10 in the depth direction.
  • the mesa portion 60 of the transistor portion 70 has the emitter region 12 exposed on the upper surface of the semiconductor substrate 10 .
  • the emitter region 12 is provided in contact with the gate trench portion 40 .
  • the mesa portion 60 in contact with the gate trench portion 40 may be provided with the contact region 15 exposed to the upper surface of the semiconductor substrate 10 .
  • Each of the contact region 15 and the emitter region 12 in the mesa portion 60 is provided from one trench portion to the other trench portion in the X-axis direction.
  • the contact regions 15 and the emitter regions 12 of the mesa portion 60 are alternately arranged along the extension direction (Y-axis direction) of the trench portion.
  • the contact regions 15 and the emitter regions 12 of the mesa portion 60 may be provided in stripes along the extending direction (Y-axis direction) of the trench portion.
  • an emitter region 12 is provided in a region in contact with the trench portion, and a contact region 15 is provided in a region sandwiched between the emitter regions 12 .
  • the mesa portion 61 of the diode portion 80 is not provided with the emitter region 12 .
  • a base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61 .
  • a contact region 15 may be provided in a region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61 so as to be in contact with each base region 14-e.
  • a base region 14 may be provided in a region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61 .
  • the base region 14 may be arranged over the entire region sandwiched between the contact regions 15 .
  • a contact hole 54 is provided above each mesa portion.
  • the contact hole 54 is arranged in a region sandwiched between the base regions 14-e.
  • the contact hole 54 of this example is provided above each region of the contact region 15 , the base region 14 and the emitter region 12 .
  • Contact hole 54 is not provided in a region corresponding to base region 14 - e and well region 11 .
  • the contact hole 54 may be arranged in the center of the mesa portion 60 in the arrangement direction (X-axis direction).
  • an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10 .
  • a P + -type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided.
  • Cathode region 82 and collector region 22 are provided between lower surface 23 of semiconductor substrate 10 and buffer region 20 . In FIG. 2, the boundary between cathode region 82 and collector region 22 is indicated by a dotted line.
  • the cathode region 82 is arranged apart from the well region 11 in the Y-axis direction. As a result, the distance between the P-type region (well region 11), which has a relatively high doping concentration and is formed to a deep position, and the cathode region 82 can be secured, and the withstand voltage can be improved.
  • the end of the cathode region 82 in the Y-axis direction in this example is located farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction.
  • the end of the cathode region 82 in the Y-axis direction may be arranged between the well region 11 and the contact hole 54 .
  • FIG. 3 is a diagram showing an example of the ee cross section in FIG.
  • the ee section is the XZ plane passing through emitter region 12 and cathode region 82 .
  • the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52 and a collector electrode 24 in the cross section.
  • the interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10 .
  • the interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with an impurity such as boron or phosphorus, a thermal oxide film, and other insulating films.
  • the contact hole 54 described with reference to FIG. 2 is provided in the interlayer insulating film 38 .
  • the emitter electrode 52 is provided above the interlayer insulating film 38 .
  • Emitter electrode 52 is in contact with top surface 21 of semiconductor substrate 10 through contact hole 54 in interlayer insulating film 38 .
  • a collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10 .
  • Emitter electrode 52 and collector electrode 24 are made of a metal material such as aluminum.
  • the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.
  • the semiconductor substrate 10 has an N-type or N ⁇ type drift region 18 .
  • Drift region 18 is provided in each of transistor section 70 and diode section 80 .
  • an N+ type emitter region 12 and a P ⁇ type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. As shown in FIG. A drift region 18 is provided below the base region 14 .
  • the mesa portion 60 may be provided with an N+ type accumulation region 16 . Accumulation region 16 is disposed between base region 14 and drift region 18 .
  • the emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and provided in contact with the gate trench portion 40 .
  • the emitter region 12 may be in contact with trench portions on both sides of the mesa portion 60 .
  • Emitter region 12 has a higher doping concentration than drift region 18 .
  • the base region 14 is provided below the emitter region 12 .
  • the base region 14 in this example is provided in contact with the emitter region 12 .
  • the base region 14 may contact trench portions on both sides of the mesa portion 60 .
  • the accumulation region 16 is provided below the base region 14 .
  • the accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18 . That is, the accumulation region 16 has a higher donor concentration than the drift region 18 .
  • the carrier injection promoting effect IE effect
  • the accumulation region 16 may be provided so as to cover the entire bottom surface of the base region 14 in each mesa portion 60 .
  • a P ⁇ type base region 14 is provided in the mesa portion 61 of the diode portion 80 in contact with the upper surface 21 of the semiconductor substrate 10 .
  • a drift region 18 is provided below the base region 14 .
  • An accumulation region 16 may be provided below the base region 14 in the mesa portion 61 .
  • An N+ type buffer region 20 may be provided under the drift region 18 in each of the transistor section 70 and the diode section 80 .
  • the doping concentration of buffer region 20 is higher than the doping concentration of drift region 18 .
  • Buffer region 20 may have a concentration peak with a higher doping concentration than drift region 18 .
  • the doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak.
  • an average value of doping concentrations in a region where the doping concentration distribution is substantially flat may be used as the doping concentration of the drift region 18.
  • the buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10 .
  • the concentration peak of the buffer region 20 may be provided at the same depth position as the chemical concentration peak of hydrogen (protons) or phosphorus, for example.
  • Buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the bottom edge of base region 14 from reaching P + -type collector region 22 and N + -type cathode region 82 .
  • a P+ type collector region 22 is provided under the buffer region 20 in the transistor section 70 .
  • the acceptor concentration of collector region 22 is higher than the acceptor concentration of base region 14 .
  • Collector region 22 may contain the same acceptor as base region 14 or may contain a different acceptor.
  • the acceptor of the collector region 22 is boron, for example.
  • An N+ type cathode region 82 is provided under the buffer region 20 in the diode section 80 .
  • the donor concentration in cathode region 82 is higher than the donor concentration in drift region 18 .
  • the donor for cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as donors and acceptors in each region are not limited to the above examples.
  • Collector region 22 and cathode region 82 are exposed at lower surface 23 of semiconductor substrate 10 and connected to collector electrode 24 .
  • Collector electrode 24 may contact the entire bottom surface 23 of semiconductor substrate 10 .
  • Emitter electrode 52 and collector electrode 24 are made of a metal material such as aluminum.
  • One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10 .
  • Each trench portion extends from the upper surface 21 of the semiconductor substrate 10 through the base region 14 to below the base region 14 .
  • the contact region 15 and/or the storage region 16 are provided, each trench section also passes through these doping regions.
  • the fact that the trench penetrates the doping region is not limited to the order of forming the doping region and then forming the trench.
  • a structure in which a doping region is formed between the trench portions after the trench portions are formed is also included in the structure in which the trench portion penetrates the doping regions.
  • the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30 .
  • the diode section 80 is provided with the dummy trench section 30 and is not provided with the gate trench section 40 .
  • the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22 .
  • the gate trench portion 40 has a gate trench provided in the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42 and a gate conductive portion 44.
  • a gate insulating film 42 is provided to cover the inner wall of the gate trench.
  • the gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench.
  • the gate conductive portion 44 is provided inside the gate insulating film 42 inside the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10 from each other.
  • the gate conductive portion 44 is formed of a conductive material such as polysilicon.
  • the gate conductive portion 44 may be provided longer than the base region 14 in the depth direction.
  • the gate trench portion 40 in the cross section is covered with the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10 .
  • the gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44 , a channel is formed by an electron inversion layer in the surface layer of the interface contacting the gate trench portion 40 in the base region 14 .
  • the dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section.
  • the dummy trench section 30 has a dummy trench provided in the upper surface 21 of the semiconductor substrate 10 , a dummy insulating film 32 and a dummy conductive section 34 .
  • the dummy conductive portion 34 is electrically connected to the emitter electrode 52 .
  • a dummy insulating film 32 is provided to cover the inner wall of the dummy trench.
  • the dummy conductive portion 34 is provided inside the dummy trench and inside the dummy insulating film 32 .
  • the dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10 .
  • the dummy conductive portion 34 may be made of the same material as the gate conductive portion 44 .
  • the dummy conductive portion 34 is made of a conductive material such as polysilicon.
  • the dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.
  • the gate trench portion 40 and the dummy trench portion 30 of this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10 .
  • the bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross section) convex downward.
  • the depth position of the lower end of the gate trench portion 40 is defined as Zt.
  • the semiconductor device 100 of this example includes a P-type lower end region 202 provided in contact with the lower end of the trench portion.
  • the doping concentration of bottom region 202 may be less than or equal to the doping concentration of base region 14 .
  • the doping concentration of the bottom region 202 in this example is less than the doping concentration of the base region 14 .
  • the lower end region 202 is arranged apart from the base region 14 .
  • An N-type region (at least one of the accumulation region 16 and the drift region 18 in this example) is provided between the lower end region 202 and the base region 14 .
  • the lower end region 202 is provided continuously so as to contact the lower ends of two or more trench portions in the X-axis direction. That is, the lower end region 202 is provided so as to cover the mesa portion between the trench portions. Bottom region 202 may cover multiple mesas.
  • the bottom end region 202 may be in contact with the bottom ends of two or more trench portions in each transistor portion 70 . Also, the lower end region 202 may be in contact with the lower ends of two or more gate trench portions 40 in each transistor portion 70 . The bottom region 202 may contact the bottom ends of all the trench portions in at least one transistor portion 70 . Also, the lower end region 202 may be in contact with the lower ends of all the gate trench portions 40 in at least one transistor portion 70 .
  • the bottom end region 202 may be in contact with the bottom ends of two or more trench portions in each diode portion 80 .
  • the bottom region 202 may contact the bottom ends of all the trench portions in at least one diode portion 80 .
  • the lower end region 202 is provided extending in the Y-axis direction.
  • the length of the lower end region 202 in the Y-axis direction is shorter than the length of the trench portion in the Y-axis direction.
  • the length of the lower end region 202 in the Y-axis direction may be 50% or more, 70% or more, or 90% or more of the length of the trench portion in the Y-axis direction.
  • the lower end region 202 By providing the lower end region 202, it is possible to suppress the potential rise in the vicinity of the lower end of the trench portion when the semiconductor device 100 is turned on. Therefore, the gradient (dv/dt) of the waveform of the emitter-collector voltage during turn-on can be reduced, and noise in the voltage or current waveform during switching can be reduced.
  • the potential of the lower end region 202 is different from the potential of the emitter electrode 52 .
  • the lower end region 202 is arranged apart from the base region 14 connected to the emitter electrode 52 in the Z-axis direction.
  • the lower end region 202 is arranged apart from the well region connected to the emitter electrode 52 when viewed from above.
  • the active portion 160 may have a portion where the lower end region 202 is not provided in at least one of the X-axis direction and the Y-axis direction.
  • FIG. 4 is a diagram showing an arrangement example of the well region 11 and the lower end region 202 in top view.
  • the bottom region 202 in this example is provided in the active portion 160 .
  • the lower end region 202 may be provided in an area of 50% or more of the active portion 160 in top view, may be provided in an area of 70% or more, or may be provided in an area of 90% or more.
  • a well region 11 is provided below the gate wiring shown in FIG.
  • the well region 11 and the lower end region 202 are arranged at different positions when viewed from above. As shown in FIG. 4, the well region 11 may be arranged so as to surround the lower end region 202 in top view. If the bottom region 202 is divided into multiple regions, as shown in FIG. 4, the well region 11 may surround each bottom region 202 .
  • the semiconductor device 100 includes a high resistance region 204 arranged between the well region 11 and the lower end region 202 in top view.
  • the high resistance region 204 may be arranged at a position in contact with the well region 11 in the active portion 160 .
  • the high resistance region 204 is hatched with oblique lines.
  • the high resistance region 204 may surround the lower end region 202 in top view.
  • the high resistance region 204 may surround the active portion 160 in top view.
  • the high resistance region 204 is a P ⁇ type region with a lower doping concentration than the lower end region 202 .
  • the high resistance region 204 is a region with higher electrical resistance than the lower end region 202 .
  • the high resistance region 204 may connect the bottom region 202 and the well region 11 .
  • the lower end region 202 can be prevented from becoming the same potential as the well region 11 .
  • the lower end region 202 is prevented from becoming the emitter potential, and the transistor section 70 and the diode section 80 can be operated.
  • the high resistance region 204 is provided in the entire region of the active portion 160 where the lower end region 202 is not provided. If there is a portion in the active portion 160 where the lower end region 202 is not provided, the high resistance region 204 may be provided in that portion as well.
  • the high resistance region 204 arranged inside the active portion 160 may be surrounded by the lower end region 202 when viewed from above.
  • FIG. 5A is a diagram showing an example of the ff section in FIG.
  • the ff cross section is the XZ plane passing through the lower end region 202 , the high resistance region 204 and the well region 11 . That is, the ff section is the XZ plane near the boundary between the active portion 160 and the well region 11 .
  • FIG. 5A shows the structure of the semiconductor substrate 10 and omits the configuration of electrodes, insulating films, and the like arranged above and below the semiconductor substrate 10 .
  • the gate trench portion 40 is denoted by G
  • the dummy trench portion 30 is denoted by E. As shown in FIG.
  • the ff cross section shown in FIG. 5A includes the transistor section 70 arranged at the end in the X-axis direction among the plurality of transistor sections 70 .
  • the structure of the transistor section 70 is similar to that of the transistor section 70 described with reference to FIGS. 5A, one dummy trench portion 30 is arranged between two gate trench portions 40 like G/E/G/E/. Two dummy trench portions 30 may be arranged between two gate trench portions 40 like E/E/.
  • the arrangement of gate trench portions 40 and dummy trench portions 30 may have other structures.
  • a boundary portion 210 is defined between the transistor portion 70 and the well region 11 shown in FIG. 5A.
  • the center of the gate trench portion 40 (G) arranged at the end in the X-axis direction among the gate trench portions 40 (G) in which the emitter regions 12 are provided adjacent to each other is the end portion of the transistor portion 70 in the X-axis direction. and
  • the range of the boundary portion 210 in the X-axis direction is from the gate trench portion 40 (G) to the well region 11 .
  • the well region 11 is provided from the upper surface 21 of the semiconductor substrate 10 to below the base region 14 .
  • the well region 11 is a P + -type region with a higher doping concentration than the base region 14 .
  • One or more trench portions are provided in the boundary portion 210 .
  • One or more gate trench portions 40 and one or more dummy trench portions 30 are provided in the boundary portion 210 of this example.
  • the arrangement of the trench portions in the X-axis direction in the boundary portion 210 may be the same as or different from that in the transistor portion 70 .
  • a base region 14 is provided in the mesa portion of the boundary portion 210 .
  • a contact region 15 may be provided between the base region 14 and the top surface 21 of the semiconductor substrate 10 .
  • the accumulation region 16 may be provided in one or more mesa portions closest to the transistor portion 70 among the mesa portions of the boundary portion 210 .
  • the lower end region 202 in this example is a P-type region with a lower doping concentration than the well region 11 .
  • the lower end region 202 is arranged in at least a partial region of the transistor section 70 .
  • the lower end region 202 of this example extends from the end of the transistor portion 70 toward the well region 11 side.
  • bottom region 202 may terminate at the edge of transistor portion 70 or may terminate within transistor portion 70 .
  • the high resistance region 204 is a P ⁇ type region with a lower doping concentration than the lower end region 202 .
  • the high-resistance region 204 is provided in at least part of the boundary portion 210 in the X-axis direction.
  • the high-resistance region 204 may be provided over the entire boundary portion 210 in the X-axis direction.
  • the high resistance region 204 may be in contact with the lower end region 202 and may be in contact with the well region 11 .
  • the high resistance region 204 in this example contacts both the bottom region 202 and the well region 11 .
  • the high resistance region 204 and the emitter region 12 may be arranged apart from each other when viewed from above. In other words, the high resistance region 204 may not be provided in the transistor section 70 .
  • the distance between the high-resistance region 204 and the emitter region 12 in top view may be equal to or greater than the width of the mesa portion in the X-axis direction.
  • a part of the high-resistance region 204 and a part of the accumulation region 16 may be arranged so as to overlap when viewed from above.
  • the storage area 16 may also be provided at the border 210 .
  • the high resistance region 204 may have a portion provided at the same depth position as the lower end region 202 . That is, the range in the Z-axis direction in which the high resistance region 204 is provided and the range in the Z-axis direction in which the lower end region 202 is provided may at least partially overlap.
  • the high-resistance region 204 may be in contact with the lower end of the trench portion arranged at the boundary portion 210 . At least one of the drift region 18 and the accumulation region 16 may be disposed between the high resistance region 204 and the base region 14 .
  • Wz be the width of the high-resistance region 204 in the Z-axis direction.
  • Wz the maximum width of the high-resistance region 204 in the Z-axis direction may be used.
  • Lx be the second length of the high-resistance region 204 connecting the well region 11 and the lower end region 202 in the X-axis direction.
  • the length Lx may be the maximum length of the high-resistance region 204 in the X-axis direction.
  • Length Lx is preferably greater than width Wz.
  • the length Lx may be twice or more the width Wz, may be five times or more, may be ten times or more, or may be one hundred times or more.
  • the high resistance region 204 may be in contact with the lower ends of two or more trench portions in the X-axis direction.
  • the high-resistance region 204 may be in contact with the lower ends of all trench portions provided in the boundary portion 210 .
  • the high resistance region 204 may cover two or more mesas in the X-axis direction.
  • the high resistance region 204 may be in contact with the bottom end of at least one gate trench portion 40 .
  • the high resistance region 204 may be in contact with the lower ends of two or more gate trench portions 40 .
  • the high resistance region 204 may be in contact with the lower ends of all the gate trench portions 40 provided in the boundary portion 210 .
  • FIG. 5B is a diagram showing an example of the net doping concentration distribution of the aa cross section and the bb cross section in FIG. 5A.
  • the horizontal axis in FIG. 5B indicates the position in the Z-axis direction with the upper surface 21 of the semiconductor substrate 10 as a reference position (0 ⁇ m).
  • the net doping concentration distribution along the aa cross section in the transistor portion 70 is indicated by a dotted line
  • the net doping concentration distribution along the bb cross section in the boundary portion 210 is indicated by a solid line.
  • An emitter region 12 and a base region 14 are provided in the vicinity of the upper surface 21 of the aa section of the transistor section 70 .
  • a contact region 15 and a base region 14 are provided in the vicinity of the upper surface 21 of the bb cross section of the boundary portion 210 .
  • the net doping concentration profile of high resistance region 204 (solid line) is lower than the net doping concentration profile of bottom region 202 (dotted line).
  • the net doping concentration distributions of high resistance region 204 and bottom region 202 may each have a peak or maximum.
  • the full width at half maximum (FWHM1) of high resistance region 204 may be less than the full width at half maximum (FWHM2) of bottom region 202 .
  • FIG. 6 is a diagram showing an example of the doping concentration distribution in the cc section (X-axis direction) of FIG. 5A.
  • FIG. 6 shows the concentration distribution in the high resistance region 204 and the lower end region 202 near the high resistance region 204 and the well region 11 .
  • the cc cross section may be the cross section at the peak position Zp in the net doping concentration distribution of the lower end region 202 or the high resistance region 204, respectively, shown in FIG. 5B.
  • the doping concentration of the bottom region 202 be D 202 .
  • the doping concentration D 202 of the lower end region 202 may be the maximum value of the doping concentration in the X-axis direction in the lower end region 202 .
  • the doping concentration of the well region 11 be D11 .
  • the maximum doping concentration in the well region 11 may be used.
  • D 204 be the doping concentration of the high resistance region 204 .
  • the doping concentration D 204 of the high-resistance region 204 may use the average value of the doping concentration in the X-axis direction in the high-resistance region 204, or may use the minimum value.
  • Doping concentration D 204 is less than doping concentration D 202 .
  • the doping concentration D 204 may be 10% or less, 5% or less, or 1% or less of the doping concentration D 202 of the bottom region 202 .
  • the doping concentration D 204 of the high resistance region 204 may be greater than or equal to 1 ⁇ 10 14 /cm 3 and less than or equal to 1 ⁇ 10 17 /cm 3 .
  • the doping concentration D 204 of the high resistance region 204 may be greater than or equal to 1 ⁇ 10 15 /cm 3 .
  • the doping concentration D 204 of the high resistance region 204 may be 1 ⁇ 10 16 /cm 3 or less.
  • Db be the doping concentration at both ends of the high-resistance region 204 in the X-axis direction.
  • the doping concentration Db is the concentration between the maximum doping concentration in the bottom region 202 and the minimum doping concentration in the high resistance region 204 .
  • the doping concentration Db may be the middle concentration between the maximum doping concentration in the bottom region 202 and the minimum doping concentration in the high resistance region 204 .
  • a boundary position between the lower end region 202 and the high resistance region 204 is defined as the position where the doping concentration first becomes Db in the direction from the lower end region 202 toward the high resistance region 204 .
  • the position where the doping concentration first becomes Db is defined as the boundary position between the well region 11 and the high resistance region 204 .
  • the high resistance region 204 may have an overall doping concentration of Db or less.
  • the high resistance region 204 may have a flat portion 206 with a flat doping concentration distribution in the X-axis direction.
  • a flat doping concentration distribution means that the variation of the doping concentration is ⁇ 10% or less.
  • the flat portion 206 may have a length in the X-axis direction of 1 ⁇ m or more, 5 ⁇ m or more, or 10 ⁇ m or more.
  • the length of the flat portion 206 may be 50% or more of the length Lx of the high resistance region 204, or may be 70% or more.
  • high resistance region 204 may include portions with a doping concentration greater than Db .
  • High resistance region 204 may include a portion with a higher doping concentration than bottom region 202 .
  • the doping concentration distribution in the X-axis direction in the high resistance region 204 may have a peak.
  • the average doping concentration of the high resistance region 204 is lower than the average doping concentration of the bottom region 202 .
  • FIG. 7 is a diagram showing an example of a gg section in FIG.
  • the gg cross section is the YZ plane passing through the lower end region 202 , the high resistance region 204 and the well region 11 .
  • the gg cross section passes through the mesa portion of the transistor portion 70 .
  • the position where the gate trench portion 40 is projected on the gg cross section is indicated by a broken line.
  • FIG. 7 shows the structure of the semiconductor substrate 10 and omits the configuration of electrodes, insulating films, etc. arranged above and below the semiconductor substrate 10 .
  • the region between the transistor portion 70 and the well region 11 is defined as the boundary portion 210 .
  • the end of the emitter region 12 arranged at the end in the Y-axis direction among the emitter regions 12 is the end of the transistor section 70 in the Y-axis direction.
  • the range of the boundary portion 210 in the Y-axis direction is from the emitter region 12 to the well region 11 .
  • the emitter regions 12 and the contact regions 15 are alternately arranged along the Y-axis direction on the upper surface 21 of the transistor section 70 .
  • a contact region 15 is provided on the upper surface 21 of the boundary portion 210 .
  • the accumulation region 16 of this example extends from the end of the transistor section 70 toward the well region 11 side.
  • the storage region 16 may terminate at the edge of the transistor portion 70 or may terminate within the transistor portion 70 .
  • the lower end region 202 of this example extends from the end of the transistor section 70 toward the well region 11 side.
  • bottom region 202 may terminate at the edge of transistor portion 70 or may terminate within transistor portion 70 .
  • the accumulation region 16 may extend toward the well region 11 from the lower end region 202 .
  • the high-resistance region 204 is provided in at least part of the boundary 210 in the Y-axis direction.
  • the high-resistance region 204 may be provided over the entire boundary portion 210 in the Y-axis direction.
  • the high resistance region 204 may be in contact with the lower end region 202 and may be in contact with the well region 11 .
  • the high resistance region 204 in this example contacts both the bottom region 202 and the well region 11 .
  • the high resistance region 204 may overlap the accumulation region 16 when viewed from above. That is, the end portion of the accumulation region 16 may be inside the high resistance region 204 or inside the boundary portion 210 when viewed from above. In another example, the high resistance region 204 may not overlap the accumulation region 16 in top view.
  • the end portion of the accumulation region 16 may be located inside (-Y-axis direction side) of the high-resistance region 204 or the boundary portion 210 when viewed from above.
  • the high resistance region 204 may be provided so as not to overlap with the transistor portion 70 in the cross section. In another example, the high resistance region 204 may overlap the transistor section 70 in the cross section.
  • Ly be the first length of the high-resistance region 204 that connects the well region 11 and the lower end region 202 in the Y-axis direction.
  • the length Ly may be the maximum length of the high-resistance region 204 in the Y-axis direction.
  • the Y-axis direction is the longitudinal direction of the trench
  • the X-axis direction is the lateral direction of the trench.
  • a ratio (Ly/Lx) between the length Ly and the length Lx may be 0.9 or more and 1.1 or less. That is, length Ly and length Lx may be substantially equal. As a result, variations in breakdown voltage in the XY plane can be reduced.
  • the length Ly may be greater than the width Wz.
  • the length Ly may be two times or more, five times or more, ten times or more, or one hundred times or more the width Wz.
  • FIG. 8 shows the results of measuring the relationship between the doping concentration of the high resistance region 204 and the withstand voltage of the portion where the high resistance region 204 is formed.
  • the breakdown voltage VB1 indicates the breakdown voltage of the portion where the lower end region 202 is formed
  • the breakdown voltage VB2 indicates the breakdown voltage when neither the lower end region 202 nor the high resistance region 204 is formed.
  • the doping concentration of the high resistance region 204 may be set so that the breakdown voltage of the portion where the high resistance region 204 is provided is higher than the breakdown voltage VB2 and lower than the breakdown voltage VB1.
  • the lower limit of the setting range of the doping concentration of the high-resistance region 204 is 1 ⁇ 10 14 /cm 3 or more and 1 ⁇ 10 15 /cm 3 or less.
  • the upper limit of the setting range is 1 ⁇ 10 15 /cm 3 or more and 1 ⁇ 10 16 /cm 3 or less.
  • FIG. 8 shows two setting ranges A and B as examples of setting ranges.
  • the setting range A is 1 ⁇ 10 14 /cm 3 or more and 1 ⁇ 10 16 /cm 3 or less.
  • the setting range B is 7 ⁇ 10 14 /cm 3 or more and 6 ⁇ 10 15 /cm 3 or less.
  • the ratio ⁇ of the peak doping concentration of the high-resistance region 204 to the peak doping concentration of the lower end region 202 may be 0.05 or more, 0.08 or more, or 0.1 or more. and may be 0.3 or more. Also, the ratio ⁇ may be 0.9 or less, 0.8 or less, 0.6 or less, or 0.5 or less.
  • FIG. 9 is a diagram showing another arrangement example of the high-resistance regions 204 when viewed from above.
  • the high resistance region 204 of this example is partially provided in the region between the bottom end region 202 and the well region 11 . That is, the region (boundary portion 210) between the lower end region 202 and the well region 11 has a portion where the high resistance region 204 is provided and a portion where it is not provided.
  • a drift region 18 may be provided instead of the high resistance region 204 in the region where the high resistance region 204 is not provided.
  • the high resistance region 204 of this example is arranged at the corner of the active portion 160 surrounded by the well region 11 .
  • the active portion 160 surrounded by the well region 11 has sides parallel to the Y-axis and sides parallel to the X-axis.
  • the high resistance region 204 may be provided at a position where the two sides intersect. As shown in FIG. 9, the high resistance regions 204 may be located at multiple corners. Since the electric field tends to concentrate on these corners, it is preferable to improve the withstand voltage by providing the high resistance region 204 .
  • FIG. 10 is a diagram showing another arrangement example of the high-resistance regions 204 when viewed from above.
  • the high resistance region 204 of this example has a first high resistance portion 205-1 and a second high resistance portion 205-2.
  • the second high resistance portion 205-2 (straight portion) is a region having a lower doping concentration than the first high resistance portion 205-1 (corner portion).
  • the first high resistance portion 205-1 is preferably arranged in a portion that requires a higher withstand voltage.
  • the first high-resistance portion 205-1 may be arranged at the corners in the same manner as the high-resistance region 204 described with reference to FIG.
  • the second high resistance portion 205-2 is arranged in a region between the lower end region 202 and the well region 11 where the first high resistance portion 205-1 is not provided. As a result, variations in breakdown voltage in the XY plane can be suppressed.
  • the doping concentration is lower than that of the lower end region 202 in both the first high resistance portion 205-1 and the second high resistance portion 205-2.
  • the high resistance region 204 may have a lower doping concentration than the base region 14.
  • the maximum doping concentration in the high resistance region 204 may be less than half the maximum doping concentration in the base region 14, may be less than 10%, or may be less than 1%.
  • the maximum doping concentration in the bottom region 202 may be less than the maximum doping concentration in the base region 14 and greater than the maximum doping concentration in the high resistance region 204 .
  • FIG. 11A and 11B are diagrams showing a part of the steps of the method for manufacturing the semiconductor device 100.
  • FIG. 11 In the manufacturing method of the semiconductor device 100, each configuration described with reference to FIGS. 1 to 10 is formed.
  • the process shown in FIG. 11 includes a first region forming step S1100, a trench forming step S1102, a second region forming step S1104 and a trench structure forming step S1106.
  • doping regions arranged on the upper surface 21 side of the semiconductor substrate 10 are formed.
  • the doping regions include, for example, at least one of well region 11 , emitter region 12 , base region 14 , contact region 15 and storage region 16 .
  • the drift region 18 may be a region in which these doping regions are not formed.
  • trenches are formed in the upper surface 21 of the semiconductor substrate 10. As shown in FIG. A trench is a groove for forming each trench portion. Each trench is formed from top surface 21 to a depth reaching drift region 18 . At least the conductive portion in the trench is not formed in the trench forming step S1102. An insulating film in the trench may or may not be formed.
  • the lower end region 202 and the high resistance region 204 are formed.
  • P-type dopant ions may be implanted into the semiconductor substrate 10 through the trench.
  • P-type dopant ions may be implanted from the upper surface 21 of the semiconductor substrate 10 while masking portions other than the trench. As a result, P-type dopant ions can be easily implanted into the region in contact with the lower end of the trench.
  • the semiconductor substrate 10 is heat-treated after the dopant is implanted.
  • a conductive portion and an insulating film are formed inside each trench.
  • the insulating layer may be formed by thermally oxidizing the inner wall of the trench.
  • a conductive portion may be formed by filling a conductive material such as polysilicon into the trench in which the insulating layer is formed.
  • FIG. 12 is a diagram illustrating an example of the second region forming step S1104.
  • the second region forming step S1104 of this example comprises a first implanting step S1201 and a second implanting step S1202. Either the first injection step S1201 or the second injection step S1202 may be performed first.
  • the first implantation step S1201 P-type dopant ions are implanted at a predetermined concentration (/cm 2 ) into the region where the bottom region 202 is to be formed.
  • P-type dopant ions are implanted in a different concentration (/cm 2 ) from the first implantation step S1201 into the region where the high resistance region 204 is to be formed.
  • the concentration (dose amount) in the second implantation step S1202 is lower than the concentration in the first implantation step S1201.
  • dopants may be implanted into the semiconductor substrate 10 through the trenches 45 in both the first implantation step S1201 and the second implantation step S1202.
  • mask 300 may mask areas other than trenches 45 .
  • the dopant implanted through trench 45 is diffused by heat treatment. Thereby, the lower end region 202 and the high resistance region 204 which are continuous in the XY plane can be formed.
  • FIG. 13 is a diagram explaining another example of the second region forming step S1104.
  • the second region forming step S1104 of this example comprises a first injection step S1301 and a second injection step S1302. Either the first injection step S1301 or the second injection step S1302 may be performed first.
  • the first implantation step S1301 P-type dopant ions of a predetermined concentration (/cm 2 ) are implanted into both the region where the high resistance region 204 is to be formed and the region where the lower end region 202 is to be formed.
  • a predetermined concentration (/cm 2 ) of P-type dopant ions are further implanted into the region where the bottom region 202 is to be formed.
  • no dopant ions are implanted in the region where the high resistance region 204 is to be formed.
  • dopants may be implanted into the semiconductor substrate 10 through the trenches 45 in both the first implantation step S1301 and the second implantation step S1302.
  • the dopant implanted through trench 45 is diffused by heat treatment. Thereby, the lower end region 202 and the high resistance region 204 which are continuous in the XY plane can be formed.
  • FIG. 14 is a diagram explaining another example of the second region forming step S1104.
  • the second region forming step S1104 of this example comprises a first implanting step S1401 and a second implanting step S1402. Either the first injection step S1401 or the second injection step S1402 may be performed first, or may be performed simultaneously.
  • the first implantation step S1401 P-type dopant ions are implanted at a predetermined concentration (/cm 2 ) into the region where the bottom region 202 is to be formed.
  • P-type dopant ions of a predetermined concentration (/cm 2 ) are implanted into the region where the high resistance region 204 is to be formed.
  • the dopant of the second conductivity type is implanted into a region 203 of the region where the high resistance region 204 is to be formed, which is distant from the region where the lower end region 202 is to be formed. Region 203 may also be remote from well region 11 .
  • the distance in the X-axis direction between the region 203 and the lower end region 202 may be greater than the width of one mesa portion of the boundary portion 210 in the X-axis direction.
  • the distance in the X-axis direction between the region 203 and the well region 11 may also be greater than the width of one mesa portion of the boundary portion 210 in the X-axis direction.
  • the implanted dopant is diffused toward the region where the lower end region 202 is to be formed.
  • the heat treatment also diffuses the dopant in the direction of the well region 11 .
  • the heat treatment is preferably performed at a temperature and for a time that allows the dopant implanted into region 203 to reach bottom region 202 and well region 11 .
  • the implantation concentration (/cm 2 ) in the second implantation step S1402 may be lower than, the same as, or higher than the implantation concentration (/cm 2 ) in the first implantation step S1401.
  • the dopant implanted in the second implantation step S1402 diffuses toward the bottom region 202 and the well region 11 even though the implantation concentration in the second implantation step S1402 is greater than or equal to the implantation concentration in the first implantation step S1401. Therefore, the average doping concentration in the high-resistance region 204 can be reduced.
  • FIG. 15 is a diagram showing another example of doping concentration distribution in the X-axis direction.
  • FIG. 15 shows the concentration distribution in the high-resistance region 204, the lower end region 202 in the vicinity of the high-resistance region 204, and the well region 11.
  • FIG. The doping concentrations of the bottom region 202 and the well region 11 are the same as in the example of FIG.
  • the high resistance region 204 of this example is formed by the method described in FIG.
  • the high-resistance region 204 of this example has a doping concentration peak 207 in the direction connecting the lower end region 202 and the well region 11 (for example, the X-axis direction).
  • the apex of peak 207 may be plateau 206 .
  • the high resistance region 204 may have one or more valleys 208 in the doping concentration distribution along the X-axis.
  • a valley 208 may be positioned between the peak 207 and the bottom region 202 .
  • a valley 208 may be positioned between the peak 207 and the well region 11 .
  • the doping concentration of valley 208 may be the doping concentration D 204 of high resistance region 204 .
  • the doping concentration D 204 may be 10% or less, 5% or less, or 1% or less of the doping concentration D 202 of the bottom region 202 .
  • Doping concentration D 204 may be higher than the doping concentration of drift region 18 .
  • the doping concentration of peak 207 be Dp .
  • the doping concentration Dp of the peak 207 may be greater than or equal to 0.5 times and less than or equal to 1.5 times the doping concentration D 202 of the bottom region 202 .
  • the doping concentration Dp may be greater than or equal to 0.7 times the doping concentration D 202 , and may be greater than or equal to 0.9 times.
  • the doping concentration Dp may be 1.3 times or less the doping concentration D202 , or may be 1.1 times or less.
  • the doping concentration D p may be the same as the doping concentration D 202 .
  • FIG. 16 is a diagram showing another example of doping concentration distribution in the X-axis direction.
  • FIG. 16 shows the concentration distribution in the high resistance region 204, the lower end region 202 near the high resistance region 204, and the well region 11.
  • FIG. The doping concentrations of the bottom region 202 and the well region 11 are the same as in the example of FIG.
  • the high resistance region 204 in this example has a plurality of doping concentration peaks 207 .
  • the doping concentration Dp of each peak 207 may be the same or different. For example, closer to the well region 11, the doping concentration Dp of the peak 207 may increase.
  • Multiple peaks 207 can be formed by locally implanting dopants at multiple locations in the region where high resistance region 204 is to be formed.
  • FIG. 17 is a diagram showing another example of doping concentration distribution in the X-axis direction.
  • FIG. 17 shows the concentration distribution in the high resistance region 204, the lower end region 202 near the high resistance region 204, and the well region 11.
  • FIG. The doping concentrations of the bottom region 202 and the well region 11 are the same as in the example of FIG.
  • the high resistance region 204 in this example has a doping concentration valley 208 .
  • the valley portion 208 of this example is arranged closer to the lower end region 202 than the center of the high resistance region 204 in the X-axis direction.
  • the slope of the slope from the valley 208 to the well region 11 may be gentler than the slope of the slope from the valley 208 to the bottom region 202 .
  • FIG. 18 is a diagram showing another example of doping concentration distribution in the X-axis direction.
  • FIG. 18 shows the concentration distribution in the high-resistance region 204, the lower end region 202 in the vicinity of the high-resistance region 204, and the well region 11.
  • FIG. The doping concentrations of the bottom region 202 and the well region 11 are the same as in the example of FIG.
  • the high resistance region 204 in this example has a doping concentration valley 208 .
  • the valley portion 208 in this example is arranged closer to the well region 11 than the center of the high resistance region 204 in the X-axis direction.
  • the slope of the slope from the valley 208 to the well region 11 may be steeper than the slope of the slope from the valley 208 to the bottom region 202 .
  • the potential distribution in the high resistance region 204 can be controlled by controlling the doping concentration distribution in the high resistance region 204.
  • FIG. 6 and 15 to 18 the doping concentration distribution of the high-resistance region 204 connecting the well region 11 and the bottom region 202 in the X-axis direction was described. The doping concentration distribution of the high resistance region 204 connecting the .
  • FIG. 19 is a diagram showing another configuration example of the lower end region 202 and the high resistance region 204.
  • the lower end region 202 has a lower end portion 302 contacting the lower end of the trench portion and a low concentration portion 304 having a lower doping concentration than the lower end portion 302 .
  • the high resistance region 204 also has a lower end portion 312 contacting the lower end of the trench portion and a low concentration portion 314 having a lower doping concentration than the lower end portion 312 .
  • the low-concentration portion 304 and the low-concentration portion 314 overlap the center of the mesa portion in the X-axis direction.
  • the lower end region 202 and the high resistance region 204 in this example are formed by implanting dopants into the semiconductor substrate 10 through the trenches 45 and thermally diffusing the dopants, as described with reference to FIGS. Therefore, the doping concentration of the lower end portion 302 and the lower end portion 312 contacting the trench portion is relatively high. Then, the doping concentration of the lightly doped portion 304 and the lightly doped portion 314 away from the trench portion is relatively low.
  • the width of the low concentration portion 304 in the Z-axis direction is smaller than the width of the lower end portion 302 in the Z-axis direction.
  • the width of the low concentration portion 314 in the Z-axis direction is smaller than the width of the lower end portion 312 in the Z-axis direction.
  • a voltage (eg, ⁇ 15 V) lower than the voltage (eg, 0 V) of the emitter electrode 52 is applied to the gate trench portion 40 . Therefore, holes are likely to be attracted near the lower end of the gate trench portion 40 . By increasing the doping concentration of the lower end portion 312 , holes attracted to the lower end of the gate trench portion 40 can be easily extracted toward the upper surface 21 side of the semiconductor substrate 10 . Thereby, the switching time of the semiconductor device 100 can be shortened. Further, lower end regions 202 extending in the horizontal direction (X-axis direction) from adjacent trench portions in the transistor portion 70 are connected at the central portion of the mesa portion 60, thereby preventing a decrease in breakdown voltage. The same applies to the boundary portion 210 and the boundary between the boundary portion 210 and the transistor portion 70 .
  • FIG. 20 is a diagram showing an example of doping concentration distribution in the high resistance region 204.
  • FIG. 20 the doping concentration distribution in the X-axis direction of the high-resistance region 204 connecting the well region 11 and the lower end region 202 in the X-axis direction, and the high resistance region 204 connecting the well region 11 and the lower end region 202 in the Y-axis direction.
  • Doping concentration distribution in the Y-axis direction of the resistive region 204 is shown.
  • the high resistance region 204 of this example has lower end portions 312 and low concentration portions 314 alternately in the X-axis direction. Therefore, in the doping concentration distribution in the X-axis direction, high-concentration portions and low-concentration portions appear alternately.
  • the doping concentration distribution of the high-resistance region 204 in the Y-axis direction is substantially flat. That is, the doping concentration distribution of the high resistance region 204 in the Y-axis direction is flatter than the doping concentration distribution of the high resistance region 204 in the X-axis direction.
  • the degree of flatness in the doping concentration distribution is indicated by the difference between the maximum value Dmax and the minimum value Dmin of the doping concentration in the unit length L in the X-axis direction or the Y-axis direction.
  • the unit length L may be larger than the array period T of the trench portions in the X-axis direction (or the peak-to-peak distance T of the doping concentration distribution of the high resistance region 204). According to this example, the electric field distribution in the Y-axis direction can be made flatter.
  • the high-resistance region 204 has been described in FIG. 20, the doping concentration distribution in the lower end region 202 is the same.
  • FIG. 21 is a diagram showing another arrangement example of the high-resistance regions 204 in the X-axis direction.
  • a portion of the emitter region 12 and a portion of the high-resistance region 204 are arranged so as to overlap when viewed from above.
  • the high-resistance region 204 of this example extends to the interior of the transistor section 70 .
  • the X-axis direction length Lx1 of the high resistance region 204 provided in the boundary portion 210 may be larger than the X-axis direction length Lx2 of the high resistance region 204 provided in the transistor portion 70 .
  • Length Lx1 and length Lx2 may be the same, and length Lx2 may be greater than length Lx1.
  • Reference Signs List 10 Semiconductor substrate 11 Well region 12 Emitter region 14 Base region 15 Contact region 16 Accumulation region 18 Drift region 20 Buffer region 21 Top surface 22 Collector region 23 Bottom surface 24 Collector electrode 29 Linear portion 30 Dummy trench portion 31 Tip portion 32 Dummy insulating film 34 Dummy conductive portion 38 Interlayer insulating film 39 Straight portion 40 Gate trench portion 41 Tip portion 42 Gate insulating film 44 Gate conductive portion 45 Trench 52 Emitter electrode 54 Contact hole 60, 61 Mesa portion 70 Transistor Part, 80... Diode part, 81... Extension region, 82... Cathode region, 90... Edge termination structure part, 100... Semiconductor device, 130... Peripheral gate wiring, 131...

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WO2013132568A1 (ja) * 2012-03-05 2013-09-12 三菱電機株式会社 半導体装置
JP2017028250A (ja) * 2015-07-16 2017-02-02 富士電機株式会社 半導体装置及びその製造方法
JP2019054043A (ja) * 2017-09-13 2019-04-04 株式会社日立製作所 半導体装置およびその製造方法
JP2019110288A (ja) * 2017-10-24 2019-07-04 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ ｄＶ／ｄｔ制御性を備えたＩＧＢＴを製造する方法
JP2019153646A (ja) * 2018-03-01 2019-09-12 トヨタ自動車株式会社 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2026053658A1 (ja) * 2024-09-05 2026-03-12 富士電機株式会社 半導体装置

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