JPWO2023063412A1 - - Google Patents
Info
- Publication number
- JPWO2023063412A1 JPWO2023063412A1 JP2023554643A JP2023554643A JPWO2023063412A1 JP WO2023063412 A1 JPWO2023063412 A1 JP WO2023063412A1 JP 2023554643 A JP2023554643 A JP 2023554643A JP 2023554643 A JP2023554643 A JP 2023554643A JP WO2023063412 A1 JPWO2023063412 A1 JP WO2023063412A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
- H10D12/441—Vertical IGBTs
- H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
- H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/01—Manufacture or treatment
- H10D12/031—Manufacture or treatment of IGBTs
- H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
- H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
- H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
- H10D62/107—Buried supplementary regions, e.g. buried guard rings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
- H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
- H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/393—Body regions of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021169472 | 2021-10-15 | ||
| JP2021169472 | 2021-10-15 | ||
| PCT/JP2022/038348 WO2023063412A1 (ja) | 2021-10-15 | 2022-10-14 | 半導体装置および半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2023063412A1 true JPWO2023063412A1 (https=) | 2023-04-20 |
| JPWO2023063412A5 JPWO2023063412A5 (https=) | 2024-01-05 |
| JP7670158B2 JP7670158B2 (ja) | 2025-04-30 |
Family
ID=85988337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023554643A Active JP7670158B2 (ja) | 2021-10-15 | 2022-10-14 | 半導体装置および半導体装置の製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20240006519A1 (https=) |
| JP (1) | JP7670158B2 (https=) |
| CN (1) | CN117063293A (https=) |
| DE (1) | DE112022000977T5 (https=) |
| WO (1) | WO2023063412A1 (https=) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2026053658A1 (ja) * | 2024-09-05 | 2026-03-12 | 富士電機株式会社 | 半導体装置 |
| CN120224711B (zh) * | 2025-05-28 | 2025-09-16 | 深圳平湖实验室 | 半导体器件及其制备方法 |
| CN120224710A (zh) * | 2025-05-28 | 2025-06-27 | 深圳平湖实验室 | 半导体器件及其制备方法 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013132568A1 (ja) * | 2012-03-05 | 2013-09-12 | 三菱電機株式会社 | 半導体装置 |
| JP2019110288A (ja) * | 2017-10-24 | 2019-07-04 | インフィネオン テクノロジーズ アーゲーInfineon Technologies Ag | dV/dt制御性を備えたIGBTを製造する方法 |
| JP2019153646A (ja) * | 2018-03-01 | 2019-09-12 | トヨタ自動車株式会社 | 半導体装置 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8785278B2 (en) * | 2012-02-02 | 2014-07-22 | Alpha And Omega Semiconductor Incorporated | Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact |
| JP6472714B2 (ja) * | 2015-06-03 | 2019-02-20 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| JP6728953B2 (ja) * | 2015-07-16 | 2020-07-22 | 富士電機株式会社 | 半導体装置及びその製造方法 |
| US10347764B2 (en) * | 2017-06-30 | 2019-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with multi-layered source/drain regions having different dopant concentrations and manufacturing method thereof |
| JP6847007B2 (ja) * | 2017-09-13 | 2021-03-24 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
| DE102017124871B4 (de) | 2017-10-24 | 2021-06-17 | Infineon Technologies Ag | Leistungshalbleiter-Vorrichtung und Verfahren zum Herstellen einer Leistungshalbleiter-Vorrichtung |
| JP7131003B2 (ja) * | 2018-03-16 | 2022-09-06 | 富士電機株式会社 | 半導体装置 |
| WO2019244681A1 (ja) * | 2018-06-21 | 2019-12-26 | 富士電機株式会社 | 半導体装置および製造方法 |
-
2022
- 2022-10-14 JP JP2023554643A patent/JP7670158B2/ja active Active
- 2022-10-14 CN CN202280024178.2A patent/CN117063293A/zh active Pending
- 2022-10-14 DE DE112022000977.2T patent/DE112022000977T5/de active Pending
- 2022-10-14 WO PCT/JP2022/038348 patent/WO2023063412A1/ja not_active Ceased
-
2023
- 2023-09-18 US US18/469,541 patent/US20240006519A1/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013132568A1 (ja) * | 2012-03-05 | 2013-09-12 | 三菱電機株式会社 | 半導体装置 |
| JP2019110288A (ja) * | 2017-10-24 | 2019-07-04 | インフィネオン テクノロジーズ アーゲーInfineon Technologies Ag | dV/dt制御性を備えたIGBTを製造する方法 |
| JP2019153646A (ja) * | 2018-03-01 | 2019-09-12 | トヨタ自動車株式会社 | 半導体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023063412A1 (ja) | 2023-04-20 |
| DE112022000977T5 (de) | 2023-11-23 |
| JP7670158B2 (ja) | 2025-04-30 |
| US20240006519A1 (en) | 2024-01-04 |
| CN117063293A (zh) | 2023-11-14 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20230929 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20230929 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20241112 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20250114 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20250318 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20250331 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 7670158 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |