JPWO2023063412A1 - - Google Patents

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Publication number
JPWO2023063412A1
JPWO2023063412A1 JP2023554643A JP2023554643A JPWO2023063412A1 JP WO2023063412 A1 JPWO2023063412 A1 JP WO2023063412A1 JP 2023554643 A JP2023554643 A JP 2023554643A JP 2023554643 A JP2023554643 A JP 2023554643A JP WO2023063412 A1 JPWO2023063412 A1 JP WO2023063412A1
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JP
Japan
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JP2023554643A
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Japanese (ja)
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JPWO2023063412A5 (https=
JP7670158B2 (ja
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Publication of JPWO2023063412A1 publication Critical patent/JPWO2023063412A1/ja
Publication of JPWO2023063412A5 publication Critical patent/JPWO2023063412A5/ja
Application granted granted Critical
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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411Insulated-gate bipolar transistors [IGBT]
    • H10D12/441Vertical IGBTs
    • H10D12/461Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01Manufacture or treatment
    • H10D12/031Manufacture or treatment of IGBTs
    • H10D12/032Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107Buried supplementary regions, e.g. buried guard rings 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126Top-view geometrical layouts of the regions or the junctions
    • H10D62/127Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142Anode regions of thyristors or collector regions of gated bipolar-mode devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393Body regions of DMOS transistors or IGBTs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/111Field plates
    • H10D64/117Recessed field plates, e.g. trench field plates or buried field plates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811Combinations of field-effect devices and one or more diodes, capacitors or resistors
JP2023554643A 2021-10-15 2022-10-14 半導体装置および半導体装置の製造方法 Active JP7670158B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2021169472 2021-10-15
JP2021169472 2021-10-15
PCT/JP2022/038348 WO2023063412A1 (ja) 2021-10-15 2022-10-14 半導体装置および半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JPWO2023063412A1 true JPWO2023063412A1 (https=) 2023-04-20
JPWO2023063412A5 JPWO2023063412A5 (https=) 2024-01-05
JP7670158B2 JP7670158B2 (ja) 2025-04-30

Family

ID=85988337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023554643A Active JP7670158B2 (ja) 2021-10-15 2022-10-14 半導体装置および半導体装置の製造方法

Country Status (5)

Country Link
US (1) US20240006519A1 (https=)
JP (1) JP7670158B2 (https=)
CN (1) CN117063293A (https=)
DE (1) DE112022000977T5 (https=)
WO (1) WO2023063412A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2026053658A1 (ja) * 2024-09-05 2026-03-12 富士電機株式会社 半導体装置
CN120224711B (zh) * 2025-05-28 2025-09-16 深圳平湖实验室 半导体器件及其制备方法
CN120224710A (zh) * 2025-05-28 2025-06-27 深圳平湖实验室 半导体器件及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013132568A1 (ja) * 2012-03-05 2013-09-12 三菱電機株式会社 半導体装置
JP2019110288A (ja) * 2017-10-24 2019-07-04 インフィネオン テクノロジーズ アーゲーInfineon Technologies Ag dV/dt制御性を備えたIGBTを製造する方法
JP2019153646A (ja) * 2018-03-01 2019-09-12 トヨタ自動車株式会社 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8785278B2 (en) * 2012-02-02 2014-07-22 Alpha And Omega Semiconductor Incorporated Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact
JP6472714B2 (ja) * 2015-06-03 2019-02-20 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6728953B2 (ja) * 2015-07-16 2020-07-22 富士電機株式会社 半導体装置及びその製造方法
US10347764B2 (en) * 2017-06-30 2019-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with multi-layered source/drain regions having different dopant concentrations and manufacturing method thereof
JP6847007B2 (ja) * 2017-09-13 2021-03-24 株式会社日立製作所 半導体装置およびその製造方法
DE102017124871B4 (de) 2017-10-24 2021-06-17 Infineon Technologies Ag Leistungshalbleiter-Vorrichtung und Verfahren zum Herstellen einer Leistungshalbleiter-Vorrichtung
JP7131003B2 (ja) * 2018-03-16 2022-09-06 富士電機株式会社 半導体装置
WO2019244681A1 (ja) * 2018-06-21 2019-12-26 富士電機株式会社 半導体装置および製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013132568A1 (ja) * 2012-03-05 2013-09-12 三菱電機株式会社 半導体装置
JP2019110288A (ja) * 2017-10-24 2019-07-04 インフィネオン テクノロジーズ アーゲーInfineon Technologies Ag dV/dt制御性を備えたIGBTを製造する方法
JP2019153646A (ja) * 2018-03-01 2019-09-12 トヨタ自動車株式会社 半導体装置

Also Published As

Publication number Publication date
WO2023063412A1 (ja) 2023-04-20
DE112022000977T5 (de) 2023-11-23
JP7670158B2 (ja) 2025-04-30
US20240006519A1 (en) 2024-01-04
CN117063293A (zh) 2023-11-14

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