JPWO2023063412A5 - - Google Patents

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JPWO2023063412A5
JPWO2023063412A5 JP2023554643A JP2023554643A JPWO2023063412A5 JP WO2023063412 A5 JPWO2023063412 A5 JP WO2023063412A5 JP 2023554643 A JP2023554643 A JP 2023554643A JP 2023554643 A JP2023554643 A JP 2023554643A JP WO2023063412 A5 JPWO2023063412 A5 JP WO2023063412A5
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semiconductor device
high resistance
doping concentration
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JP2023554643A
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JPWO2023063412A1 (https=
JP7670158B2 (ja
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Priority claimed from PCT/JP2022/038348 external-priority patent/WO2023063412A1/ja
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JP2023554643A 2021-10-15 2022-10-14 半導体装置および半導体装置の製造方法 Active JP7670158B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2021169472 2021-10-15
JP2021169472 2021-10-15
PCT/JP2022/038348 WO2023063412A1 (ja) 2021-10-15 2022-10-14 半導体装置および半導体装置の製造方法

Publications (3)

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JPWO2023063412A1 JPWO2023063412A1 (https=) 2023-04-20
JPWO2023063412A5 true JPWO2023063412A5 (https=) 2024-01-05
JP7670158B2 JP7670158B2 (ja) 2025-04-30

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JP2023554643A Active JP7670158B2 (ja) 2021-10-15 2022-10-14 半導体装置および半導体装置の製造方法

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US (1) US20240006519A1 (https=)
JP (1) JP7670158B2 (https=)
CN (1) CN117063293A (https=)
DE (1) DE112022000977T5 (https=)
WO (1) WO2023063412A1 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2026053658A1 (ja) * 2024-09-05 2026-03-12 富士電機株式会社 半導体装置
CN120224711B (zh) * 2025-05-28 2025-09-16 深圳平湖实验室 半导体器件及其制备方法
CN120224710A (zh) * 2025-05-28 2025-06-27 深圳平湖实验室 半导体器件及其制备方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8785278B2 (en) * 2012-02-02 2014-07-22 Alpha And Omega Semiconductor Incorporated Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact
DE112012005981B4 (de) * 2012-03-05 2025-04-30 Mitsubishi Electric Corporation Halbleitervorrichtungen
JP6472714B2 (ja) * 2015-06-03 2019-02-20 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6728953B2 (ja) * 2015-07-16 2020-07-22 富士電機株式会社 半導体装置及びその製造方法
US10347764B2 (en) * 2017-06-30 2019-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with multi-layered source/drain regions having different dopant concentrations and manufacturing method thereof
JP6847007B2 (ja) * 2017-09-13 2021-03-24 株式会社日立製作所 半導体装置およびその製造方法
DE102017124872B4 (de) * 2017-10-24 2021-02-18 Infineon Technologies Ag Verfahren zur Herstellung eines IGBT mit dV/dt-Steuerbarkeit
DE102017124871B4 (de) 2017-10-24 2021-06-17 Infineon Technologies Ag Leistungshalbleiter-Vorrichtung und Verfahren zum Herstellen einer Leistungshalbleiter-Vorrichtung
JP7091714B2 (ja) * 2018-03-01 2022-06-28 株式会社デンソー 半導体装置
JP7131003B2 (ja) * 2018-03-16 2022-09-06 富士電機株式会社 半導体装置
WO2019244681A1 (ja) * 2018-06-21 2019-12-26 富士電機株式会社 半導体装置および製造方法

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