WO2023005819A1 - 超β晶体三极管及其制作方法 - Google Patents

超β晶体三极管及其制作方法 Download PDF

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WO2023005819A1
WO2023005819A1 PCT/CN2022/107260 CN2022107260W WO2023005819A1 WO 2023005819 A1 WO2023005819 A1 WO 2023005819A1 CN 2022107260 W CN2022107260 W CN 2022107260W WO 2023005819 A1 WO2023005819 A1 WO 2023005819A1
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conductivity type
region
doping concentration
base region
doped
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PCT/CN2022/107260
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English (en)
French (fr)
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李永顺
金华俊
宋亮
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无锡华润上华科技有限公司
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Priority to US18/254,986 priority Critical patent/US20240006477A1/en
Priority to JP2023547839A priority patent/JP2024506901A/ja
Publication of WO2023005819A1 publication Critical patent/WO2023005819A1/zh

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Definitions

  • the invention belongs to the field of design and manufacture of semiconductor devices, in particular to a super-beta crystal triode and a manufacturing method thereof.
  • a transistor has two N-type regions surrounding a P-type region. One of the N-type regions is the collector, the second of the N-type regions is the emitter, and the P-type region is the base. Depending on how the voltage of the transistor is biased, the transistor will have different modes of operation. A transistor operates in an off mode when the emitter-base junction is reverse biased and the collector-base junction is reverse biased. A transistor operates in an active mode when the emitter-base junction is forward biased and the collector-base junction is reverse biased. A transistor operates in saturation mode when the emitter-base junction is forward biased and the collector-base junction is forward biased. Active mode is used when the transistor is used as an amplifier, and cut-off and saturation modes are used when the transistor is used as a switch.
  • One parameter of a triode is the common emitter current gain, which is often referred to as beta or HFE. When in active mode, the common emitter current gain is the ratio of collector current to base current.
  • the purpose of the present invention is to provide a super-beta transistor and its manufacturing method, which are used to solve the problem of relatively large base punch-through risk in the crystal transistor structure in the prior art.
  • the present invention provides a method for manufacturing a super-beta transistor, the method includes: providing a substrate, forming an isolation buried layer of the first conductivity type and a first A doped layer of conductivity type, the isolation buried layer is located at the bottom of the doped layer; a base region of the second conductivity type is formed in the doped layer; a base region of the second conductivity type is formed on the peripheral side of the base region a doped island, the doping concentration of the doped island is greater than that of the base region; a collector region of the first conductivity type is formed in the doped layer, and the collector region is connected to the base region Disposed at intervals; forming an emitter region of the first conductivity type in the base region.
  • the doping concentration range of the base region is 5e17cm -3 to 8e17cm -3
  • the doping concentration range of the doping island is greater than or equal to 5e18cm -3 .
  • the doping concentration of the collector region is greater than that of the doped layer, and the doping concentration of the isolation buried layer is greater than that of the doped layer.
  • the implanted junction depth of the base region is less than or equal to the implanted junction depth of the doped island.
  • the contact region of the second conductivity type is greater than the doping concentration of the doping island, and the doping concentration of the contact region of the first conductivity type is greater than the doping concentration of the collector region.
  • the bottom of the collector region is at least connected to a part of the buried isolation layer, and the bottom of the doped island is at least connected to a part of the buried isolation layer.
  • forming an isolation buried layer of the first conductivity type and a doped layer of the first conductivity type in the substrate, wherein the isolation buried layer is located at the bottom of the doped layer includes: performing an ion implantation process on the forming an isolation buried layer inside the substrate; forming a doped layer on the surface of the substrate by ion implantation; or forming an isolation buried layer on the surface of the substrate by ion implantation; forming an isolation buried layer on the substrate by epitaxy A doped layer is formed.
  • the present invention also provides a super-beta crystal triode, comprising: a substrate, in which an isolation buried layer of the first conductivity type is formed; a doped layer of the first conductivity type, formed on the surface layer of the substrate or on the On the substrate, the isolation buried layer is located at the bottom of the doped layer; the base region of the second conductivity type is formed in the doped layer; the doped island of the second conductivity type is formed in the base region On the peripheral side, the doping concentration of the doped island is greater than the doping concentration of the base region; the collector region of the first conductivity type is formed in the doped layer, and the collector region and the base region set at intervals; the emitter region of the first conductivity type is formed in the base region.
  • the doping concentration range of the base region is 5e17cm -3 to 8e17cm -3
  • the doping concentration range of the doping island is greater than or equal to 5e18cm -3 .
  • the doping concentration range of the isolation buried layer is 1e17cm -3 ⁇ 3e17cm -3
  • the doping concentration range of the doping layer is 1e16cm -3 ⁇ 4e16cm -3
  • the doping concentration of the collector region The concentration range is 1e17cm -3 -5e17cm -3
  • the doping concentration range of the emission region is 1e17cm -3 -5e17cm -3 .
  • a contact region of a second conductivity type is further formed in the base region, the doping concentration of the contact region of the second conductivity type is greater than that of the doped island, and in the collector region A contact region of the first conductivity type is also formed, and the doping concentration of the contact region of the first conductivity type is greater than that of the collector region.
  • the bottom of the collector region is at least connected to a part of the buried isolation layer, and the bottom of the doped island is at least connected to a part of the buried isolation layer.
  • the doping concentration of the collector region is greater than that of the doped layer, and the doping concentration of the isolation buried layer is greater than that of the doped layer.
  • the implanted junction depth of the base region is less than or equal to the implanted junction depth of the doped island.
  • the base region is formed on the upper surface layer of the doped layer, and the base region is surrounded by a surrounding mask structure composed of the doped island and the isolation buried layer.
  • the super-beta crystal triode and its manufacturing method of the present invention have the following beneficial effects:
  • a doped island is formed by performing high-concentration ion implantation on the peripheral side of the base region, the doping concentration of the doped island is higher than that of the base region, and a concentration gradient is formed between the doped island and the base region.
  • the doped island can be depleted laterally at the bottom of the auxiliary base, and the bottom of the auxiliary base can be quickly pinched off, preventing the base region from punching through, while still reducing the base recombination and improving the common emitter current gain; on the other hand, due to the There is a higher P-type concentration in the non-working base region, which greatly reduces the leakage of the lateral NPN, so that the device can generate a higher current gain.
  • the super-beta crystal triode of the invention can effectively reduce the longitudinal electric field of the base region, reduce the lateral leakage of the device, and can better realize the balance of preventing base region punch-through and increasing the current amplification factor.
  • FIG. 7 shows the schematic structural diagram of the super-beta transistor according to the embodiment of the present invention.
  • spatial relation terms such as “below”, “below”, “below”, “below”, “above”, “on” etc. may be used herein to describe an element or element shown in the drawings.
  • a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • structures described as having a first feature "on top of" a second feature may include embodiments where the first and second features are formed in direct contact, as well as additional features formed between the first and second features. Embodiments between the second feature such that the first and second features may not be in direct contact.
  • the doped island 105 is formed by performing high-concentration ion implantation on the peripheral side of the base region 104.
  • the doping concentration of the doped island 105 is greater than that of the base region 104. Concentration gradient, on the one hand, the doped island 105 can be depleted laterally at the bottom of the auxiliary base, and the bottom of the auxiliary base can be quickly pinched off, preventing the base region from punching through, while still reducing base recombination and increasing the common emitter current gain; on the other hand On the one hand, due to the existence of the doped island 105, the P-type concentration of the non-working base region is higher, which greatly reduces the leakage of the lateral NPN, so that the device can generate a higher current gain.
  • the present embodiment provides a method for manufacturing a super-beta transistor, and the method includes the following steps:
  • step 1) is firstly performed, a substrate 101 is provided, and an isolation buried layer 102 of the first conductivity type is formed in the substrate 101 .
  • the substrate may be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (silicon on insulator) or GOI (germanium on insulator) and the like.
  • the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other Epitaxial structure, such as SGOI (silicon germanium on insulator), etc.
  • the substrate is a Si substrate.
  • the buried isolation layer 102 of the first conductivity type may be formed in the substrate by an ion implantation process and an annealing process.
  • the doping concentration of the isolation buried layer 102 ranges from 1e17cm ⁇ 3 to 3e17cm ⁇ 3 .
  • step 2) is then performed to form a doped layer 103 of the first conductivity type on the substrate 101 , and the isolation buried layer 102 is located at the bottom of the doped layer.
  • a doped layer 103 of the first conductivity type can be formed on the substrate 101 by vapor phase epitaxy.
  • the material of the doped layer 103 is selected to be the same as that of the substrate 101.
  • the material of the doped layer 103 is Si.
  • the doping concentration range of the doping layer 103 may be 1e16cm ⁇ 3 to 4e16cm ⁇ 3 . In a specific implementation process, the doping concentration of the doped layer 103 is 2e16cm ⁇ 3 . By adjusting the doping concentration of the doped layer 103, the on-resistance and breakdown voltage of the device can be effectively adjusted to meet the performance requirements of different devices.
  • the isolation buried layer 102 may also be firstly formed inside the substrate by an ion implantation process, and then the doped layer 103 is formed on the surface layer of the substrate by an ion implantation process, by controlling the The depth position of the isolation buried layer 102 is such that the isolation buried layer 102 is located at the bottom of the doped layer 103 .
  • step 3 is then performed to form a base region 104 of the second conductivity type in the doped layer 103 .
  • a base region 104 of the second conductivity type can be formed in the doped layer 103 by photolithography, ion implantation and annealing, and the doping concentration range of the base region 104 can be 5e17cm ⁇ 3 to 8e17cm ⁇ 3 3 . In a specific implementation process, the doping concentration of the base region 104 is 6e17cm ⁇ 3 .
  • the doping concentration of the base region 104 in this embodiment is relatively low, that is, the doping concentration of the base region 104 is further reduced, and is lower than the conventional base region doping concentration, which can effectively reduce the recombination of the base region 104 and ensure sufficient base region While the transport coefficient is 104, it can still reduce the risk of base region punch-through, and in addition, it can also shield the leakage of the lateral non-working base region, so as to achieve a better balance between the three.
  • step 4) is then performed to form a doped island 105 of the second conductivity type on the peripheral side of the base region 104, and the doping concentration of the doped island 105 is greater than that of the base region 104. concentration.
  • the bottom of the doped island 105 is at least connected to a part of the isolation buried layer 102 .
  • the implanted junction depth of the base region 104 is less than or equal to the implanted junction depth of the doped island 105 .
  • the base region 104 is formed on the upper surface of the doped layer 103 .
  • the surrounding cover structure composed of the doped island 105 and the isolation buried layer 102 surrounds the base region 104 .
  • doped islands 105 of the second conductivity type can be formed around the base region 104 by photolithography, ion implantation and annealing, and the doping concentration of the doped islands 105 is higher than that of the base region 104. doping concentration.
  • the doping concentration range of the doped island 105 is greater than or equal to 5e18cm -3 , for example, it may be 8e18cm -3 -9e18cm -3 .
  • the present invention forms the doped island 105 by performing high-concentration ion implantation on the side of the base region 104.
  • the high concentration of the doped island 105 and the low concentration of the base region 104 form a concentration gradient.
  • the doped island 105 can be The auxiliary bottom is laterally depleted, and the bottom of the auxiliary base region 104 is quickly pinched off, preventing the base region 104 from punching through, while still reducing the base region recombination and improving the common emitter current gain; on the other hand, due to the existence of the doped island 105, The high P-type concentration of the non-working base region 104 greatly reduces the leakage of the lateral NPN, so that the device can generate a higher current gain.
  • step 5 is followed to form a collector region 106 of the first conductivity type in the doped layer 103 , and the collector region 106 is spaced apart from the base region 104 .
  • a collector region 106 of the first conductivity type may be formed in the doped layer 103 by photolithography, ion implantation and annealing, the collector region 106 is spaced from the base region 104, and the The bottom of the collector region 106 is at least partially connected to the isolation buried layer 102 .
  • the doping concentration of the collector region 106 ranges from 1e17cm ⁇ 3 to 5e17cm ⁇ 3 . In a specific implementation process, the doping concentration of the collector region 106 is 3e17cm ⁇ 3 .
  • step 6 proceed to step 6) to form a contact region 107 of the second conductivity type in the base region 104 , and the doping concentration of the contact region 107 of the second conductivity type is greater than that of the doped island 105 doping concentration to reduce the contact resistance of the base region 104 .
  • step 7) is finally performed to form an emitter region 108 of the first conductivity type in the base region 104 .
  • the emitter region 108 of the first conductivity type may be formed in the base region 104 by photolithography, ion implantation and annealing, and the doping concentration of the emitter region 108 is in the range of 1e17cm ⁇ 3 to 5e17cm ⁇ 3 .
  • the doping concentration of the emission region 108 is 5e17cm -3 .
  • the step of forming a contact region 109 of the first conductivity type in the collector region 106 is also included, and the doping concentration of the contact region 109 of the first conductivity type is higher than that of the collector region 106. impurity concentration.
  • the emitter region 108 of the first conductivity type and the contact region 109 of the first conductivity type may be formed in the same doping step, that is, the photolithography process, the ion implantation process and the annealing process are simultaneously formed.
  • the emitter region 108 of the first conductivity type and the contact region 109 of the first conductivity type are used to reduce process cost and improve process efficiency.
  • the collector region 106 , the base region 104 , and the emitter region 108 are all drawn out to the surface of the substrate, and the way of drawing out includes but not limited to implanting a contact region, drawing out a doped region, and through holes.
  • the first conductivity type is N-type conductivity
  • the second conductivity type is P-type conductivity
  • the first conductivity type may also be P-type conductivity
  • the second conductivity type may also be N-type conductivity
  • this embodiment also provides a super-beta transistor, including: a substrate 101 in which an isolation buried layer 102 of the first conductivity type is formed; a doped layer 103 of the first conductivity type , formed on the surface layer of the substrate 101 or on the substrate 101, the isolation buried layer 102 is located at the bottom of the doped layer 103; the base region 104 of the second conductivity type is formed on the doped layer 103 Middle; the doped island 105 of the second conductivity type is formed on the peripheral side of the base region 104, and the doping concentration of the doped island 105 is greater than the doping concentration of the base region 104; the current collector of the first conductivity type A region 106 is formed in the doped layer 103 , and the collector region 106 is spaced apart from the base region 104 ; an emitter region 108 of the first conductivity type is formed in the base region 104 .
  • the substrate 101 may be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (silicon on insulator) or GOI (germanium on insulator) and the like.
  • the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other Epitaxial structure, such as SGOI (silicon germanium on insulator), etc.
  • the substrate is a Si substrate.
  • the doping concentration of the doped layer 103 may range from 1e16cm ⁇ 3 to 4e16cm ⁇ 3 . In a specific implementation process, the doping concentration of the doped layer 103 is 2e16cm ⁇ 3 . By adjusting the doping concentration of the doped layer 103, the on-resistance and breakdown voltage of the device can be effectively adjusted to meet the performance requirements of different devices.
  • the doping concentration of the base region 104 may range from 5e17cm ⁇ 3 to 8e17cm ⁇ 3 . In a specific implementation process, the doping concentration of the base region 104 is 6e17cm ⁇ 3 .
  • the doping concentration of the base region 104 in this embodiment is relatively low, that is, the doping concentration of the base region 104 is further reduced, and is lower than the conventional base region doping concentration, which can effectively reduce the recombination of the base region 104 and ensure sufficient base region While the transport coefficient is 104, it can still reduce the risk of base region punch-through, and in addition, it can also shield the leakage of the lateral non-working base region, so as to achieve a better balance between the three.
  • the doping concentration range of the doped island 105 is greater than or equal to 5e18cm -3 , for example, it may be 8e18cm -3 -9e18cm -3 .
  • the present invention forms the doped island 105 by performing high-concentration ion implantation on the side of the base region 104.
  • the high concentration of the doped island 105 and the low concentration of the base region 104 form a concentration gradient.
  • the doped island 105 can be The auxiliary bottom is laterally depleted, and the bottom of the auxiliary base region 104 is quickly pinched off, preventing the base region 104 from punching through, while still reducing base region recombination and improving the common emitter current gain; on the other hand, due to the existence of the doped island 105, The high P-type concentration of the non-working base region 104 greatly reduces the leakage of the lateral NPN, so that the device can generate a higher current gain.
  • the implanted junction depth of the base region 104 is less than or equal to the implanted junction depth of the doped island 105 .
  • the base region 104 is formed on the upper surface layer of the doped layer 103 , and the surrounding mask structure composed of the doped island 105 and the isolation buried layer 102 surrounds the base region 104 .
  • the doping concentration of the isolation buried layer 102 ranges from 1e17cm ⁇ 3 to 3e17cm ⁇ 3 .
  • the doping concentration of the collector region 106 ranges from 1e17cm ⁇ 3 to 5e17cm ⁇ 3 .
  • the doping concentration of the collector region 106 is 3e17cm ⁇ 3 .
  • the doping concentration of the emitter region 108 ranges from 1e17cm ⁇ 3 to 5e17cm ⁇ 3 .
  • the doping concentration of the emission region 108 is 5e17cm -3 .
  • a contact region 107 of a second conductivity type is further formed in the base region 104, and the doping concentration of the contact region 107 of the second conductivity type is greater than that of the doped island 105;
  • a contact region 109 of the first conductivity type is also formed in the collector region 106 , and the doping concentration of the contact region 109 of the first conductivity type is greater than that of the collector region 106 .
  • the bottom of the collector region 106 is at least connected to a part of the buried isolation layer 102
  • the bottom of the doped island 105 is at least connected to a part of the buried isolation layer 102 .
  • the first conductivity type is N-type conductivity
  • the second conductivity type is P-type conductivity
  • the first conductivity type may also be P-type conductivity
  • the second conductivity type may also be N-type conductivity
  • the super-beta crystal triode and its manufacturing method of the present invention have the following beneficial effects:
  • the doped island 105 is formed by performing high-concentration ion implantation on the peripheral side of the base region 104.
  • the doping concentration of the doped island 105 is higher than that of the base region 104.
  • Forming a concentration gradient, on the one hand, the doped island 105 can be laterally depleted at the bottom of the auxiliary base region, and the bottom of the auxiliary base region 104 can be quickly pinched off, preventing the base region 104 from punching through, while still reducing base region recombination and improving the common emitter current gain
  • the P-type concentration of the non-working base region 104 is relatively high, which greatly reduces the leakage of the lateral NPN, so that the device can generate a higher current gain.
  • the super-beta crystal triode of the present invention can effectively reduce the longitudinal electric field of the base region 104, reduce the lateral leakage of the device, and can better realize the balance between preventing the base region 104 from punching through and increasing the current amplification factor.
  • the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

Abstract

本发明提供一种超β晶体三极管及其制作方法，该制作方法包括：提供一衬底，基于衬底形成第一导电类型的隔离埋层及第一导电类型的掺杂层；于掺杂层中形成第二导电类型的基区；于基区周侧形成第二导电类型的掺杂岛，掺杂岛的掺杂浓度大于基区的掺杂浓度；于掺杂层中形成第一导电类型的集电区，集电区与基区间隔设置；于基区中形成第一导电类型的发射区。本发明的超β晶体三极管能有效降低基区纵向电场，减小器件的横向漏电，可以较好地实现防止基区穿通和提高电流放大系数的平衡。

Description

超β晶体三极管及其制作方法
相关申请的交叉引用
本申请要求于2021年7月28日提交中国专利局、申请号为202110858844.X、发明名称为“超β晶体三极管及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于半导体器件设计及制造领域，特别是涉及一种超β晶体三极管及其制作方法。
背景技术
晶体三极管具有围绕P型区域的两个N型区域。N型区域中的一个是集电极，N型区域中的第二个是发射极，P型区域是基极。根据晶体三极管的电压偏置方式，晶体三极管将具有不同的操作模式。当发射极-基极结被反向偏置并且集电极-基极结被反向偏置时，晶体三极管以截止模式操作。当发射极-基极结被正向偏置且集电极-基极结被反向偏置时，晶体三极管以有源模式操作。当发射极-基极结被正向偏置且集电极-基极结被正向偏置时，晶体三极管以饱和模式操作。当晶体管用作放大器时使用有源模式，以及当晶体管用作开关时使用截止模式和饱和模式。晶体三极管的一个参数是共发射极电流增益，其通常被称为β或HFE。当处于有源模式时，共发射极电流增益是集电极电流与基极电流的比率。
现有的晶体三极管为了减少基区复合，保证足够的基区输运系数，提高共发射极电流增益，通常都追求更浅的基区，以及更低的基区掺杂浓度，但这会导致晶体三极管存在较大的基区穿通风险。此外，由于横向(导电沟道的宽度方向)均匀分布的基区浓度会导致横向NPN的非工作基区产生漏电流，现有的晶体三极管还存在发射结的注入效率较低、漏电大、电流增益较小等弊端。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种超β晶体三极管及其制作方法，用于解决现有技术中的晶体三极管结构存在较大的基区穿通风险的问题。
为实现上述目的及其他相关目的，本发明提供一种超β晶体三极管的制作方法，所述 制作方法包括：提供一衬底，基于所述衬底形成第一导电类型的隔离埋层及第一导电类型的掺杂层，所述隔离埋层位于所述掺杂层的底部；于所述掺杂层中形成第二导电类型的基区；于所述基区周侧形成第二导电类型的掺杂岛，所述掺杂岛的掺杂浓度大于所述基区的掺杂浓度；于所述掺杂层中形成第一导电类型的集电区，所述集电区与所述基区间隔设置；于所述基区中形成第一导电类型的发射区。
可选地，所述基区的掺杂浓度范围为5e17cm -3～8e17cm -3，所述掺杂岛的掺杂浓度范围为大于或等于5e18cm -3。
可选地，所述集电区的掺杂浓度大于所述掺杂层的掺杂浓度，且所述隔离埋层的掺杂浓度大于所述掺杂层的掺杂浓度。
可选地，所述基区的注入结深小于或等于所述掺杂岛的注入结深。
可选地，还包括于所述基区中形成第二导电类型的接触区的步骤及于所述集电区中形成第一导电类型的接触区的步骤，所述第二导电类型的接触区的掺杂浓度大于所述掺杂岛的掺杂浓度，所述第一导电类型的接触区的掺杂浓度大于所述集电区的掺杂浓度。
可选地，所述集电区的底部至少与部分所述隔离埋层相连，所述掺杂岛的底部至少与部分所述隔离埋层相连。
可选地，于所述衬底中形成第一导电类型的隔离埋层及第一导电类型的掺杂层，所述隔离埋层位于所述掺杂层的底部包括：通过离子注入工艺于所述衬底内部形成隔离埋层；通过离子注入工艺于所述衬底表层形成掺杂层；或者：通过离子注入工艺于所述衬底表层形成隔离埋层；通过外延工艺于所述衬底上形成掺杂层。
本发明还提供一种超β晶体三极管，包括：衬底，所述衬底中形成第一导电类型的隔离埋层；第一导电类型的掺杂层，形成于所述衬底表层或所述衬底上，所述隔离埋层位于所述掺杂层的底部；第二导电类型的基区，形成于所述掺杂层中；第二导电类型的掺杂岛，形成于所述基区周侧，所述掺杂岛的掺杂浓度大于所述基区的掺杂浓度；第一导电类型的集电区，形成于所述掺杂层中，所述集电区与所述基区间隔设置；第一导电类型的发射区，形成于所述基区中。
可选地，所述基区的掺杂浓度范围为5e17cm -3～8e17cm -3，所述掺杂岛的掺杂浓度范围为大于或等于5e18cm -3。
可选地，所述隔离埋层的掺杂浓度范围为1e17cm -3～3e17cm -3，所述掺杂层的掺杂浓度范围为1e16cm -3～4e16cm -3，所述集电区的掺杂浓度范围为1e17cm -3～5e17cm -3，所述发射区的掺杂浓度范围为1e17cm -3～5e17cm -3。
可选地，所述基区中还形成有第二导电类型的接触区，所述第二导电类型的接触区的 掺杂浓度大于所述掺杂岛的掺杂浓度，所述集电区中还形成有第一导电类型的接触区，所述第一导电类型的接触区的掺杂浓度大于所述集电区的掺杂浓度。
可选地，所述集电区的底部至少与部分所述隔离埋层相连，所述掺杂岛的底部至少与部分所述隔离埋层相连。
可选地，所述集电区的掺杂浓度大于所述掺杂层的掺杂浓度，且所述隔离埋层的掺杂浓度大于所述掺杂层的掺杂浓度。
可选地，所述基区的注入结深小于或等于所述掺杂岛的注入结深。
可选地，所述基区形成于所述掺杂层的上表层，所述掺杂岛、所述隔离埋层组成的包围罩结构将所述基区包围。
如上所述，本发明的超β晶体三极管及其制作方法，具有以下有益效果：
本发明通过在基区周侧进行高浓度的离子注入形成掺杂岛，该掺杂岛的掺杂浓度大于基区的掺杂浓度，该掺杂岛与基区间形成浓度梯度，一方面，该掺杂岛能在辅助底部横向耗尽，辅助基区底部快速夹断，防止基区穿通的同时，仍可以减少基区复合，提高共发射极电流增益；另一方面，由于该掺杂岛的存在，非工作基区的P型浓度较高，极大幅度地减小了横向NPN的漏电，从而使器件可以产生较高的电流增益。
本发明的超β晶体三极管能有效降低基区纵向电场，减小器件的横向漏电，可以较好地实现防止基区穿通和提高电流放大系数的平衡。
附图说明
图1～图7显示为本发明实施例的超β晶体三极管的制作方法中各步骤所呈现的结构示意图，其中，图7显示为本发明实施例的超β晶体三极管的结构示意图。
元件标号说明
101                    衬底
102                    隔离埋层
103                    掺杂层
104                    基区
105                    掺杂岛
106                    集电区
107                    第二导电类型的接触区
108                    发射区
109                    第一导电类型的接触区
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。应当理解的是，这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。此外，当一层被称为在两层“之间”时，它可以是所述两层之间仅有的层，或者也可以存在一个或多个介于其间的层。
在本申请的上下文中，所描述的第一特征在第二特征“之上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
现有的晶体三极管为了减少基区复合，保证足够的基区输运系数，提高共发射极电流增益，通常都追求更浅的基区，以及更低的基区掺杂浓度，但这会导致晶体三极管存在较大的基区穿通风险；此外，由于横向(导电沟道的宽度方向)均匀分布的基区浓度会导致横向NPN的非工作基区产生漏电流，现有的晶体三极管还存在发射结的注入效率较低、漏电大、电流增益较小等弊端。本发明通过在基区104周侧进行高浓度的离子注入形成掺杂岛105，该掺杂岛105的掺杂浓度大于基区104的掺杂浓度，该掺杂岛105与基区104间形成浓度梯度，一方面，该掺杂岛105能在辅助底部横向耗尽，辅助基区底部快速夹断，防止基区穿通的同时，仍可以减少基区复合，提高共发射极电流增益；另一方面，由于该掺杂岛105的存在，非工作基区的P型浓度较高，极大幅度地减小了横向NPN的漏电， 从而使器件可以产生较高的电流增益。
为了解决上述问题，如图1～图7所示，本实施例提供一种超β晶体三极管的制作方法，所述制作方法包括以下步骤：
如图1所示，首先进行步骤1)，提供一衬底101，于所述衬底101中形成第一导电类型的隔离埋层102。
作为示例，所述衬底可以为半导体衬底，例如可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅)或GOI(绝缘体上锗)等。在其它实施例中，所述半导体衬底还可以为包括其它元素半导体或化合物半导体的衬底，例如GaAs、InP或SiC等，还可以为叠层结构，例如Si/SiGe等，还可以为其它外延结构，例如SGOI(绝缘体上锗硅)等。在本实施例中，所述衬底为Si衬底。
作为示例，可以通过离子注入工艺及退火工艺于所述衬底中形成第一导电类型的隔离埋层102。在本实施例中，所述隔离埋层102的掺杂浓度范围为1e17cm -3～3e17cm -3。
如图2所示，然后进行步骤2)，于所述衬底101上形成第一导电类型的掺杂层103，所述隔离埋层102位于所述掺杂层底部。
作为示例，可以采用气相外延工艺于所述衬底101上形成第一导电类型的掺杂层103，优选地，所述掺杂层103的材料与所述衬底101选用为相同的材料，在本实施例中，所述掺杂层103的材料为Si。
所述掺杂层103的掺杂浓度范围可以为1e16cm -3～4e16cm -3。在一个具体的实施过程中，所述掺杂层103的掺杂浓度为2e16cm -3。通过调整所述掺杂层103的掺杂浓度，可以有效调整器件的导通电阻和击穿电压，以满足不同的器件的性能要求。
在另一实施例中，也可以首先通过离子注入工艺于所述衬底内部形成所述隔离埋层102，然后通过离子注入工艺于所述衬底的表层形成掺杂层103，通过控制所述隔离埋层102的深度位置，使所述隔离埋层102位于所述掺杂层103的底部。
如图3所示，接着进行步骤3)，于所述掺杂层103中形成第二导电类型的基区104。
例如，可以通过光刻工艺、离子注入工艺及退火工艺于所述掺杂层103中形成第二导电类型的基区104，所述基区104的掺杂浓度范围可以为5e17cm -3～8e17cm -3。在一个具体实施过程中，所述基区104的掺杂浓度为6e17cm -3。本实施例的基区104掺杂浓度较低，也即基区104的掺杂浓度进一步降低，且低于常规的基区掺杂浓度，可以在有效减少基区104复合，保证足够的基区104输运系数的同时，仍可以减少基区穿通的风险，此外还能屏蔽横向非工作基区的漏电，较好地达到三者的平衡。
如图4所示，接着进行步骤4)，于所述基区104周侧形成第二导电类型的掺杂岛105， 所述掺杂岛105的掺杂浓度大于所述基区104的掺杂浓度。所述掺杂岛105的底部至少与部分所述隔离埋层102相连。
在本实施例中，所述基区104的注入结深小于或等于所述掺杂岛105的注入结深。所述基区104形成于所述掺杂层103的上表层。所述掺杂岛105、所述隔离埋层102组成的包围罩结构将所述基区104包围。
例如，可以通过光刻工艺、离子注入工艺及退火工艺于所述基区104周侧形成第二导电类型的掺杂岛105，所述掺杂岛105的掺杂浓度大于所述基区104的掺杂浓度。在本实施例中，所述掺杂岛105的掺杂浓度范围为大于或等于5e18cm -3，例如可以为8e18cm -3～9e18cm -3。本发明通过在基区104周侧进行高浓度的离子注入形成掺杂岛105，该掺杂岛105的高浓度与基区104的低浓度形成浓度梯度，一方面，该掺杂岛105能在辅助底部横向耗尽，辅助基区104底部快速夹断，防止基区104穿通的同时，仍可以减少基区复合，提高共发射极电流增益；另一方面，由于该掺杂岛105的存在，非工作基区104的P型浓度较高，极大幅度地减小了横向NPN的漏电，从而使器件可以产生较高的电流增益。
如图5所示，接着进行步骤5)，于所述掺杂层103中形成第一导电类型的集电区106，所述集电区106与所述基区104间隔设置。
例如，可以通过光刻工艺、离子注入工艺及退火工艺于所述掺杂层103中形成第一导电类型的集电区106，所述集电区106与所述基区104间隔设置，同时所述集电区106的底部至少与所述隔离埋层102部分相连。作为示例，所述集电区106的掺杂浓度范围为1e17cm -3～5e17cm -3。在一个具体的实施过程中，所述集电区106的掺杂浓度为3e17cm -3。
如图6所示，接着进行步骤6)，于所述基区104中形成第二导电类型的接触区107，所述第二导电类型的接触区107的掺杂浓度大于所述掺杂岛105的掺杂浓度，以降低基区104的接触电阻。
如图7所示，最后进行步骤7)，于所述基区104中形成第一导电类型的发射区108。
例如，可以通过光刻工艺、离子注入工艺及退火工艺于所述基区104中形成第一导电类型的发射区108，所述发射区108的掺杂浓度范围为1e17cm -3～5e17cm -3。在一个具体的实施过程中，所述发射区108的掺杂浓度为5e17cm -3。在本步骤中，还包括于所述集电区106中形成第一导电类型的接触区109的步骤，所述第一导电类型的接触区109的掺杂浓度大于所述集电区106的掺杂浓度。作为示例，所述第一导电类型的发射区108与所述第一导电类型的接触区109可以在同一掺杂步骤中形成，即通过一道光刻工艺、离子注入工艺及退火工艺同时形成所述第一导电类型的发射区108与所述第一导电类型的接触区109， 以降低工艺成本，提高工艺效率。在其他实施例中，所述集电区106、所述基区104、所述发射区108均引出至衬底表面，引出方式包括但不限于注入接触区、掺杂区引出、通孔。
在本实施例中，所述第一导电类型为N型导电，所述第二导电类型为P型导电。当然，在其他的实施例中，所述第一导电类型也可以为P型导电，所述第二导电类型也可以为N型导电。
如图7所示，本实施例还提供一种超β晶体三极管，包括：衬底101，所述衬底101中形成第一导电类型的隔离埋层102；第一导电类型的掺杂层103，形成于所述衬底101表层或所述衬底101上，所述隔离埋层102位于所述掺杂层103的底部；第二导电类型的基区104，形成于所述掺杂层103中；第二导电类型的掺杂岛105，形成于所述基区104周侧，所述掺杂岛105的掺杂浓度大于所述基区104的掺杂浓度；第一导电类型的集电区106，形成于所述掺杂层103中，所述集电区106与所述基区104间隔设置；第一导电类型的发射区108，形成于所述基区104中。
作为示例，所述衬底101可以为半导体衬底，例如可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅)或GOI(绝缘体上锗)等。在其它实施例中，所述半导体衬底还可以为包括其它元素半导体或化合物半导体的衬底，例如GaAs、InP或SiC等，还可以为叠层结构，例如Si/SiGe等，还可以为其它外延结构，例如SGOI(绝缘体上锗硅)等。在本实施例中，所述衬底为Si衬底。
作为示例，所述掺杂层103的掺杂浓度范围可以为1e16cm -3～4e16cm -3。在一个具体的实施过程中，所述掺杂层103的掺杂浓度为2e16cm -3。通过调整所述掺杂层103的掺杂浓度，可以有效调整器件的导通电阻和击穿电压，以满足不同的器件的性能要求。
作为示例，所述基区104的掺杂浓度范围可以为5e17cm -3～8e17cm -3。在一个具体实施过程中，所述基区104的掺杂浓度为6e17cm -3。本实施例的基区104掺杂浓度较低，也即基区104的掺杂浓度进一步降低，且低于常规的基区掺杂浓度，可以在有效减少基区104复合，保证足够的基区104输运系数的同时，仍可以减少基区穿通的风险，此外还能屏蔽横向非工作基区的漏电，较好地达到三者的平衡。
在本实施例中，所述掺杂岛105的掺杂浓度范围为大于或等于5e18cm -3，例如可以为8e18cm -3～9e18cm -3。本发明通过在基区104周侧进行高浓度的离子注入形成掺杂岛105，该掺杂岛105的高浓度与基区104的低浓度形成浓度梯度，一方面，该掺杂岛105能在辅助底部横向耗尽，辅助基区104底部快速夹断，防止基区104穿通的同时，仍可以减少基区复合，提高共发射极电流增益；另一方面，由于该掺杂岛105的存在，非工作基区104的P型浓度较高，极大幅度地减小了横向NPN的漏电，从而使器件可以产生较高的电流 增益。
在本实施例中，所述基区104的注入结深小于或等于所述掺杂岛105的注入结深。所述基区104形成于所述掺杂层103的上表层，所述掺杂岛105、所述隔离埋层102组成的包围罩结构将所述基区104包围。
作为示例，所述隔离埋层102的掺杂浓度范围为1e17cm -3～3e17cm -3。所述集电区106的掺杂浓度范围为1e17cm -3～5e17cm -3。在一个具体的实施过程中，所述集电区106的掺杂浓度为3e17cm -3。所述发射区108的掺杂浓度范围为1e17cm -3～5e17cm -3。在一个具体的实施过程中，所述发射区108的掺杂浓度为5e17cm -3。
在本实施例中，所述基区104中还形成有第二导电类型的接触区107，所述第二导电类型的接触区107的掺杂浓度大于所述掺杂岛105的掺杂浓度；所述集电区106中还形成有第一导电类型的接触区109，所述第一导电类型的接触区109的掺杂浓度大于所述集电区106的掺杂浓度。
在本实施例中，所述集电区106的底部至少与部分所述隔离埋层102相连，所述掺杂岛105的底部至少与部分所述隔离埋层102相连。
在本实施例中，所述第一导电类型为N型导电，所述第二导电类型为P型导电。当然，在其他的实施例中，所述第一导电类型也可以为P型导电，所述第二导电类型也可以为N型导电。
如上所述，本发明的超β晶体三极管及其制作方法，具有以下有益效果：
本发明通过在基区104周侧进行高浓度的离子注入形成掺杂岛105，该掺杂岛105的掺杂浓度与大于基区104的掺杂浓度，该掺杂岛105与基区104间形成浓度梯度，一方面，该掺杂岛105能在辅助底部横向耗尽，辅助基区104底部快速夹断，防止基区104穿通的同时，仍可以减少基区复合，提高共发射极电流增益；另一方面，由于该掺杂岛105的存在，非工作基区104的P型浓度较高，极大幅度地减小了横向NPN的漏电，从而使器件可以产生较高的电流增益。
本发明的超β晶体三极管能有效降低基区104纵向电场，减小器件的横向漏电，可以较好地实现防止基区104穿通和提高电流放大系数的平衡。
所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (15)

  1. 一种超β晶体三极管的制作方法，其特征在于，所述制作方法包括：
    提供一衬底，基于所述衬底形成第一导电类型的隔离埋层及第一导电类型的掺杂层，所述隔离埋层位于所述掺杂层的底部；
    于所述掺杂层中形成第二导电类型的基区；
    于所述基区周侧形成第二导电类型的掺杂岛，所述掺杂岛的掺杂浓度大于所述基区的掺杂浓度；
    于所述掺杂层中形成第一导电类型的集电区，所述集电区与所述基区间隔设置；
    于所述基区中形成第一导电类型的发射区。
  2. 根据权利要求1所述的超β晶体三极管的制作方法，其特征在于：所述基区的掺杂浓度范围为5e17cm -3～8e17cm -3，所述掺杂岛的掺杂浓度范围为大于或等于5e18cm -3。
  3. 根据权利要求1所述的超β晶体三极管的制作方法，其特征在于：所述集电区的掺杂浓度大于所述掺杂层的掺杂浓度，且所述隔离埋层的掺杂浓度大于所述掺杂层的掺杂浓度。
  4. 根据权利要求1所述的超β晶体三极管的制作方法，其特征在于：所述基区的注入结深小于或等于所述掺杂岛的注入结深。
  5. 根据权利要求1所述的超β晶体三极管的制作方法，其特征在于：还包括于所述基区中形成第二导电类型的接触区的步骤及于所述集电区中形成第一导电类型的接触区的步骤，所述第二导电类型的接触区的掺杂浓度大于所述掺杂岛的掺杂浓度，所述第一导电类型的接触区的掺杂浓度大于所述集电区的掺杂浓度。
  6. 根据权利要求1所述的超β晶体三极管的制作方法，其特征在于：所述集电区的底部至少与部分所述隔离埋层相连，所述掺杂岛的底部至少与部分所述隔离埋层相连。
  7. 根据权利要求1所述的超β晶体三极管的制作方法，其特征在于：基于所述衬底形成第一导电类型的隔离埋层及第一导电类型的掺杂层，所述隔离埋层位于所述掺杂层的底部包括：
    通过离子注入工艺于所述衬底内部形成所述隔离埋层；
    通过离子注入工艺于所述衬底表层形成所述掺杂层；
    或者：
    通过离子注入工艺于所述衬底表层形成所述隔离埋层；
    通过外延工艺于所述衬底上形成所述掺杂层。
  8. 一种超β晶体三极管，其特征在于，包括：
    衬底，所述衬底中形成有第一导电类型的隔离埋层；
    第一导电类型的掺杂层，形成于所述衬底表层或所述衬底上，所述隔离埋层位于所述掺杂层的底部；
    第二导电类型的基区，形成于所述掺杂层中；
    第二导电类型的掺杂岛，形成于所述基区周侧，所述掺杂岛的掺杂浓度大于所述基区的掺杂浓度；
    第一导电类型的集电区，形成于所述掺杂层中，所述集电区与所述基区间隔设置；
    第一导电类型的发射区，形成于所述基区中。
  9. 根据权利要求8所述的超β晶体三极管，其特征在于：所述基区的掺杂浓度范围为5e17cm -3～8e17cm -3，所述掺杂岛的掺杂浓度范围为大于或等于5e18cm -3。
  10. 根据权利要求8所述的超β晶体三极管，其特征在于：所述隔离埋层的掺杂浓度范围为1e17cm -3～3e17cm -3，所述掺杂层的掺杂浓度范围为1e16cm -3～4e16cm -3，所述集电区的掺杂浓度范围为1e17cm -3～5e17cm -3，所述发射区的掺杂浓度范围为1e17cm -3～5e17cm -3。
  11. 根据权利要求8所述的超β晶体三极管，其特征在于：所述基区中还形成有第二导电类型的接触区，所述第二导电类型的接触区的掺杂浓度大于所述掺杂岛的掺杂浓度；所述集电区中还形成有第一导电类型的接触区，所述第一导电类型的接触区的掺杂浓度大于所述集电区的掺杂浓度。
  12. 根据权利要求8所述的超β晶体三极管，其特征在于：所述集电区的底部至少与部分所述隔离埋层相连，所述掺杂岛的底部至少与部分所述隔离埋层相连。
  13. 根据权利要求8所述的超β晶体三极管，其特征在于：所述集电区的掺杂浓度大于所述掺杂层的掺杂浓度，且所述隔离埋层的掺杂浓度大于所述掺杂层的掺杂浓度。
  14. 根据权利要求8所述的超β晶体三极管，其特征在于：所述基区的注入结深小于或等于所述掺杂岛的注入结深。
  15. 根据权利要求8所述的超β晶体三极管，其特征在于：所述基区形成于所述掺杂层的上表层，所述掺杂岛、所述隔离埋层组成的包围罩结构将所述基区包围。
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