WO2023060432A1 - 一种封装结构、电路板组件及电子设备 - Google Patents

一种封装结构、电路板组件及电子设备 Download PDF

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Publication number
WO2023060432A1
WO2023060432A1 PCT/CN2021/123255 CN2021123255W WO2023060432A1 WO 2023060432 A1 WO2023060432 A1 WO 2023060432A1 CN 2021123255 W CN2021123255 W CN 2021123255W WO 2023060432 A1 WO2023060432 A1 WO 2023060432A1
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WO
WIPO (PCT)
Prior art keywords
pad
shielding
electrical connection
circuit board
substrate
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Application number
PCT/CN2021/123255
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English (en)
French (fr)
Inventor
刘立筠
张珊
刘国文
童亮
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180099434.XA priority Critical patent/CN117501442A/zh
Priority to PCT/CN2021/123255 priority patent/WO2023060432A1/zh
Publication of WO2023060432A1 publication Critical patent/WO2023060432A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present application relates to the technical field of electronic equipment, in particular to a packaging structure, a circuit board assembly and electronic equipment.
  • radio frequency (radio frequency, RF) functional modules need to be integrated in a limited volume, such as WCDMA (wideband code division multiple access, wideband code division multiple access) module, LTE (long term evolution, long-term evolution) module, WiFi module, Bluetooth module and GPS (global positioning system, global positioning system) module, etc.
  • WCDMA wideband code division multiple access, wideband code division multiple access
  • LTE long term evolution, long-term evolution
  • WiFi long-term evolution
  • Bluetooth module GPS (global positioning system, global positioning system) module
  • the packaging structure includes a stacked chip and a packaging substrate, and an electromagnetic interference shielding covering the outside of the chip and the packaging substrate.
  • the electromagnetic shielding cover can isolate the entire chip and the side surface of the packaging substrate from the outside world.
  • the electromagnetic shielding cover cannot shield the welding position between the bottom of the package substrate and the printed circuit board. Therefore, there will be a problem of electromagnetic leakage at the soldering position, which seriously affects the product performance of the packaging structure.
  • the embodiment of the present application provides a packaging structure, circuit board assembly and electronic equipment, which are used to solve the problem in the prior art that there will be electromagnetic leakage at the welding position between the bottom of the packaging substrate and the printed circuit board, which will affect the product performance of the packaging structure. .
  • an embodiment of the present application provides a packaging structure including a chip, a shielding case, and an interconnection substrate.
  • the chip is arranged on the top of the interconnection substrate and is electrically connected with the interconnection substrate.
  • the interconnection substrate may be a package substrate or a redistribution layer.
  • the shielding case is arranged outside the chip, and the chip is accommodated in the space surrounded by the shielding case and the interconnection substrate.
  • the interconnect substrate includes a first electrical connection structure, a second electrical connection structure, a first pad array and a first shielding pad. Wherein, the first electrical connection structure is electrically connected to the chip.
  • the second electrical connection structure is isolated from the first electrical connection structure.
  • a portion of the second electrical connection structure exposed on the top surface or the side surface of the interconnection substrate is in contact with the shielding case.
  • Both the first pad array and the first shielding pad are disposed on the bottom surface of the interconnection substrate.
  • the first pad array may include first ground pads and first signal pads, the first ground pads are used to provide ground, and the first signal pads are used to transmit signals.
  • the first shielding pad is electrically connected to the first electrical connection structure, and the first shielding pad is disposed around the periphery of the first pad array. Therefore, when the interconnection substrate in the package structure is installed on the printed circuit board, the first shielding pad of the interconnection substrate can be connected with the second shielding pad on the printed circuit board, and can pass through the second shielding pad on the printed circuit board.
  • the shielding pad (the second shielding pad can be electrically connected to the ground structure in the printed circuit board) is grounded, and the first pad array of the interconnection substrate can be electrically connected to the second pad array on the printed circuit board. Since the first shielding pads of the interconnection substrate are wound around the periphery of the first pad array, the welding structure formed by connecting the first shielding pads of the interconnection substrate to the second shielding pads on the printed circuit board can shield the interconnection substrate. Soldering positions of the first pad array and the second pad array on the printed circuit board. The grounded solder structure can prevent crosstalk signals from entering or passing through the connection between the packaging structure and the printed circuit board.
  • electromagnetic shielding is formed on the joint between the first pad array of the interconnection substrate and the second pad array on the printed circuit board, which improves the shielding performance of the joint between the packaging structure and the printed circuit board, reduces electromagnetic leakage, and improves the Product performance of package structure.
  • the chip is electrically connected to the second pad array on the printed circuit board through the first electrical connection structure and the first pad array.
  • the second electrical connection structure is electrically connected to the second shielding pad on the printed circuit board through the first shielding pad. Since the first electrical connection structure and the second electrical connection structure are isolated from each other, the transmission of the reference ground signal of the chip and the transmission of the ground signal of the second electrical connection structure have less mutual influence.
  • the shielding case can be grounded to the printed circuit board through the second electrical connection structure and the first shielding pad, and the grounded shielding case can pass the induced charge generated by the external electromagnetic field of other radio frequency devices on the printed circuit board through the first The second electrical connection structure and the first shielding pad lead to the ground terminal, and the accumulated induced charge is released. Therefore, the shielding cover can further prevent the external electromagnetic field from diffusing into the shielding cover, the signal transmission of the chip is not interfered by the external electromagnetic field, avoiding the antenna effect, and improving the shielding ability of the solder joint between the interconnection substrate and the printed circuit board. Moreover, there is no need to set a special circuit structure to realize the grounding of the shielding case, which simplifies the circuit structure in the interconnection substrate.
  • the first pad array is a rectangular array.
  • the first shielding pad can be wound around the two sides or three sides of the first pad array, and by setting the first shielding pad at different positions and coverage areas outside the first pad array, it can be applied to The case where there are different sources of interference outside the package structure.
  • the second electrical connection structure includes at least one layer of metal wiring.
  • the metal wiring is exposed on at least one side of the interconnection substrate and is in contact with the shield case.
  • the structure of the second electrical connection structure is relatively simple.
  • the above-mentioned first electrical connection structure includes multiple circuit layers.
  • the interconnect substrate also includes a multi-layer dielectric layer, the multi-layer dielectric layer and the multi-layer circuit layer are laminated, and the dielectric layer is located between two adjacent circuit layers. Adjacent circuit layers can be connected through via holes, and the circuit layers electrically connected by multiple layers can constitute the circuit structure of the packaging substrate.
  • the above-mentioned metal wiring may be one layer or multiple layers.
  • the metal wiring of one layer can be the same layer and the same material as the circuit layer of one layer. Therefore, the embodiment of the present application can use the same patterning process to fabricate the metal wiring and the circuit layer at the same time, reducing the process flow and reducing the production cost.
  • the above-mentioned second electrical connection structure includes multilayer metal wiring.
  • the second electrical connection structure further includes a plurality of first electrical connection vias penetrating through the dielectric layer, and the first electrical connection vias electrically connect two adjacent layers of metal wiring.
  • the plurality of first electrical connection vias may be in contact with the shielding case.
  • the connection area between the second electrical connection structure and the shielding case is larger and the connection positions are more, so that the connection strength between the two is relatively high, and the shielding case can be reliably grounded.
  • the line widths of any two layers of metal wiring are different, so that when the interference signal passes around the multi-layer ground pattern, the path bends more and the path is longer, which is beneficial to Loss and reduction of interfering signals.
  • the above-mentioned second electrical connection structure includes a second electrical connection via hole.
  • the second electrical connection via hole runs through the bottom surface and the top surface of the interconnection substrate. A portion of the second electrical connection via hole exposed on the top surface is electrically connected to the shielding case. A portion of the second electrical connection via hole exposed on the bottom surface is electrically connected to the first shielding pad.
  • the manufacturing process of the electrical connection structure is also relatively simple and convenient.
  • the above-mentioned first shielding pad is a ring structure connected end to end.
  • One week of the first shielding pad can be connected to the pads on the printed circuit board, and the welding structure formed by the first shielding pad and the pads on the printed circuit board can connect the first pad array of the interconnection substrate to the printed circuit board.
  • the welding part of the second pad array on the upper part is completely shielded for a week, and the shielding effect is better.
  • the above-mentioned first shielding pad includes a plurality of strip-shaped sub-pads, and the plurality of strip-shaped sub-pads are arranged at intervals and sequentially arranged in a ring structure.
  • the first shielding pad with the gap can facilitate the reflow soldering operation between the first shielding pad and the pad on the printed circuit board.
  • the foregoing interconnection substrate is a package substrate or a redistribution layer.
  • the embodiment of the present application further includes a circuit board assembly.
  • the circuit board assembly includes a printed circuit board and the packaging structure described in the above embodiments.
  • the printed circuit board includes a second shielding pad, a second pad array and at least one grounding structure.
  • the second shielding pad is arranged around the periphery of the second pad array, and the second shielding pad and the second pad array are electrically connected to the ground structure.
  • the second pad array may include a second ground pad and a second signal pad. The second ground pad is used to provide ground, and the second signal pad is used to transmit signals.
  • the first shielding pad of the interconnection substrate in the packaging structure is electrically connected to the second shielding pad
  • the first pad array of the interconnection substrate in the packaging structure is electrically connected to the second pad array. Since the package structure in the circuit board assembly of the embodiment of the present application is the same as the package structure in the above-mentioned embodiments, they can solve the same technical problem and obtain the same technical effect, and will not be repeated here.
  • the at least one ground structure includes a first ground structure and a second ground structure, the first ground structure is electrically connected to the second shielding pad, and the second ground structure is connected to the second solder pad. Part of the pads in the pad array are electrically connected. Therefore, the shielding case and the second electrical connection structure can be electrically connected to the first ground structure through the second shielding pad to achieve grounding, and the first ground pad in the first pad array passes through the second pad array in the second pad array.
  • the grounding pad is electrically connected to the second grounding structure to achieve grounding, which further prevents the grounding signal of the shielding cover and the second electrical connection structure from interacting with the reference ground signal of some pads in the first pad array, and the signal transmission is more stable , and the shielding effect of the shielding case and the second electrical connection structure is also better.
  • the projection of the first shielding pad on the printed circuit board coincides with the second shielding pad, so as to facilitate the connection between the first shielding pad and the second shielding pad.
  • the embodiment of the present application further includes an electronic device.
  • the electronic device includes a casing and the above-mentioned circuit board assembly inside the casing. Since the structure of the circuit board assembly in the electronic device of the embodiment of the present application is the same as that of the above embodiment, both can solve the same technical problem and obtain the same technical effect, and will not be repeated here.
  • FIG. 1 is a schematic structural diagram of an electronic device in an embodiment of the present application.
  • Fig. 2 is the explosion diagram of the electronic equipment of the embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a circuit board assembly in an electronic device according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a packaging structure in an electronic device according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an interconnected substrate in an electronic device according to an embodiment of the present application.
  • FIG. 6 is an exploded schematic diagram of a circuit board assembly in an electronic device according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the connection between the interconnect substrate and the printed circuit board in the electronic device of the embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional view of a circuit board assembly in an electronic device according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of the packaging structure having an electrical connection structure in the electronic device of the embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of two interconnected substrates in the packaging structure of the electronic device according to the embodiment of the present application.
  • FIG. 11 is a structural schematic diagram of the electrical connection between the packaging structure in the electronic device of the embodiment of the present application and the grounding structure in the printed circuit board;
  • FIG. 12 is a schematic cross-sectional view of a packaging substrate in an electronic device according to an embodiment of the present application.
  • FIG. 13 is a schematic perspective view of the second connection structure of the packaging substrate including metal wiring in the electronic device of the embodiment of the present application;
  • FIG. 14 is a schematic perspective view of the second connection structure of the packaging substrate in the electronic device according to the embodiment of the present application, including multilayer metal wiring;
  • 16 is a schematic cross-sectional view of the second connection structure of the packaging substrate in the electronic device according to the embodiment of the present application, including the second electrical connection via hole;
  • 17 is a schematic cross-sectional view of the second connection structure of the packaging structure in the electronic device according to the embodiment of the present application, including the second electrical connection via hole;
  • FIG. 18 is a schematic perspective view of a packaging substrate in an electronic device according to an embodiment of the present application.
  • Fig. 19 is a bottom view of the packaging structure in the electronic device according to the embodiment of the present application, in which the first shielding pad is wound around one side of the first pad array;
  • FIG. 20 is a structural schematic diagram of the second shielding pad of the circuit board assembly in the electronic device according to the embodiment of the present application, which is wound around one side of the second pad array;
  • Fig. 21 is a perspective view of three connecting parts of the shielding cover of the package structure in the electronic device according to the embodiment of the present application covering one side of the package substrate respectively;
  • Fig. 22 is a bottom view of the packaging structure in the electronic device according to the embodiment of the present application, in which the first shielding pads are wound around the opposite sides of the first pad array;
  • Fig. 23 is a bottom view of the packaging structure in the electronic device according to the embodiment of the present application, in which the first shielding pads are wound around the adjacent two sides of the first pad array;
  • FIG. 24 is a schematic structural diagram of the second shielding pads of the circuit board assembly in the electronic device according to the embodiment of the present application, which are wound around opposite sides of the second pad array;
  • Fig. 25 is a perspective view of three connection parts of the shielding cover of the package structure in the electronic device according to the embodiment of the present application covering the opposite sides of the package substrate respectively;
  • Fig. 26 is a bottom view of the packaging structure in the electronic device according to the embodiment of the present application, in which the first shielding pad is wound around three sides of the first pad array;
  • 27 is a schematic structural diagram of the second shielding pad of the circuit board assembly in the electronic device according to the embodiment of the present application, which is wound around three sides of the second pad array;
  • Fig. 28 is a perspective view of the three connecting parts of the shielding cover of the packaging structure in the electronic device according to the embodiment of the present application covering the three sides of the packaging substrate respectively;
  • FIG. 29 is a schematic structural diagram of a ring-shaped first shielding pad in the packaging structure of the electronic device according to the embodiment of the present application.
  • Fig. 30 is a schematic structural view of the second shielding pad of the circuit board assembly in the electronic device according to the embodiment of the present application, which is arranged outside the second pad array;
  • 31 is a perspective view of the four connecting parts of the shielding cover of the packaging structure in the electronic device according to the embodiment of the present application covering the four sides of the packaging substrate respectively;
  • FIG. 32 is a schematic structural diagram of a first shielding pad with a ring-shaped packaging structure and gaps in the electronic device according to the embodiment of the present application;
  • FIG. 33 is a structural schematic diagram of the circuit board assembly in the electronic device according to the embodiment of the present application, where the ring-shaped second shielding pads with gaps are arranged around the circumference of the second pad array;
  • FIG. 34 is a schematic projection diagram of a three-layer metal wiring in an electronic device according to an embodiment of the present application.
  • FIG. 35 is a schematic structural diagram of the second connection structure of the packaging substrate in the electronic device according to the embodiment of the present application including a ring-shaped second electrical connection via hole;
  • FIG. 36 is a schematic structural view of the second connection structure of the packaging substrate in the electronic device according to the embodiment of the present application including second electrical connection via holes that are ring-shaped and have gaps.
  • first”, second, etc. are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • a feature defined as “first”, “second”, etc. may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • connection should be understood in a broad sense, for example, “connection” can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection, or It can be connected indirectly through an intermediary.
  • electrical connection may be a direct electrical connection or an indirect electrical connection through an intermediary.
  • the present application provides an electronic device, which may include a mobile phone, a tablet personal computer, a laptop computer, a personal digital assistant (PDA), a camera, a personal computer, a notebook computer , smart watch, tablet computer, car equipment, wearable device, augmented reality (augmented reality, AR) glasses, AR helmet, virtual reality (virtual reality, VR) glasses, VR helmet, server, switch, network bridge (also known as bridge devices), repeaters, routers, or gateways (also known as protocol converters).
  • PDA personal digital assistant
  • FIG. 1 is a perspective view of an electronic device provided by some embodiments of the present application
  • FIG. 2 is an exploded view of the electronic device shown in FIG. 1
  • the electronic device 1000 may be a mobile phone.
  • the electronic device 1000 may include a screen 100 , a middle frame 200 , a casing 300 and a circuit board assembly 400 fixed on the middle frame 200 as shown in FIG. 2 .
  • FIG. 1 and FIG. 2 only schematically show some components included in the electronic device 1000, and the actual shape, actual size, actual position and actual configuration of these components are not limited by FIG. 1 and FIG. 2 .
  • the electronic device 1000 may not include the screen 100 .
  • the electronic device 1000 may further include a camera 500 as shown in FIG. 2 .
  • the circuit board assembly 400 may include a packaging structure 10 and a printed circuit board (printed circuit board, PCB) 20 .
  • the packaging structure 10 can be disposed on the printed circuit board 20 and electrically connected to the printed circuit board 20 .
  • the above-mentioned printed circuit board 20 may be a main board.
  • the present application does not limit the number of packaging structures 10 on the printed circuit board 20 , there may be one, two or more than two.
  • the plane where the printed circuit board 20 shown in Figure 3 can be the XY plane, take the printed circuit board 20 shown in Figure 3 as a cuboid as an example, the X axis can be the length direction of the printed circuit board 20, and the Y axis can be the In the width direction of the circuit board 20 , the Z-axis is a direction perpendicular to or approximately perpendicular to the printed circuit board 20 within the manufacturing tolerance range. It can be understood that the width dimension of the printed circuit board 20 is smaller than the length dimension of the printed circuit board 20 .
  • the above is described by taking the printed circuit board 20 as an example of a cuboid.
  • the printed circuit board 20 may also be in the shape of a square, a polygon, etc. The embodiment of the present application does not limit the shape of the printed circuit board 20 .
  • the packaging structure 10 may include an interconnection substrate (substrate, SUB) 1 , a chip 2 disposed on the interconnection substrate 1 , and a molding compound (molding) 3 wrapping the chip 2 .
  • the interconnection substrate 1 may be a package substrate, which is used in a package process to carry a chip or a chip stack structure to form a chip package structure.
  • it may also be a rewiring layer, and the rewiring layer is provided with a rewiring structure inside, and the rewiring structure is used to realize the electrical connection between chips or between chips and the substrate.
  • the interconnect substrate 1 is located between the printed circuit board 20 and the chip 2 .
  • the chip 2 is electrically connected to the interconnection substrate 1 .
  • the chip 2 may be a bare chip (that is, a single die), or may be a packaging structure obtained by packaging one or more bare chips.
  • the present application does not limit the number of interconnection substrates 1 packaged in the packaging structure 10 , and may be one or two, or more than two. Moreover, the number of chips 2 is not limited, and may be one or two, or more than two.
  • the chip 2 above can be a processing chip with data processing functions, such as a central processing unit (central processing unit, CPU), a system on chip (system on chip, SOC) or an image processing unit (graphics processing unit, GPU) And other chips that can process data.
  • the aforementioned chip 2 may also be a memory chip, such as a double-rate synchronous DRAM, a low-power double-rate synchronous DRAM, and the like.
  • the chip 2 is fixed on the top of the interconnection substrate 1 .
  • the bottom surface 101 of the interconnect substrate 1 is provided with a first pad array 11 as shown in FIG. 5 , and the first pad array 11 is used for electrical connection with the printed circuit board 20 .
  • the first pad array 11 includes a first ground pad 111 for providing grounding, and a first signal pad 112 for transmitting signals.
  • the printed circuit board 20 includes a second pad array 201 and a ground structure 202 , and the second pad array 201 is located on the printed circuit board 20 opposite to the bottom surface 101 of the interconnection structure 1 .
  • the second pad array 201 includes a second ground pad 2011 for providing ground and a second signal pad 2012 for transmitting signals.
  • the ground structure 202 may be one or two, or more than two.
  • the second ground pad 2011 is electrically connected to a ground structure 202 , so as to realize the grounding of the second ground pad 2011 .
  • the ground structure 202 may be a bare metal (such as copper) area disposed on the surface or inside of the printed circuit board 20 .
  • the first ground pad 111 may be electrically connected to the second ground pad 2011 .
  • the first ground pad 111 may be electrically connected to the second ground pad 2011 through solder ball array (ball grid array, BGA) or solder paste formed by stencil printing process.
  • the chip 2 can be connected to the second ground pad 2011 of the printed circuit board 20 through the first ground pad 111 of the interconnection substrate 1 , so as to realize the grounding of the chip 2 .
  • the chip 2 can also be electrically connected to the second signal pad 2012 through the first signal pad 112 of the interconnection substrate 1 .
  • the first signal pad 112 may be electrically connected to the second signal pad 2012 through a solder ball array, or solder paste formed by a stencil printing process.
  • the package structure 10 of the embodiment of the present application may also include a shielding case 4 as shown in FIG. Outside the chip 2 and the interconnection substrate 1 . Therefore, the shielding cover 4 can cover the side surface 102 of the interconnection substrate 1 and the entire chip 2 .
  • the shielding case 4 can compress the electromagnetic field generated by the interconnection substrate 1 and the chip 2 inside the shielding case 4, and at the same time prevent the radio frequency interference of other radio frequency devices on the printed circuit board 20 from entering the shielding The inside of the hood 4. Therefore, other radio frequency devices on the printed circuit board 20 are prevented from being interfered by the chip 2 and the signal transmission of the chip 2 is affected by other radio frequency devices on the printed circuit board 20 .
  • the surface of the molding compound 3 and the side surface 102 of the interconnection substrate 1 can be covered with electromagnetic shielding materials (such as resins, diluents, additives, and conductive materials) through processes such as sputtering, electroplating, or spraying.
  • electromagnetic shielding materials such as resins, diluents, additives, and conductive materials
  • Composite material composed of conductive fillers, etc. to form the shielding case 4
  • the shielding case 4 provides electromagnetic shielding for the packaging structure 10 .
  • the shielding case 4 can also be formed by stamping or bending a thin metal shell, and the thin metal shell structure can be made of nickel nickel, pure copper, or tinned iron.
  • the interconnect substrate 1 in the package structure 10 of the embodiment of the present application includes a first electrical connection structure 13 , a second electrical connection structure 12 and a first shielding pad 16 as shown in FIG. 9 .
  • the first electrical connection structure 13 is electrically connected to the chip 2 and the first pad array 11 .
  • the second electrical connection structure 12 is isolated from the first electrical connection structure 13 .
  • a part of the second electrical connection structure 12 may be exposed on the top surface 103 or the side surface 102 of the interconnection substrate 1 , and this part is in contact with the shielding case 4 .
  • the first shielding pads 16 are disposed on the bottom surface 101 of the interconnection substrate 1 and wrap around the periphery of the first pad array 11 .
  • the printed circuit board 20 includes a second shielding pad 203 and at least one grounding structure 202 , and the second shielding pad 203 can be arranged around the periphery of the second pad array 201 and electrically connected to the grounding structure 202 .
  • the projection of the first shielding pad 16 on the printed circuit board 20 may coincide with the second shielding pad 203 .
  • the first shielding pad 16 of the interconnection substrate 1 can be electrically connected with the second shielding pad 203 on the printed circuit board 20, and the interconnection substrate 1
  • the first pad array 11 is electrically connected to the second pad array 201 on the printed circuit board 20 .
  • the electrical connection between the interconnection substrate 1 and the printed circuit board 20 is realized.
  • the solder required for connecting the first shielding pad 16 of the above-mentioned interconnection substrate 1 to the second shielding pad 203 on the printed circuit board 20 and the connection between the first pad array 11 of the interconnection substrate 1 and the printed circuit board
  • the solder required for connecting the second pad array 201 on the 20 can be solder paste formed by a stencil printing process.
  • the first shielding pad 16 can be grounded through the second shielding pad 203 .
  • the first shielding pad 16 can be set around the periphery of the first pad array 11, and the second shielding pad 203 can be set around the periphery of the second pad array 201, so the first shielding pad 16 and
  • the welding structure formed by the connection of the second shielding pads 203 can shield the welding position between the first pad array 11 of the interconnection substrate 1 and the second pad array 201 on the printed circuit board 20 .
  • the grounded solder structure can prevent crosstalk signals from entering or passing through the connection between the packaging structure 10 and the printed circuit board 20 .
  • electromagnetic shielding is formed on the joint between the first pad array 11 of the interconnection substrate 1 and the second pad array 201 on the printed circuit board 20, which improves the shielding performance of the connection between the packaging structure 10 and the printed circuit board 20, and reduces Electromagnetic leakage is reduced, and the product performance of the packaging structure 10 is improved.
  • the second ground pads 2011 in the second pad array 201 may be electrically connected to the ground structure 202 . Therefore, after the chip 2 is electrically connected to the second pad array 201 on the printed circuit board 20 through the first electrical connection structure 13 and the first pad array 11 , the signal of the chip 2 and the reference ground can be transmitted.
  • the second electrical connection structure 12 is electrically connected to the second shielding pad 203 on the printed circuit board 20 through the first shielding pad 16 to achieve grounding.
  • the transmission paths of the ground signal of the first electrical connection structure 13 and the reference ground signal of the second electrical connection structure 12 are different, and the first electrical connection structure 13 and the second electrical connection structure 12 are isolated from each other, so the chip 2
  • the transmission of the reference ground signal and the transmission of the ground signal of the second electrical connection structure 12 have little mutual influence.
  • the shielding case 4 can also be grounded to the printed circuit board 20 through the electrical connection structure 12 and the first shielding pad 16 .
  • the grounded shield 4 can guide the induced charge generated by the external electromagnetic field of other radio frequency devices on the printed circuit board 20 to the ground terminal through the electrical connection structure 12 and the first shielding pad 16, and the accumulated induced charge can be released.
  • the shielding case 4 can further block the diffusion of the external electromagnetic field toward the shielding case 4, the signal transmission of the chip 2 is not interfered by the external electromagnetic field, avoids the antenna effect, and improves the shielding of the welding place between the interconnection substrate 1 and the printed circuit board 20 ability. Moreover, there is no need to provide a special circuit structure to realize the grounding of the shielding case 4 , which can simplify the circuit structure of the interconnection substrate 1 .
  • interconnection substrate 1 (encapsulation substrate or redistribution layer) in the package structure 10 shown in FIG. 9
  • the interconnection substrate 1 is directly electrically connected to the printed circuit board 20 .
  • a chip stack structure 2a and a chip 2b are electrically connected to the packaging substrate 1a.
  • the redistribution layer 1b is located above the packaging substrate 1a and is electrically connected to the packaging substrate 1a. The connection of the package substrate 1 a and the printed circuit board 20 .
  • Both the packaging substrate 1a and the redistribution layer 1b may have the above-mentioned second electrical connection structure 12 and the second shielding pad 16 .
  • the second electrical connection structure 12 and the second shielding pad 16 in the redistribution layer 1 b can further reduce external interference signals from entering the package structure 10 .
  • first ground pad 111 in the first pad array 11 on the interconnection substrate 1 and the second electrical connection structure 12 are electrically connected to the same ground structure 202, that is, the second ground pad in the second pad array 201
  • the pad 2011 and the second shielding pad 16 are electrically connected to the same ground structure 202 .
  • the reference ground signal transmitted by the first ground pad 111 and the ground signal of the electrical connection structure 12 will affect each other. Therefore, as shown in FIG. 11 , there are two ground structures 202 in the printed circuit board 20 of the embodiment of the present application, and the two ground structures 202 are respectively a first ground structure 202 a and a second ground structure 202 b.
  • the electrical connection structure 12 is electrically connected to the first ground structure 202a, and the first ground pad 111 in the first pad array 11 is electrically connected to the second ground structure 202b through the second ground pad 2011 of the second pad array 201. connect. Therefore, the ground signal of the shielding case 4 and the electrical connection structure 12 will not interfere with the reference ground signal transmitted by the first ground pad 111 in the first pad array 11, and the signal transmission of the first ground pad 111 will be more stable. , and the shielding effect of the shielding case 4 and the electrical connection structure 12 is better.
  • the interconnection substrate 1 is a packaging substrate as an example, in combination with the specific structure of the packaging substrate, the above-mentioned first electrical connection structure 13 and the second electrical connection structure 12 are carried out. illustrate.
  • the packaging substrate 1 a includes multiple dielectric layers 130 .
  • the above-mentioned first electrical connection structure 13 includes a plurality of circuit layers 14 and via holes 15 as shown in FIG. 13 .
  • Multiple dielectric layers 130 and multiple circuit layers 14 are laminated, and the dielectric layer 130 is located between two adjacent circuit layers 14 .
  • Two adjacent circuit layers 14 can be electrically connected through a via (Via) 15 formed in the dielectric layer 130 .
  • Multiple layers of circuit layers 14 electrically connected through via holes 15 can constitute the circuit structure of the packaging substrate 1a.
  • a first dielectric layer is formed first, and then a whole metal layer is formed on the first dielectric layer through a film-forming process. Then, a patterning process is used to remove the metal material in a part of the metal layer, and the metal material remaining in the metal layer can be used as the first circuit layer. Afterwards, the second dielectric layer, the second circuit layer, the third dielectric layer, ..., and the Nth dielectric layer are sequentially stacked in the same manner, and the internal circuit structure of the packaging substrate 1a can be produced.
  • the above-mentioned patterning process may refer to include photolithography process, or include photolithography process and etching steps, and may also include other processes for forming predetermined patterns such as printing and inkjet; The process of using photoresist, mask plate, exposure machine, etc. to form graphics in the process of film, exposure, and development.
  • a corresponding patterning process can be selected according to the structure formed in this application.
  • the one-time patterning process in the embodiment of the present application is based on forming different exposure areas through one mask exposure process, and then performing multiple etching, ashing and other removal processes on different exposure areas to finally obtain the expected pattern. instruction of.
  • the second electrical connection structure 12 can have various structures.
  • the second electrical connection structure 12 may include a metal wiring 121a embedded in the packaging substrate 1a as shown in FIG. 13, and the metal wiring 121a may be exposed from the side surface 102 of the packaging substrate 1a, And it is in contact with the shield cover 4 .
  • the second electrical connection structure 12 in FIG. 12 includes a metal wiring 121a, and the above-mentioned first shielding pad 16 may be electrically connected to the metal wiring 121a.
  • the metal wiring 121 a can be electrically connected to the ground structure 202 on the printed circuit board 20 through the first shielding pad 16 and the second shielding pad 203 in sequence. Therefore, the shielding case 4 can be electrically connected to the ground structure 202 on the printed circuit board 20 through the metal wiring 121a.
  • the metal wiring 121a in the packaging substrate 1a can be made of the same layer and the same material as the circuit layer 14 .
  • the above-mentioned metal wiring 121a may also be formed by a patterning process. A whole layer of metal layer is formed on the dielectric layer 130 through a film forming process, and then the metal material in a part of the metal layer is removed by patterning process, and the metal material remaining in the metal layer can be used as a layer of metal wiring 121a and circuit layer 14 . In this way, the preparation of the metal wiring 121a can also be completed while the circuit layer 14 is being manufactured, thereby reducing the process flow and reducing the manufacturing cost.
  • the above-mentioned “same layer” refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • the same patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous.
  • These specific graphics may also be at different heights or have different thicknesses.
  • the second electrical connection structure 12 may include only one layer of metal wiring 121a as shown in FIG. 13 , or may include multiple layers of metal wiring 121a as shown in FIG. 14 , which is not limited in the present application.
  • each wiring layer 14 can be located in the metal wiring 121a of the same layer, and the multilayer metal wiring 121a can play a role of shielding protection for the multilayer wiring layer 14 respectively.
  • the metal wiring 121a of the same layer can be made of the same layer and the same material as the circuit layer 14 .
  • the second electrical connection structure 12 in order to realize the connection between two adjacent layers of metal wiring 121a, as shown in FIG. 14 , the second electrical connection structure 12 also includes a plurality of first electrical connections Vias 122 . Two adjacent layers of metal wiring 121a may be electrically connected through the first electrical connection via hole 122 .
  • the above-mentioned plurality of first electrical connection vias 122 may also be in contact with the shielding case 4 .
  • the first electrical connection via hole 122 can be cut directly, so that the first electrical connection via hole 122 can be exposed from the side surface 102 of the packaging substrate 1a. Therefore, the shielding case 4 of the shielding layer structure formed on the side surface 102 of the packaging substrate 1a can have a larger connection area and more connection positions with the first electrical connection via hole 122 and the multilayer metal wiring 121a, so that the shielding case 4 and the first The connection strength between the two electrical connection structures 12 is relatively high, and the shielding case 4 can be reliably grounded.
  • the above-mentioned shielding cover 4 can be formed on the side surface 102 of the packaging substrate 1a and the outer surface of the molding compound 3 by sputtering, electroplating or spraying, which can facilitate the exposure of the shielding cover 4 and the side surface 102 of the packaging substrate 1a.
  • the metal wiring 121a is in contact, and the contact between the shield case 4 and the metal wiring 121a is more reliable.
  • the shielding case 4 can be The molding compound 3 and the side surface 102 of the packaging substrate 1 a are wrapped in the form of a shielding layer. Since the electromagnetic shielding layer is thinner, the package structure 10 with the shielding layer has a smaller volume. Therefore, when the package structure 10 is soldered on the printed circuit board 20 , the shielding layer will not occupy a large space on the printed circuit board 20 , thereby improving the integration of the electronic devices on the printed circuit board 20 .
  • the above-mentioned second electrical connection structure 12 may include a second electrical connection via hole (Via) 121 b as shown in FIG. 16 .
  • the second electrical connection via hole 121b runs through the bottom surface 101 and the top surface 103 of the package substrate 1a.
  • the top surface 103 of the packaging substrate 1 a refers to the surface connected to the chip 2
  • the bottom surface 101 of the packaging substrate 1 a refers to the surface connected to the printed circuit board 20 .
  • the second electrical connection via hole 121 b may be exposed from the top surface 103 of the package substrate 1 a and be electrically connected to the shielding case 4 .
  • the shielding case 4 electrically connected to the second electrical connection via hole 121b is only covered on the outside of the molding compound 3, and the lower end surface of the shielding case 4 can be connected to the second electrical connection via hole 121b from the The exposed portion of the top surface 103 of the package substrate 1a is in contact.
  • the second electrical connection via hole 121b may also be exposed from the bottom surface 101 of the package substrate 1a, and be electrically connected to the second shielding pad 203 on the printed circuit board 20 .
  • the second electrical connection via hole 121b can be manufactured by the following process: after the circuit structure in the packaging substrate 1a is manufactured, chemical etching (such as chemical etching using hydrofluoric acid) , laser (laser), laser induced wet etching (laser induced wet etch) and other methods to open through holes on the packaging substrate 1a. Afterwards, a metal film such as titanium (Ti) or nickel (Ni) may be formed in the through hole by a sputtering (physical vapor deposition, PVD) process, and the metal film may be used as an adhesive layer.
  • chemical etching such as chemical etching using hydrofluoric acid
  • laser laser
  • laser induced wet etching laser induced wet etch
  • PVD physical vapor deposition
  • a copper (Cu) layer is formed as a seed layer on the metal thin film by using a sputtering (such as magnetron sputtering or ion beam sputtering) process.
  • a sputtering such as magnetron sputtering or ion beam sputtering
  • the thickness of the seed layer is increased by means of electrochemical deposition (ECD), so that the through hole is filled with copper material, thereby forming the above-mentioned second electrical connection via hole 121b.
  • ECD electrochemical deposition
  • the second electrical connection via hole 121b can also be manufactured by the following process: After opening a through hole on the packaging substrate 1a, inject silver paste into the through hole, and then use a thermal process to solidify the silver paste, thereby forming the above-mentioned second electrical connection via hole 121b.
  • the connection via hole 121b After opening a through hole on the packaging substrate 1a, inject silver paste into the through hole, and then use a thermal process to solidify the silver paste, thereby forming the above-mentioned second electrical connection via hole 121b.
  • the first shielding pad 16 can be designed according to the distribution positions of other radio frequency devices (interference sources) on the printed circuit board 20 relative to the package structure 10.
  • the pads 16 are located outside the first pad array 11 .
  • the second shielding pad 203 coincides with the projection of the first shielding pad 16 on the printed circuit board 20 , so the second shielding pad 203 can be adjusted according to the structure of the first shielding pad 16 .
  • the structure of the shielding case 4 can also be adjusted according to the distribution positions of other radio frequency devices (interference sources) on the printed circuit board 20 relative to the package structure 10 .
  • the second electrical connection structure 12 since the second electrical connection structure 12 needs to be connected to the first shielding pad 16 and the shielding case 4, the second electrical connection structure 12 also needs to be carried out according to the structure of the first shielding pad 16 and the structure of the shielding case 4. Adjustment.
  • the package structure 10 and the package substrate 1a as cuboids, the first pad array 11 and the second pad array 201 as rectangular arrays, and the second electrical connection structure 12 including the above-mentioned metal wiring 121a as an example, it is described in the setting of the interference source
  • the structure of the first shielding pad 16 , the second shielding pad 203 , the shielding case 4 and the metal wiring 121 a is different at different positions on the outer periphery of the package structure 10 .
  • there are four sides of the packaging substrate 1 a there are four sides of the packaging substrate 1 a, and the four sides are respectively 102 a, 102 b, 102 c, and 102 d.
  • the other radio frequency devices on the printed circuit board 20 are located opposite to the side surface 102 a of the package substrate 1 a.
  • the arrow on the left side in FIG. 19 indicates the transmission direction of electromagnetic interference signals generated by other radio frequency devices on the printed circuit board 20 .
  • the first shielding pads 16 are elongated, and are only wound around the edge of one side of the first pad array 11 close to the side surface 102a.
  • the second shielding pads 203 in the printed circuit board 20 may also be elongated and located outside the edge of one side of the second pad array 201 corresponding to the side surface 102a.
  • the metal wiring 121a may be exposed only on the side surface 102a of the package substrate 1a.
  • the shielding case 4 includes a main body portion 41 covering the top of the molding compound 3 , and a connecting portion 42 connected to the main body portion 41 .
  • the connecting portion 42 may cover the side surface 102a of the package substrate 1a to be connected to the metal wiring 121a.
  • the connecting portion 42 of the shielding case 4 may only cover the upper side of the package substrate 1 a, or may cover the upper side and the middle of the side of the package substrate 1 a.
  • the connecting portion 42 of the shielding case 4 may also directly cover an entire side surface of the packaging substrate 1a, and the manufacturing of the shielding case 4 is more convenient. Specifically, it can be selected according to the position where the metal wiring 121a is exposed on the side of the package substrate 1a, as long as the connection portion 42 of the shielding cover 4 can be in contact with the metal wiring 121a.
  • the first shielding pad 16 includes two strip-shaped pads, and the two strip-shaped pads are respectively the first strip-shaped pad 16a and the second strip-shaped pad as shown in FIG. 22 16b.
  • the first strip-shaped pad 16a can be arranged outside the side edge of the first pad array 11 near the side 102a, and the second strip-shaped pad 16b can be arranged on the side edge of the first pad array 11 near the side 102c. outside.
  • the two strip-shaped pads of the first shielding pad 16 are relatively arranged and relatively independent.
  • the first strip-shaped pad 16a and the second strip-shaped pad 16b may be connected.
  • the first shielding pad 16 is L-shaped.
  • the second shielding pad 203 in the printed circuit board 20 also includes two strip-shaped pads 203a and 203b, and the two strip-shaped pads 203a and 203b are respectively located in the second pad array 201 outside the edges on both sides.
  • the strip pad 203a is opposite to the first strip pad 16a
  • the strip pad 203b is opposite to the second strip pad 16b.
  • the metal wiring 121a may be exposed only on the side surfaces 102a and 102c of the package substrate 1a.
  • One connecting portion 42a of the shielding case 4 covers the side surface 102a of the packaging substrate 1a, and the other connecting portion 42b covers the side surface 102c of the packaging substrate 1a, so that both connecting portions 42a and 42b are electrically connected to the metal wiring 121a. .
  • the first shielding pad 16 includes three interconnected strip pads.
  • the three strip-shaped pads are respectively a first strip-shaped pad 16a, a second strip-shaped pad 16b and a third strip-shaped pad 16c as shown in FIG. 26 .
  • the first strip-shaped pad 16a can be arranged on the first pad array 11 near the side edge of the side surface 102a
  • the second strip-shaped pad 16b can be arranged on the first pad array 11 near the side edge of the side surface 102b.
  • the third strip-shaped pads 16c may be disposed outside the edge of one side of the first pad array 11 that is close to the side surface 102c.
  • the second shielding pad 203 in the printed circuit board 20 also includes three bar-shaped pads 203a, 203b and 203c, and the three bar-shaped pads 203a, 203b and 203c are respectively located in the second pad array 201 outside the edge on three sides. Furthermore, the strip pad 203a is opposite to the first strip pad 16a, the strip pad 203b is opposite to the second strip pad 16b, and the strip pad 203c is opposite to the third strip pad 16c.
  • the metal wiring 121a may be exposed only on three sides of the package substrate 1a.
  • the shielding case 4 includes three connecting portions 42a, 42b, 42c, the connecting portion 42a of the shielding case 4 can cover the side surface 102a of the packaging substrate 1a, and the connecting portion 42b of the shielding case 4 can cover the side surface of the packaging substrate 1a 102b, the connection portion 42c of the shielding case 4 may cover the side surface 102c of the package substrate 1a, so that the three connection portions 42a, 42b, 42c are all electrically connected to the metal wiring 121a.
  • radio frequency devices (interference sources) on the printed circuit board 20 are only distributed in a partial area of the outer periphery of the rectangular package structure 10 .
  • the above-mentioned first shielding pad 16 can be made into a ring structure.
  • the first shielding pad 16 may be a ring structure connected end to end, for example, the ring structure may be a rectangular ring.
  • the first pad arrays 11 in the packaging substrate 1a may all be located within the ring structure.
  • the second shielding pad 203 in the printed circuit board 20 may also be a ring structure connected end to end.
  • the first shielding pad 16 can be the same size as the second shielding pad 203, so that a circle of the first shielding pad 16 can be connected to a circle of the second shielding pad 203, and the first shielding pad 16 and the second shielding pad 203 can be connected to each other.
  • the welding structure formed by the connection of the second shielding pads 203 can completely shield the solder joints between the first pad array 11 of the package substrate 1 a and the second pad array 201 on the printed circuit board 20 , and the shielding effect is better.
  • the above-mentioned metal wiring 121a can also be made as a ring circuit connected end to end, and the metal wiring 121a can be exposed on the four sides 102a, 102b, 102c and 102d of the package substrate 1a.
  • the shield case 4 includes four connecting portions 42a, 42b, 42c and 42d.
  • the connecting portion 42a of the shielding case 4 can cover the side surface 102a of the packaging substrate 1a
  • the connecting portion 42b of the shielding case 4 can cover the side surface 102b of the packaging substrate 1a
  • the connecting portion 42c of the shielding case 4 can cover the side surface of the packaging substrate 1a.
  • the connecting portion 42d of the shielding case 4 may cover the side surface 102d of the package substrate 1a. Therefore, the whole circumference of the shielding case 4 can be in contact with the metal wiring 121a, so that the grounding signal of each area along the circumferential direction of the shielding case 4 is stable, and the shielding effect is better.
  • the first shielding pad 16 may include a plurality of first strip-shaped sub-pads 161 arranged at intervals and sequentially arranged in a ring structure.
  • the second shielding pad 203 in the printed circuit board 20 may also include a plurality of second strip-shaped sub-pads 2031, the plurality of second strip-shaped sub-pads 2031 are arranged at intervals, and Arranged sequentially in a ring structure.
  • the first strip-shaped sub-pad 161 in each first shielding pad 16 may correspond to the second strip-shaped sub-pad 2031 in the second shielding pad 203 and have the same size.
  • the first strip-shaped sub-pad 161 in any one of the first shielding pads 16 can be soldered to the second strip-shaped sub-pad 2031 in the corresponding second shielding pad 203 .
  • the first shielding pad 16 with a gap can facilitate the reflow soldering operation with the second shielding pad 203 of the printed circuit board 20 .
  • the first shielding pad 16 it can be understood that when designing the distance between two adjacent first strip-shaped sub-pads 161 in the first shielding pad 16, the distance should be reduced as much as possible to reduce interference. The signal passes through this gap.
  • soldering structure formed by the first shielding pad 16 and the second shielding pad 203 with a gap can also connect the first pad array 11 on the package substrate 1a and the second pad array 201 on the printed circuit board 20.
  • the welding place has a good shielding effect.
  • the metal wiring 121a can also be made as a ring circuit with a gap, and the metal wiring 121a can also be exposed on the side surface 102 of the package substrate 1a for a week.
  • the four connecting parts 42 of the shielding case 4 can also be in contact with the metal wiring 121a on a circle, so that the grounding signal of each area along the circumferential direction of the shielding case 4 is stable, and the shielding effect is better.
  • the interference signal can directly pass through the gap between the metal wiring 121a and the circuit layer 14 from the bottom of the package substrate 1a, the transmission path of the interference signal is relatively short, and the loss during transmission is relatively small. less, the electromagnetic interference inside the package structure 10 is greater. Therefore, referring to FIG.
  • the line widths W of any two layers of the multilayer metal wiring 121 a are different ring structures. That is, the vertical projections of the multilayer metal wiring 121a on the packaging substrate 1a may partially overlap.
  • the line width W of the metal wiring 121a of any two layers is different, so that when the interference signal passes through or passes through the multi-layer metal wiring 121a, the path bends more and the path is longer, which is beneficial to the loss and reduction of the interference signal. Therefore, the electromagnetic interference to the inside of the package structure 10 is further reduced.
  • FIG. 34 shows the projections of the three-layer metal wiring 121a on the package substrate 1a.
  • the second electrical connection structure 12 includes the above-mentioned metal wiring 121a.
  • the second electrical connection via hole 121b can also The plate 16 and the shielding case 4 are adjusted, for example, the second electrical connection via hole 121b is in an annular or non-annular structure.
  • the second electrical connection via hole 121b can also be made as an end-to-end ring-shaped via hole. Moreover, the second electrical connection via hole 121b can be exposed on the top surface 103 of the package substrate 1a for a week, so that the grounding signal of each area along the circumferential direction of the shielding cover 4 is stable, and the shielding effect is better.
  • the second electrical connection via hole 121b may include a plurality of strip-shaped via holes 1211 , and the plurality of strip-shaped via holes 1211 are arranged at intervals and sequentially arranged in a ring structure.
  • the plurality of strip-shaped via holes 1211 in the second electrical connection via hole 121b may be exposed on the top surface 103 of the package substrate 1a, and the shielding cover 4 may be in contact with each of the plurality of strip-shaped via holes 1211 from the top surface 103 of the package substrate 1a, The grounding signal of each area along the circumferential direction of the shielding cover 4 is stabilized, and the shielding effect is better.
  • the first pad array 11 may also adopt other array forms, such as a circular array.
  • the first shielding pads 16 can be wound around a part of the area or outside the entire area of the circular array.
  • the second shielding pad 203 , the second electrical connection structure 12 and the shielding case 4 can also be adjusted accordingly, and will not be illustrated here one by one.

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Abstract

本申请实施例提供一种封装结构、电路板组件及电子设备，涉及电子封装技术领域。本申请的封装结构包括芯片、屏蔽罩和互联基板。芯片设置在互联基板的顶部，且与互联基板电连接。该屏蔽罩罩设在芯片外。互联基板包括第一电连接结构、第二电连接结构、第一焊盘阵列及第一屏蔽焊盘。第一电连接结构与芯片电连接，第二电连接结构暴露于互联基板的顶面或侧面上的部分与屏蔽罩相接触。第一焊盘阵列和第一屏蔽焊盘均设置在互联基板的底面上。第一屏蔽焊盘与第一电连接结构电性连接，且绕设在第一焊盘阵列的外围。第一屏蔽焊盘与印刷电路板上的焊盘连接形成的焊接结构可以对互联基板的第一焊盘阵列与印刷电路板上的第二焊盘阵列的焊接位置形成电磁屏蔽。

Description

一种封装结构、电路板组件及电子设备 技术领域
本申请涉及电子设备技术领域，尤其涉及一种封装结构、电路板组件及电子设备。
背景技术
随着半导体产品系统化、微小化的不断发展，在有限的体积上需要集成的射频(radio frequency，RF)功能模块越来越多，如WCDMA(wideband code division multiple access，宽带码分多址)模块、LTE(long term evolution，长期演进)模块、WiFi模块、蓝牙模块及GPS(global positioning system，全球定位系统)模块等。射频功能模块的数据传输速率越来越快，数据量越来越大，使得射频功能模块之间的干扰也越来越大，严重影响信号传输的连续性和准确性。因此，半导体产品的抗电磁干扰设计变得越来越重要。
以半导体产品为封装结构为例，封装结构包括层叠设置的芯片和封装基板，以及罩设在芯片和封装基板的外侧的电磁屏蔽罩(electromagnetic interference shielding)。该电磁屏蔽罩可以将整个芯片、封装基板的侧面与外界隔离。但是，当将封装结构安装在印刷电路板上时，该电磁屏蔽罩无法对封装基板的底部与印刷电路板之间的焊接位置形成屏蔽。所以在该焊接位置会存在电磁泄露的问题，而严重影响封装结构的产品性能。
发明内容
本申请实施例提供一种封装结构、电路板组件及电子设备，用于解决现有技术中封装基板的底部与印刷电路板之间的焊接位置会存在电磁泄露而影响封装结构的产品性能的问题。
第一方面，本申请实施例提供一种封装结构包括芯片、屏蔽罩和互联基板。其中，芯片设置在互联基板的顶部，且与互联基板电连接。该互联基板可以为封装基板或重布线层。该屏蔽罩罩设在芯片外，芯片被收容在屏蔽罩和互联基板围成的空间中。该互联基板包括第一电连接结构、第二电连接结构、第一焊盘阵列及第一屏蔽焊盘。其中，第一电连接结构与芯片电连接。第二电连接结构与第一电连接结构隔离。第二电连接结构暴露于互联基板的顶面或侧面上的部分与屏蔽罩相接触。第一焊盘阵列和第一屏蔽焊盘均设置在互联基板的底面上。第一焊盘阵列可以包括第一接地焊盘和第一信号焊盘，第一接地焊盘用于提供接地，第一信号焊盘用于传输信号。第一屏蔽焊盘与第一电连接结构电性连接，且第一屏蔽焊盘绕设在第一焊盘阵列的外围。因此，当将封装结构中的互联基板安装在印刷电路板上时，互联基板的第一屏蔽焊盘可以与印刷电路板上的第二屏蔽焊盘连接，并可以通过印刷电路板上的第二屏蔽焊盘(该第二屏蔽焊盘可以与印刷电路板内的接地结构电连接)接地，互联基板的第一焊盘阵列可以与印刷电路板上的第二焊盘阵列电连接。由于互联基板的第一屏蔽焊盘绕设在第一焊盘阵列的外围，所以，互联基板的第一屏蔽焊盘与印刷电路板上的第二屏蔽焊盘连 接形成的焊接结构可以遮挡互联基板的第一焊盘阵列与印刷电路板上的第二焊盘阵列的焊接位置。接地后的该焊接结构能够阻挡串扰信号进入或穿出封装结构与印刷电路板的连接处。从而，对互联基板的第一焊盘阵列与印刷电路板上的第二焊盘阵列的焊接处形成电磁屏蔽，提高了封装结构与印刷电路板的连接处屏蔽性能，减少了电磁泄露，提高了封装结构的产品性能。并且，芯片通过第一电连接结构、第一焊盘阵列与印刷电路板上的第二焊盘阵列电连接。第二电连接结构通过第一屏蔽焊盘与印刷电路板上的第二屏蔽焊盘电连接。由于第一电连接结构与第二电连接结构相互隔离，所以，芯片的参考地信号的传输与第二电连接结构的接地信号的传输相互影响较小。此外，屏蔽罩可以通过第二电连接结构和第一屏蔽焊盘接地于印刷电路板上，接地后的屏蔽罩可以将因印刷电路板上其他射频器件的外部电磁场而产生的感应电荷，通过第二电连接结构和第一屏蔽焊盘导入接地端，积累的感应电荷得以释放。因此，屏蔽罩可以进一步阻挡外部电磁场朝屏蔽罩内扩散，芯片的信号传输不受外部电磁场的干扰，避免出现天线效应，提高了对互联基板与印刷电路板的焊接处的屏蔽能力。并且，不需设置专门的电路结构来实现屏蔽罩的接地，简化互联基板内的电路结构。
在第一方面的一种可能的实现方式中，第一焊盘阵列为矩形阵列。第一屏蔽焊盘可以绕设在第一焊盘阵列的两侧边沿、或三侧边沿外，通过将第一屏蔽焊盘设置在第一焊盘阵列外不同的位置和覆盖区域，可以适用于封装结构外具有不同位置干扰源的情况。
在第一方面的一种可能的实现方式中，该第二电连接结构包括至少一层金属布线。金属布线暴露于互联基板的至少一个侧面上，且与屏蔽罩相接触。该第二电连接结构的结构较简单。
在第一方面的一种可能的实现方式中，上述第一电连接结构包括多层线路层。该互联基板还包括多层介质层，多层介质层与多层线路层层叠设置，且介质层位于相邻两层线路层之间。相邻线路层可以通过过孔连接，多层电连接的线路层可以构成该封装基板的电路结构。上述金属布线可以为一层或多层。一层的金属布线可以与一层线路层可以同层同材料。因此，本申请实施例能够采用同一次构图工艺同时制作金属布线与线路层，减少工艺流程，降低制作成本。
在第一方面的一种可能的实现方式中，上述第二电连接结构包括多层金属布线。第二电连接结构还包括多个贯穿介质层的第一电连接过孔，第一电连接过孔将相邻两层金属布线电连接。并且，多个第一电连接过孔可以与屏蔽罩相接触。第二电连接结构与屏蔽罩的连接面积较大、连接位置较多，从而两者之间的连接强度较大，屏蔽罩能够可靠接地。
在第一方面的一种可能的实现方式中，任两层金属布线的线宽不同，可以使得干扰信号在绕过多层接地图案传出时，路径弯折更多，路径更长，有利于干扰信号的损耗、消减。
在第一方面的一种可能的实现方式中，上述第二电连接结构包括第二电连接过孔。第二电连接过孔贯穿互联基板的底面和顶面。第二电连接过孔暴露于顶面的部分与屏蔽罩电连接。第二电连接过孔暴露于底面的部分与第一屏蔽焊盘电连接。该电连接结构工艺制作也较简单方便。
在第一方面的一种可能的实现方式中，上述第一屏蔽焊盘为首尾相接的环形结构。第一屏蔽焊盘的一周可以均与印刷电路板上的焊盘连接，第一屏蔽焊盘与印刷电路板上的焊盘形成的焊接结构可以将互联基板的第一焊盘阵列与印刷电路板上的第二焊盘阵列的焊接处一周完全遮挡，屏蔽效果较好。
在第一方面的一种可能的实现方式中，上述第一屏蔽焊盘包括多个条形子焊盘，多个条形子焊盘间隔设置、且依次排列成环形结构。该具有间隙的第一屏蔽焊盘能够便于第一屏蔽焊盘与印刷电路板上的焊盘之间的回流焊接操作。
在第一方面的一种可能的实现方式中，上述互联基板为封装基板或重布线层。
第二方面，本申请实施例还包括一种电路板组件。该电路板组件包括印刷电路板和上述实施例所述的封装结构。其中，印刷电路板包括第二屏蔽焊盘、第二焊盘阵列和至少一个接地结构。第二屏蔽焊盘绕设在第二焊盘阵列的外围，且第二屏蔽焊盘、第二焊盘阵列与接地结构电连接。第二焊盘阵列可以包括第二接地焊盘和第二信号焊盘。第二接地焊盘用于提供接地，第二信号焊盘用于传输信号。封装结构中互联基板的第一屏蔽焊盘与第二屏蔽焊盘电连接，封装结构中互联基板的第一焊盘阵列与第二焊盘阵列电连接。由于本申请实施例的电路板组件中的封装结构与上述实施例中的封装结构的结构相同，所以，两者能够解决相同的技术问题，并获得相同的技术效果，此处不再赘述。
在第二方面的一种可能的实现方式中，上述至少一个接地结构包括第一接地结构和第二接地结构，第一接地结构与第二屏蔽焊盘电连接，第二接地结构与第二焊盘阵列中的部分焊盘电连接。因此，屏蔽罩和第二电连接结构可以通过第二屏蔽焊盘与第一接地结构电连接来实现接地，第一焊盘阵列中的第一接地焊盘通过第二焊盘阵列中的第二接地焊盘与第二接地结构电连接来实现接地，进一步使得屏蔽罩和第二电连接结构的接地信号与第一焊盘阵列中部分焊盘的参考地信号不会相互影响，信号传输更稳定，且屏蔽罩和第二电连接结构的屏蔽效果也较好。
在第二方面的一种可能的实现方式中，第一屏蔽焊盘在印刷电路板上的投影与第二屏蔽焊盘重合，从而便于第一屏蔽焊盘与第二屏蔽焊盘的连接。
第三方面，本申请实施例还包括一种电子设备。该电子设备包括壳体、以及位于壳体内的上述电路板组件。由于本申请实施例的电子设备中的电路板组件与上述实施例中的电路板组件的结构相同，所以，两者能够解决相同的技术问题，并获得相同的技术效果，此处不再赘述。
附图说明
图1为本申请实施例中电子设备的结构示意图；
图2为本申请实施例电子设备的爆炸图；
图3为本申请实施例电子设备中电路板组件的结构示意图；
图4为本申请实施例电子设备中封装结构的结构示意图；
图5为本申请实施例电子设备中互联基板的结构示意图；
图6为本申请实施例电子设备中电路板组件的爆炸示意图；
图7为本申请实施例电子设备中互联基板与印刷电路板的连接示意图；
图8为本申请实施例电子设备中电路板组件的截面示意图；
图9为本申请实施例电子设备中封装结构具有电连接结构的结构示意图；
图10为本申请实施例电子设备中封装结构具有两个互联基板的结构示意图；
图11为本申请实施例电子设备中封装结构与印刷电路板中的接地结构电连接的结构示意图；
图12为本申请实施例电子设备中封装基板的截面示意图；
图13为本申请实施例电子设备中封装基板的第二连接结构包括金属布线的立体结构示意图；
图14为本申请实施例电子设备中封装基板的第二连接结构包括多层金属布线的立体结构示意图；
图15为相关技术中电路板组件的结构示意图；
图16为本申请实施例电子设备中封装基板的第二连接结构包括第二电连接过孔的截面示意图；
图17为本申请实施例电子设备中封装结构的第二连接结构包括第二电连接过孔的截面示意图；
图18为本申请实施例电子设备中封装基板的立体示意图；
图19为本申请实施例电子设备中封装结构的第一屏蔽焊盘绕设在第一焊盘阵列一侧外的仰视图；
图20为本申请实施例电子设备中电路板组件的第二屏蔽焊盘绕设在第二盘阵列一侧外的结构示意图；
图21为本申请实施例电子设备中封装结构的屏蔽罩的三个连接部分别覆盖在封装基板的一侧外的透视图；
图22为本申请实施例电子设备中封装结构的第一屏蔽焊盘绕设在第一焊盘阵列相对两侧外的仰视图；
图23为本申请实施例电子设备中封装结构的第一屏蔽焊盘绕设在第一焊盘阵列相邻两侧外的仰视图；
图24为本申请实施例电子设备中电路板组件的第二屏蔽焊盘绕设在第二焊盘阵列相对两侧外的结构示意图；
图25为本申请实施例电子设备中封装结构的屏蔽罩的三个连接部分别覆盖在封装基板的相对两侧外的透视图；
图26为本申请实施例电子设备中封装结构的第一屏蔽焊盘绕设在第一焊盘阵列三侧外的仰视图；
图27为本申请实施例电子设备中电路板组件的第二屏蔽焊盘绕设在第二焊盘阵列三侧外的结构示意图；
图28为本申请实施例电子设备中封装结构的屏蔽罩的三个连接部分别覆盖在封装基板的三侧外的透视图；
图29为本申请实施例电子设备中封装结构具有环形的第一屏蔽焊盘的结构示意图；
图30为本申请实施例电子设备中电路板组件的第二屏蔽焊盘绕设在第二焊盘阵 列一周外的结构示意图；
图31为本申请实施例电子设备中封装结构的屏蔽罩的四个连接部分别覆盖在封装基板的四个侧面外的透视图；
图32为本申请实施例电子设备中封装结构具有环形、且有间隙的第一屏蔽焊盘的结构示意图；
图33为本申请实施例电子设备中电路板组件的环形、且有间隙的第二屏蔽焊盘绕设在第二焊盘阵列一周外的结构示意图；
图34为本申请实施例电子设备中3层金属布线的投影示意图；
图35为本申请实施例电子设备中封装基板的第二连接结构包括环形的第二电连接过孔的结构示意图；
图36为本申请实施例电子设备中封装基板的第二连接结构包括环形且有间隙的第二电连接过孔的结构示意图。
附图标记：
1000-电子设备，100-屏幕，200-中框，300-后壳，400-电路板组件，500-摄像头，10-封装结构，1-互联基板，1a-封装基板，1b-重布线层，101-底面，102、102a、102b、102c、102d-侧面，103-顶面，12-第二电连接结构，121a-金属布线，122-第一电连接过孔，121b-第二电连接过孔，1211-条形过孔，13-第一电连接结构，130-介质层，14-线路层，15-过孔，16-第一屏蔽焊盘，161-第一条形子焊盘，16a-第一条形焊盘，16b-第二条形焊盘，16c-第三条形焊盘，2-芯片，3-塑封料，4-屏蔽罩，41-主体部，42、42a、42b、42c；42d-连接部，20-印刷电路板，201-第二焊盘阵列，2011-第二接地焊盘，2012-第二信号焊盘，202-接地结构，202a-第一接地结构，202b-第二接地结构，203-第二屏蔽焊盘，2031-第二条形子焊盘；203a、203b、203c-条形焊盘。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请中，“上”、“下”、“左”、“右”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“电连接”可以是直接的电性连接，也可以是通过中间媒介间接的电性连接。
本申请提供一种电子设备，该电子设备可以包括手机、平板电脑(tablet personal computer)、膝上型电脑(laptop computer)、个人数码助理(personal digital assistant，PDA)、照相机、个人计算机、笔记本电脑、智能手表、平板电脑、车载设备、可穿 戴设备、增强现实(augmented reality，AR)眼镜、AR头盔、虚拟现实(virtual reality，VR)眼镜、VR头盔、服务器、交换机、网桥(又称桥接器)、中继器、路由器或者网关(又称协议转换器)等设备。本申请实施例对上述电子设备的具体形式不做特殊限制。以下为了方便说明，均是以该电子设备为如图1所示的手机为例进行的举例说明。
请参照图1和图2，图1为本申请一些实施例提供的电子设备的立体图，图2为图1所示电子设备的爆炸图。由上述可知，在本实施例中，电子设备1000可以为手机。电子设备1000可以包括如图2所示的屏幕100、中框200、壳体300及固定在中框200上的电路板组件400。
可以理解的是，图1和图2仅示意性的示出了电子设备1000包括的一些部件，这些部件的实际形状、实际大小、实际位置和实际构造不受图1和图2的限制。在其他一些示例中，电子设备1000也可以不包括屏幕100。或者，电子设备1000还可以包括如图2所示的摄像头500。
在本申请的一些实施例中，如图3所示，上述电路板组件400可以包括封装结构10和印刷电路板(printed circuit board，PCB)20。该封装结构10可以设置于该印刷电路板20上、且与印刷电路板20电连接。需要说明的是，上述印刷电路板20可以为主板。本申请对印刷电路板20上的封装结构10的数量不做限制，可以一个、两个或两个以上。
为了方便下文对描述，可以在部分附图中建立X、Y、Z坐标系。图3所示的印刷电路板20的所在平面可以为XY平面，以图3中示出的印刷电路板20为长方体为例，X轴可以为印刷电路板20的长度方向，Y轴可以为印刷电路板20的宽度方向，Z轴为垂直于或在制作公差范围内近似垂直于印刷电路板20的方向。可以理解的是，印刷电路板20的宽度尺寸小于印刷电路板20的长度尺寸。上述是以印刷电路板20为长方体为例进行的说明，印刷电路板20还可以为正方形、多边形等形状，本申请实施例对印刷电路板20的形状不做限定。
以下对上述封装结构10的结构进行举例说明。请参照图4，封装结构10可以包括互联基板(substrate，SUB)1、设置在互联基板1上的芯片2以及包裹芯片2的塑封料(molding)3。该互联基板1可以为封装基板，该封装基板应用于封装工艺中，用于承载芯片或者芯片堆叠结构，以形成芯片封装结构。或者，还可以为重布线层，该重布线层内部设置有重布线结构，该重布线结构用于实现芯片与芯片之间，或者芯片与基板之间的电连接。互联基板1位于印刷电路板20与芯片2之间。该芯片2与互联基板1电连接。芯片2可以为裸芯片(即single die)，也可以为对一个或多个裸芯片进行封装得到的封装结构。本申请对封装于封装结构10内的互联基板1的数量不做限制，可以为一个或两个，也可以为两个以上。并且，芯片2数量不做限制，可以为一个或两个，也可以为两个以上。
需要说明的是，上述芯片2可以为具有数据处理功能的处理芯片，例如中央处理器(central processing unit，CPU)、片上系统(system on chip，SOC)或者图像处理器(graphics processing unit，GPU)等能够对数据进行处理的芯片。或者，上述芯片2还可以为存储芯片，例如双倍速率同步动态随机存储器、低功耗双倍速率同步动态随 机存储器等。
在图4所示的封装结构10中，芯片2被固定在所述互联基板1的顶部。所述互联基板1的底面101设置有如图5所示的第一焊盘阵列11，第一焊盘阵列11用于与印刷电路板20电连接。所述第一焊盘阵列11中包括用于提供接地的第一接地焊盘111，以及用于传递信号的第一信号焊盘112。参照图6，上述印刷电路板20包括第二焊盘阵列201和接地结构202，第二焊盘阵列201位于印刷电路板20上与互联结构1的底面101相对的区域。该第二焊盘阵列201包括用于提供接地的第二接地焊盘2011和用于传递信号的第二信号焊盘2012。该接地结构202可以为一个或两个，也可以为两个以上。第二接地焊盘2011与一个接地结构202电连接，从而实现第二接地焊盘2011的接地。例如，该接地结构202可以为设置在印刷电路板20的表面上或内部的裸露的金属(如铜)区域。如图7所示，第一接地焊盘111可以与第二接地焊盘2011电连接。例如，第一接地焊盘111可以通过焊球阵列(ball grid array，BGA)、或采用钢网印刷工艺所形成的锡膏与第二接地焊盘2011电连接。即芯片2可以通过互联基板1的第一接地焊盘111与印刷电路板20的第二接地焊盘2011连接，从而实现芯片2的接地。芯片2还可以通过互联基板1的第一信号焊盘112可以与第二信号焊盘2012电连接。例如，第一信号焊盘112可以通过焊球阵列、或采用钢网印刷工艺所形成的锡膏与第二信号焊盘2012电连接。从而，实现了芯片2的信号与印刷电路板20上其他芯片或芯片堆叠结构的信号传输。
基于以上结构，考虑到印刷电路板20上其他射频器件对封装结构10的电磁干扰问题，本申请实施例的封装结构10还可以包括如图8所示的屏蔽罩4，屏蔽罩4可以罩设在芯片2和互联基板1外。从而，屏蔽罩4能够对互联基板1的侧面102，以及整个芯片2进行覆盖。当封装结构10焊接在印刷电路板20上时，屏蔽罩4能够将互联基板1和芯片2产生的电磁场压缩在屏蔽罩4的内部，同时阻挡印刷电路板20上其他射频器件的射频干扰进入屏蔽罩4的内部。从而，避免了印刷电路板20上其他射频器件受到芯片2的射频干扰、以及芯片2的信号传输受印刷电路板20上其他射频器件的影响。
需要说明的是，如图8所示，可以通过溅镀、电镀或喷涂等工艺方式在塑封料3的表面和互联基板1的侧面102覆盖电磁屏蔽材料(如由树脂、稀释剂、添加剂以及导电性填料等所组成的复合材料)以形成所述屏蔽罩4，屏蔽罩4为所述封装结构10提供电磁屏蔽。屏蔽罩4在其他可选择的方式中，还可以通过对金属薄壳冲压或弯折来形成所述屏蔽罩4，金属薄壳结构可以采用洋白铜、纯铜或镀锡铁等材料制作。
考虑到图8所示的屏蔽罩4无法对封装结构10与印刷电路板20的焊接处产生屏蔽作用，因此在该处会产生电磁泄露问题。为了解决该问题。本申请实施例封装结构10中的互联基板1包括如图9所示的第一电连接结构13、第二电连接结构12及第一屏蔽焊盘16。第一电连接结构13与芯片2、第一焊盘阵列11电性连接。第二电连接结构12与第一电连接结构13隔离。第二电连接结构12的一部分可以暴露于互联基板1的顶面103或侧面102上，且该部分与屏蔽罩4相接触。第一屏蔽焊盘16设置在互联基板1的底面101上，且绕设在第一焊盘阵列11的外围。相应地，印刷电路板20包括第二屏蔽焊盘203和至少一个接地结构202，第二屏蔽焊盘203可以绕设在第二 焊盘阵列201的外围，且与上述接地结构202电连接。并且，为了便于第一屏蔽焊盘16与第二屏蔽焊盘203连接，第一屏蔽焊盘16在印刷电路板20上的投影可以与第二屏蔽焊盘203重合。
当将封装结构10中的互联基板1安装在印刷电路板20上时，互联基板1的第一屏蔽焊盘16可以与印刷电路板20上的第二屏蔽焊盘203电连接，互联基板1的第一焊盘阵列11与印刷电路板20上的第二焊盘阵列201电连接。从而实现互联基板1与印刷电路板20的电连接。需要说明的是，上述互联基板1的第一屏蔽焊盘16与印刷电路板20上的第二屏蔽焊盘203连接所需的焊料、以及互联基板1的第一焊盘阵列11与印刷电路板20上的第二焊盘阵列201连接所需的焊料均可以为采用钢网印刷工艺形成的锡膏。
因第二屏蔽焊盘203与接地结构202电连接，所以，第一屏蔽焊盘16可以通过第二屏蔽焊盘203实现接地。并且，由于第一屏蔽焊盘16可以绕设在第一焊盘阵列11的外围，第二屏蔽焊盘203可以绕设在第二焊盘阵列201的外围，所以，第一屏蔽焊盘16与第二屏蔽焊盘203连接形成的焊接结构可以遮挡互联基板1的第一焊盘阵列11与印刷电路板20上的第二焊盘阵列201之间的焊接位置。接地后的焊接结构能够阻挡串扰信号进入或穿出封装结构10与印刷电路板20的连接处。从而，对互联基板1的第一焊盘阵列11与印刷电路板20上的第二焊盘阵列201的焊接处形成电磁屏蔽，提高了封装结构10与印刷电路板20的连接处屏蔽性能，减少了电磁泄露，提高了封装结构10的产品性能。
并且，第二焊盘阵列201中的第二接地焊盘2011可以与接地结构202电连接。所以，芯片2通过第一电连接结构13、第一焊盘阵列11与印刷电路板20上的第二焊盘阵列201电连接后，可以实现芯片2的信号与参考地的传输。而第二电连接结构12通过第一屏蔽焊盘16与印刷电路板20上的第二屏蔽焊盘203电连接以实现接地。这样一来，第一电连接结构13的接地信号与第二电连接结构12的参考地信号的传输路径不同，且第一电连接结构13与第二电连接结构12相互隔离，所以，芯片2的参考地信号的传输与第二电连接结构12的接地信号的传输相互影响较小。
此外，由于第二电连接结构12暴露于互联基板1的顶面103或侧面102上的部分可以与屏蔽罩4相接触。所以，屏蔽罩4还可以通过电连接结构12和第一屏蔽焊盘16接地于印刷电路板20上。接地后的屏蔽罩4可以将因印刷电路板20上其他射频器件的外部电磁场而产生的感应电荷，通过电连接结构12和第一屏蔽焊盘16导入接地端，积累的感应电荷得以释放。因此，屏蔽罩4可以进一步阻挡外部电磁场朝屏蔽罩4内扩散，芯片2的信号传输不受外部电磁场的干扰，避免出现天线效应，提高了对互联基板1与印刷电路板20的焊接处的屏蔽能力。并且，还不需设置专门的电路结构来实现屏蔽罩4的接地，可以简化互联基板1的电路结构。
需要说明的是，上述是以图9示出的封装结构10中互联基板1(封装基板或重布线层)仅为一个，该互联基板1直接与印刷电路板20电连接为例进行说明。对于封装结构10中互联基板1有两个或两个以上时，以图10示出的封装结构10中互联基板1有两个为例，一个互联基板为封装基板1a，另一个互联基板为重布线层1b。封装基板1a上电连接有一个芯片堆叠结构2a和一个芯片2b。重布线层1b位于封装基板1a的 上方，且与封装基板1a电连接。封装基板1a与印刷电路板20的连接。该封装基板1a和重布线层1b均可以具有上述第二电连接结构12和第二屏蔽焊盘16。重布线层1b内的第二电连接结构12和第二屏蔽焊盘16，能够进一步减少外部干扰信号进入封装结构10内部。
并且，考虑到互联基板1上第一焊盘阵列11中的第一接地焊盘111和第二电连接结构12与同一个接地结构202电连接，即第二焊盘阵列201中的第二接地焊盘2011和第二屏蔽焊盘16与同一个接地结构202电连接。第一接地焊盘111传输的参考地信号与电连接结构12的接地信号会相互影响。因此，如图11所示，本申请实施例的印刷电路板20中的接地结构202为两个，两个接地结构202分别为第一接地结构202a、第二接地结构202b。其中，电连接结构12与第一接地结构202a电连接，第一焊盘阵列11中的第一接地焊盘111通过第二焊盘阵列201的第二接地焊盘2011与第二接地结构202b电连接。所以，进一步使得屏蔽罩4和电连接结构12的接地信号与第一焊盘阵列11中第一接地焊盘111传输的参考地信号不会相互影响，第一接地焊盘111的信号传输更稳定，且屏蔽罩4和电连接结构12的屏蔽效果较好。当然，本申请实施例的印刷电路板20中的接地结构202也可以为两个以上，本申请对此不做限制。基于以上，以下以封装结构10中互联基板1仅为一个，且该互联基板1为封装基板为例，结合封装基板的具体结构，对上述第一电连接结构13和第二电连接结构12进行说明。
参照图12，封装基板1a包括多层介质层130。上述第一电连接结构13包括如图13所示的多个线路层14和过孔15。多层介质层130和多个线路层14层叠设置，且介质层130位于相邻两层线路层14之间。相邻两层线路层14可以通过形成于介质层130中的过孔(Via)15电连接。多层通过过孔15电连接的线路层14可以构成该封装基板1a的电路结构。
例如，在制作封装基板1a时，先形成第一层介质层，再在第一层介质层上通过成膜工艺形成一整层金属层。然后采用构图(pattern)工艺，去除金属层的部分区域的金属材料，该金属层中保留的金属材料可以作为第一层线路层。之后，以相同的方式依次叠加第二层介质层、第二层线路层、第三层介质层、……、第N层介质层，即可制作得到封装基板1a的内部电路结构。
其中，上述构图工艺，可指包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本申请中所形成的结构选择相应的构图工艺。其中，本申请实施例中的一次构图工艺，是以通过一次掩膜曝光工艺形成不同的曝光区域，然后对不同的曝光区域进行多次刻蚀、灰化等去除工艺最终得到预期图案为例进行的说明。
接下来，对上述第二电连接结构12进行简单说明。该第二电连接结构12可以具有多种结构。
例如，在本申请的一些实施例中，第二电连接结构12可以包括如图13所示的嵌入在封装基板1a内的金属布线121a，金属布线121a可以从封装基板1a的侧面102暴露出，且与屏蔽罩4相接触。返回参照图12，图12中的第二电连接结构12包括金属布线121a，并且，上述第一屏蔽焊盘16可以与金属布线121a电连接。
在将封装基板1a安装于印刷电路板20时，金属布线121a可依次通过第一屏蔽焊盘16、第二屏蔽焊盘203与印刷电路板20上的接地结构202电连接。因此，屏蔽罩4可以通过金属布线121a与印刷电路板20上的接地结构202电连接。
为了简化制作工艺，上述封装基板1a中的金属布线121a可以与线路层14同层同材料制作。例如，上述金属布线121a也可以采用构图工艺形成。在介质层130上通过成膜工艺形成一整层金属层，然后采用构图工艺，去除金属层的部分区域的金属材料，该金属层中保留的金属材料可以作为一层金属布线121a和线路层14。这样一来，在制作线路层14的同时，还可以完成金属布线121a的制备，从而减少了工艺流程，降低了制作成本。
需要说明的是，上述“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，同一构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的，也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
可以理解的是，上述第二电连接结构12可以仅包括一层如图13所示的金属布线121a，也可以包括如图14所示的多层金属布线121a，本申请对此不做限制。对于具有多层金属布线121a的封装基板1a，每层线路层14可以均位于同层的金属布线121a内，多层金属布线121a可以分别对多层线路层14可以起到屏蔽保护的作用。并且，同一层金属布线121a可以与线路层14同层同材料制作。其中，对于具有多层金属布线121a的第二电连接结构12，为了实现相邻两层金属布线121a的连接，如图14所示，该第二电连接结构12还包括多个第一电连接过孔122。相邻两层金属布线121a可以通过第一电连接过孔122电连接。
并且，在本申请的一些实施例中，上述多个第一电连接过孔122还可以与屏蔽罩4相接触。例如，在制作完成封装基板1a后，可直接在第一电连接过孔122处裁切，使得第一电连接过孔122能够从封装基板1a的侧面102暴露出。因此，在封装基板1a的侧面102形成的屏蔽层结构的屏蔽罩4能够与第一电连接过孔122、多层金属布线121a的连接面积较大、连接位置较多，从而屏蔽罩4与第二电连接结构12之间的连接强度较大，屏蔽罩4能够可靠接地。基于以上，上述屏蔽罩4可以采用溅镀、电镀或喷涂等工艺方式形成在封装基板1a的侧面102和塑封料3的外表面上，可以便于屏蔽罩4与封装基板1a的侧面102暴露出的金属布线121a接触，屏蔽罩4与金属布线121a的接触较可靠。
相较于图15所示的表面贴装技术(surface mounted technology，SMT)形成的封装结构10中屏蔽罩4的设置方式，在图14示出的本示例的封装结构10中，屏蔽罩4可以以屏蔽层的形式包裹塑封料3和封装基板1a的侧面102。由于该电磁屏蔽层厚度较薄，所以具有屏蔽层的封装结构10的体积较小。因此，当封装结构10焊接在印刷电路板20上时，屏蔽层不会占用印刷电路板20上较大的空间，从而提高了印刷电路板20上电子器件的集成度。
又如，在另一些实施例中，上述第二电连接结构12可以包括如图16所示的第二电连接过孔(Via)121b。第二电连接过孔121b贯穿封装基板1a的底面101和顶面 103。其中，封装基板1a的顶面103是指与芯片2连接的表面，封装基板1a的底面101是指与印刷电路板20连接的表面。如图17所示，第二电连接过孔121b可以从封装基板1a的顶面103暴露出、且与屏蔽罩4电连接。
可以理解的是，与第二电连接过孔121b电连接的屏蔽罩4，该屏蔽罩4仅覆盖在塑封料3的外侧，屏蔽罩4的下端面可以与第二电连接过孔121b上从封装基板1a的顶面103暴露出的部分接触。并且，第二电连接过孔121b还可以从封装基板1a的底面101暴露出，且与印刷电路板20上的第二屏蔽焊盘203电连接。
基于以上第二电连接结构12的结构，该第二电连接过孔121b可以采用如下流程制作：在制作完成封装基板1a中的电路结构后，采用化学腐蚀(如采用氢氟酸进行化学腐蚀)、激光(laser)、激光诱导湿法刻蚀(laser induced wet etch)等方式在封装基板1a上开设通孔。之后，在该通孔内可以采用溅射(physical vapour deposition，PVD)工艺形成钛(Ti)或镍(Ni)等金属薄膜，将该金属薄膜作为粘结层。然后，在金属薄膜上采用溅射(如磁控溅射或离子束溅射)工艺形成铜(Cu)层作为种子层。之后，采用电镀(electrochemical deposition，ECD)方式增加种子层的厚度，使得通孔内充满铜材料，从而形成上述第二电连接过孔121b。第二电连接过孔121b的制作工艺较成熟，加工制作较方便。或者，还可以采用如下工艺制作第二电连接过孔121b：在封装基板1a上开设通孔后，在通孔内注入银浆，之后再采用热制程工艺固化银浆，从而形成上述第二电连接过孔121b。
以上是对第二电连接结构12的结构说明。为了在实现较好的屏蔽效果的基础上，降低第一屏蔽焊盘16的制作成本，可以根据印刷电路板20上的其他射频器件(干扰源)相对封装结构10的分布位置，设计第一屏蔽焊盘16在第一焊盘阵列11外的绕设位置。而第二屏蔽焊盘203与第一屏蔽焊盘16在印刷电路板20上的投影重合，所以，第二屏蔽焊盘203可以根据第一屏蔽焊盘16的结构进行调整。
可以理解的是，屏蔽罩4的结构也可以根据印刷电路板20上的其他射频器件(干扰源)相对封装结构10的分布位置进行调整。相应地，由于第二电连接结构12需要与第一屏蔽焊盘16、屏蔽罩4连接，所以，第二电连接结构12也需根据第一屏蔽焊盘16的结构和屏蔽罩4的结构进行调整。
以封装结构10和封装基板1a均为长方体，第一焊盘阵列11和第二焊盘阵列201均为矩形阵列，以及第二电连接结构12包括上述金属布线121a为例，阐述在干扰源设置在封装结构10外周的不同位置时，上述第一屏蔽焊盘16、第二屏蔽焊盘203、屏蔽罩4及金属布线121a的结构。其中，如图18所示，封装基板1a的侧面为4个，4个侧面分别为102a、102b、102c、102d。
当印刷电路板20上的其他射频器件均分布在封装结构10的同一侧时，例如，印刷电路板20上的其他射频器件位于与封装基板1a的侧面102a相对的位置。图19中左侧的箭头表示印刷电路板20上的其他射频器件产生的电磁干扰信号的传输方向。在一些实施例中，第一屏蔽焊盘16为长条形，且仅绕设在第一焊盘阵列11靠近侧面102a的一侧边沿外。对应地，如图20所示，印刷电路板20中的第二屏蔽焊盘203也可以为长条形，且位于第二焊盘阵列201对应侧面102a的一侧边沿外。
需要说明的是，下述图20至图33中的箭头(非标号的引线箭头)均表示印刷电 路板20上的其他射频器件产生的电磁干扰信号的传输方向。
相应地，如图21所示，金属布线121a可以仅暴露在封装基板1a的侧面102a。而屏蔽罩4包括覆盖在塑封料3顶部的主体部41，以及与主体部41连接的一个连接部42。该连接部42可以覆盖在封装基板1a的侧面102a上，以与金属布线121a连接。
可以理解的是，屏蔽罩4的连接部42可以仅覆盖在封装基板1a的侧面上部，也可以封装基板1a的侧面上部和侧面中部。或者，屏蔽罩4的连接部42也可以直接覆盖至封装基板1a的一整个侧面，屏蔽罩4的制作较方便。具体可以根据金属布线121a暴露在封装基板1a的侧面位置来选择，只要保证屏蔽罩4的连接部42可以与金属布线121a接触即可。
当印刷电路板20上的其他射频器件设置在封装结构10的两侧时，例如，印刷电路板20上的其他射频器件分布在与封装基板1a的侧面102a和102c相对的位置。因此，在一些实施例中，第一屏蔽焊盘16包括两个条形焊盘，两个条形焊盘分别为如图22所示的第一条形焊盘16a和第二条形焊盘16b。第一条形焊盘16a可以设置在第一焊盘阵列11上靠近侧面102a的一侧边沿外，第二条形焊盘16b可以设置在第一焊盘阵列11上靠近侧面102c的一侧边沿外。
可以理解的是，除了图22示出的第一焊盘阵列11的两个侧边沿为相对的两条侧边沿，第一屏蔽焊盘16的两个条形焊盘相对设置且相对独立。当第一焊盘阵列11的两个侧边沿为相邻的两条侧边沿时，如图23所示，第一条形焊盘16a和第二条形焊盘16b可以相连接。第一屏蔽焊盘16呈L形。
以图22示出的第一屏蔽焊盘16为例。对应地，如图24所示，印刷电路板20中的第二屏蔽焊盘203也包括两个条形焊盘203a和203b，两个条形焊盘203a和203b分别位于第二焊盘阵列201的两侧边沿外。并且，条形焊盘203a与第一条形焊盘16a相对，条形焊盘203b与第二条形焊盘16b相对。
相应地，如图25所示，金属布线121a可以仅暴露在封装基板1a的侧面102a和102c上。而屏蔽罩4的一个连接部42a覆盖在封装基板1a的侧面102a上，另一个连接部42b覆盖在封装基板1a的侧面102c上，以使两个连接部42a和42b均与金属布线121a电连接。
当印刷电路板20上的其他射频器件设置在封装结构10的三侧时，例如，印刷电路板20上的其他射频器件分布在与封装基板1a的侧面102a、102b和102c相对的位置。在本申请的一些实施例中，第一屏蔽焊盘16包括三个相互连接的条形焊盘。三个条形焊盘分别为如图26所示的第一条形焊盘16a、第二条形焊盘16b和第三条形焊盘16c。第一条形焊盘16a可以设置在第一焊盘阵列11上靠近侧面102a的一侧边沿外，第二条形焊盘16b可以设置在第一焊盘阵列11上靠近侧面102b的一侧边沿外，第三条形焊盘16c可以设置在第一焊盘阵列11上靠近侧面102c的一侧边沿外。
如图27所示，印刷电路板20中的第二屏蔽焊盘203也包括三个条形焊盘203a、203b和203c，三个条形焊盘203a、203b和203c分别位于第二焊盘阵列201的三侧边沿外。并且，条形焊盘203a与第一条形焊盘16a相对，条形焊盘203b与第二条形焊盘16b相对，条形焊盘203c与第三条形焊盘16c相对。
相应地，如图28所示，金属布线121a可以仅暴露在封装基板1a的三个侧面上。 相应地，屏蔽罩4包括三个连接部42a、42b、42c，屏蔽罩4的连接部42a可以覆盖在封装基板1a的侧面102a上，屏蔽罩4的连接部42b可以覆盖在封装基板1a的侧面102b上，屏蔽罩4的连接部42c可以覆盖在封装基板1a的侧面102c上，以使三个连接部42a、42b、42c均与金属布线121a电连接。
以上实施例中，印刷电路板20上的其他射频器件(干扰源)仅分布在矩形的封装结构10外周的部分区域中。当矩形的封装结构10的一周均分布有其他射频器件(干扰源)沿时，上述第一屏蔽焊盘16可以制作为环形结构。
例如，如图29所示，第一屏蔽焊盘16可以为首尾相接的环形结构，如该环形结构可以为矩形环。封装基板1a中的第一焊盘阵列11可以均位于该环形结构内。相应地，如图30所示，印刷电路板20中的第二屏蔽焊盘203也可以为与首尾相接的环形结构。并且，第一屏蔽焊盘16可以与第二屏蔽焊盘203的大小相同，以便于第一屏蔽焊盘16的一周可以与第二屏蔽焊盘203的一周均连接，第一屏蔽焊盘16与第二屏蔽焊盘203连接形成的焊接结构可以将封装基板1a的第一焊盘阵列11与印刷电路板20上的第二焊盘阵列201的焊接处完全遮挡，屏蔽效果较好。
并且，上述金属布线121a也可以制作为首尾相接的环形线路，且金属布线121a可以暴露在封装基板1a的四个侧面102a、102b、102c及102d上。相应地，如图31所示，屏蔽罩4包括4个连接部42a、42b、42c及42d。屏蔽罩4的连接部42a可以覆盖在封装基板1a的侧面102a上，屏蔽罩4的连接部42b可以覆盖在封装基板1a的侧面102b上，屏蔽罩4的连接部42c可以覆盖在封装基板1a的侧面102c上，屏蔽罩4的连接部42d可以覆盖在封装基板1a的侧面102d上。从而屏蔽罩4的一周均可以与该金属布线121a相接触，使得屏蔽罩4沿周向各区域的接地信号稳定，屏蔽效果较好。
又如，参照图32，第一屏蔽焊盘16可以包括多个第一条形子焊盘161，多个第一条形子焊盘161间隔设置、且依次排列成环形结构。相应地，如图33所示，印刷电路板20中的第二屏蔽焊盘203也可以为包括多个第二条形子焊盘2031，多个第二条形子焊盘2031间隔设置、且依次排列成环形结构。每一个第一屏蔽焊盘16中的第一条形子焊盘161均可以与第二屏蔽焊盘203中的第二条形子焊盘2031位置对应且大小相同。从而，任一个第一屏蔽焊盘16中的第一条形子焊盘161可以与对应的第二屏蔽焊盘203中的第二条形子焊盘2031焊接。该具有间隙的第一屏蔽焊盘16能够便于与印刷电路板20第二屏蔽焊盘203回流焊接操作。以第一屏蔽焊盘16为例，可以理解的是，在设计第一屏蔽焊盘16中相邻两个第一条形子焊盘161的间距时，需尽可能缩小该间距，以减少干扰信号穿过该间隙。从而，保证了具有间隙的第一屏蔽焊盘16与第二屏蔽焊盘203所形成的焊接结构也能够对封装基板1a第一焊盘阵列11与印刷电路板20上的第二焊盘阵列201的焊接处具有良好的屏蔽效果。
相应地，金属布线121a也可以制作为具有间隙的环形线路，且金属布线121a同样可以暴露在封装基板1a的侧面102一周。屏蔽罩4的4个连接部42同样可以与金属布线121a的一周均接触，使得屏蔽罩4沿周向各区域的接地信号稳定，屏蔽效果较好。
基于以上，对于上述具有间隙的第一屏蔽焊盘16、以及多层金属布线121a的封装基板1a，当封装基板1a安装在印刷电路板20上时，可能会有少量干扰信号穿过第 一屏蔽焊盘16中相邻两个第一条形子焊盘161之间的间隙进入封装结构10内。若多层金属布线121a的线宽相等，干扰信号可以直接从封装基板1a的底部经金属布线121a与线路层14之间的间隙穿过，干扰信号的传输路径较短，传输过程中的损耗较少，对封装结构10内部的电磁干扰较大。因此，参照图34，本申请实施例中的多层金属布线121a中任两层的线宽W不同的环形结构。即多层金属布线121a在封装基板1a上的垂直投影可以部分重叠。任两层的金属布线121a线宽W不同，可以使得干扰信号在绕过多层金属布线121a传出或穿入时，路径弯折更多，路径更长，有利于干扰信号的损耗、消减，从而进一步降低了对封装结构10内部的电磁干扰。其中，图34中示出了3层金属布线121a分别在封装基板1a上的投影。
以上是以第二电连接结构12包括上述金属布线121a进行说明的，当第二电连接结构12包括上述第二电连接过孔121b时，第二电连接过孔121b也可以根据第一屏蔽焊盘16和屏蔽罩4进行调整，例如第二电连接过孔121b为环形或非环形结构。
以第二电连接过孔121b为环形结构为例，如图35所示，第二电连接过孔121b也可以制作为首尾相接的环形过孔。并且，第二电连接过孔121b可以暴露在封装基板1a的顶面103一周，使得屏蔽罩4沿周向各区域的接地信号稳定，屏蔽效果较好。
或者，如图36所示，第二电连接过孔121b可以包括多个条形过孔1211，多个条形过孔1211间隔设置、且依次排列成环形结构。第二电连接过孔121b中的多个条形过孔1211可以暴露在封装基板1a的顶面103，屏蔽罩4可以从封装基板1a的顶面103与多个条形过孔1211均接触，使得屏蔽罩4沿周向各区域的接地信号稳定，屏蔽效果较好。
需要说明的是，第一焊盘阵列11也可以采用其他阵列形式，如圆形阵列。相应地，根据干扰源的分布位置，第一屏蔽焊盘16可以绕设在圆形阵列的部分区域或全部区域外。第二屏蔽焊盘203、第二电连接结构12及屏蔽罩4也可相应进行调整，此处不再一一举例说明。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种封装结构，其特征在于，包括芯片，屏蔽罩，以及互联基板；
    所述芯片设置在所述互联基板的顶部，且与所述互联基板电连接；
    所述屏蔽罩罩设在所述芯片外，所述芯片被收容在所述屏蔽罩和所述互联基板围成的空间中；
    所述互联基板内包括：
    第一电连接结构，与所述芯片电连接；
    第二电连接结构，与所述第一电连接结构隔离，所述第二电连接结构的部分暴露于所述互联基板的顶面或侧面，并与所述屏蔽罩相接触；
    第一焊盘阵列和第一屏蔽焊盘，设置在所述互联基板的底面上；第一焊盘阵列与所述第一电连接结构电性连接，所述第一屏蔽焊盘绕设在所述第一焊盘阵列的外围。
  2. 根据权利要求1所述的封装结构，其特征在于，所述第一焊盘阵列为矩形阵列，所述第一屏蔽焊盘绕设在所述第一焊盘阵列的两侧边沿、或三侧边沿外。
  3. 根据权利要求1或2所述的封装结构，其特征在于，所述第二电连接结构包括：
    至少一层金属布线，所述金属布线暴露于所述互联基板的至少一个侧面上，且与所述屏蔽罩相接触。
  4. 根据权利要求3所述的封装结构，其特征在于，所述第一电连接结构包括多层线路层，所述互联基板还包括多层介质层，所述多层介质层与所述多层线路层层叠设置，且所述介质层位于相邻两层所述线路层之间；一层所述金属布线与一层所述线路层同层同材料。
  5. 根据权利要求4所述的封装结构，其特征在于，所述第二电连接结构包括多层所述金属布线；
    所述第二电连接结构还包括多个贯穿所述介质层的第一电连接过孔，所述第一电连接过孔将相邻两层所述金属布线电连接，所述第一电连接过孔与所述屏蔽罩相接触。
  6. 根据权利要求5所述的封装结构，其特征在于，任两层所述金属布线的线宽不同。
  7. 根据权利要求1或2所述的封装结构，其特征在于，所述第二电连接结构包括：
    第二电连接过孔，所述第二电连接过孔贯穿所述互联基板的底面和顶面；所述第二电连接过孔暴露于所述顶面的部分与所述屏蔽罩电连接所述第二电连接过孔暴露于所述底面的部分与所述第一屏蔽焊盘电连接。
  8. 根据权利要求1-7中任一项所述的封装结构，其特征在于，所述第一屏蔽焊盘为首尾相接的环形结构。
  9. 根据权利要求1-7中任一项所述的封装结构，其特征在于，所述第一屏蔽焊盘包括多个条形子焊盘；所述多个条形子焊盘间隔设置、且依次排列成环形结构。
  10. 根据权利要求1-9中任一项所述的封装结构，其特征在于，所述互联基板为封装基板或重布线层。
  11. 一种电路板组件，其特征在于，包括：
    印刷电路板，所述印刷电路板包括第二屏蔽焊盘、第二焊盘阵列和至少一个接地结构，所述第二屏蔽焊盘绕设在所述第二焊盘阵列的外围，且所述第二屏蔽焊盘、所 述第二焊盘阵列与所述接地结构电连接；
    上述权利要求1-10中任一项所述的封装结构，所述封装结构中互联基板的第一屏蔽焊盘与所述第二屏蔽焊盘电连接，所述封装结构中互联基板的第一焊盘阵列与所述第二焊盘阵列电连接。
  12. 根据权利要求11所述的电路板组件，其特征在于，所述至少一个接地结构包括第一接地结构和第二接地结构，所述第一接地结构与所述第二屏蔽焊盘电连接，所述第二接地结构与所述第二焊盘阵列中的部分焊盘电连接。
  13. 根据权利要求11或12所述的电路板组件，其特征在于，所述第一屏蔽焊盘在所述印刷电路板上的投影与所述第二屏蔽焊盘重合。
  14. 一种电子设备，其特征在于，包括壳体、以及位于所述壳体内的上述权利要求11-13中任一项所述的电路板组件。
PCT/CN2021/123255 2021-10-12 2021-10-12 一种封装结构、电路板组件及电子设备 WO2023060432A1 (zh)

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