WO2023044984A1 - 一种显示面板 - Google Patents

一种显示面板 Download PDF

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Publication number
WO2023044984A1
WO2023044984A1 PCT/CN2021/123303 CN2021123303W WO2023044984A1 WO 2023044984 A1 WO2023044984 A1 WO 2023044984A1 CN 2021123303 W CN2021123303 W CN 2021123303W WO 2023044984 A1 WO2023044984 A1 WO 2023044984A1
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WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
reset
gate
emission control
Prior art date
Application number
PCT/CN2021/123303
Other languages
English (en)
French (fr)
Inventor
戴超
李波
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/611,559 priority Critical patent/US20240046862A1/en
Publication of WO2023044984A1 publication Critical patent/WO2023044984A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present application relates to the display field, in particular to a display panel.
  • LTPS Low Temperature Poly-Silicon
  • OLED display devices organic light-emitting display devices
  • the leakage current of LTPS thin film transistors is large, especially During low-frequency display, due to the large leakage current, the gate voltage is likely to be unstable, thereby making the potential difference between the gate and the source unstable, resulting in unstable current of the OLED light-emitting element, and flickering phenomenon in the display device.
  • the embodiment of the present application provides a display panel, which can solve the problem of flickering in the display device due to the large leakage current of the transistor in the pixel circuit using the polysilicon thin film transistor, which makes the current of the OLED light-emitting element unstable.
  • An embodiment of the present application provides a display panel, including a plurality of light-emitting elements arranged in an array and a pixel circuit for driving the light-emitting elements to emit light, the first electrode of the light-emitting element is electrically connected to a first power supply, and the first electrode of the light-emitting element The two electrodes are electrically connected to a second power supply, the pixel circuit is coupled between the first power supply and the first electrode of the light emitting element, and the pixel circuit includes:
  • a driving transistor the gate of the driving transistor is electrically connected to the first node, the source of the driving transistor is electrically connected to the second node, the drain of the driving transistor is electrically connected to the third node, and the first node of the light emitting element
  • An electrode is electrically connected to the first power supply through the driving transistor
  • a data writing transistor the gate of the data writing transistor is electrically connected to the first scan line, the source of the data writing transistor is electrically connected to the data line, and the drain of the data writing transistor is electrically connected to the second node;
  • a storage capacitor including a first capacitor electrode and a second capacitor electrode, the first capacitor electrode is electrically connected to the first power supply, and the second capacitor electrode is electrically connected to the first node;
  • a first reset transistor the gate of the first reset transistor is electrically connected to the second scan line, the source of the first reset transistor is electrically connected to the first node, and the drain of the first reset transistor is electrically connected to the first node.
  • a reset signal source
  • the first reset transistor is an oxide transistor
  • the driving transistor and the data writing transistor are polysilicon transistors.
  • the pixel circuit further includes:
  • a compensation transistor the gate of the compensation transistor is electrically connected to the first scan line, the source of the compensation transistor is electrically connected to the third node, and the drain of the compensation transistor is electrically connected to the first reset transistor Drain;
  • a second reset transistor the gate of the second reset transistor is electrically connected to the third scan line, the source of the second reset transistor is electrically connected to the drain of the first reset transistor, and the drain of the second reset transistor The electrode is electrically connected to the first reset signal source;
  • both the compensation transistor and the second reset transistor are polysilicon transistors.
  • the second reset transistor and the compensation transistor have a single-gate structure.
  • it includes a substrate, a first active layer, a first metal layer, a second metal layer, a second active layer, and a third metal layer stacked from bottom to top;
  • the first active layer forms an active layer of a polysilicon transistor, and the second active layer forms an active layer of an oxide transistor;
  • the first metal layer forms a gate of the polysilicon transistor; the second metal layer forms a first gate of the oxide transistor;
  • the orthographic projection of the first gate of the oxide transistor on the substrate and the orthographic projection of the active layer of the oxide transistor on the substrate have an overlapping region
  • the orthographic projection of the gate of the polysilicon transistor on the substrate and the orthographic projection of the active layer of the polysilicon transistor on the substrate have an overlapping area.
  • the third metal layer forms the second gate of the oxide transistor
  • the orthographic projection of the second gate of the oxide transistor on the substrate has an overlapping area with the orthographic projection of the active layer of the oxide transistor on the substrate, and the oxide transistor The second gate at least partially overlaps the orthographic projection of the first gate of the oxide transistor on the substrate.
  • the pixel circuit further includes:
  • a reset transistor the gate of the reset transistor is electrically connected to the first scan line, the source of the reset transistor is electrically connected to the second reset signal source, and the drain of the reset transistor is connected to the light emitting element said first electrode;
  • a first light emission control transistor the gate of the first light emission control transistor is electrically connected to the light emission control signal line, the source of the first light emission control transistor is electrically connected to the first power supply, and the drain of the first light emission control transistor electrically connected to the second node;
  • a second light emission control transistor the gate of the second light emission control transistor is electrically connected to the light emission control signal line, the source of the second light emission control transistor is electrically connected to the third node, and the drain of the second light emission control transistor The electrode is electrically connected to the first electrode of the light emitting element.
  • the reset transistor, the first light emission control transistor and the second light emission control transistor are all polysilicon transistors.
  • the polysilicon transistor is a P-type transistor; the oxide transistor is an N-type transistor.
  • the first reset signal source and the second reset signal source are the same reset signal source.
  • the first scan line and the second scan line are scan lines of a current row
  • the third scan line is a scan line of a previous row.
  • a display panel which can reduce the magnitude of the leakage current of the pixel circuit using the polysilicon thin film transistor, make the current of the OLED light-emitting element more stable, and improve the flickering phenomenon of the display panel.
  • FIG. 1 is a schematic diagram of an equivalent circuit of a pixel circuit on a display panel provided by an embodiment of the present application;
  • FIG. 2 is a timing diagram of an equivalent circuit of a pixel circuit on a display panel provided by an embodiment of the present application;
  • FIG. 3 is a schematic diagram of a cross-sectional film layer structure of a pixel circuit on a display panel provided by an embodiment of the present application;
  • FIG. 4 is a schematic layout diagram of a pixel circuit on a display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a pattern of a first active layer in a pixel circuit layout provided by an embodiment of the present application
  • FIG. 6 is a schematic diagram of a pattern of a first metal layer in a pixel circuit layout provided by an embodiment of the present application
  • FIG. 7 is a schematic diagram of a pattern of a second metal layer in a pixel circuit layout provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a pattern of a second active layer in a pixel circuit layout provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a pattern of a third metal layer in a pixel circuit layout provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a pattern of a fourth metal layer in a pixel circuit layout provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a pattern of a fifth metal layer in a pixel circuit layout provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a stacked structure from the first active layer to the first metal layer in the pixel circuit layout provided by an embodiment of the present application;
  • FIG. 13 is a schematic diagram of the stacked structure of the first active layer to the fourth metal layer in the pixel circuit layout provided by an embodiment of the present application.
  • An embodiment of the present application provides a display panel.
  • the display panel includes a plurality of light-emitting elements arranged in an array and a pixel circuit for driving the light-emitting elements to emit light.
  • the first electrode of the light-emitting element is electrically connected to the first power supply, and the second electrode of the light-emitting element is electrically connected to the The second power supply, the pixel circuit is coupled between the first power supply and the first electrode of the light emitting element, the pixel circuit includes: a driving transistor, the gate of the driving transistor is electrically connected to the first node, and the source of the driving transistor is electrically connected to the second node,
  • the drain of the driving transistor is electrically connected to the third node, the first electrode of the light-emitting element is electrically connected to the first power supply through the driving transistor;
  • the data write transistor, the gate of the data write transistor is electrically connected to the first scan line, and the data write transistor
  • the source is electrically connected to the data line, and the drain of
  • An embodiment of the present application provides a display panel. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • Figure 1 is a schematic diagram of an equivalent circuit of a pixel circuit on a display panel provided by an embodiment of the present application
  • Figure 2 is a schematic diagram of a pixel circuit on a display panel provided by an embodiment of this application
  • FIG. 3 is a schematic diagram of the cross-sectional film layer structure of the pixel circuit on the display panel provided by the embodiment of the present application
  • FIG. 4 is a schematic diagram of the layout of the pixel circuit on the display panel provided by the embodiment of the present application.
  • the display panel 100 provided by the embodiment of the present application includes a plurality of light-emitting elements OL arranged in an array and a pixel circuit 200 for driving the light-emitting elements OL to emit light.
  • the first electrode O11 of the light-emitting element OL is electrically connected to the first power supply VDD, and the OL of the light-emitting element second
  • the electrode O12 is electrically connected to the second power supply VSS, and the pixel circuit 200 is coupled between the first power supply VDD and the first electrode O11 of the light emitting element OL.
  • the pixel circuit 200 includes a driving transistor T1, a data writing transistor T2, a storage capacitor Cst and a first Reset transistor T8.
  • the driving transistor T1, the gate T1G of the driving transistor T1 is electrically connected to the first node A, the source T1S of the driving transistor T1 is electrically connected to the second node B, the drain T1D of the driving transistor T1 is electrically connected to the third node C, and the light emitting element OL
  • the first electrode O11 is electrically connected to the first power supply VDD through the driving transistor T1;
  • the data writing transistor T2 the gate T2G of the data writing transistor T2 is electrically connected to the first scanning line Sn, the source T2S of the data writing transistor T2 is electrically connected to the data line Data, and the drain T2D of the data writing transistor T2 is electrically connected to the first scanning line Sn.
  • the storage capacitor Cst includes a first capacitor electrode C11 and a second capacitor electrode C12, the first capacitor electrode C11 is electrically connected to the first power supply VDD, and the second capacitor electrode C12 is electrically connected to the first node A;
  • the first reset transistor T8 the gate T8G of the first reset transistor T8 is electrically connected to the second scanning line NSn, the source T8S of the first reset transistor T8 is electrically connected to the first node A, and the drain T8D of the first reset transistor T8 is electrically connected The first reset signal source VI1;
  • the first reset transistor T8 is an oxide transistor
  • the driving transistor T1 and the data writing transistor T2 are polysilicon transistors.
  • the pixel circuit 200 further includes a compensation transistor T3 and a second reset transistor T4.
  • the compensation transistor T3, the gate T3G of the compensation transistor T3 is electrically connected to the first scan line Sn, the source T3S of the compensation transistor T3 is electrically connected to the third node C, and the drain T3D of the compensation transistor T3 is electrically connected to the drain of the first reset transistor T8 T8D;
  • the second reset transistor T4, the gate T4G of the second reset transistor T4 is electrically connected to the third scan line Sn-1, the source T4S of the second reset transistor T4 is electrically connected to the drain T8D of the first reset transistor T8, and the second reset transistor T8
  • the drain T4D of T4 is electrically connected to the first reset signal source VI1;
  • both the compensation transistor T3 and the second reset transistor T4 are polysilicon transistors.
  • the display panel 100 includes a substrate 11, a first active layer 13, a first metal layer 15, a second metal layer 17, a second active layer 19, and a third metal layer 21 stacked from bottom to top;
  • the first active layer 13 forms an active layer of a polysilicon transistor, and the second active layer 19 forms an active layer of an oxide transistor;
  • the first metal layer 15 forms the gate of the polysilicon transistor; the second metal layer 17 forms the first gate of the oxide transistor;
  • the first metal layer 15 forms the gate of the polysilicon transistor, that is, the first metal layer 15 forms the top gate of the polysilicon transistor;
  • the second metal layer 17 forms the first gate of the oxide transistor, that is, the second metal layer 17
  • the bottom gate of the oxide transistor is formed.
  • the orthographic projection of the first gate of the oxide transistor on the substrate 11 and the orthographic projection of the active layer of the oxide transistor on the substrate 11 have an overlapping area
  • the orthographic projection of the gate of the polysilicon transistor on the substrate 11 and the orthographic projection of the active layer of the polysilicon transistor on the substrate 11 have an overlapping area.
  • the structure of the display panel 100 also includes:
  • the third metal layer 21 forms the second gate of the oxide transistor
  • the orthographic projection of the second gate of the oxide transistor on the substrate 11 and the orthographic projection of the active layer of the oxide transistor on the substrate 11 have an overlapping area, and the second gate of the oxide transistor and the oxide transistor Orthographic projections of the first grid on the substrate at least partially overlap.
  • the third metal layer 21 forms the second gate of the oxide transistor, that is, the third metal layer 21 forms the top gate of the oxide transistor.
  • the pixel circuit 200 further includes a reset transistor T7, a first light emission control transistor T5 and a second light emission control transistor T6.
  • the reset transistor T7, the gate T7G of the reset transistor T7 is electrically connected to the first scanning line Sn, the source T7S of the reset transistor T7 is electrically connected to the second reset signal source VI2, and the drain T7D of the reset transistor T7 is electrically connected to the light emitting element the first electrode O11 of the OL;
  • the first light emission control transistor T5, the gate T5G of the first light emission control transistor T5 is electrically connected to the light emission control signal line EM, the source T5S of the first light emission control transistor T5 is electrically connected to the first power supply VDD, and the drain of the first light emission control transistor T5 pole T5D is electrically connected to the second node B;
  • the second light emission control transistor T6 the gate T6G of the second light emission control transistor T6 is electrically connected to the light emission control signal line EM, the source T6S of the second light emission control transistor T6 is electrically connected to the third node C, and the drain of the second light emission control transistor T6
  • the pole T6D is electrically connected to the first electrode O11 of the light emitting element OL.
  • the reset transistor T7, the first light emission control transistor T5, and the second light emission control transistor T6 are all polysilicon transistors.
  • the polysilicon transistor is a P-type transistor; the oxide transistor is an N-type transistor.
  • first reset signal source VI1 and the second reset signal source VI2 are the same reset signal source.
  • first scan line Sn and the second scan line NSn are the current scan line
  • the third scan line Sn-1 is the previous scan line.
  • the second reset transistor T4 and the compensation transistor T3 have a single-gate structure.
  • the second reset transistor T4 has only one gate on one side of its active layer
  • the compensation transistor T3 has only one gate on one side of its active layer, which is a single-gate structure.
  • the drive transistor T1, the data writing transistor T2, the first reset transistor T8, the compensation transistor T3, the second reset transistor T4, the reset transistor T7, the first light emission control transistor T5 and the second light emission control transistor T6 Both are single-gate structures, that is, there is only one gate on one side of each active layer.
  • the first reset signal source VI1 and the second reset signal source VI2 can supply signals to two separate independent signal lines, and at this time, the first reset transistor T8 and the second reset transistor T4 are used to supply the first node A with the first reset signal.
  • the first reset signal from the signal source VI1 supplies the second reset signal to the first electrode O11 of the light-emitting element OL through the reset transistor T7.
  • the first reset signal is different from the second reset signal.
  • the first node A and the second reset signal of the light-emitting element OL One electrode O11 independently supplies different reset signals to prevent the reset signal of the first node A from interfering with the reset signal of the first electrode O11 of the light-emitting element OL, which can improve the luminous efficiency and brightness of the light-emitting element OL.
  • the first reset signal source VI1 and the second reset signal source VI2 can be the same reset signal source, and the first node A and the first electrode O11 of the light emitting element OL supply the same reset signal, which can reduce the number of wirings.
  • the first scanning line Sn and the second scanning line NSn are the scanning lines of the current row, indicating that the pixels in the nth row include the first scanning line Sn and the second scanning line NSn, and the third scanning line Sn-1 is the scanning line of the previous row, indicating that the nth row of pixels
  • One row of pixels includes the first scan line Sn-1 of the previous row and the second scan line NSn-1 of the previous row, that is, the first scan line Sn-1 of the previous row is the third scan line Sn-1 of the nth row of pixels .
  • Sn represents the scanning line of the pixel in the nth row, which supplies the scanning line signal of the polysilicon transistor;
  • NSn represents the scanning line of the pixel in the nth row, and supplies the scanning line signal of the oxide transistor.
  • the first reset transistor T8 is an oxide transistor, and the material of the active layer of the oxide transistor is an oxide semiconductor, such as IGZO (indium gallium zinc oxide, indium gallium zinc oxide).
  • the compensation transistor T3, the second reset transistor T4, the drive transistor T1, the data writing transistor T2, the reset transistor T7, the first light emission control transistor T5, and the second light emission control transistor T6 are all polysilicon transistors, and the material of the active layer of the polysilicon transistors is is polysilicon, such as low temperature polysilicon (LTPS).
  • the signal of the first scanning line Sn and the signal of the second scanning line NSn are high potential
  • the signal of the third scanning line Sn-1 is low potential
  • the signal of the light emission control signal line EM is high potential
  • the driving transistor T1, data writing transistor T2, compensation transistor T3, reset transistor T7, first light emission control transistor T5, second light emission control transistor T6 are closed
  • first reset transistor T8, second reset transistor T4 are open
  • first reset signal source The first node A is supplied with a first reset signal.
  • the signal of the first scanning line Sn is at a low potential
  • the signal of the second scanning line NSn and the signal of the third scanning line Sn-1 are at a high potential
  • the signal of the light emission control signal line EM is at a high potential.
  • the compensation transistor T3 and the first reset transistor T8 are turned on, and the gate T1G and the drain T1D of the driving transistor T1 are turned on, and a voltage difference is generated between the gate T1G and the source T1S of the driving transistor T1 by the threshold voltage of the driving transistor T1 , at this time, the drive transistor T1 is turned on, the data writing transistor T2 is turned on, and the data signal of the data line Data is input to the second node B.
  • the data signal of the data line Data contains a compensated threshold voltage and is input to the gate of the drive transistor T1 Pole T1G, thereby compensating the threshold voltage deviation of the drive transistor T1.
  • the written data signal of the data line Data charges the first node A through the driving transistor T1 until the voltage of the first node A becomes Vdata-Vth, and the driving transistor T1 is turned off.
  • the reset transistor T7 is turned on, and the second reset signal source VI2 supplies the first electrode O11 of the light emitting element OL with a second reset signal.
  • the signal of the first scanning line Sn and the signal of the third scanning line Sn-1 are high potential
  • the signal of the second scanning line NSn is low potential
  • the potential of the light-emitting control signal line EM is low potential
  • the input transistor T2, the compensation transistor T3, the first reset transistor T8, the second reset transistor T4, and the reset transistor T7 are turned off, the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the drive transistor T1 remains on.
  • the signal of the power supply VDD flows to the light-emitting element OL, and at this moment, the light-emitting element OL works by emitting light.
  • the first electrode O11 and the second electrode O12 of the light emitting element OL may be an anode and a cathode, respectively.
  • the first reset transistor T8 is an oxide transistor, specifically, the orthographic projection of the second gate of the oxide transistor on the substrate 11 and the orthographic projection of the active layer of the oxide transistor on the substrate 11 With an overlapping region, the second active layer 19 forms the active layer of the oxide transistor, and the second active layer 19 is a metal oxide active layer.
  • the compensation transistor T3, the second reset transistor T4, the drive transistor T1, the data writing transistor T2, the reset transistor T7, the first light emission control transistor T5, and the second light emission control transistor T6 are all polysilicon transistors, specifically Yes, the orthographic projection of the gate of the polysilicon transistor on the substrate 11 and the orthographic projection of the active layer of the polysilicon transistor on the substrate 11 have an overlapping area, and the first active layer 13 forms the active layer of the polysilicon transistor.
  • the third metal layer 21 forms the second gate of the oxide transistor; wherein, the orthographic projection of the second gate of the oxide transistor on the substrate 11 is the same as the orthographic projection of the active layer of the oxide transistor on the substrate 11 There is an overlapping region, and the orthographic projection of the second gate of the oxide transistor on the substrate at least partially overlaps with the first gate of the oxide transistor.
  • the first reset transistor T8 is an oxide transistor, and a metal oxide semiconductor is used as the active layer, which can reduce the leakage current of the pixel circuit, make the current of the light emitting element OL more stable, and avoid flickering of the display device.
  • the second reset transistor T4 and the compensation transistor T3 adopt a single-gate structure, which can avoid the layout (layout) of the pixel circuit 200 from being bloated, reduce the layout space occupied by the pixel circuit 200 on the display panel 100, and facilitate the improvement of the resolution of the display device
  • the compensation transistor T3, the second reset transistor T4, the drive transistor T1, the data writing transistor T2, the reset transistor T7, the first light emission control transistor T5, and the second light emission control transistor T6 are all polysilicon transistors, which can improve the pixel circuit.
  • the charge transfer rate improves the charging capability of the pixel circuit; further, the compensation transistor T3, the first reset transistor T8, the second reset transistor T4, the drive transistor T1, the data writing transistor T2, the reset transistor T7, and the first light emission control transistor
  • Both T5 and the second light emission control transistor T6 have a single-gate structure, which can further simplify the layout (layout) of the pixel circuit 200, and further reduce the layout space occupied by the pixel circuit 200 on the display panel 100, which is beneficial to the improvement of the resolution of the display device. , the resolution of the display device can be increased by 8% through experiments.
  • the embodiment of the present application further details the display panel 100 and the pixel circuit 200 in the above embodiments.
  • FIG. 3 is a schematic diagram of the pattern of the first metal layer in the pixel circuit layout provided by the embodiment of the present application
  • FIG. 7 is a schematic diagram of the pattern of the second metal layer in the pixel circuit layout provided by the embodiment of the present application
  • FIG. 8 is a schematic diagram of the pattern of the second active layer in the pixel circuit layout provided by the embodiment of the present application
  • FIG. 9 is a schematic diagram of the pattern of the third metal layer in the pixel circuit layout provided by the embodiment of the present application
  • FIG. 10 is A schematic diagram of the pattern of the fourth metal layer in the pixel circuit layout provided by the embodiment of the present application
  • FIG. 11 is a schematic diagram of the pattern of the fifth metal layer in the pixel circuit layout provided by the embodiment of the present application
  • FIG. 12 is a schematic diagram of the pattern of the fifth metal layer in the pixel circuit layout provided by the embodiment of the present application.
  • FIG. 13 is a schematic diagram of the stacked structure of the first active layer to the fourth metal layer in the pixel circuit layout provided by the embodiment of the present application.
  • the layer structure of the display panel 100 may be as follows, but not limited to the number and order of the layer structure as follows, the layer structure of the display panel 100 includes : substrate 11; buffer layer 12 arranged on the substrate 11, first active layer 13 arranged on the buffer layer 12; first gate insulating layer 14 arranged on the first active layer 13; arranged on the first The first metal layer 15 on the gate insulating layer 14; the capacitor insulating layer 16 arranged on the first metal layer 15; the second metal layer 17 arranged on the capacitor insulating layer 16; the capacitor insulating layer 17 arranged on the second metal layer 17
  • the first active layer 13 includes the active layer T1B, the source T1S and the drain T1D of the driving transistor T1, and the first active layer 13 includes the data writing transistor T2
  • the active layer T2B, the source T2S and the drain T2D of the first active layer 13 include the active layer T3B, the source T3S and the drain T3D of the compensation transistor T3, and the first active layer 13 includes the second reset transistor T4
  • the active layer T4B, the source T4S and the drain T4D of the first active layer 13 include the active layer T5B, the source T5S and the drain T5D of the first light emission control transistor T5, and the first active layer 13 includes the second The active layer T6B, the source T6S and the drain T6D of the light emitting control transistor T6, the first active layer 13 includes the active layer T7B, the source T7S and the drain T7D of the reset transistor T7, and the active layers of each transistor are connected to each other To connect,
  • the first metal layer 15 includes the first scanning line Sn, the third scanning line Sn-1, the light emission control signal line EM, and the gate T1G of the driving transistor T1, wherein,
  • the first scanning line Sn includes the first sub-scanning line Sn1 and the second sub-scanning line Sn2, the gate T2G of the data writing transistor T2 and the gate T3G of the compensation transistor T3 are part of the first sub-scanning line Sn1, and the reset transistor
  • the gate T7G of T7 is a part of the second sub-scanning line Sn2, the gate T5G of the first light emission control transistor T5 and the gate T6G of the second light emission control transistor T6 are part of the light emission control signal line EM, and the second reset transistor T4
  • the gate T4G of the drive transistor T1 is a part of the third scan line Sn-1, and the gate T1G of the driving transistor T1 is multiplexed as the second capacitor electrode C12 of the
  • the second metal layer 17 includes the wiring of the first reset signal source VI1, the third sub-scanning line NSn1 of the second scanning line NSn, and the first capacitor electrode C11 of the storage capacitor Cst,
  • the first gate T8G1 of the first reset transistor T8 is a part of the third sub-scanning line NSn1. That is, the second metal layer 17 is patterned to form the first gate of the oxide transistor.
  • the second active layer 19 includes the active layer T8B of the first reset transistor T8 , the source T8S, and the drain T8D.
  • the third metal layer 21 includes the fourth sub-scanning line NSn2 of the second scanning line NSn and the routing of the second reset signal source VI2, and the second scanning line NSn includes the third sub-scanning line NSn Line NSn1 and the fourth sub-scanning line NSn2, the top gate T8G2 of the first reset transistor T8 is a part of the fourth sub-scanning line NSn2, at this time, the gate of the first reset transistor T8 includes a bottom gate T8G1 and a top gate T8G2. That is, the third metal layer 21 is patterned to form the second gate of the oxide transistor.
  • the fourth metal layer 23 includes the data line Data, the first connection electrode 201 , the second connection electrode 202 , the third connection electrode 203 , the fourth connection electrode 204 , and the fifth connection electrode 205 , the first connection electrode 201 , the second connection electrode 202 , the third connection electrode 203 , the fourth connection electrode 204 , and the fifth connection electrode 205 play the role of transmitting signals, and the specific functions of the transmission stage will be introduced later.
  • the fifth metal layer 25 includes the wiring of the first power supply VDD.
  • the display panel 100 includes a first type via hole Via1 , a second type via hole Via2 , a third type via hole Via3 , a fourth type via hole Via4 , a fifth type via hole Via5 , and a sixth type via hole Via6 .
  • the second metal layer 17 is connected to the fourth metal layer 23 through the first type via hole Via1, the fourth metal layer 23 is connected to the first active layer 13 through the second type via hole Via2, and the fourth metal layer 23 is connected to the second type active layer Via2.
  • the source layer 19 is connected through the third type via hole Via3, the fourth metal layer 23 is connected with the first metal layer 15 through the fourth type via hole Via4, and the fifth metal layer 25 and the first active layer 13 are connected through the fifth type via hole Via5 is connected, and the third metal layer 21 and the fourth metal layer 23 are connected through the sixth via hole Via6.
  • the first reset transistor T8 and the second reset transistor T4 are turned on, and the first reset signal source VI1 supplies the first reset signal to the first node A, and its current path includes: the second metal layer 17 formed by patterning
  • the wiring of a reset signal source V12 transmits signals to the first connecting electrodes 201 patterned and formed on the fourth metal layer 23 through the first-type via holes Via1, and the first connecting electrodes 201 transmit signals to the first active electrodes through the second-type via holes.
  • the signal is transmitted to the second connection electrode 202 formed by patterning the fourth metal layer 23, and the signal is transmitted from the second connection electrode 202 to the drain T8D of the first reset transistor T8 through the third via hole Via3, and the signal passes through the first reset transistor T8
  • the active layer T8B of the active layer T8B reaches the source T8S, and the signal is transmitted from the source T8S of the first reset transistor T8 to the third connection electrode 203 formed by patterning the fourth metal layer 23 through the third type via Via3, and the signal passes through the fourth type
  • the via hole Via4 passes from the third connection electrode 203 to the first node A (the second capacitor electrode C12 ).
  • the current path includes: the data line Data formed by patterning the fourth metal layer 23 transmits the signal to the first active layer 13 through the second via hole Via2, and the signal passes through the source T2S of the data writing transistor T2, the active Layer T2B and drain T2D reach the source of the driving transistor T1 (or the second node), the signal reaches the source T3S of the compensation transistor T3 through the driving transistor T1, and the signal reaches the drain of the compensation transistor T3 through the active layer T3B of the compensation transistor T3 T3D, the signal is transmitted from the drain T3D of the compensation transistor T3 to the second connection electrode 202 formed by patterning the fourth metal layer 23 through the second type via hole Via2, and the signal is transmitted from the second connection electrode 202 through the third type via hole Vi
  • the reset transistor T7 is turned on, and the second reset signal source VI2 supplies the first electrode O11 of the light-emitting element OL with a second reset signal, and its current path includes: the third metal layer 21 is patterned to form the second reset signal source VI2 through the second
  • the six vias transmit the signal to the fourth metal layer 23 and form the fourth connection electrode 204 by patterning.
  • the signal is transmitted from the fourth connection electrode 204 to the source T7S of the reset transistor T7 through the second type of via hole, and the signal is reset in turn.
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, the driving transistor T1 remains on, and the signal of the first power supply VDD flows to the light-emitting element OL. At this time, the light-emitting element OL is working to emit light.
  • the wiring of the first power supply VDD formed by patterning the fifth metal layer 25 transmits the signal to the source T5S of the first light emission control transistor T5 through the fifth via hole Via5, and the signal passes through the drain of the first light emission control transistor T5 T5D transfers to the source of the drive transistor T1 (or the second node), the signal passes through the drive transistor T1 to the source T6S of the second light emission control transistor T6, the signal is then transmitted to the drain T6D of the second light emission control transistor T6, and the signal passes through The second type of via Via2 passes from the drain T6D of the second light emission control transistor T6 to the fifth connection electrode 205 formed by patterning the fourth metal layer 23 , and the fifth connection electrode 205 is electrically connected to the first electrode O11 of the light emitting element OL.
  • the first reset transistor T8 is an oxide transistor, and a metal oxide semiconductor is used as the active layer, which can reduce the leakage current of the pixel circuit and make the current of the light emitting element OL more stable.
  • the second reset transistor T4 and the compensation transistor T3 adopt a single-gate structure, which can avoid the bloated layout of the pixel circuit 200, reduce the layout space occupied by the pixel circuit 200 on the display panel 100, and facilitate display The resolution of the device is improved;
  • the compensation transistor T3, the second reset transistor T4, the drive transistor T1, the data writing transistor T2, the reset transistor T7, the first light emission control transistor T5, and the second light emission control transistor T6 are all polysilicon transistors, which can Improve the charge transfer rate in the pixel circuit, improve the charging capacity of the pixel circuit;
  • An embodiment of the present application also provides a display device, including the display panel 100 described in any one of the above embodiments, and the display device further includes a support layer disposed on the back side of the display panel, and a supporting layer disposed on the back side of the display panel.
  • the display panel may further include an encapsulation layer covering the surface of the light emitting element OL.
  • the single-gate structure in the embodiment of the present application refers to only one of the bottom gate and the top gate, and only one gate when there is a bottom gate, or only one gate when there is a top gate.
  • the second reset transistor T4 and the compensation transistor T3 have a single-gate structure, that is, the second reset transistor T4 has only one top gate of the gate T4G, that is, the compensation transistor T3 has only one top gate of the gate T3G, and in the prior art, some transistors have multiple top gates or multiple bottom gates, and in the embodiment of the present application, the first reset transistor T8 includes a bottom gate T8G1 and a top gate T8G2 , which need to be distinguished.

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Abstract

一种显示面板（100），像素电路（200）包括驱动晶体管（T1）、数据写入晶体管（T2）、存储电容（Cst）和第一复位晶体管（T8），第一复位晶体管（T8）的栅极（T8G）电连接第二扫描线（NSn），第一复位晶体管（T8）的源极（T8S）电连接第一节点（A），第一复位晶体管（T8）的漏极（T8D）电连接第一复位信号源（VI1）；其中，第一复位晶体管（T8）为氧化物晶体管，驱动晶体管（T1）和数据写入晶体管（T2）为多晶硅晶体管。

Description

一种显示面板 技术领域
本申请涉及显示领域，具体涉及一种显示面板。
 背景技术
随着多媒体的发展，显示装置变得越来越重要。相应地，对各种类型的显示装置的要求越来越高，尤其是智能手机领域，超高频驱动显示，低功耗驱动显示，以及低频驱动显示都是现阶段和未来的发展需求方向。
由于低温多晶硅（Low Temperature Poly-Silicon，LTPS）的迁移率高、驱动能力强，因此LTPS薄膜晶体管广泛地应用于OLED显示装置（有机发光显示装置）中的像素电路，但是，LTPS薄膜晶体管的漏电流较大，尤其是在低频显示时由于漏电流较大而容易导致栅极电压不稳定，从而使栅极和源极电位差不稳定，导致OLED发光元件的电流不稳定，显示装置出现闪烁现象。
因此，有必要提出一种显示面板，以解决采用LTPS薄膜晶体管的像素电路由于晶体管的漏电流较大，使得OLED发光元件电流不稳定，显示面板出现闪烁现象的问题。
 技术问题
本申请实施例提供了一种显示面板，可以解决采用多晶硅薄膜晶体管的像素电路由于晶体管的漏电流较大，使得OLED发光元件电流不稳定，显示装置出现闪烁现象的问题。
 技术解决方案
本申请实施例提供了一种显示面板，包括阵列设置的多个发光元件和驱动所述发光元件发光的像素电路，所述发光元件的第一电极电连接第一电源，所述发光元件的第二电极电连接第二电源，所述像素电路耦合在所述第一电源和所述发光元件的所述第一电极之间，所述像素电路包括：
驱动晶体管，所述驱动晶体管的栅极电连接第一节点，所述驱动晶体管的源极电连接第二节点，所述驱动晶体管的漏极电连接第三节点，所述发光元件的所述第一电极通过所述驱动晶体管电连接所述第一电源；
数据写入晶体管，所述数据写入晶体管的栅极电连接第一扫描线，所述数据写入晶体管的源极电连接数据线，所述数据写入晶体管的漏极电连接所述第二节点；
存储电容，包括第一电容电极和第二电容电极，所述第一电容电极电连接所述第一电源，所述第二电容电极电连接所述第一节点；
第一复位晶体管，所述第一复位晶体管的栅极电连接第二扫描线，所述第一复位晶体管的源极电连接所述第一节点，所述第一复位晶体管的漏极电连接第一复位信号源；
其中，所述第一复位晶体管为氧化物晶体管，所述驱动晶体管和所述数据写入晶体管为多晶硅晶体管。
可选的，在本申请的一些实施例中，所述像素电路还包括：
补偿晶体管，所述补偿晶体管的栅极电连接所述第一扫描线，所述补偿晶体管的源极电连接所述第三节点，所述补偿晶体管的漏极电连所述第一复位晶体管的漏极；
第二复位晶体管，所述第二复位晶体管的栅极电连接第三扫描线，所述第二复位晶体管的源极电连接所述第一复位晶体管的漏极，所述第二复位晶体管的漏极电连接所述第一复位信号源；
其中，所述补偿晶体管和所述第二复位晶体管均为多晶硅晶体管。
可选的，在本申请的一些实施例中，所述第二复位晶体管和所述补偿晶体管为单栅结构。
可选的，在本申请的一些实施例中，包括自下而上层叠设置的基底、第一有源层、第一金属层、第二金属层、第二有源层、第三金属层；
所述第一有源层形成多晶硅晶体管的有源层，所述第二有源层形成氧化物晶体管的有源层；
所述第一金属层形成所述多晶硅晶体管的栅极；所述第二金属层形成所述氧化物晶体管的第一栅极；
其中，所述氧化物晶体管的第一栅极在所述基底上的正投影与所述氧化物晶体管的有源层在所述基底上的正投影具有一个重叠区；
其中，所述多晶硅晶体管的栅极在所述基底上的正投影与所述多晶硅晶体管的有源层在所述基底上的正投影具有一个重叠区。
可选的，在本申请的一些实施例中，所述第三金属层形成所述氧化物晶体管的第二栅极；
其中，所述氧化物晶体管的第二栅极在所述基底上的正投影与所述氧化物晶体管的有源层在所述基底上的正投影具有一个重叠区，且所述氧化物晶体管的第二栅极与所述氧化物晶体管的第一栅极在所述基底上的正投影至少部分重叠。
可选的，在本申请的一些实施例中，所述像素电路还包括：
重置晶体管，所述重置晶体管的栅极电连接第一扫描线，所述重置晶体管的源极电连接第二复位信号源，所述重置晶体管的漏极连接在所述发光元件的所述第一电极；
第一发光控制晶体管，所述第一发光控制晶体管的栅极电连接发光控制信号线，所述第一发光控制晶体管的源极电连接所述第一电源，所述第一发光控制晶体管的漏极电连接所述第二节点；
第二发光控制晶体管，所述第二发光控制晶体管的栅极电连接发光控制信号线，所述第二发光控制晶体管的源极电连接所述第三节点，所述第二发光控制晶体管的漏极电连接所述发光元件的所述第一电极。
可选的，在本申请的一些实施例中，所述重置晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管均为多晶硅晶体管。
可选的，在本申请的一些实施例中，所述多晶硅晶体管为P型晶体管；所述氧化物晶体管为N型晶体管。
可选的，在本申请的一些实施例中，所述第一复位信号源和所述第二复位信号源为同一复位信号源。
可选的，在本申请的一些实施例中，所述第一扫描线和所述第二扫描线为当前行扫描线，所述第三扫描线为前一行扫描线。
 有益效果
本申请实施例中，提供了一种显示面板，可以降低采用多晶硅薄膜晶体管的像素电路的漏电流的大小，使得OLED发光元件电流更加稳定，改善显示面板出现的闪烁现象。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一实施例提供的显示面板上像素电路的等效电路的示意图；
图2是本申请一实施例提供的显示面板上像素电路的等效电路的时序图；
图3是本申请一实施例提供的显示面板上的像素电路的截面膜层结构示意图；
图4是本申请一实施例提供的显示面板上的像素电路的版图布局示意图；
图5是本申请一实施例提供的像素电路版图中的第一有源层的图案示意图；
图6为本申请一实施例提供的像素电路版图中的第一金属层的图案示意图；
图7为本申请一实施例提供的像素电路版图中的第二金属层的图案示意图；
图8为本申请一实施例提供的像素电路版图中的第二有源层的图案示意图；
图9为本申请一实施例提供的像素电路版图中的第三金属层的图案示意；
图10为本申请一实施例提供的像素电路版图中的第四金属层的图案示意图；
图11为本申请一实施例提供的像素电路版图中的第五金属层的图案示意图；
图12为本申请一实施例提供的像素电路版图中的第一有源层至第一金属层的堆叠结构示意图；
图13为本申请一实施例提供的像素电路版图中的第一有源层至第四金属层的堆叠结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
本申请实施例提供了一种显示面板，显示面板包括阵列设置的多个发光元件和驱动发光元件发光的像素电路，发光元件的第一电极电连接第一电源，发光元件的第二电极电连接第二电源，像素电路耦合在第一电源和发光元件的第一电极之间，像素电路包括：驱动晶体管，驱动晶体管的栅极电连接第一节点，驱动晶体管的源极电连接第二节点，驱动晶体管的漏极电连接第三节点，发光元件的第一电极通过驱动晶体管电连接第一电源；数据写入晶体管，数据写入晶体管的栅极电连接第一扫描线，数据写入晶体管的源极电连接数据线，数据写入晶体管的漏极电连接第二节点；存储电容，包括第一电容电极和第二电容电极，第一电容电极电连接第一电源，第二电容电极电连接第一节点；第一复位晶体管，第一复位晶体管的栅极电连接第二扫描线，第一复位晶体管的源极电连接第一节点，第一复位晶体管的漏极电连接第一复位信号源；其中，第一复位晶体管为氧化物晶体管，驱动晶体管和数据写入晶体管为多晶硅晶体管。
本申请实施例提供了一种显示面板。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
实施例一、
请参阅图1、图2，图3、图4，图1为本申请实施例提供的显示面板上像素电路的等效电路的示意图，图2为本申请实施例提供的显示面板上像素电路的等效电路图的时序图，图3为本申请实施例提供的显示面板上的像素电路的截面膜层结构示意图，图4为本申请实施例提供的显示面板上的像素电路版图布局的示意图。
本申请实施例提供的显示面板100包括阵列设置的多个发光元件OL和驱动发光元件OL发光的像素电路200，发光元件OL的第一电极O11电连接第一电源VDD，发光元件的OL第二电极O12电连接第二电源VSS，像素电路200耦合在第一电源VDD和发光元件OL的第一电极O11之间，像素电路200包括驱动晶体管T1、数据写入晶体管T2、存储电容Cst和第一复位晶体管T8。
驱动晶体管T1，驱动晶体管T1的栅极T1G电连接第一节点A，驱动晶体管T1的源极T1S电连接第二节点B，驱动晶体管T1的漏极T1D电连接第三节点C，发光元件OL的第一电极O11通过驱动晶体管T1电连接第一电源VDD；
数据写入晶体管T2，数据写入晶体管T2的栅极T2G电连接第一扫描线Sn，数据写入晶体管T2的源极T2S电连接数据线Data，数据写入晶体管T2的漏极T2D电连接第二节点B；
存储电容Cst，包括第一电容电极C11和第二电容电极C12，第一电容电极C11电连接第一电源VDD，第二电容电极C12电连接第一节点A；
第一复位晶体管T8，第一复位晶体管T8的栅极T8G电连接第二扫描线NSn，第一复位晶体管T8的源极T8S电连接第一节点A，第一复位晶体管T8的漏极T8D电连接第一复位信号源VI1；
其中，第一复位晶体管T8为氧化物晶体管，驱动晶体管T1和数据写入晶体管T2为多晶硅晶体管。
进一步的，像素电路200还包括补偿晶体管T3、第二复位晶体管T4。
补偿晶体管T3，补偿晶体管T3的栅极T3G电连接第一扫描线Sn，补偿晶体管T3的源极T3S电连接第三节点C，补偿晶体管T3的漏极T3D电连第一复位晶体管T8的漏极T8D；
第二复位晶体管T4，第二复位晶体管T4的栅极T4G电连接第三扫描线Sn-1，第二复位晶体管T4的源极T4S电连接第一复位晶体管T8的漏极T8D，第二复位晶体管T4的漏极T4D电连接第一复位信号源VI1；
其中，补偿晶体管T3和第二复位晶体管T4均为多晶硅晶体管。
进一步的，显示面板100包括自下而上层叠设置的基底11、第一有源层13、第一金属层15、第二金属层17、第二有源层19、第三金属层21；
第一有源层13形成多晶硅晶体管的有源层，第二有源层19形成氧化物晶体管的有源层；
第一金属层15形成多晶硅晶体管的栅极；第二金属层17形成氧化物晶体管的第一栅极；
具体的，第一金属层15形成多晶硅晶体管的栅极，即第一金属层15形成多晶硅晶体管的顶栅极；第二金属层17形成氧化物晶体管的第一栅极，即第二金属层17形成氧化物晶体管的底栅极。
其中，氧化物晶体管的第一栅极在基底11上的正投影与氧化物晶体管的有源层在基底11上的正投影具有一个重叠区；
其中，多晶硅晶体管的栅极在基底11上的正投影与多晶硅晶体管的有源层在基底11上的正投影具有一个重叠区。
进一步的，显示面板100的结构还包括：
第三金属层21形成氧化物晶体管的第二栅极；
其中，氧化物晶体管的第二栅极在基底11上的正投影与氧化物晶体管的有源层在基底11上的正投影具有一个重叠区，且氧化物晶体管的第二栅极与氧化物晶体管的第一栅极在基底上的正投影至少部分重叠。
具体的，第三金属层21形成氧化物晶体管的第二栅极，即第三金属层21形成氧化物晶体管的顶栅极。
进一步的，像素电路200还包括重置晶体管T7、第一发光控制晶体管T5和、第二发光控制晶体管T6。
重置晶体管T7，重置晶体管T7的栅极T7G电连接第一扫描线Sn，重置晶体管T7的源极T7S电连接第二复位信号源VI2，重置晶体管T7的漏极T7D电连接发光元件OL的第一电极O11；
第一发光控制晶体管T5，第一发光控制晶体管T5的栅极T5G电连接发光控制信号线EM，第一发光控制晶体管T5的源极T5S电连接第一电源VDD，第一发光控制晶体管T5的漏极T5D电连接第二节点B；
第二发光控制晶体管T6，第二发光控制晶体管T6的栅极T6G电连接发光控制信号线EM，第二发光控制晶体管T6的源极T6S电连接第三节点C，第二发光控制晶体管T6的漏极T6D电连接发光元件OL的第一电极O11。
进一步的，重置晶体管T7、第一发光控制晶体管T5、第二发光控制晶体管T6均多晶硅晶体管。
进一步的，多晶硅晶体管为P型晶体管；氧化物晶体管为N型晶体管。
进一步的，第一复位信号源VI1和第二复位信号源VI2为同一复位信号源。
进一步的，第一扫描线Sn和第二扫描线NSn为当前行扫描线，第三扫描线Sn-1为前一行扫描线。
进一步的，第二复位晶体管T4和补偿晶体管T3为单栅结构。
具体的，第二复位晶体管T4在其有源层的一侧只有一个栅极，补偿晶体管T3在其有源层的一侧只有一个栅极，为单栅结构。
在一些实施例中，驱动晶体管T1、数据写入晶体管T2、第一复位晶体管T8、补偿晶体管T3、第二复位晶体管T4、重置晶体管T7、第一发光控制晶体管T5和第二发光控制晶体管T6均为单栅结构，即在各自的有源层的一侧只有一个栅极。
下面对上述实施例的结构和连接关系进行进一步的说明。
第一复位信号源VI1和第二复位信号源VI2可以为分开的两条独立的信号线分别供给信号，此时通过第一复位晶体管T8、第二复位晶体管T4供给第一节点A以第一复位信号源VI1的第一复位信号，通过重置晶体管T7供给发光元件OL的第一电极O11以第二复位信号，第一复位信号与第二复位信号不同，第一节点A和发光元件OL的第一电极O11分别独立供给不同的复位信号，避免第一节点A的复位信号干扰发光元件OL的第一电极O11的复位信号，可以提升发光元件OL的发光效率和亮度。
第一复位信号源VI1和第二复位信号源VI2可以为同一复位信号源，第一节点A和发光元件OL的第一电极O11供给相同的复位信号，可以减小布线数量。
第一扫描线Sn和第二扫描线NSn为当前行扫描线表示第n行像素包括第一扫描线Sn和第二扫描线NSn，第三扫描线Sn-1为前一行扫描线表示第n-1行像素包括前一行的第一扫描线Sn-1和前一行的第二扫描线NSn-1，即前一行的第一扫描线Sn-1为第n行像素的第三扫描线Sn-1。
Sn表示第n行像素的扫描线，供给多晶硅晶体管的扫描线信号；NSn表示第n行像素的扫描线，供给氧化物晶体管的扫描线信号。
请继续参阅图1、图2和图3，下面结合图1、图2和图3说明像素电路的200的工作过程。第一复位晶体管T8为氧化物晶体管，氧化物晶体管的有源层的材料为氧化物半导体，例如IGZO（indium gallium zinc oxide，铟镓锌氧化物）。补偿晶体管T3、第二复位晶体管T4、驱动晶体管T1、数据写入晶体管T2、重置晶体管T7、第一发光控制晶体管T5、第二发光控制晶体管T6均多晶硅晶体管，多晶硅晶体管的有源层的材料为多晶硅，例如低温多晶硅（LTPS）。
在复位阶段t1，第一扫描线Sn的信号和第二扫描线NSn的信号为高电位，第三扫描线Sn-1的信号为低电位，发光控制信号线EM的信号为高电位，驱动晶体管T1、数据写入晶体管T2、补偿晶体管T3、重置晶体管T7、第一发光控制晶体管T5、第二发光控制晶体管T6关闭，第一复位晶体管T8、第二复位晶体管T4打开，第一复位信号源供给第一节点A以第一复位信号。
在数据写入阶段t2，第一扫描线Sn的信号为低电位，第二扫描线NSn的信号和第三扫描线Sn-1的信号为高电位，发光控制信号线EM的信号为高电位，补偿晶体管T3和第一复位晶体管T8打开，将驱动晶体管T1的栅极T1G与漏极T1D导通，通过驱动晶体管T1的阈值电压在驱动晶体管T1的栅极T1G与源极T1S之间生成电压差，此时，驱动晶体管T1打开，数据写入晶体管T2打开，向第二节点B输入数据线Data的数据信号，数据线Data的数据信号包含补偿的阈值电压，并被输入至驱动晶体管T1的栅极T1G，从而补偿了驱动晶体管T1的阈值电压偏差。写入的数据线Data的数据信号通过驱动晶体管T1给第一节点A充电，直至第一节点A的电压变为Vdata-Vth，驱动晶体管T1截止。此外，重置晶体管T7打开，第二复位信号源VI2供给发光元件OL的第一电极O11以第二复位信号。
在发光阶段t3，第一扫描线Sn的信号和第三扫描线Sn-1的信号为高电位，第二扫描线NSn的信号为低电位，发光控制信号线EM的电位为低电位，数据写入晶体管T2、补偿晶体管T3、第一复位晶体管T8、第二复位晶体管T4、重置晶体管T7关闭，第一发光控制晶体管T5、第二发光控制晶体管T6打开，驱动晶体管T1保持打开状态，第一电源VDD的信号流向发光元件OL，此时发光元件OL发光工作。
在一些实施例中，发光元件OL的第一电极O11和第二电极O12可以分别为阳极和阴极。
在本申请实施例中，第一复位晶体管T8为氧化物晶体管，具体的，氧化物晶体管的第二栅极在基底11上的正投影与氧化物晶体管的有源层在基底11上的正投影具有一个重叠区，第二有源层19形成氧化物晶体管的有源层，第二有源层19为金属氧化物有源层。
在本申请实施例中，补偿晶体管T3、第二复位晶体管T4、驱动晶体管T1、数据写入晶体管T2、重置晶体管T7、第一发光控制晶体管T5、第二发光控制晶体管T6均多晶硅晶体管，具体的，多晶硅晶体管的栅极在基底11上的正投影与多晶硅晶体管的有源层在基底11上的正投影具有一个重叠区，第一有源层13形成多晶硅晶体管的有源层。进一步的，第三金属层21形成氧化物晶体管的第二栅极；其中，氧化物晶体管的第二栅极在基底11上的正投影与氧化物晶体管的有源层在基底11上的正投影具有一个重叠区，且氧化物晶体管的第二栅极与氧化物晶体管的第一栅极在基底上的正投影至少部分重叠。
在本申请实施例中，第一复位晶体管T8为氧化物晶体管，采用金属氧化物半导体作为有源层，可以减小像素电路的漏电流，使得发光元件OL的电流更加稳定，避免显示装置出现闪烁现象；第二复位晶体管T4和补偿晶体管T3采用单栅结构，可以避免像素电路200的版图（layout）臃肿，减小像素电路200在显示面板100上占据的版图空间，利于显示装置的分辨率提升；补偿晶体管T3、第二复位晶体管T4、驱动晶体管T1、数据写入晶体管T2、重置晶体管T7、第一发光控制晶体管T5、第二发光控制晶体管T6均为多晶硅晶体管，可以提升像素电路中的电荷迁移速率，提升像素电路的充电能力；进一步的，补偿晶体管T3、第一复位晶体管T8、第二复位晶体管T4、驱动晶体管T1、数据写入晶体管T2、重置晶体管T7、第一发光控制晶体管T5、第二发光控制晶体管T6均为单栅结构，可以进一步的简化像素电路200的版图（layout），进一步减小像素电路200在显示面板100上占据的版图空间，利于显示装置的分辨率提升，通过实验证可以提升显示装置的分辨率8%。
实施例二、
本申请实施例对上述实施例中的显示面板100和像素电路200进一步详细说明。
请参阅图3、图4、图5、图6、图7、图8、图9、图10、图11、图12、图13，图5为本申请实施例提供的像素电路版图中的第一有源层的图案示意图，图6为本申请实施例提供的像素电路版图中的第一金属层的图案示意图，图7为本申请实施例提供的像素电路版图中的第二金属层的图案示意图，图8为本申请实施例提供的像素电路版图中的第二有源层的图案示意图，图9为本申请实施例提供的像素电路版图中的第三金属层的图案示意图，图10为本申请实施例提供的像素电路版图中的第四金属层的图案示意图，图11为本申请实施例提供的像素电路版图中的第五金属层的图案示意图，图12为本申请实施例提供的像素电路版图中的第一有源层至第一金属层的堆叠结构示意图，图13为本申请实施例提供的像素电路版图中的第一有源层至第四金属层的堆叠结构示意图。
在一些实施例中，请参阅图2、图4，像素电路200设置于显示面板100上，显示面板100的层结构可以如下，但不限于如下层结构数量和顺序，显示面板100的层结构包括：基底11；设于基底11上的缓冲层12，设于缓冲层12上的第一有源层13；设于第一有源层13上的第一栅极绝缘层14；设于第一栅极绝缘层14上的第一金属层15；设于第一金属层15上的电容绝缘层16；设于电容绝缘层16上的第二金属层17；设于第二金属层17上的第二栅极绝缘层18；设于第二栅极绝缘层18上的第二有源层19；设于第二有源层19上的第三栅极绝缘层20；设于第三栅极绝缘层20上的第三金属层21；设于第三金属层21上的层间绝缘层22；设于层间绝缘层22上的第四金属层23；设于第四金属层23上的第一平坦层24；设于第一平坦层24上的第五金属层25；设于第五金属层25上的第二平坦层26；设于第二平坦层上的阳极27；设于阳极27上的像素定义层28。
请结合图3、图4、图5、图12，第一有源层13包括驱动晶体管T1的有源层T1B、源极T1S和漏极T1D，第一有源层13包括数据写入晶体管T2的有源层T2B、源极T2S和漏极T2D，第一有源层13包括补偿晶体管T3的有源层T3B、源极T3S和漏极T3D，第一有源层13包括第二复位晶体管T4的有源层T4B、源极T4S和漏极T4D，第一有源层13包括第一发光控制晶体管T5的有源层T5B、源极T5S和漏极T5D，第一有源层13包括第二发光控制晶体管T6的有源层T6B、源极T6S和漏极T6D，第一有源层13包括重置晶体管T7的有源层T7B、源极T7S和漏极T7D，各晶体管的有源层相互连接，不同晶体管之间的第一有源层的材料被导体化，以便充当源极或漏极的走线或电极进行电性连接。
请结合图3、图4、图6、图12，第一金属层15包括第一扫描线Sn、第三扫描线Sn-1、发光控制信号线EM、驱动晶体管T1的栅极T1G，其中，第一扫描线Sn包括第一子扫描线Sn1和第二子扫描线Sn2，数据写入晶体管T2的栅极T2G和补偿晶体管T3的栅极T3G为第一子扫描线Sn1的一部分，重置晶体管T7的栅极T7G为第二子扫描线Sn2的一部分，第一发光控制晶体管T5的栅极T5G和第二发光控制晶体管T6的栅极T6G为发光控制信号线EM的一部分，第二复位晶体管T4的栅极T4G为第三扫描线Sn-1的一部分，驱动晶体管T1的栅极T1G复用为存储电容Cst的第二电容电极C12。即，第一金属层15图案化形成了多晶硅晶体管的栅极。
请结合图3、图4、图7，第二金属层17包括第一复位信号源VI1的走线、第二扫描线NSn的第三子扫描线NSn1和存储电容Cst的第一电容电极C11，第一复位晶体管T8的第一栅极T8G1为第三子扫描线NSn1的一部分。即，第二金属层17图案化形成了氧化物晶体管的第一栅极。
请结合图3、图4、图8，第二有源层19包括第一复位晶体管T8的有源层T8B、源极T8S、漏极T8D。
请结合图3、图4、图9，第三金属层21包括第二扫描线NSn的第四子扫描线NSn2和第二复位信号源VI2的走线，第二扫描线NSn包括第三子扫描线NSn1和第四子扫描线NSn2，第一复位晶体管T8的顶栅T8G2为第四子扫描线NSn2的一部分，此时，第一复位晶体管T8的栅极包括底栅T8G1和顶栅T8G2。即，第三金属层21图案化形成了氧化物晶体管的第二栅极。
请结合图3、图4、图10，第四金属层23包括数据线Data、第一连接电极201、第二连接电极202、第三连接电极203、第四连接电极204、第五连接电极205，第一连接电极201、第二连接电极202、第三连接电极203、第四连接电极204、第五连接电极205起到传递信号的作用，具体传递阶段的作用在后续介绍。
请结合图3、图4、图11，第五金属层25包括第一电源VDD的走线。
下面结合图1、图2、图4、说明显示面板100上像素电路200和发光元件OL的电流路径。其中，显示面板100包括第一种过孔Via1、第二种过孔Via2、第三种过孔Via3、第四种过孔Via4、第五种过孔Via5、第六种过孔Via6。第二金属层17与第四金属层23通过第一种过孔Via1连接，第四金属层23与第一有源层13通过第二种过孔Via2连接，第四金属层23与第二有源层19通过第三种过孔Via3连接，第四金属层23与第一金属层15通过第四种过孔Via4连接，第五金属层25与第一有源层13通过第五种过孔Via5连接，第三金属层21与第四金属层23通过第六种过孔Via6连接。
在复位阶段t1，第一复位晶体管T8、第二复位晶体管T4打开，第一复位信号源VI1供给第一节点A以第一复位信号，其电流路径包括：第二金属层17图案化形成的第一复位信号源V12的走线通过第一种过孔Via1传递信号至第四金属层23图案化形成的第一连接电极201，第一连接电极201通过第二种过孔传递信号至第一有源层13中的第二复位晶体管T4的漏极T4D，信号经过第二复位晶体管T4的有源层T4B到达源极T4S，信号通过第二种过孔Via2从第二复位晶体管T4的源极T4S传递至第四金属层23图案化形成的第二连接电极202，信号通过第三种过孔Via3从第二连接电极202传递至第一复位晶体管T8的漏极T8D，信号经过第一复位晶体管T8的有源层T8B到达源极T8S，信号通过第三种过孔Via3从第一复位晶体管T8的源极T8S传递至第四金属层23图案化形成的第三连接电极203，信号通过第四种过孔Via4从第三连接电极203传递至第一节点A（第二电容电极C12）。
在数据写入阶段t2，驱动晶体管T1、数据写入晶体管T2、补偿晶体管T3和第一复位晶体管T8打开，向第二节点B输入数据线Data的数据信号，并将信号传递至第一节点A，其电流路径包括：第四金属层23图案化形成的数据线Data通过第二种过孔Via2将信号传递至第一有源层13，信号经过数据写入晶体管T2的源极T2S、有源层T2B、漏极T2D达到驱动晶体管T1源极（或第二节点），信号经过驱动晶体管T1到达补偿晶体管T3的源极T3S，信号经过补偿晶体管T3的有源层T3B到达补偿晶体管T3的漏极T3D，信号通过第二种过孔Via2从补偿晶体管T3的漏极T3D传递至第四金属层23图案化形成的第二连接电极202，信号通过第三种过孔Via3从第二连接电极202传递至第一复位晶体管T8的漏极T8D，信号经过第一复位晶体管T8的有源层T8B到达源极T8S，信号通过第三种过孔Via3从第一复位晶体管T8的源极T8S传递至第四金属层23图案化形成的第三连接电极203，信号通过第四种过孔Via4从第三连接电极203传递至第一节点A（第二电容电极C12）。此外，重置晶体管T7打开，第二复位信号源VI2供给发光元件OL的第一电极O11以第二复位信号，其电流路径包括：第三金属层21图案化形成第二复位信号源VI2通过第六过孔将信号传递至第四金属层23图案化形成第四连接电极204，信号通过第二种过孔从第四连接电极204传递至重置晶体管T7的源极T7S，信号依次经过重置晶体管T7的源极T7S、有源层T7B、漏极T7D，信号再通过第二种过孔Via2从重置晶体管T7的漏极T7D传递至第四金属层23图案化形成的第五连接电极205，第五连接电极205电连接发光元件OL的第一电极O11。
在发光阶段t3，第一发光控制晶体管T5、第二发光控制晶体管T6打开，驱动晶体管T1保持打开状态，第一电源VDD的信号流向发光元件OL，此时发光元件OL发光工作，其电流路径包括：第五金属层25图案化形成的第一电源VDD的走线将信号通过第五种过孔Via5传递至第一发光控制晶体管T5的源极T5S，信号经过第一发光控制晶体管T5的漏极T5D传递达到驱动晶体管T1源极（或第二节点），信号经过驱动晶体管T1到达第二发光控制晶体管T6的源极T6S，信号再传递至第二发光控制晶体管T6的漏极T6D，信号再通过第二种过孔Via2从第二发光控制晶体管T6的漏极T6D传递至第四金属层23图案化形成的第五连接电极205，第五连接电极205电连接发光元件OL的第一电极O11。
请参阅图4，在本申请实施例中，第一复位晶体管T8为氧化物晶体管，采用金属氧化物半导体作为有源层，可以减小像素电路的漏电流，使得发光元件OL的电流更加稳定，避免显示装置出现闪烁现象；第二复位晶体管T4和补偿晶体管T3采用单栅结构，可以避免像素电路200的版图（layout）臃肿，减小像素电路200在显示面板100上占据的版图空间，利于显示装置的分辨率提升；补偿晶体管T3、第二复位晶体管T4、驱动晶体管T1、数据写入晶体管T2、重置晶体管T7、第一发光控制晶体管T5、第二发光控制晶体管T6均为多晶硅晶体管，可以提升像素电路中的电荷迁移速率，提升像素电路的充电能力；进一步的，补偿晶体管T3、第一复位晶体管T8、第二复位晶体管T4、驱动晶体管T1、数据写入晶体管T2、重置晶体管T7、第一发光控制晶体管T5、第二发光控制晶体管T6均为单栅结构，可以进一步的简化像素电路200的版图（layout），进一步减小像素电路200在显示面板100上占据的版图空间，利于显示装置的分辨率提升，通过实验证可以提升显示装置的分辨率8%。
实施例三、
本申请实施例还提供了一种显示装置，包括如上述实施例中任一项所述的显示面板100，所述显示装置还包括设置于所述显示面板背侧的支撑层，以及设置于所述显示面板正侧的保护层。显示面板还可以包括封装层，封装层覆盖在发光元件OL的表面。
需要说明的是，本申请实施例中的单栅结构是指：只具有底栅和顶栅中的一个，且具有底栅时只有一个栅极，或具有顶栅时只有一个栅极。例如在一些实施例中，第二复位晶体管T4和补偿晶体管T3为单栅结构，即第二复位晶体管T4只有栅极T4G的一个顶栅，即补偿晶体管T3只有栅极T3G一个顶栅，而在现有技术中，一些晶体管具有多个顶栅或多个底栅，且本申请实施例之中第一复位晶体管T8包括底栅T8G1和顶栅T8G2，这是需要区分的。
以上对本申请实施例所提供的一种显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (10)

  1. 一种显示面板，其中，包括阵列设置的多个发光元件和驱动所述发光元件发光的像素电路，所述发光元件的第一电极电连接第一电源，所述发光元件的第二电极电连接第二电源，所述像素电路耦合在所述第一电源和所述发光元件的所述第一电极之间，所述像素电路包括：
    驱动晶体管，所述驱动晶体管的栅极电连接第一节点，所述驱动晶体管的源极电连接第二节点，所述驱动晶体管的漏极电连接第三节点，所述发光元件的所述第一电极通过所述驱动晶体管电连接所述第一电源；
    数据写入晶体管，所述数据写入晶体管的栅极电连接第一扫描线，所述数据写入晶体管的源极电连接数据线，所述数据写入晶体管的漏极电连接所述第二节点；
    存储电容，包括第一电容电极和第二电容电极，所述第一电容电极电连接所述第一电源，所述第二电容电极电连接所述第一节点；
    第一复位晶体管，所述第一复位晶体管的栅极电连接第二扫描线，所述第一复位晶体管的源极电连接所述第一节点，所述第一复位晶体管的漏极电连接第一复位信号源；
    其中，所述第一复位晶体管为氧化物晶体管，所述驱动晶体管和所述数据写入晶体管为多晶硅晶体管。
  2. 如权利要求1所述的显示面板，其中，所述像素电路还包括：
    补偿晶体管，所述补偿晶体管的栅极电连接所述第一扫描线，所述补偿晶体管的源极电连接所述第三节点，所述补偿晶体管的漏极电连所述第一复位晶体管的漏极；
    第二复位晶体管，所述第二复位晶体管的栅极电连接第三扫描线，所述第二复位晶体管的源极电连接所述第一复位晶体管的漏极，所述第二复位晶体管的漏极电连接所述第一复位信号源；
    其中，所述补偿晶体管和所述第二复位晶体管均为多晶硅晶体管。
  3. 如权利要求2所述的显示面板，其中，所述第二复位晶体管和所述补偿晶体管为单栅结构。
  4. 如权利要求2所述的显示面板，其中，包括自下而上层叠设置的基底、第一有源层、第一金属层、第二金属层、第二有源层、第三金属层；
    所述第一有源层形成多晶硅晶体管的有源层，所述第二有源层形成氧化物晶体管的有源层；
    所述第一金属层形成所述多晶硅晶体管的栅极；所述第二金属层形成所述氧化物晶体管的第一栅极；
    其中，所述氧化物晶体管的第一栅极在所述基底上的正投影与所述氧化物晶体管的有源层在所述基底上的正投影具有一个重叠区；
    其中，所述多晶硅晶体管的栅极在所述基底上的正投影与所述多晶硅晶体管的有源层在所述基底上的正投影具有一个重叠区。
  5. 如权利要求4所述的显示面板，其中，所述第三金属层形成所述氧化物晶体管的第二栅极；
    其中，所述氧化物晶体管的第二栅极在所述基底上的正投影与所述氧化物晶体管的有源层在所述基底上的正投影具有一个重叠区，且所述氧化物晶体管的第二栅极与所述氧化物晶体管的第一栅极在所述基底上的正投影至少部分重叠。
  6. 如权利要求2所述的显示面板，其中，所述像素电路还包括：
    重置晶体管，所述重置晶体管的栅极电连接第一扫描线，所述重置晶体管的源极电连接第二复位信号源，所述重置晶体管的漏极连接在所述发光元件的所述第一电极；
    第一发光控制晶体管，所述第一发光控制晶体管的栅极电连接发光控制信号线，所述第一发光控制晶体管的源极电连接所述第一电源，所述第一发光控制晶体管的漏极电连接所述第二节点；
    第二发光控制晶体管，所述第二发光控制晶体管的栅极电连接发光控制信号线，所述第二发光控制晶体管的源极电连接所述第三节点，所述第二发光控制晶体管的漏极电连接所述发光元件的所述第一电极。
  7. 如权利要求6所述的显示面板，其中，所述重置晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管均为多晶硅晶体管。
  8. 如权利要求7所述的显示面板，其中，所述多晶硅晶体管为P型晶体管；所述氧化物晶体管为N型晶体管。
  9. 如权利要求6所述的显示面板，其中，所述第一复位信号源和所述第二复位信号源为同一复位信号源。
  10. 如权利要求2所述的显示面板，其中，所述第一扫描线和所述第二扫描线为当前行扫描线，所述第三扫描线为前一行扫描线。
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