WO2023028901A1 - 半导体器件的制作方法、半导体器件及三维存储器 - Google Patents

半导体器件的制作方法、半导体器件及三维存储器 Download PDF

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WO2023028901A1
WO2023028901A1 PCT/CN2021/115851 CN2021115851W WO2023028901A1 WO 2023028901 A1 WO2023028901 A1 WO 2023028901A1 CN 2021115851 W CN2021115851 W CN 2021115851W WO 2023028901 A1 WO2023028901 A1 WO 2023028901A1
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region
insulating layer
semiconductor device
layer
sidewall
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PCT/CN2021/115851
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English (en)
French (fr)
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张权
姚兰
吴加吉
朱贝贝
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长江存储科技有限责任公司
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Priority to PCT/CN2021/115851 priority Critical patent/WO2023028901A1/zh
Priority to CN202180004315.1A priority patent/CN114175218A/zh
Priority to US17/871,519 priority patent/US20230082694A1/en
Publication of WO2023028901A1 publication Critical patent/WO2023028901A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device, a semiconductor device and a three-dimensional memory.
  • the area of the source and drain regions of transistors (especially low-voltage transistors) in the peripheral structure (CMOS) is small, so that the connection window between the source region and the drain region and the contact structure (CT) (landing window) is smaller.
  • CT contact structure
  • the source region and the drain region are arranged adjacent to the shallow trench isolation structure, if the connection position of the contact structure is slightly deviated from the source region or the drain region, for example, the contact structure is partly located on the source region or the drain region, and partly Located on the shallow trench isolation structure, since the material of the shallow trench isolation structure is oxide, it is easy to cause the collapse of the contact structure and affect the performance of the semiconductor device.
  • the invention provides a manufacturing method of a semiconductor device, a semiconductor device and a three-dimensional memory, which can increase the connection window between a source region and a drain region and improve the performance of the semiconductor device.
  • the invention provides a method for manufacturing a semiconductor device, comprising:
  • a shallow trench isolation trench is formed in a substrate, the substrate includes an active region, the shallow trench isolation trench is located on a peripheral side of the active region, and the active region includes a source region, which is connected in sequence, channel region and drain region;
  • a hard insulating layer is formed on the sidewall of the active region so that the hard insulating layer covers the source region and the drain region.
  • the step of forming a bottom isolation layer in the shallow trench isolation trench includes:
  • the dielectric layer is etched, so that the etched dielectric layer forms the bottom isolation layer.
  • the step of forming a gate structure on the channel region includes:
  • Etching the gate insulating layer and the gate layer so that the etched gate insulating layer and gate layer form the gate structure on the channel region.
  • the method also includes:
  • step of forming a hard insulating layer on the sidewall of the active region further comprising:
  • a sidewall is formed on the sidewall of the shallow trench isolation trench and the sidewall of the gate structure.
  • step of forming a hard insulating layer on the sidewall of the active region further comprising:
  • An ohmic contact layer is formed on the source region, the drain region and the gate structure.
  • the method also includes:
  • a first contact structure and a second contact structure are formed, and the first contact structure is connected to the source region, and the second contact structure is connected to the drain region.
  • the present invention also provides a semiconductor device, comprising:
  • an active region comprising a source region, a channel region and a drain region connected in sequence
  • the gate structure includes a gate insulating layer and a gate layer on the gate insulating layer.
  • the hard insulating layer is also located on the bottom isolation layer, the source region, the drain region and the gate structure.
  • the semiconductor device further includes:
  • An ohmic contact layer located between the source region, the drain region, and the gate structure and the hard insulating layer.
  • the semiconductor device further includes:
  • the semiconductor device further includes:
  • a first contact structure and a second contact structure wherein the first contact structure is connected to the source region, and the second contact structure is connected to the drain region.
  • the gate structure also extends to the bottom isolation layer along the sidewall of the active region.
  • the present invention also provides a three-dimensional memory, including a storage array structure, and a peripheral structure connected to the storage array structure, and the peripheral structure includes a semiconductor device;
  • the semiconductor device includes:
  • an active region comprising a source region, a channel region and a drain region connected in sequence
  • the hard insulating layer is also located on the bottom isolation layer, the source region, the drain region and the gate structure.
  • the semiconductor device further includes:
  • An ohmic contact layer located between the source region, the drain region, and the gate structure and the hard insulating layer.
  • the semiconductor device further includes:
  • the semiconductor device further includes:
  • a first contact structure and a second contact structure wherein the first contact structure is connected to the source region, and the second contact structure is connected to the drain region.
  • the gate structure also extends to the bottom isolation layer along the sidewall of the active region.
  • the beneficial effects of the present invention are as follows: firstly forming a shallow trench isolation trench in the substrate, forming a bottom isolation layer in the shallow trench isolation trench, and then forming a gate structure, so that the gate structure is located between the source region and the substrate in the substrate On the channel region between the drain regions, and then form a hard insulating layer on the sidewall of the active region, so that the hard insulating layer covers the source region and the drain region, and subsequently when forming the contact structure, even if the contact structure Part is located on the source region or drain region, and part is located on the hard insulating layer, which will not cause the collapse of the contact structure, thereby increasing the connection window of the source region and the drain region and improving the performance of the semiconductor device.
  • FIG. 1 is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention
  • FIGS. 2a to 2j are structural schematic diagrams of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a transistor in a semiconductor device provided by an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a three-dimensional memory provided by an embodiment of the present invention.
  • a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means two or more.
  • the term “comprise” and any variations thereof, are intended to cover a non-exclusive inclusion.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations.
  • FIG. 1 it is a schematic flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.
  • this embodiment provides a method for manufacturing a semiconductor device, the method includes steps 101 to 104, specifically as follows:
  • Step 101 forming shallow trench isolation trenches in the substrate, the substrate includes an active region, the shallow trench isolation trenches are located on the peripheral side of the active region, and the active region includes sequentially connected sources pole region, channel region and drain region.
  • the substrate is provided first, and the substrate may be a silicon substrate, a germanium substrate, or a semiconductor substrate including other elements.
  • the substrate can be doped with traces of trivalent elements, such as boron, indium, gallium, aluminum, etc., to form a P-type semiconductor substrate; the substrate can also be doped with traces of pentavalent elements, such as phosphorus, antimony, arsenic, etc.,
  • An N-type semiconductor substrate is formed.
  • An active region may also be formed in the substrate, the active region being adjacent to the upper surface of the substrate.
  • P-type doping or N-type doping is implanted into the active region by ion implantation (Implantation, IMP), and a P-type active region or N-type active region can be formed in the substrate.
  • specific regions in the active region of the substrate can be doped to form source and drain regions in the active region of the substrate, which are close to the substrate
  • the upper surface of the upper surface, and the source region and the drain region are arranged at intervals, and the active region between the source region and the drain region is a channel region, that is, the source region, the channel region and the drain region are connected in sequence.
  • the source region and the drain region can form a P-type doped region or an N-type doped region by implanting P-type doped or N-type doped.
  • the doping type of the source and drain regions is the same.
  • the semiconductor device to be formed is an N-type transistor, N-type doping is implanted in the source region and the drain region; if the semiconductor device to be formed is a P-type transistor, P is injected into the source region and the drain region. type doping.
  • specific regions in the active region of the substrate can also be doped to form a first doped region and a second doped region in the active region of the substrate, the first doped region and the second doped region
  • the second doped region is close to the upper surface of the substrate.
  • the first doped region and the second doped region are arranged at intervals, and the first doped region is located on a side of the source region away from the drain region, and the second doped region is located on a side of the drain region away from the source region.
  • P-type doping or N-type doping can be implanted into the first doping region and the second doping region to form a P-type doping region or an N-type doping region.
  • the doping types of the first doped region and the second doped region are the same.
  • the first doped region and the second doped region are used to lead out the active region, so that an external bias voltage can be applied to the active region, so as to provide different substrate bias voltages for the transistor.
  • the substrate 1 includes an active region 2 , and the active region 2 includes a source region 21 , a channel region 23 and a drain region 22 connected in sequence.
  • Shallow trench isolation trenches 3 are formed around the active region 2 of the substrate 1 , that is, the shallow trench isolation trenches 3 are arranged around the active region 2 .
  • Step 102 forming a bottom isolation layer in the shallow trench isolation trench.
  • the bottom isolation layer can be directly formed on the bottom of the shallow trench isolation trench by spin coating, or can be formed by first filling the dielectric layer in the shallow trench isolation trench and then etching.
  • forming the bottom isolation layer in the shallow trench isolation trench in step 102 includes:
  • the dielectric layer is etched, so that the etched dielectric layer forms the bottom isolation layer.
  • the dielectric layer is filled with the shallow groove isolation trench, and then the dielectric layer is partially etched, so that the remaining dielectric layer after etching forms the bottom isolation layer.
  • a bottom isolation layer 4 is formed in the shallow trench isolation trench 3 .
  • FIG. 2 c which is a schematic cross-sectional view at the dotted line A in FIG. 2 b , the bottom isolation layer 4 is located at the bottom of the shallow trench isolation trench 3 .
  • Step 103 forming a gate structure on the channel region.
  • a gate structure is formed on the channel region between the source region and the drain region to form a transistor with the source region and the drain region in the active region.
  • the active region can be an ultra-low voltage active region, a low voltage active region or a high voltage active region.
  • the transistor corresponding to the ultra-low voltage active region is an ultra-low voltage transistor
  • the transistor corresponding to the low voltage active region is a low voltage transistor
  • the transistor corresponding to the high voltage active region is a high voltage transistor.
  • ultra-low pressure, low pressure and high pressure are relative concepts.
  • the operating voltage of the ultra-low voltage transistor (that is, the voltage applied to the gate layer in the gate structure) is relatively small, such as 0V to 5V, the operating voltage of the high-voltage transistor is relatively large, such as 15V to 25V, and the operating voltage of the low-voltage transistor is between
  • the operating voltage of the ultra-low voltage transistor and the operating voltage of the high voltage transistor are between, for example, 5V to 15V.
  • the high-voltage active area is the largest, the ultra-low-voltage active area is the smallest, and the low-voltage active area is located between the high-voltage active area and the low-voltage active area;
  • the channel depth of the high-voltage transistor is the largest, The channel depth of the ultra-low voltage transistor is the smallest, and the channel depth of the low voltage transistor is between the channel depth of the high voltage transistor and the channel depth of the ultra low voltage transistor.
  • the transistor in this embodiment can be applied to the peripheral structure in the three-dimensional memory, and the peripheral structure can include a page buffer (page buffer) circuit, an IO circuit, a word line driver (WL driver) circuit, and the like.
  • the page buffer circuit may include the above-mentioned high-voltage transistor
  • the IO circuit may include the above-mentioned low-voltage transistor
  • the word line driving circuit may include the above-mentioned ultra-low voltage transistor.
  • the gate structure is located on the channel region and extends along the sidewall of the active region, which can reduce the area of the transistor, thereby reducing the area of the semiconductor device.
  • the forming a gate structure on the channel region in step 103 includes:
  • Etching the gate insulating layer and the gate layer so that the etched gate insulating layer and the gate layer constitute the gate structure located on the channel region.
  • FIG. 2d is a schematic cross-sectional view at the dotted line B in FIG. 2b.
  • a gate insulating layer 51 is formed on the inner surface of the shallow trench isolation trench 3 and the substrate 1 , and the thickness of the gate insulating layer 51 is very thin.
  • a gate layer 52 is formed on the gate insulating layer 51 , and the gate layer 52 fills the shallow trench isolation trench 3 .
  • the gate insulating layer 51 and the gate layer 52 are etched to form the gate structure 5 , and the gate structure 5 includes the etched gate insulating layer 51 and the gate layer 52 .
  • the gate structure 5 is located on the channel region 23 between the source region 21 and the drain region 22 .
  • the gate structure 5 can also extend to the bottom isolation layer 4 along the sidewall of the active region 2 .
  • the sidewall of the active region 2 covered by the gate structure 5 is the sidewall between the source region 21 and the drain region 22 , as shown in FIG. 2b and FIG. 2d .
  • the gate insulating layer 51 is located between the active region 2 and the gate layer 52 for isolating the active region 2 and the gate layer 52 .
  • Step 104 forming a hard insulating layer on the sidewall of the active region, so that the hard insulating layer covers the source region and the drain region.
  • part of the sidewall of the active region is covered by the gate structure, and a hard insulating layer can be formed on the sidewall of the active region not covered by the gate structure, so that the hard insulating layer covers at least the source region and the drain area.
  • the material of the hard insulating layer and the hard mask layer may be the same, for example, the material of the hard insulating layer may be silicon nitride SiN.
  • the contact structure When the contact structure is subsequently formed on the source region and the drain region, the contact structure is partly located on the source region or the drain region, and partly located on the hard insulating layer, which will not cause the contact structure to collapse, thereby increasing the source
  • the connecting window of the electrode region and the drain region improves the performance of the semiconductor device.
  • the step of forming a hard insulating layer on the sidewall of the active region it further includes:
  • a sidewall is formed on the sidewall of the shallow trench isolation trench and the sidewall of the gate structure.
  • a sidewall 6 is formed on the bottom 1 , and then the sidewall 6 is etched, so that the etched sidewall 6 is located on the sidewall of the shallow trench isolation trench 3 and the sidewall of the gate structure 5 .
  • the sidewall 6 can be an ONO (silicon oxide-silicon nitride-silicon oxide) structure (not shown in the figure), that is, the sidewall 6 can include the sidewall of the shallow trench isolation trench 3 and the gate structure 5.
  • the sidewall 6 is used to protect the active region 2 and the gate structure 5 .
  • the step of forming a hard insulating layer on the sidewall of the active region it further includes:
  • An ohmic contact layer is formed on the source region, the drain region and the gate structure.
  • the upper surface of the source region 21, the upper surface of the drain region 22 and the gate structure Ohmic contact layer 7 is formed on the upper surface of 5 .
  • the ohmic contact layer 7 is used to reduce the contact resistance between the source region 21, the drain region 22 and the gate structure 5 and the corresponding contact structure.
  • the ohmic contact layer 7 forms an ohmic contact with the source region 21, the drain region 22, and the gate structure 5, so that the voltage drop at the contact is sufficiently small when a voltage is applied to the source region 21, the drain region 22, and the gate structure 5 , reducing the impact on the electrical performance of the device.
  • the material of the ohmic contact layer 7 may be nickel silicide NiSi.
  • a hard insulating layer 8 may be formed on the sidewall 20 of the active region 2, so that the hard insulating layer 8 covers at least the source region 21 and the drain region 22, as shown in FIG. 2f. Since the source region 21 and the drain region 22 are arranged at intervals in the active region 2, and the source region 21 and the drain region 22 are located at opposite ends of the active region 2, part of the sidewalls of the active region 2 (i.e.
  • the sidewall 20) of the active region 2 is the sidewall of the source region 21 and the drain region 22, and the hard insulating layer 8 covers at least the sidewall 20 of the active region 2, so that the hard insulating layer 8 is in the active region 2
  • the source region 21 and the drain region 22 are covered on the sidewalls.
  • the hard insulating layer 8 is formed on the surface of the sidewalls 6 .
  • the hard insulating layer 8 may only cover the source region 21 and the drain region 22 on the sidewall 20 of the active region 2, and the hard insulating layer 8 may not cover other active regions except the sidewall 20.
  • Region 2 sidewall (the other active region 2 sidewalls include the active region 2 sidewall between the source region 21 and the drain region 22), as shown in Figure 2f and Figure 2g, Figure 2g is the dotted line C in Figure 2f Schematic diagram of the cross section.
  • the hard insulating layer 8 can completely cover the current structure, that is, the hard insulating layer 8 can cover all sidewalls of the active region 2, the upper surface of the bottom isolation layer 4, and the upper surface of the source region 21.
  • FIG. 2i is a schematic cross-sectional view at the dotted line D in FIG. 2h.
  • the hard insulating layer 8 completely covers the current structure, which can prevent the water vapor generated in the subsequent manufacturing process from entering the transistor.
  • the method also includes:
  • a first contact structure and a second contact structure are formed, and the first contact structure is connected to the source region, and the second contact structure is connected to the drain region.
  • a hard insulating layer 8 covers the upper surface of the bottom isolation layer 4, all the sidewalls of the active region 2, the upper surface of the source region 21, After the upper surface of the drain region 22 and the sidewall and upper surface of the gate structure 5 ), an insulating layer 9 is formed on the hard insulating layer 8 , and the insulating layer 9 fills the shallow trench isolation trench 3 . Then, a first contact structure 11 and a second contact structure 12 are formed through the insulating layer 9, the first contact structure 11 is connected to the upper surface of the source region 21, and the second contact structure 12 is connected to the top surface of the drain region 22. connection on the upper surface.
  • the first contact structure 11 and the second contact structure 12 also penetrate through the source region 21 and the upper surface of the drain region 22 respectively.
  • the hard insulating layer 8 on the drain region 22 is shown in FIG. 2j.
  • the ohmic contact layer 7 is formed on the upper surface of the source region 21 and the upper surface of the drain region 22, the first contact structure 11 is connected to the source region 21 through the ohmic contact layer 7, and the second contact structure 12 is connected to the source region 21 through the ohmic contact layer 7.
  • the ohmic contact layer 7 is connected to the drain region 22 .
  • the hard insulating layer 8 is located on the sidewall of the active region 2 and covers the source region 21 and the drain region 22, when the first contact structure 11 is slightly deviated from the source region 21, that is, the first contact structure 11 is partially located at the source region. Part of the pole region 21 is located on the hard insulating layer 8 , which will not cause the first contact structure 11 to collapse, thereby increasing the connection window of the source region 21 .
  • the second contact structure 12 deviates slightly from the drain region 22, that is, the second contact structure 12 is partly located on the drain region 22 and partly located on the hard insulating layer 8, it will not cause the second contact structure 12 to collapse. , thereby increasing the connection window of the drain region 22 .
  • the manufacturing method of the semiconductor device can first form the shallow trench isolation trench in the substrate, form the bottom isolation layer in the shallow trench isolation trench, and then form the gate structure, so that the gate structure is located on the substrate On the channel region between the source region and the drain region, and then form a hard insulating layer on the sidewall of the active region, so that the hard insulating layer covers the source region and the drain region, and subsequently form a contact structure , even if the contact structure is partly located on the source region or the drain region, and partly located on the hard insulating layer, it will not cause the contact structure to collapse, thereby increasing the connection window between the source region and the drain region and improving the semiconductor device. performance.
  • An embodiment of the present invention also provides a semiconductor device.
  • the semiconductor device includes a substrate 1 , a bottom isolation layer 4 , a gate structure 5 and a hard insulating layer 8 .
  • the substrate 1 includes an active region 2 including a source region 21 , a channel region 23 and a drain region 22 connected in sequence. As shown in FIG. 4 , the bottom isolation layer 4 is located around the bottom of the active region 2 , that is, the isolation layer 4 is disposed around the bottom of the active region 2 .
  • the gate structure 5 is located on the channel region 23 between the source region 21 and the drain region 22 . In some embodiments, the gate structure 5 may also extend to the bottom isolation layer 4 along the sidewall of the active region 2 . The sidewall of the active region 2 covered by the gate structure 5 may be the sidewall between the source region 21 and the drain region 22 .
  • the gate structure 5 includes a gate insulating layer 51 and a gate layer 52 on the gate insulating layer 51 , as shown in FIG. 3 .
  • the gate insulating layer 51 is used to isolate the gate layer 52 from the active region 2 .
  • the material of the gate insulating layer 51 may be silicon oxide or the like, and the material of the gate layer 52 may be polysilicon or the like.
  • the source region 21, the drain region 22 and the gate layer 52 in the active region 2 can form a transistor, and the gate layer 52 in the transistor is located on the channel region 23 and extends along the sidewall of the active region 2 , reducing the transistor area.
  • the hard insulating layer 8 may be located on the sidewall of the active region 2 , so that the hard insulating layer 8 at least covers the source region 21 and the drain region 22 .
  • the material of the hard insulating layer 8 and the hard mask layer may be the same, for example, the material of the hard insulating layer may be silicon nitride SiN.
  • the semiconductor device further includes a first contact structure 11 and a second contact structure 22 , the first contact structure 11 is connected to the source region 21 , and the second contact structure 12 is connected to the drain region 22 .
  • the hard insulating layer 8 is located on the sidewall of the active region 2 and covers the source region 21 and the drain region 22, when the first contact structure 11 is slightly deviated from the source region 21, that is, the first contact structure 11 is partially located at the source region. Part of the pole region 21 is located on the hard insulating layer 8 , which will not cause the first contact structure 11 to collapse, thereby increasing the connection window of the source region 21 .
  • the second contact structure 12 deviates slightly from the drain region 22, that is, the second contact structure 12 is partly located on the drain region 22 and partly located on the hard insulating layer 8, it will not cause the second contact structure 12 to collapse. , thereby increasing the connection window of the drain region 22 .
  • the hard insulating layer 8 can cover the source region 21 and the drain region 22 on the sidewall of the active region 2, and can also cover the upper surface of the bottom isolation layer 4, all the sidewalls of the active region 2, and the sides of the source region 21.
  • the upper surface, the upper surface of the drain region 22 , and the sidewall and upper surface of the gate structure 5 are used to prevent water vapor from subsequent manufacturing processes from entering the transistor.
  • the semiconductor device may further include sidewalls 6 located between the sidewalls of the active region 2 and the hard insulating layer 8 , and between the sidewalls of the gate structure 5 and the hard insulating layer 8 .
  • the sidewall 6 is used to protect the active region 2 and the gate structure 5 .
  • the sidewall 6 may be an ONO (silicon oxide-silicon nitride-silicon oxide) structure (not shown in the figure).
  • the semiconductor device may further include an ohmic contact layer 7 located on the upper surface of the source region 21 , the upper surface of the drain region 22 and the upper surface of the gate structure 5 .
  • the ohmic contact layer 7 is located between the upper surface of the source region 21 and the hard insulating layer 8 between the upper surface of the drain region 22 and the hard insulating layer 8 , and between the upper surface of the gate structure 5 and the hard insulating layer 8 .
  • the material of the ohmic contact layer 7 may be nickel silicide NiSi.
  • the ohmic contact layer 7 is used to reduce the contact resistance between the source region 21 , the drain region 22 and the gate structure 5 and the corresponding contact structure.
  • the first contact structure 11 penetrates the hard insulating layer 8 and is connected to the source region 21 through the ohmic contact layer 7, and the second contact structure 12 penetrates the hard insulating layer 8 and is connected to the source region 21 through the ohmic contact layer 8.
  • the contact layer 7 is connected to the drain region 22 .
  • the ohmic contact layer 7 forms an ohmic contact with the source region 21, the drain region 22, and the gate structure 5, so that the voltage drop at the contact is sufficiently small when a voltage is applied to the source region 21, the drain region 22, and the gate structure 5 , reducing the impact on the electrical performance of the device.
  • a shallow trench isolation trench is first formed in the substrate, a bottom isolation layer is formed in the shallow trench isolation trench, and then a gate structure is formed so that the gate structure is located at the source in the substrate region and the channel region between the drain region, and then form a hard insulating layer on the sidewall of the active region, so that the hard insulating layer covers the source region and the drain region, and subsequently when forming the contact structure, even if the contact
  • the dot structure is partly located on the source region or the drain region, and partly located on the hard insulating layer, and will not cause the contact structure to collapse, thereby increasing the connection window between the source region and the drain region and improving the performance of the semiconductor device.
  • FIG. 5 it is a schematic structural diagram of a three-dimensional memory provided by an embodiment of the present invention.
  • the three-dimensional memory includes a memory array structure 100 and a peripheral structure 200 .
  • the storage array structure 100 may be a non-volatile memory array structure, for example, the storage array structure 100 may be a NAND flash memory, a NOR flash memory, or the like.
  • the memory array structure 100 may include a substrate 101 and a stack layer 102 on the substrate 101 , the stack layer 102 includes a plurality of gate layers 103 and interlayer insulating layers 104 stacked vertically and alternately.
  • the longitudinal direction refers to a direction perpendicular to the upper surface of the substrate 101 .
  • the number of stacked layers of the gate layer 103 and the interlayer insulating layer 104 is not limited, for example, 48 layers, 64 layers and so on.
  • the memory array structure 100 may further include a memory channel structure 105 vertically penetrating through the stack layer 102 and extending into the substrate 101 .
  • the storage channel structure 105 may include a longitudinally extending channel layer (not shown in the figure) and a storage medium layer (not shown in the figure) disposed around the periphery of the channel layer.
  • the peripheral structure 200 may include CMOS (Complementary Metal Oxide Semiconductor), SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), Xpoint chip and other devices.
  • CMOS Complementary Metal Oxide Semiconductor
  • SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • FPGA Field Programmable Gate Array
  • CPU Central Processing Unit
  • Xpoint chip and other devices.
  • the peripheral structure 200 may be located on the storage array structure 100 , and the peripheral structure 200 is connected to the storage array structure 100 .
  • the peripheral structure 200 may include the semiconductor devices in the above-mentioned embodiments, which will not be described in detail here.
  • the storage array structure 100 and the peripheral structure 200 can also adopt other architectural forms, for example, the peripheral structure 200 is located below the storage array structure 100, that is, a PUC (periphery under core array) architecture, or the peripheral structure 200 and the storage array structure 100 are arranged side by side. That is, PNC (periphery near core array) architecture, etc., which are not specifically limited here.
  • PUC peripheral under core array
  • PNC peripheral near core array
  • the three-dimensional memory provided by the embodiment of the present invention can first form a shallow trench isolation trench in the substrate, form a bottom isolation layer in the shallow trench isolation trench, and then form a gate structure, so that the gate structure is located at the source of the substrate.
  • On the channel region between the pole region and the drain region and then form a hard insulating layer on the sidewall of the active region, so that the hard insulating layer covers the source region and the drain region, and then when forming the contact structure, even
  • the contact structure is partly located on the source region or the drain region, and partly located on the hard insulating layer, which will not cause the contact structure to collapse, thereby increasing the connection window between the source region and the drain region and improving the performance of the three-dimensional memory.

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Abstract

本发明公开了一种半导体器件的制作方法、半导体器件及三维存储器。所述方法包括：在衬底中形成浅槽隔离沟槽，所述浅槽隔离沟槽位于衬底的有源区的周侧；在所述浅槽隔离沟槽中形成底部隔离层；在衬底的沟道区上形成栅极结构；在有源区的侧壁上形成硬绝缘层，使硬绝缘层覆盖衬底的源极区和漏极区。

Description

半导体器件的制作方法、半导体器件及三维存储器 技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体器件的制作方法、半导体器件及三维存储器。
背景技术
在半导体器件中，外围结构(CMOS)中的晶体管(尤其是低压晶体管)的源极区和漏极区的面积较小，使得源极区和漏极区与触点结构(CT)的连接窗口(landing window)较小。而源极区和漏极区与浅槽隔离结构相邻设置，若触点结构的连接位置稍微偏离源极区或漏极区，例如触点结构部分位于源极区或漏极区上，部分位于浅槽隔离结构上，由于浅槽隔离结构的材料为氧化物，容易导致触点结构塌陷，影响半导体器件的性能。
技术问题
本发明提供一种半导体器件的制作方法、半导体器件及三维存储器，能够增大源极区和漏极区的连接窗口，提高半导体器件的性能。
技术解决方案
本发明提供一种半导体器件的制作方法，包括：
在衬底中形成浅槽隔离沟槽，所述衬底包括有源区，所述浅槽隔离沟槽位于所述有源区的周侧，所述有源区包括依次连接的源极区、沟道区和漏极区；
在所述浅槽隔离沟槽中形成底部隔离层；
在所述沟道区上形成栅极结构；
在所述有源区的侧壁上形成硬绝缘层，使所述硬绝缘层覆盖所述源极区和所述漏极区。
进一步优选地，所述在所述浅槽隔离沟槽中形成底部隔离层的步骤，包括：
在所述浅槽隔离沟槽中填充介质层；
对所述介质层进行刻蚀，使刻蚀后的介质层构成所述底部隔离层。
进一步优选地，所述在所述沟道区上形成栅极结构的步骤，包括：
在所述浅槽隔离沟槽的内表面和所述衬底上形成栅极绝缘层；
在所述栅极绝缘层上形成栅极层；
对所述栅极绝缘层和所述栅极层进行刻蚀，使刻蚀后的栅极绝缘层和栅极层构成位于所述沟道区上的所述栅极结构。
进一步优选地，所述方法还包括：
将所述硬绝缘层延伸至所述底部隔离层、所述源极区、所述漏极区和所述栅极结构上。
进一步优选地，所述在所述有源区的侧壁上形成硬绝缘层的步骤之前，还包括：
在所述浅槽隔离沟槽的侧壁和所述栅极结构的侧壁形成侧墙。
进一步优选地，所述在所述有源区的侧壁上形成硬绝缘层的步骤之前，还包括：
在所述源极区、所述漏极区和所述栅极结构上形成欧姆接触层。
进一步优选地，所述方法还包括：
形成第一触点结构和第二触点结构，且所述第一触点结构连接所 述源极区，所述第二触点结构连接所述漏极区。
本发明还提供一种半导体器件，包括：
有源区，包括依次连接的源极区、沟道区和漏极区；
位于所述有源区周侧的底部隔离层；
栅极结构，所述栅极结构位于所述沟道区上；以及，
位于所述有源区的侧壁上的硬绝缘层，所述硬绝缘层覆盖所述源极区和所述漏极区。
进一步优选地，所述栅极结构包括栅极绝缘层以及位于所述栅极绝缘层上的栅极层。
进一步优选地，所述硬绝缘层还位于所述底部隔离层、所述源极区、所述漏极区和所述栅极结构上。
进一步优选地，所述半导体器件还包括：
位于所述源极区、所述漏极区、及所述栅极结构与所述硬绝缘层之间的欧姆接触层。
进一步优选地，所述半导体器件还包括：
位于所述硬绝缘层与所述有源区的侧壁之间以及所述栅极结构侧壁上的侧墙。
进一步优选地，所述半导体器件还包括：
第一触点结构和第二触点结构，且所述第一触点结构连接所述源极区，所述第二触点结构连接所述漏极区。
进一步优选地，所述栅极结构还沿所述有源区的侧壁延伸至所述底部隔离层上。
本发明还提供一种三维存储器，包括存储阵列结构，以及与所述存储阵列结构连接的外围结构，所述外围结构包括半导体器件；
所述半导体器件包括：
有源区，包括依次连接的源极区、沟道区和漏极区；
位于所述有源区周侧的底部隔离层；
栅极结构，所述栅极结构位于所述沟道区上；以及，
位于所述有源区的侧壁上的硬绝缘层，所述硬绝缘层覆盖所述源极区和所述漏极区。
进一步优选地，所述硬绝缘层还位于所述底部隔离层、所述源极区、所述漏极区和所述栅极结构上。
进一步优选地，所述半导体器件还包括：
位于所述源极区、所述漏极区、及所述栅极结构与所述硬绝缘层之间的欧姆接触层。
进一步优选地，所述半导体器件还包括：
位于所述硬绝缘层与所述有源区的侧壁之间以及所述栅极结构侧壁上的侧墙。
进一步优选地，所述半导体器件还包括：
第一触点结构和第二触点结构，且所述第一触点结构连接所述源极区，所述第二触点结构连接所述漏极区。
进一步优选地，所述栅极结构还沿所述有源区的侧壁延伸至所述底部隔离层上。
有益效果
本发明的有益效果为：先在衬底中形成浅槽隔离沟槽，在浅槽隔离沟槽中形成底部隔离层，然后形成栅极结构，使栅极结构位于衬底中的源极区和漏极区之间的沟道区上，然后在有源区的侧壁上形成硬绝缘层，使硬绝缘层覆盖源极区和漏极区，后续在形成触点结构时，即使触点结构部分位于源极区或漏极区上，部分位于硬绝缘层上，也不会导致触点结构塌陷，从而增大源极区和漏极区的连接窗口，提高半导体器件的性能。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的半导体器件的制作方法的一个流程示意图；
图2a至图2j为本发明实施例提供的半导体器件的制作方法的结构示意图；
图3是本发明实施例提供的半导体器件的结构示意图；
图4是本发明实施例提供的半导体器件中晶体管的结构示意图；
图5是本发明实施例提供的三维存储器的结构示意图。
本发明的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于 描述本发明的示例性实施例的目的。但是本发明可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本发明的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用 的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
参见图1，是本发明实施例提供的半导体器件的制作方法的流程示意图。
如图1所示，本实施例提供一种半导体器件的制作方法，所述方法包括步骤101至步骤104，具体如下：
步骤101、在衬底中形成浅槽隔离沟槽，所述衬底包括有源区，所述浅槽隔离沟槽位于所述有源区的周侧，所述有源区包括依次连接的源极区、沟道区和漏极区。
本发明实施例中，先提供衬底，衬底可以是硅衬底、锗衬底，也可以是包括其他元素的半导体衬底。衬底中可以掺入微量的三价元素，如硼、铟、镓、铝等，构成P型半导体衬底；衬底中也可以掺入微量的五价元素，如磷、锑、砷等，构成N型半导体衬底。衬底中还可以形成有源区，有源区靠近衬底的上表面。通过离子注入(Implantation，IMP)，向有源区中注入P型掺杂或N型掺杂，可以在衬底中形成P型有源区或N型有源区。
然后，通过离子注入，可以对衬底的有源区中的特定区域进行掺杂，以在衬底的有源区中形成源极区和漏极区，源极区和漏极区靠近衬底的上表面，且源极区和漏极区间隔设置，源极区和漏极区之间的有源区为沟道区，即源极区、沟道区和漏极区依次连接。源极区和漏极区通过注入P型掺杂或N型掺杂，可以形成P型掺杂区或N型掺 杂区。源极区和漏极区的掺杂类型相同。若所需形成的半导体器件为N型晶体管，则源极区和漏极区中注入N型掺杂；若所需形成的半导体器件为P型晶体管，则源极区和漏极区中注入P型掺杂。
通过离子注入，还可以对衬底的有源区中的特定区域进行掺杂，以在衬底的有源区中形成第一掺杂区和第二掺杂区，第一掺杂区和第二掺杂区靠近衬底的上表面。第一掺杂区和第二掺杂区间隔设置，且第一掺杂区位于源极区背离漏极区的一侧，第二掺杂区位于漏极区背离源极区的一侧。第一掺杂区与第二掺杂区通过注入P型掺杂或N型掺杂，可以形成P型掺杂区或N型掺杂区。第一掺杂区与第二掺杂区的掺杂类型相同。第一掺杂区和第二掺杂区用于将有源区引出，使外部施加偏置电压到有源区，以给晶体管提供不同的基底偏置电压。
如图2a所示，衬底1中包括有源区2，有源区2包括依次连接的源极区21、沟道区23和漏极区22。在衬底1的有源区2的周侧形成浅槽隔离沟槽3，即浅槽隔离沟槽3环绕有源区2设置。
步骤102、在所述浅槽隔离沟槽中形成底部隔离层。
本发明实施例中，底部隔离层可以通过旋涂的方式直接形成于浅槽隔离沟槽的底部，也可以通过先在浅槽隔离沟槽中填充介质层再刻蚀的方式来形成。
具体地，步骤102中的所述在所述浅槽隔离沟槽中形成底部隔离层，包括：
在所述浅槽隔离沟槽中填充介质层；
对所述介质层进行刻蚀，使刻蚀后的介质层构成所述底部隔离层。
其中，介质层填充满浅槽隔离沟槽，然后对介质层进行部分刻蚀，使刻蚀后剩余的介质层构成底部隔离层。如图2b所示，浅槽隔离沟槽3中形成底部隔离层4。结合图2c所示，图2c为图2b中虚线A处的截面示意图，底部隔离层4位于浅槽隔离沟槽3的底部。
步骤103、在所述沟道区上形成栅极结构。
本发明实施例中，在源极区和漏极区之间的沟道区上形成栅极结构，以与有源区中的源极区和漏极区构成晶体管。有源区可以为超低压有源区、低压有源区或高压有源区。超低压有源区对应的晶体管为超低压晶体管，低压有源区对应的晶体管为低压晶体管，高压有源区对应的晶体管为高压晶体管。其中，超低压、低压和高压为相对概念。超低压晶体管的工作电压(即施加到栅极结构中栅极层上的电压)相对较小，例如0V至5V，高压晶体管的工作电压相对较大，例如15V至25V，低压晶体管的工作电压位于超低压晶体管的工作电压和高压晶体管的工作电压之间，例如5V至15V。在超低压晶体管、低压晶体管和高压晶体管中，高压有源区最大，超低压有源区最小，低压有源区位于高压有源区和低压有源区之间；高压晶体管的沟道深度最大，超低压晶体管的沟道深度最小，低压晶体管的沟道深度位于高压晶体管的沟道深度和超低压晶体管的沟道深度之间。
本实施例中的晶体管可以应用于三维存储器中的外围结构中，外围结构可以包括页缓冲(page buffer)电路、IO电路、字线驱动(WL driver)电路等。其中，页缓冲电路可以包括上述高压晶体管，IO电路可以包括上述低压晶体管，字线驱动电路可以包括上述超低压晶体 管。
在一些实施方式中，栅极结构位于沟道区上且沿有源区的侧壁延伸，可以减小晶体管的面积，从而减小半导体器件的面积。
具体地，步骤103中的所述在所述沟道区上形成栅极结构，包括：
在所述浅槽隔离沟槽的内表面和所述衬底上形成栅极绝缘层；
在所述栅极绝缘层上形成栅极层；
对所述栅极绝缘层和所述栅极层进行刻蚀，使刻蚀后的栅极绝缘层和栅极层构成位于所述沟道区上所述栅极结构。
结合图2b和图2d所示，图2d为图2b中虚线B处的截面示意图。先在浅槽隔离沟槽3的内表面和衬底1上形成栅极绝缘层51，栅极绝缘层51的厚度很薄。然后，在栅极绝缘层51上形成栅极层52，且栅极层52填充浅槽隔离沟槽3中。然后，对栅极绝缘层51和栅极层52进行刻蚀，以形成栅极结构5，栅极结构5包括刻蚀后的栅极绝缘层51和栅极层52。栅极结构5位于源极区21和漏极区22之间的沟道区23上。栅极结构5还可以沿有源区2的侧壁延伸至底部隔离层4。栅极结构5覆盖的有源区2侧壁为源极区21和漏极区22之间的侧壁，结合图2b和图2d所示。其中，栅极绝缘层51位于有源区2与栅极层52之间，用于对有源区2与栅极层52进行隔离。
步骤104、在所述有源区的侧壁上形成硬绝缘层，使所述硬绝缘层覆盖所述源极区和所述漏极区。
本发明实施例中，有源区的部分侧壁被栅极结构覆盖，在有源区的未被栅极结构覆盖的侧壁上可以形成硬绝缘层，使硬绝缘层至少覆 盖源极区和漏极区。其中，硬绝缘层与硬掩膜层的材料可以相同，例如硬绝缘层的材料可以为氮化硅SiN。
后续在源极区和漏极区上形成触点结构时，触点结构部分位于源极区或漏极区上，部分位于硬绝缘层上，也不会导致触点结构塌陷，从而增大源极区和漏极区的连接窗口，提高半导体器件的性能。
进一步地，所述在所述有源区的侧壁上形成硬绝缘层的步骤之前，还包括：
在所述浅槽隔离沟槽的侧壁和所述栅极结构的侧壁形成侧墙。
在图2c的基础上，如图2e所示，先在浅槽隔离沟槽3的内表面(包括侧壁和槽底)、栅极结构5的外表面(包括侧壁和上表面)和衬底1上形成侧墙6，然后对侧墙6进行刻蚀，使刻蚀后的侧墙6位于浅槽隔离沟槽3的侧壁和栅极结构5的侧壁。其中，侧墙6可以为ONO(氧化硅-氮化硅-氧化硅)结构(图中未示出)，即侧墙6可以包括位于浅槽隔离沟槽3的侧壁和栅极结构5的侧壁上的氧化硅层，位于氧化硅层表面的氮化硅层，以及位于氮化硅表面的另一氧化硅层。侧墙6用于对有源区2和栅极结构5进行保护。
进一步地，在所述在所述有源区的侧壁上形成硬绝缘层的步骤之前，还包括：
在所述源极区、所述漏极区和所述栅极结构上形成欧姆接触层。
如图2e所示，在浅槽隔离沟槽3的侧壁和栅极结构5的侧壁形成侧墙6后，在源极区21的上表面、漏极区22的上表面和栅极结构5的上表面形成欧姆接触层7。欧姆接触层7用于减小源极区21、漏 极区22和栅极结构5与对应的触点结构的接触电阻。欧姆接触层7与源极区21、漏极区22、栅极结构5形成欧姆接触，以便在给源极区21、漏极区22、栅极结构5施加电压时接触处的压降足够小，减少了对器件电性能的影响。其中，欧姆接触层7的材料可以为硅化镍NiSi。
在形成欧姆接触层7后，可以在有源区2的侧壁20上形成硬绝缘层8，使硬绝缘层8至少覆盖源极区21和漏极区22，如图2f所示。由于源极区21和漏极区22间隔设置在有源区2中，且源极区21与漏极区22位于有源区2的相对两端，因此有源区2的部分侧壁(即有源区2的侧壁20)为源极区21和漏极区22的侧壁，硬绝缘层8至少覆盖在有源区2的侧壁20上，使硬绝缘层8在有源区2的侧壁上覆盖源极区21和漏极区22。在有源区2的侧壁上具有侧墙6时，硬绝缘层8形成于侧墙6的表面。
在一个实施方式中，硬绝缘层8可以仅在有源区2的侧壁20上覆盖源极区21和漏极区22，硬绝缘层8可以不覆盖除侧壁20之外的其他有源区2侧壁(其他有源区2侧壁包括源极区21和漏极区22之间的有源区2侧壁)，如图2f和图2g所示，图2g为图2f中虚线C处的截面示意图。在另一个实施方式中，硬绝缘层8可以对当前结构进行全部覆盖，即硬绝缘层8可以覆盖有源区2的所有侧壁、底部隔离层4的上表面、源极区21的上表面、漏极区22的上表面、栅极结构5的侧壁和上表面，如图2h和图2i所示，图2i为图2h中虚线D处的截面示意图。硬绝缘层8对当前结构进行全部覆盖，可以防止后 续制作工艺产生水汽进入晶体管。
进一步地，所述方法还包括：
形成第一触点结构和第二触点结构，且所述第一触点结构连接所述源极区，所述第二触点结构连接所述漏极区。
在图2i的基础上，如图2j所示，在形成硬绝缘层8(硬绝缘层8覆盖底部隔离层4的上表面、有源区2所有的侧壁、源极区21的上表面、漏极区22的上表面和栅极结构5的侧壁和上表面)后，在硬绝缘层8上形成绝缘层9，且绝缘层9填充浅槽隔离沟槽3。然后，形成贯穿绝缘层9的第一触点结构11和第二触点结构12，第一触点结构11与源极区21的上表面连接，第二触点结构12与漏极区22的上表面连接。需要说明的是，在硬绝缘层8还覆盖源极区21的上表面和漏极区22的上表面时，第一触点结构11和第二触点结构12还分别贯穿源极区21和漏极区22上的硬绝缘层8，如图2j所示。在源极区21的上表面和漏极区22的上表面还形成有欧姆接触层7时，第一触点结构11通过欧姆接触层7与源极区21连接，第二触点结构12通过欧姆接触层7与漏极区22连接。
由于硬绝缘层8位于有源区2的侧壁且覆盖源极区21和漏极区22，使得第一触点结构11稍微偏离源极区21时，即第一触点结构11部分位于源极区21上，部分位于硬绝缘层8上，也不会导致第一触点结构11塌陷，从而增大源极区21的连接窗口。同样，第二触点结构12稍微偏离漏极区22时，即第二触点结构12部分位于漏极区22上，部分位于硬绝缘层8上，也不会导致第二触点结构12塌陷， 从而增大漏极区22的连接窗口。
本发明实施例提供的半导体器件的制作方法，能够先在衬底中形成浅槽隔离沟槽，在浅槽隔离沟槽中形成底部隔离层，然后形成栅极结构，使栅极结构位于衬底中的源极区和漏极区之间的沟道区上，然后在有源区的侧壁上形成硬绝缘层，使硬绝缘层覆盖源极区和漏极区，后续在形成触点结构时，即使触点结构部分位于源极区或漏极区上，部分位于硬绝缘层上，也不会导致触点结构塌陷，从而增大源极区和漏极区的连接窗口，提高半导体器件的性能。
本发明实施例还提供一种半导体器件，如图3所示，半导体器件包括衬底1、底部隔离层4、栅极结构5和硬绝缘层8。
所述衬底1包括有源区2，所述有源区2包括依次连接的源极区21、沟道区23和漏极区22。结合图4所示，底部隔离层4位于所述有源区2底部周侧，即隔离层4环绕有源区2的底部设置。
所述栅极结构5位于所述源极区21和所述漏极区22之间的沟道区23上。在一些实施方式中，栅极结构5还可以沿所述有源区2的侧壁延伸至所述底部隔离层4上。栅极结构5所覆盖的有源区2的侧壁可以为源极区21和漏极区22之间的侧壁。
具体地，栅极结构5包括栅极绝缘层51以及位于所述栅极绝缘层51上的栅极层52，如图3所示。栅极绝缘层51用于对栅极层52与有源区2进行隔离。栅极绝缘层51的材料可以为氧化硅等，栅极层52的材料可以为多晶硅等。
其中，有源区2中的源极区21和漏极区22、栅极层52可以构 成晶体管，晶体管中的栅极层52位于沟道区23上，且沿有源区2的侧壁延伸，减小晶体管的面积。
如图4所示，硬绝缘层8可以位于有源区2的侧壁上，使硬绝缘层8至少覆盖所述源极区21和所述漏极区22。硬绝缘层8与硬掩膜层的材料可以相同，例如硬绝缘层的材料可以为氮化硅SiN。
如图3所示，半导体器件还包括第一触点结构11和第二触点结构22，第一触点结构11与源极区21连接，第二触点结构12与漏极区22连接。由于硬绝缘层8位于有源区2的侧壁且覆盖源极区21和漏极区22，使得第一触点结构11稍微偏离源极区21时，即第一触点结构11部分位于源极区21上，部分位于硬绝缘层8上，也不会导致第一触点结构11塌陷，从而增大源极区21的连接窗口。同样，第二触点结构12稍微偏离漏极区22时，即第二触点结构12部分位于漏极区22上，部分位于硬绝缘层8上，也不会导致第二触点结构12塌陷，从而增大漏极区22的连接窗口。
硬绝缘层8可以覆盖有源区2的侧壁上的源极区21和漏极区22，也可以覆盖底部隔离层4的上表面、有源区2所有的侧壁、源极区21的上表面、漏极区22的上表面以及栅极结构5的侧壁和上表面，如图2j所示，以防止后续制作工艺产生水汽进入晶体管。
如图2j所示，半导体器件还可以包括侧墙6，侧墙6位于有源区2的侧壁与硬绝缘层8之间，以及栅极结构5的侧壁与硬绝缘层8之间。侧墙6用于对有源区2和栅极结构5进行保护。侧墙6可以为ONO(氧化硅-氮化硅-氧化硅)结构(图中未示出)。
半导体器件还可以包括欧姆接触层7，欧姆接触层7位于源极区21的上表面、漏极区22的上表面和栅极结构5的上表面。在硬绝缘层8延伸至源极区21的上表面、漏极区22的上表面和栅极结构5的上表面时，欧姆接触层7位于源极区21的上表面与硬绝缘层8之间，漏极区22的上表面与硬绝缘层8之间，以及栅极结构5的上表面与硬绝缘层8之间。其中，欧姆接触层7的材料可以为硅化镍NiSi。
欧姆接触层7用于减小源极区21、漏极区22和栅极结构5与对应的触点结构的接触电阻。在半导体器件包括欧姆接触层7时，第一触点结构11贯穿硬绝缘层8，并通过欧姆接触层7与源极区21连接，第二触点结构12贯穿硬绝缘层8，并通过欧姆接触层7与漏极区22连接。
欧姆接触层7与源极区21、漏极区22、栅极结构5形成欧姆接触，以便在给源极区21、漏极区22、栅极结构5施加电压时接触处的压降足够小，减少了对器件电性能的影响。
本发明实施例提供的半导体器件，先在衬底中形成浅槽隔离沟槽，在浅槽隔离沟槽中形成底部隔离层，然后形成栅极结构，使栅极结构位于衬底中的源极区和漏极区之间的沟道区上，然后在有源区的侧壁上形成硬绝缘层，使硬绝缘层覆盖源极区和漏极区，后续在形成触点结构时，即使触点结构部分位于源极区或漏极区上，部分位于硬绝缘层上，也不会导致触点结构塌陷，从而增大源极区和漏极区的连接窗口，提高半导体器件的性能。
参见图5，是本发明实施例提供的三维存储器的结构示意图。
如图5所示，三维存储器包括存储阵列结构100和外围结构200。 其中，存储阵列结构100可以为非易失性存储器阵列结构，例如存储阵列结构100可以为NAND闪存、NOR闪存等。
具体地，存储阵列结构100可以包括衬底101以及位于衬底101上的堆栈层102，堆栈层102包括多个纵向交替堆叠的栅极层103和层间绝缘层104。其中，纵向是指垂直于衬底101上表面的方向。栅极层103和层间绝缘层104的堆叠层数不做限制，例如48层、64层等等。存储阵列结构100还可以包括纵向贯穿堆栈层102并延伸至衬底101内的存储沟道结构105。存储沟道结构105可以包括纵向延伸的沟道层(图中未示出)以及围绕沟道层周侧设置的存储介质层(图中未示出)。
外围结构200可以包含CMOS(互补金属氧化物半导体)、SRAM(静态随机存取存储器)、DRAM(动态随机存取存储器)、FPGA(现场可编程门阵列)、CPU(中央处理器)、Xpoint芯片等器件。
具体地，外围结构200可以位于存储阵列结构100上，且外围结构200与存储阵列结构100相连接。外围结构200可以包括上述实施例中的半导体器件，此处不再详细赘述。
存储阵列结构100与外围结构200也可以采用其他架构形式，例如外围结构200位于存储阵列结构100的下方，即PUC(periphery under core array)架构，或者，外围结构200与存储阵列结构100并列设置，即PNC(periphery near core array)架构等，此处不做具体限定。
本发明实施例提供的三维存储器，能够先在衬底中形成浅槽隔离沟槽，在浅槽隔离沟槽中形成底部隔离层，然后形成栅极结构，使栅极结构位于衬底中的源极区和漏极区之间的沟道区上，然后在有源区 的侧壁上形成硬绝缘层，使硬绝缘层覆盖源极区和漏极区，后续在形成触点结构时，即使触点结构部分位于源极区或漏极区上，部分位于硬绝缘层上，也不会导致触点结构塌陷，从而增大源极区和漏极区的连接窗口，提高三维存储器的性能。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种半导体器件的制作方法，其中，包括：
    在衬底中形成浅槽隔离沟槽，所述衬底包括有源区，所述浅槽隔离沟槽位于所述有源区的周侧，所述有源区包括依次连接的源极区、沟道区和漏极区；
    在所述浅槽隔离沟槽中形成底部隔离层；
    在所述沟道区上形成栅极结构；
    在所述有源区的侧壁上形成硬绝缘层，使所述硬绝缘层覆盖所述源极区和所述漏极区。
  2. 根据权利要求1所述的半导体器件的制作方法，其中，所述在所述浅槽隔离沟槽中形成底部隔离层的步骤，包括：
    在所述浅槽隔离沟槽中填充介质层；
    对所述介质层进行刻蚀，使刻蚀后的介质层构成所述底部隔离层。
  3. 根据权利要求1所述的半导体器件的制作方法，其中，所述在所述沟道区上形成栅极结构的步骤，包括：
    在所述浅槽隔离沟槽的内表面和所述衬底上形成栅极绝缘层；
    在所述栅极绝缘层上形成栅极层；
    对所述栅极绝缘层和所述栅极层进行刻蚀，使刻蚀后的栅极绝缘层和栅极层构成位于所述沟道区上的所述栅极结构。
  4. 根据权利要求1所述的半导体器件的制作方法，其中，所述方法还包括：
    将所述硬绝缘层延伸至所述底部隔离层、所述源极区、所述漏极 区和所述栅极结构上。
  5. 根据权利要求1所述的半导体器件的制作方法，其中，所述在所述有源区的侧壁上形成硬绝缘层的步骤之前，还包括：
    在所述浅槽隔离沟槽的侧壁和所述栅极结构的侧壁形成侧墙。
  6. 根据权利要求1所述的半导体器件的制作方法，其中，所述在所述有源区的侧壁上形成硬绝缘层的步骤之前，还包括：
    在所述源极区、所述漏极区和所述栅极结构上形成欧姆接触层。
  7. 根据权利要求1所述的半导体器件的制作方法，其中，所述方法还包括：
    形成第一触点结构和第二触点结构，且所述第一触点结构连接所述源极区，所述第二触点结构连接所述漏极区。
  8. 一种半导体器件，其中，包括：
    有源区，包括依次连接的源极区、沟道区和漏极区；
    位于所述有源区周侧的底部隔离层；
    栅极结构，所述栅极结构位于所述沟道区上；以及，
    位于所述有源区的侧壁上的硬绝缘层，所述硬绝缘层覆盖所述源极区和所述漏极区。
  9. 根据权利要求8所述的半导体器件，其中，所述栅极结构包括栅极绝缘层以及位于所述栅极绝缘层上的栅极层。
  10. 根据权利要求8所述的半导体器件，其中，所述硬绝缘层还位于所述底部隔离层、所述源极区、所述漏极区和所述栅极结构上。
  11. 根据权利要求10所述的半导体器件，其中，所述半导体器 件还包括：
    位于所述源极区、所述漏极区、及所述栅极结构与所述硬绝缘层之间的欧姆接触层。
  12. 根据权利要求8所述的半导体器件，其中，所述半导体器件还包括：
    位于所述硬绝缘层与所述有源区的侧壁之间以及所述栅极结构侧壁上的侧墙。
  13. 根据权利要求8所述的半导体器件，其中，所述半导体器件还包括：
    第一触点结构和第二触点结构，且所述第一触点结构连接所述源极区，所述第二触点结构连接所述漏极区。
  14. 根据权利要求8所述的半导体器件，其中，所述栅极结构还沿所述有源区的侧壁延伸至所述底部隔离层上。
  15. 一种三维存储器，其中，包括存储阵列结构，以及与所述存储阵列结构连接的外围结构；所述外围结构包括半导体器件；
    所述半导体器件包括：
    有源区，包括依次连接的源极区、沟道区和漏极区；
    位于所述有源区周侧的底部隔离层；
    栅极结构，所述栅极结构位于所述沟道区上；以及，
    位于所述有源区的侧壁上的硬绝缘层，所述硬绝缘层覆盖所述源极区和所述漏极区。
  16. 根据权利要求15所述的三维存储器，其中，所述硬绝缘层 还位于所述底部隔离层、所述源极区、所述漏极区和所述栅极结构上。
  17. 根据权利要求16所述的三维存储器，其中，所述半导体器件还包括：
    位于所述源极区、所述漏极区、及所述栅极结构与所述硬绝缘层之间的欧姆接触层。
  18. 根据权利要求15所述的三维存储器，其中，所述半导体器件还包括：
    位于所述硬绝缘层与所述有源区的侧壁之间以及所述栅极结构侧壁上的侧墙。
  19. 根据权利要求15所述的三维存储器，其中，所述半导体器件还包括：
    第一触点结构和第二触点结构，且所述第一触点结构连接所述源极区，所述第二触点结构连接所述漏极区。
  20. 根据权利要求15所述的三维存储器，其中，所述栅极结构还沿所述有源区的侧壁延伸至所述底部隔离层上。
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