WO2023024428A1 - 柱状电容器阵列结构的制备方法及半导体结构 - Google Patents

柱状电容器阵列结构的制备方法及半导体结构 Download PDF

Info

Publication number
WO2023024428A1
WO2023024428A1 PCT/CN2022/072658 CN2022072658W WO2023024428A1 WO 2023024428 A1 WO2023024428 A1 WO 2023024428A1 CN 2022072658 W CN2022072658 W CN 2022072658W WO 2023024428 A1 WO2023024428 A1 WO 2023024428A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
support layer
mask
mask layer
substrate
Prior art date
Application number
PCT/CN2022/072658
Other languages
English (en)
French (fr)
Inventor
宛强
夏军
占康澍
李森
刘涛
徐朋辉
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/951,122 priority Critical patent/US20230015120A1/en
Publication of WO2023024428A1 publication Critical patent/WO2023024428A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, in particular to a method for preparing a columnar capacitor array structure and a semiconductor structure.
  • DRAM Dynamic random access memory
  • DRAM Dynamic Random Access Memory
  • the capacitor is a vertical cylindrical capacitor with a high aspect ratio.
  • the columnar capacitor Since the columnar capacitor has a high aspect ratio, in order to increase the stability of the columnar capacitor, it is generally necessary to provide a support layer to support the columnar capacitor.
  • the disadvantage of the existing method for manufacturing a columnar capacitor is that the support layer on the top is easily worn out, so that the supporting force of the top support layer is insufficient, which may cause the columnar capacitor to tilt or even peel off, affecting the performance of the columnar capacitor.
  • Some embodiments of the present application provide a method for preparing a columnar capacitor array structure and a semiconductor structure, which can avoid the loss of the top support layer, thereby increasing the thickness and support strength of the top support layer, avoiding the columnar capacitor from tilting, and improving the columnar capacitor.
  • the performance of the array structure thereby improving the yield rate of the memory.
  • the present application provides a method for preparing a columnar capacitor array structure, including:
  • a substrate is provided, and several conductive pads are arranged in the substrate, and a first sacrificial layer, an intermediate support layer, a second sacrificial layer, an initial support layer and a mask layer are stacked on the substrate, and the The substrate is divided into an array area and a peripheral area, the thickness of the mask layer located in the array area is smaller than the thickness of the mask layer located in the peripheral area, and in the array area, several capacitance holes penetrate the mask layer, an initial support layer, a second sacrificial layer, an intermediate support layer and a first sacrificial layer, exposing the conductive pad;
  • part of the mask layer is removed, so that the remaining mask layer in the peripheral area has the same thickness as the mask layer in the array area;
  • a supplementary support layer on the initial support layer, the initial support layer and the supplementary support layer together serve as a top support layer;
  • dielectric layer covering the exposed surfaces of the substrate layer, the lower electrode, the middle support layer, and the top support layer;
  • An upper electrode is formed, and the upper electrode covers the surface of the dielectric layer.
  • the step of filling the capacitor hole with a conductive material and forming the lower electrode of the columnar capacitor further includes: the conductive material also covers the surface of the mask layer in the array area and the peripheral area and etch back the conductive material to expose the mask layer.
  • removing part of the mask layer so that the remaining mask layer in the peripheral region has the same thickness as the mask layer in the array region further includes:
  • a photoresist layer is formed, and the photoresist layer covers the mask layer and the lower electrode;
  • the etching rate of the etching material on the mask layer is greater than that of the lower electrode etch rate.
  • the etching rate of the etching substance for the mask layer is greater than the etching rate of the lower electrode.
  • the mask layer is a polysilicon mask layer
  • the lower electrode is a titanium nitride electrode
  • the step of forming a supplementary support layer on the initial support layer further comprises:
  • the upper surface of the covering material is a flat surface
  • Etching part of the cover material to form the supplementary supporting layer Etching part of the cover material to form the supplementary supporting layer.
  • the material of the initial support layer is the same as that of the supplementary support layer.
  • the thickness of the top support layer is the same as that of the middle support layer.
  • the step of patterning the top support layer and removing the second sacrificial layer further includes:
  • the second sacrificial layer is removed along the first opening, exposing the middle supporting layer.
  • step of patterning the intermediate support layer and removing the first sacrificial layer further comprises:
  • the first sacrificial layer is removed along the second opening to expose the substrate.
  • the first opening corresponds to the second opening.
  • the bottom support layer covers the substrate, and exposes the conductive pads, in the step of patterning the middle support layer, and removing the first sacrificial layer Thereafter, the bottom support layer is exposed.
  • the embodiment of the present application also provides a semiconductor structure, which includes:
  • a substrate a plurality of conductive pads are arranged in the substrate, and the substrate is divided into an array area and a peripheral area;
  • the lower electrode is arranged in the array area and penetrates through the top supporting layer, the second sacrificial layer, the middle supporting layer and the first sacrificial layer, and is electrically connected with the conductive pad.
  • a bottom support layer is further included, the bottom support layer covers the substrate and exposes the conductive pad, and the first sacrificial layer covers the bottom support layer.
  • the preparation method of the columnar capacitor array structure of the present application before removing the mask layer, the thickness of the mask layer in the peripheral area and the mask layer in the array area are adjusted to be the same, thereby avoiding the top support layer caused by the different thickness of the mask layer. Loss.
  • the preparation method of the present application also uses a supplementary support layer to increase the thickness of the top support layer to increase the support strength of the top support layer, thereby further avoiding the occurrence of columnar capacitance tilt due to insufficient support strength of the top support layer.
  • FIGS. 1A to 1D are schematic cross-sectional views of the semiconductor structure corresponding to the main process of forming the lower electrode of the columnar capacitor array structure provided by the first embodiment of the present application;
  • Fig. 2 is a schematic diagram of the steps of the method for manufacturing the columnar capacitor array structure provided by the second embodiment of the present application;
  • 3A to 3L are schematic cross-sectional views of main semiconductor structures formed by the preparation method provided in the second embodiment of the present application.
  • FIGS. 1A to 1D are schematic cross-sectional views of a semiconductor structure corresponding to the main process of forming the lower electrode of the columnar capacitor array structure provided by the first embodiment of the present application.
  • a substrate 100 is provided. Several conductive pads 101 are disposed in the substrate 100 .
  • a first sacrificial layer 110 , a middle support layer 120 , a second sacrificial layer 130 , a top support layer 140 and a mask layer 150 are stacked on the substrate 100 .
  • the substrate 100 is divided into an array area 100A and a peripheral area 100B, and the thickness of the mask layer 150 located in the array area 100A is smaller than that of the mask layer 150 located in the peripheral area 100B.
  • several capacitive holes 160 penetrate the mask layer 150, the top initial support layer 140, the second sacrificial layer 130, the middle support layer 120 and the first sacrificial layer 110, exposing the conductive pad 101 .
  • the mask layer 150 is removed.
  • the thickness of the mask layer 150 in the peripheral region 100B is greater than the thickness of the mask layer 150 in the array region 100A, if the mask layer 150 in the peripheral region 100B is completely removed, the As a result, the top support layer 140 in the array region 100A is lost, and the thickness becomes thinner than that in the peripheral region 100B.
  • the conductive material 170 is filled.
  • the conductive material 170 fills the capacitor hole 160 and covers the surface of the top support layer 140 .
  • the thickness of the conductive material 170 deposited in the peripheral region 100B is greater than the thickness of the conductive material deposited in the array region 100A.
  • the conductive material 170 on the surface of the top support layer 140B is removed, and the lower electrode 180 is formed in the capacitance hole 160 .
  • the thickness of the conductive material 170 deposited in the peripheral region 100B is greater than the thickness of the conductive material deposited in the array region 100A, if the conductive material 170 in the peripheral region 100B is completely removed, the top of the array region 100A will The thickness of the support layer 140 is further thinned, and even the top support layer 140 of the array region 100A will be completely removed, which makes the support strength of the top of the subsequently formed columnar capacitors insufficient, prone to tilting, and affects the performance of the columnar capacitor array structure. Furthermore, the performance of the memory will be affected, and the yield rate of the memory will be reduced.
  • the second embodiment of the present application also provides a method for preparing a columnar capacitor array structure, which can avoid the loss of the top support layer, and then increase the thickness and support strength of the top support layer to avoid its inclination. Improve the performance of the columnar capacitor, thereby improving the yield of the memory.
  • the thickness of the mask layer in the peripheral area and the mask layer in the array area are adjusted to be the same before removing the mask layer, so as to avoid the loss of the top support layer.
  • the preparation method of the present application also uses a supplementary support layer to increase the thickness of the top support layer to increase the support strength of the top support layer, thereby further avoiding the occurrence of columnar capacitance tilt due to insufficient support strength of the top support layer.
  • Fig. 2 is a schematic diagram of the steps of the preparation method of the columnar capacitor array structure provided by the second embodiment of the present application, please refer to Fig. 2, the preparation method includes the following steps: step S20, providing a substrate, and setting a substrate in the substrate Several conductive pads are stacked on the substrate with a first sacrificial layer, an intermediate support layer, a second sacrificial layer, an initial support layer and a mask layer, and the substrate is divided into an array area and a peripheral area, located at The thickness of the mask layer in the array area is smaller than the thickness of the mask layer in the peripheral area.
  • step S21 filling the capacitor hole with a conductive material to form a lower electrode of the columnar capacitor, and the lower electrode is electrically connected to the conductive pad; step S22, removing part of the mask layer in the peripheral area, so that the remaining mask layer in the peripheral area has the same thickness as the mask layer in the array area; step S23, removing the remaining mask layer in the peripheral area and the mask layer in the array area, exposing the initial support layer; Step S24, forming a supplementary support layer on the initial support layer, the initial support layer and the supplementary support layer together serve as a top support layer; Step S25, patterning the top support layer, and removing the second sacrificial layer; Step S26, patterning the middle support layer, and removing the first sacrificial layer; Step S27, forming a dielectric layer, the
  • 3A to 3L are schematic cross-sectional views of main semiconductor structures formed by the preparation method provided by an embodiment of the present application.
  • Step S20 please refer to FIG. 3A , providing a substrate 300 .
  • Several conductive pads 301 are disposed in the substrate 300 .
  • a first sacrificial layer 310 , an intermediate support layer 320 , a second sacrificial layer 330 , an initial support layer 340 and a mask layer 350 are stacked on the substrate 300 .
  • the substrate 300 is divided into an array area 300A and a peripheral area 300B.
  • the thickness of the mask layer 350 located in the array area 300A is smaller than that of the mask layer 350 located in the peripheral area 300B.
  • the substrate 300 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate or a GOI (Germanium-on-Insulator, germanium-on-insulator) substrate, etc.; the substrate The bottom 300 can also be a substrate including other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc., and the substrate 300 can also be a stacked structure, such as a silicon/germanium silicon stack, etc.; In addition, the substrate 300 can be ion-doped, and can be doped with P-type or N-type doped; multiple peripheral devices can also be formed in the substrate 300, such as field Effect transistors, capacitors, inductors and/or pn junction diodes, etc. In this embodiment, the substrate 300 is a silicon substrate, which also includes other device structures, such as bit line structures, transistor structures, etc., but are not shown because they are irrelevant to this
  • the material of the first sacrificial layer 310 and the second sacrificial layer 330 can be oxide, such as silicon oxide, and the material of the intermediate support layer 320 and the initial support layer 340 can be nitrogen compounds such as silicon nitride.
  • the material of the mask layer 350 may be polysilicon.
  • a bottom support layer 370 is further disposed on the substrate 300 .
  • the bottom supporting layer 370 covers the substrate 300 and exposes the conductive pad 301 , and the first sacrificial layer 310 covers the bottom supporting layer 370 .
  • the material of the bottom supporting layer 370 may be nitride, such as silicon nitride.
  • Step S21 please refer to FIG. 3B and FIG. 3C , filling the capacitor hole 360 with a conductive material to form the lower electrode 390 of the columnar capacitor, and the lower electrode 390 is electrically connected to the conductive pad 301 .
  • this step specifically includes the following steps:
  • a conductive material 380 is filled in the capacitor hole 360 , the conductive material 380 not only fills the capacitor hole 360 , but also covers the surface of the mask layer 350 of the array region 300A and the peripheral region 300B.
  • the conductive material can be titanium nitride material or other materials that can be used as the bottom electrode of the columnar capacitor.
  • the conductive material 380 is etched back to expose the mask layer 350 , and the conductive material located in the capacitor hole 360 forms the lower electrode 390 .
  • the conductive material 380 is etched back using a titanium nitride etch-back process to remove the conductive material 380 on the surface of the mask layer 350 and expose the mask layer 350 .
  • Step S22 please refer to FIG. 3D and FIG. 3E , in the peripheral region 300B, part of the mask layer 350 is removed, so that the remaining mask layer 350 in the peripheral region 300B is equal to the thickness of the mask layer 350 in the array region 300A same.
  • This step is to eliminate the height difference between the peripheral region 300B and the mask layer 350 of the array region 300A.
  • the remaining mask layer 350 of the peripheral region 300B has the same thickness as the mask layer 350 of the array region 300A, so that when the mask layer 350 is subsequently removed, there is no Mask layer 350, and the situation that causes loss of initial support layer 340 in array region 300A occurs (as shown in FIG. 1B ), avoiding that the thickness of initial support layer 340 in array region 300A is smaller than the thickness of initial support layer 340 in peripheral region 300B.
  • this step specifically includes the following steps:
  • a photoresist layer 400 is formed, and the photoresist layer 400 covers the mask layer 350 and the lower electrode 390 .
  • the photoresist layer 400 also covers the surface of the mask layer 350 of the peripheral region 300B, and this step also includes removing the surface of the peripheral region 300B. The step of covering the surface of the mask layer 350 with the photoresist layer 400 .
  • the etching rate of the etching substance on the mask layer 350 is greater than that on the lower electrode 390 , so as to prevent the lower electrode 390 from being etched.
  • at least one of HBr and NF 3 is used as an etching gas to perform dry etching on the mask layer 350, and the etching rate of the HBr and NF 3 etching gas to the mask layer 350 is greater than The etching rate of the bottom electrode 390.
  • the photoresist layer 400 is removed by ashing or other processes to expose the mask layer 350 .
  • step S23 please refer to FIG. 3F , removing the remaining mask layer 350 of the peripheral region 300B and the mask layer 350 of the array region 300A to expose the initial support layer 340 .
  • the mask layer 350 is removed by a dry etching process.
  • the etching rate of the etching substance on the mask layer 350 is greater than that on the lower electrode 380 , so as to prevent the lower electrode 380 from being etched.
  • the mask layer 350 is a polysilicon mask layer
  • the lower electrode 390 is a titanium nitride electrode, so at least one of HBr and NF 3 can be used as an etching gas for dry etching
  • the mask layer 350 is removed to remove the mask layer 350 .
  • the etching rate of HBr and NF 3 for etching gas on polysilicon is greater than that on titanium nitride.
  • the initial support layer 340 will also be thinned due to the influence of the actual process.
  • the thickness of the initial support layer 340 in the peripheral region 300B and the array region 300A is the same, so that after this step, the thickness of the remaining initial support layer 340 in the peripheral region 300B and the array region 300A is also the same.
  • Step S24 please refer to FIG. 3G and FIG. 3H , forming a supplementary support layer 420 on the initial support layer 340 , and the initial support layer 340 and the supplementary support layer 420 together serve as a top support layer 430 .
  • the supplementary support layer 420 is formed by depositing on the surface of the initial support layer 340 .
  • this step specifically includes the following steps:
  • a covering material 410 is formed on the initial support layer 340 , and the upper surface of the covering material 410 is a flat surface.
  • the deposited covering material 410 is thick enough so that the upper surface of the covering material 410 is a flat surface, that is, the upper surface of the covering material located in the peripheral region 300B and the covering material located in the array region 300A are separated.
  • the upper surfaces are at the same horizontal position, so as to further eliminate the thickness difference of the supplementary support layer 420 formed in the peripheral region 300B and the array region 300A.
  • a portion of the covering material 410 is etched to form the supplementary supporting layer 420 .
  • the covering material 410 may be etched by a dry etching process, so that the covering material 410 is thinned to a predetermined thickness, and the supplementary supporting layer 420 is formed.
  • the supplementary supporting layer 420 also covers the top of the lower electrode 390 to prevent the lower electrode 390 from being etched in the subsequent step of patterning the intermediate supporting layer.
  • the initial support layer 340 is made of the same material as the supplementary support layer 420 .
  • both are silicon nitride layers.
  • the thickness of the top support layer 430 formed by the initial support layer 340 and the supplementary support layer 420 is the same as that of the middle support layer 320 .
  • Step S25 please refer to FIG. 3I , pattern the top supporting layer 430 and remove the second sacrificial layer 330 .
  • the top support layer 430 is patterned to form a first opening 431 ; the second sacrificial layer 330 is removed along the first opening 431 to expose the middle support layer 320 .
  • the process of patterning the top supporting layer 430 may be a photolithography and dry etching process, and the method of removing the second sacrificial layer 330 may be a wet etching process.
  • Step S26 referring to FIG. 3J , patterning the intermediate support layer 320 and removing the first sacrificial layer 310 .
  • the intermediate support layer 320 is patterned to form the second opening 321 .
  • the position of the second opening 321 corresponds to that of the first opening 431 .
  • the first sacrificial layer 310 is removed along the second opening 321 to expose the substrate 300 .
  • the process of patterning the intermediate support layer 320 may be a photolithography and dry etching process, and the method of removing the first sacrificial layer 310 may be a wet etching process.
  • the supplementary support layer 420 is also thinned, the supplementary support layer 420 located on top of the lower electrode 390 is removed, and the top of the lower electrode 390 is exposed.
  • the bottom support layer 370 is exposed.
  • Step S27 please refer to FIG. 3K , forming a dielectric layer 440 covering exposed surfaces of the substrate layer 300 , the lower electrode 390 , the middle support layer 320 , and the top support layer 430 .
  • the dielectric layer 440 may be a high-K dielectric layer to improve the performance of the columnar capacitor.
  • Al 2 O 3 , HfO 2 , Ta 2 O 5 , ZrO 2 which can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or metal organic chemical vapor deposition (MOCVD).
  • Step S28 please refer to FIG. 3L , forming an upper electrode 450 covering the surface of the dielectric layer 440 .
  • the upper electrode 450 fills the gap among the bottom support layer 370 , the middle support layer 320 and the top support layer 430 , and covers the top support layer 430 .
  • the upper electrode 450, the dielectric layer 440 and the lower electrode 390 form a columnar capacitor.
  • a plurality of columnar capacitor arrays are arranged to form a columnar capacitor array structure.
  • the preparation method of the columnar capacitor array structure of the present application before removing the mask layer, the thickness of the mask layer in the peripheral region and the mask layer in the array region are adjusted to be the same, thereby avoiding The thickness of the top support layer has an effect.
  • the preparation method of the present application also forms a supplementary support layer and increases the thickness of the top support layer to increase the support strength of the top support layer, thereby further avoiding the tilting of the columnar capacitor due to insufficient support force of the top support layer.
  • the present application also provides a semiconductor structure.
  • the semiconductor structure includes a substrate 300 in which several conductive pads 301 are disposed, and the substrate 300 is divided into an array area 300A and a peripheral area 300B.
  • the substrate 300 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate or a GOI (Germanium-on-Insulator, germanium-on-insulator) substrate, etc.; the substrate The bottom 300 can also be a substrate including other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc., and the substrate 300 can also be a stacked structure, such as a silicon/germanium silicon stack, etc.; In addition, the substrate 300 can be ion-doped, and can be doped with P-type or N-type doped; multiple peripheral devices can also be formed in the substrate 300, such as field Effect transistors, capacitors, inductors and/or pn junction diodes, etc. In this embodiment, the substrate 300 is a silicon substrate, which also includes other device structures, such as bit line structures, transistor structures, etc., but are not shown because they are irrelevant to this
  • the first sacrificial layer 310 , the middle support layer 320 , the second sacrificial layer 330 and the top support layer 430 are stacked on the substrate 300 .
  • the surface of the top support layer 430 located in the array area 300A is flush with the surface of the top support layer 430 located in the peripheral area 300B.
  • the material of the first sacrificial layer 310 and the second sacrificial layer 330 may be oxide, such as silicon oxide, and the material of the intermediate support layer 320 may be nitride, such as silicon nitride.
  • the thickness of the top support layer 430 is the same as that of the middle support layer 320 .
  • the top support layer 430 includes the initial support layer 340 and covers the initial support layer 340 and the supplementary support layer 420 .
  • the initial support layer 340 and the supplementary support layer 420 are made of the same material, which is silicon nitride.
  • a bottom support layer 370 is further disposed on the substrate 300 .
  • the bottom supporting layer 370 covers the substrate 300 and exposes the conductive pad 301 , and the first sacrificial layer 310 covers the bottom supporting layer 370 .
  • the material of the bottom supporting layer 370 may be nitride, such as silicon nitride.
  • the lower electrode 390 is disposed in the array area 300A, penetrates through the top supporting layer 430 , the second sacrificial layer 330 , the middle supporting layer 320 and the first sacrificial layer 310 , and is electrically connected to the conductive pad 301 .
  • the bottom electrode 390 may be a titanium nitride electrode.
  • the top of the lower electrode 390 may be flush with the surface of the top supporting layer 430 , or the top supporting layer 430 covers the top of the lower electrode 390 .
  • the top support layer 430 covers the top of the bottom electrode 390 .
  • the top support layer is composed of an initial support layer and a supplementary support layer, and the surface of the top support layer located in the array area is flush with the surface of the top support layer located in the peripheral area, which greatly increases the The thickness and support strength of the top support layer avoids the columnar capacitor formed based on the semiconductor structure from inclining, and improves the performance of the subsequently formed memory.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

本申请提供一种柱状电容器阵列结构的制备方法及半导体结构，属于半导体制造技术领域，本申请柱状电容器阵列结构的制备方法在去除掩膜层之前先将外围区域的掩膜层与阵列区域的掩膜层的厚度调整为相同，从而避免由于掩膜层厚度不同而导致的顶部支撑层的损失。另外，本申请制备方法还利用补充支撑层增加顶部支撑层的厚度，以增大顶部支撑层的支撑力度，从而进一步避免由于顶部支撑层支撑力度不够而导致柱状电容倾斜的情况发生。

Description

柱状电容器阵列结构的制备方法及半导体结构
相关申请引用说明
本申请要求于2021年08月24日递交的中国专利申请号202110973561.X、申请名为“柱状电容器阵列结构的制备方法及半导体结构”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种柱状电容器阵列结构的制备方法及半导体结构。
背景技术
动态随机存储器(Dynamic Random Access Memory，简称：DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。在20nm以下的DRAM制程中，DRAM大多采用堆栈式的电容构造，其电容器(Capacitor)是垂直的高深宽比的圆柱体形状的柱状电容器。
由于所述柱状电容器具有高深宽比，为了增加所述柱状电容器的稳定性，通常需要提供支撑层，以支撑所述柱状电容器。现有的柱状电容器的制造方法的缺点在于，顶部的支撑层易被损耗，使得顶部的支撑层支撑力不足，可能会导致柱状电容的倾斜、甚至剥离，影响柱状电容器的性能。
因此，提供一种柱状电容器阵列结构的制备方法，以解决现有技术中顶部的支撑层易损耗等问题实属必要。
发明内容
本申请的一些实施例中提供一种柱状电容器阵列结构的制备方法及半导体结构，其能够避免顶部支撑层的损失，进而增加顶部支撑层的厚度及支撑力度，避免柱状电容器发生倾斜，提高柱状电容器阵列结构的性能，进而提高存储器的良率。
根据本申请的一些实施例，本申请一方面提供了一种柱状电容器阵列结构的制备方法，包括：
提供衬底，在所述衬底内设置有若干个导电垫，在所述衬底上堆叠设置有第一牺牲层、中间支撑层、第二牺牲层、初始支撑层及掩膜层，所述衬底被划分为阵列区域及外围区域，位于所述阵列区域的掩膜层的厚度小于位于所述外围区域的掩膜层的厚度，在所述阵列区域，若干个电容孔贯穿所述掩膜层、初始支撑层、第二牺牲层、中间支撑层及第一牺牲层，暴露出所述导电垫；
在所述电容孔内填充导电材料，形成所述柱状电容器的下电极，所述下电极与所述导电垫电连接；
在所述外围区域，去除部分掩膜层，使得所述外围区域剩余的掩膜层与所述阵列区域的掩膜层的厚度相同；
去除所述外围区域剩余的掩膜层及所述阵列区域的掩膜层，暴露出所述初始支撑层；
在所述初始支撑层上形成补充支撑层，所述初始支撑层与所述补充支撑层共同作为顶部支撑层；
图案化所述顶部支撑层，并去除所述第二牺牲层；
图案化所述中间支撑层，并去除所述第一牺牲层；
形成介质层，所述介质层覆盖所述衬底层、所述下电极、所述中间支撑层、所述顶部支撑层暴露的表面；
形成上电极，所述上电极覆盖所述介质层表面。
在一些实施例中，在所述电容孔内填充导电材料，形成所述柱状电容器的下电极的步骤还包括：所述导电材料还覆盖所述阵列区域及所述外围区域的掩膜层的表面，对所述导电材料进行回刻蚀，暴露出所述掩膜层。
在一些实施例中，在所述外围区域，去除部分掩膜层，使得所述外围区域剩余的掩膜层与所述阵列区域的掩膜层的厚度相同的步骤还包括：
在所述阵列区域，形成光阻层，所述光阻层覆盖所述掩膜层及所述下电极；
以所述光阻层为掩膜，刻蚀所述外围区域的掩膜层，以去除所述外围区域的部分掩膜层；
去除所述光阻层。
在一些实施例中，以所述光阻层为掩膜，刻蚀所述外围区域的掩膜层的步骤中，刻蚀物质对所述掩膜层的刻蚀速率大于对所述下电极的刻蚀速率。
在一些实施例中，去除所述外围区域剩余的掩膜层及所述阵列区域的掩膜层，暴露出所述初始支撑层的步骤中，刻蚀物质对所述掩膜层的刻蚀速率大于对所述下电极的刻蚀速率。
在一些实施例中，进一步所述掩膜层为多晶硅掩膜层，所述下电极为氮化钛电极。
在一些实施例中，在所述初始支撑层上形成补充支撑层的步骤进一步包括：
在所述初始支撑层上形成覆盖材料，所述覆盖材料上表面为平坦表面；
刻蚀部分所述覆盖材料，形成所述补充支撑层。
在一些实施例中，进一步所述初始支撑层与所述补充支撑层材料相同。
在一些实施例中，进一步所述顶部支撑层的厚度与所述中间支撑层的厚度相同。
在一些实施例中，图案化所述顶部支撑层，并去除所述第二牺牲层的步骤还包括：
图案化所述顶部支撑层，形成第一开口；
沿所述第一开口去除所述第二牺牲层，暴露出所述中间支撑层。
11.根据权利要求10所述的柱状电容器阵列结构的制备方法，其中，图案化所述中间支撑层，并去除所述第一牺牲层的步骤还包括：
图案化所述中间支撑层，形成第二开口；
沿所述第二开口去除所述第一牺牲层，暴露出所述衬底。
在一些实施例中，进一步所述第一开口与所述第二开口位置对应。
在一些实施例中，还包括底部支撑层，所述底部支撑层覆盖所述衬底，且暴露出所述导电垫，在图案化所述中间支撑层，并去除所述第一牺牲层的步骤之后，所述底部支撑层被暴露。
本申请实施例另一方面还提供一种半导体结构，其包括：
衬底，在所述衬底内设置有若干个导电垫，所述衬底被划分为阵列区域及外围区域；
在所述衬底上堆叠设置的第一牺牲层、中间支撑层、第二牺牲层及顶部支撑层，位于所述阵列区域的顶部支撑层的表面与位于所述外围区域的顶部支撑层的表面平齐，所述顶部支撑层包括初始支撑层及覆盖所述初始支撑层的补充支撑层；
下电极，设置在所述阵列区域，且贯穿所述顶部支撑层、第二牺牲层、中间支撑层及第一牺牲层，并与所述导电垫电连接。
在一些实施例中，还包括底部支撑层，所述底部支撑层覆盖所述衬底，且暴露出所述导电垫，所述第一牺牲层覆盖所述底部支撑层。
本申请柱状电容器阵列结构的制备方法在去除掩膜层之前先将外围区域的掩膜层与阵列区域的掩膜层的厚度调整为相同，从而避免由于掩膜层厚度不同而导致的顶部支撑层的损失。另外，本申请制备方法还利用补充支撑层增加顶部支撑层的厚度，以增大顶部支撑层的支撑力度，从而进一步避免由于顶部支撑层支撑力度不够而导致柱状电容倾斜的情况发生。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A～图1D是本申请第一实施例提供的形成柱状电容器阵列结构下电极的主要工艺对应的半导体结构的截面示意图；
图2是本申请第二实施例提供的柱状电容器阵列结构的制备方法的步骤示意图；
图3A～图3L是本申请第二实施例提供的制备方法形成的主要的半导体结构截面示意图。
具体实施方式
为了使本申请的目的、技术手段及其效果更加清楚明确，以下将结合附图对本申请作进一步地阐述。应当理解，此处所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例，并不用于限定本申请。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图1A～图1D是本申请第一实施例提供的形成柱状电容器阵列结构下电极的主要工艺对应的半导体结构的截面示意图。
请参阅图1A，提供衬底100。在所述衬底100内设置有若干个导电垫101。在所述衬底100上堆叠设置有第一牺牲层110、中间支撑层120、第二牺牲层130、顶部支撑层140及掩膜层150。所述衬底100被划分为阵列区域100A及外围区域100B，位于所述阵列区域100A的掩膜层150的厚度小于位于所述 外围区域100B的掩膜层150的厚度。在所述阵列区域100A，若干个电容孔160贯穿所述掩膜层150、顶部始支撑层140、第二牺牲层130、中间支撑层120及第一牺牲层110，暴露出所述导电垫101。
请参阅图1B，去除所述掩膜层150。在该步骤中，由于位于所述外围区域100B的掩膜层150的厚度大于位于所述阵列区域100A的掩膜层150的厚度，若完全去除所述外围区域100B所述掩膜层150，会导致阵列区域100A的顶部支撑层140损失，厚度相较于外围区域100B变薄。
请参阅图1C，填充导电材料170。所述导电材料170填充所述电容孔160并覆盖所述顶部支撑层140表面。在该步骤中，外围区域100B沉积的导电材料170的厚度大于所述阵列区域100A沉积的导电材料的厚度。
请参阅图1D，去除所述顶部支撑层140B表面的导电材料170，在所述电容孔160内形成下电极180。在该步骤中，由于外围区域100B沉积的导电材料170的厚度大于所述阵列区域100A沉积的导电材料的厚度，若完全去除所述外围区域100B的导电材料，会导致所述阵列区域100A的顶部支撑层140的厚度被进一步减薄，甚至所述阵列区域100A的顶部支撑层140会被完全去除，这使得后续形成的柱状电容器顶部支撑力度不够，易发生倾斜，影响柱状电容器阵列结构的性能，进而会影响存储器的性能，降低存储器的良率。
为了解决上述技术问题，本申请第二实施例还提供了一种柱状电容器阵列结构的制备方法，其能够避免顶部支撑层的损失，进而增加顶部支撑层的厚度及支撑力度，避免其发生倾斜，提高柱状电容器的性能，进而提高存储器的良率。具体地说，本申请柱状电容器阵列结构的制备方法在去除掩膜层之前先将外围区域的掩膜层与阵列区域的掩膜层的厚度调整为相同，从而避免由于掩膜层厚度不同而导致的顶部支撑层的损失。另外，本申请制备方法还利用补充支撑层增加顶部支撑层的厚度，以增大顶部支撑层的支撑力度，从而进一步避免由于顶部支撑层支撑力度不够而导致柱状电容倾斜的情况发生。
图2是本申请第二实施例提供的柱状电容器阵列结构的制备方法的步骤示意图，请参阅图2，所述制备方法包括如下步骤：步骤S20，提供衬底，在所述衬底内设置有若干个导电垫，在所述衬底上堆叠设置有第一牺牲层、中间支撑层、第二牺牲层、初始支撑层及掩膜层，所述衬底被划分为阵列区域及外围区域，位于所述阵列区域的掩膜层的厚度小于位于所述外围区域的掩膜层的厚度，在所述阵列区域，若干个电容孔贯穿所述掩膜层、初始支撑层、第二牺牲层、中间支撑层及第一牺牲层，暴露出所述导电垫；步骤S21，在所述电容孔内填充导电材料，形成所述柱状电容器的下电极，所述下电极与所述导电垫电连接；步骤S22，在所述外围区域，去除部分掩膜层，使得所述外围区域剩余的掩膜层与所述阵列区域的掩膜层的厚度相同；步骤S23，去除所述外围区域剩余的掩膜层及所述阵列区域的掩膜层，暴露出所述初始支撑层；步骤S24，在所述初始支撑层上形成补充支撑层，所述初始支撑层与所述补充支撑层共同作为顶部支撑层；步骤S25，图案化所述顶部支撑层，并去除所述第二牺牲层；步骤S26，图案化所述中间支撑层，并去除所述第一牺牲层；步骤S27，形成介质层，所述介质层覆盖所述衬底层、所 述下电极、所述中间支撑层、所述顶部支撑层暴露的表面；步骤S28，形成上电极，所述上电极覆盖所述介质层表面。
图3A～图3L是本申请一实施例提供的制备方法形成的主要的半导体结构截面示意图。
步骤S20，请参阅图3A，提供衬底300。在所述衬底300内设置有若干个导电垫301。在所述衬底300上堆叠设置有第一牺牲层310、中间支撑层320、第二牺牲层330、初始支撑层340及掩膜层350。所述衬底300被划分为阵列区域300A及外围区域300B，位于所述阵列区域300A的掩膜层350的厚度小于位于所述外围区域300B的掩膜层350的厚度。在所述阵列区域300A，若干个电容孔360贯穿所述掩膜层350、初始支撑层340、第二牺牲层330、中间支撑层320及第一牺牲层310，暴露出所述导电垫301。
所述衬底300可以包括硅衬底、锗(Ge)衬底、锗化硅(SiGe)衬底、SOI衬底或GOI(Germanium-on-Insulator，绝缘体上锗)衬底等；所述衬底300还可以为包括其他元素半导体或化合物半导体的衬底，例如砷化镓、磷化铟或碳化硅等，所述衬底300还可以为叠层结构，例如硅/锗硅叠层等；另外，所述衬底300可以为进行离子掺杂后的衬底，可以进行P型掺杂，也可以进行N型掺杂；所述衬底300中还可以形成有多个外围器件，如场效应晶体管、电容、电感和/或pn结二极管等。本实施例中，所述衬底300为硅衬底，其内部还包括其他器件结构，例如位线结构，晶体管结构等，但由于与本申请无关，所以不绘示。
在本实施例中，所述第一牺牲层310及所述第二牺牲层330的材料可为氧化物，例如氧化硅，所述中间支撑层320及所述初始支撑层340的材料可为氮化物，例如氮化硅。所述掩膜层350的材料可为多晶硅。
在本实施例中，在所述衬底300上还设置有底部支撑层370。所述底部支撑层370覆盖所述衬底300，且暴露出所述导电垫301，所述第一牺牲层310覆盖所述底部支撑层370。所述底部支撑层370的材料可以为氮化物，例如氮化硅。
步骤S21，请参阅图3B及图3C，在所述电容孔360内填充导电材料，形成所述柱状电容器的下电极390，所述下电极390与所述导电垫301电连接。
在该步骤中，在所述电容孔360内形成下电极390。在本实施例中，该步骤具体包括如下步骤：
请参阅图3B，在所述电容孔360内填充导电材料380，所述导电材料380不仅填充所述电容孔360，还覆盖所述阵列区域300A及所述外围区域300B的掩膜层350的表面。所述导电材料可为氮化钛材料或者其他能够作为柱状电容器下电极的材料。
请参阅图3C，对所述导电材料380进行回刻蚀，暴露出所述掩膜层350，位于所述电容孔360内的导电材料形成所述下电极390。在本实施例中，在该步骤中，采用氮化钛回刻工艺对导电材料380进行回刻蚀，去除所述掩膜层350表面的导电材料380，暴露出所述掩膜层350。
步骤S22，请参阅图3D及图3E，在所述外围区域300B，去除部分掩膜层350，使得所述外围区域300B剩余的掩膜层350与所述阵列区域300A的掩膜层350的厚度相同。
该步骤的目的在于，消除外围区域300B与阵列区域300A的掩膜层350的高度差。所述外围区域300B剩余的掩膜层350与所述阵列区域300A的掩膜层350的厚度相同，使得在后续去除所述掩膜层350时，不存在为了完全去除所述外围区域300B所述掩膜层350，而导致阵列区域300A的初始支撑层340损失的情况发生(如图1B所示)，避免阵列区域300A的初始支撑层340的厚度小于外围区域300B的初始支撑层340的厚度。
在该步骤中，减薄所述外围区域300B的掩膜层350的厚度。在本实施例中，该步骤具体包括如下步骤：
请参阅图3D，在所述阵列区域300A，形成光阻层400，所述光阻层400覆盖所述掩膜层350及所述下电极390。在本申请一些实施例中，受限于实际工艺，所述光阻层400还覆盖所述外围区域300B的掩膜层350的表面，则在该步骤中还包括，去除所述外围区域300B的掩膜层350表面覆盖的光阻层400的步骤。
以所述光阻层400为掩膜，刻蚀所述外围区域300B的掩膜层350，以去除所述外围区域300B的部分掩膜层，使得所述外围区域300B剩余的掩膜层350与所述阵列区域300A的掩膜层350的厚度相同。在该步骤中，刻蚀物质对所述掩膜层350的刻蚀速率大于对所述下电极390的刻蚀速率，以避免所述下电极390被刻蚀。例如，采用HBr与NF 3中的至少一种作为刻蚀气体对所述掩膜层350进行干法刻蚀，所述HBr与NF 3刻蚀气体对所述掩膜层350的刻蚀速率大于对所述下电极390的刻蚀速率。
请参阅图3E，在刻蚀完成后，采用灰化等工艺去除所述光阻层400，暴露出所述掩膜层350。
步骤S23，请参阅图3F，去除所述外围区域300B剩余的掩膜层350及所述阵列区域300A的掩膜层350，暴露出所述初始支撑层340。
在该步骤中，采用干法刻蚀工艺去除所述掩膜层350。其中，刻蚀物质对所述掩膜层350的刻蚀速率大于对所述下电极380的刻蚀速率，以避免所述下电极380被刻蚀。在本实施例中，所述掩膜层350为多晶硅掩膜层，所述下电极390为氮化钛电极，则可采用HBr与NF 3中的至少一种作为刻蚀气体，干法刻蚀所述掩膜层350，以去除所述掩膜层350。HBr与NF 3对刻蚀气体对多晶硅的刻蚀速率大于对氮化钛的刻蚀速率。
在该步骤中，受限于实际工艺的影响，所述初始支撑层340也会被减薄，但是，由于所述外围区域300B剩余的掩膜层350与所述阵列区域300A的掩膜层350的厚度相同，则外围区域300B与阵列区域300A的所述初始支撑层340减薄程度相同，使得在该步骤之后，外围区域300B与阵列区域300A剩余的初始支撑层340的厚度也相同。
步骤S24，请参阅图3G与图3H，在所述初始支撑层340上形成补充支撑层420，所述初始支撑层 340与所述补充支撑层420共同作为顶部支撑层430。
在该步骤中，在所述初始支撑层340表面沉积形成所述补充支撑层420。在本实施例中，该步骤具体包括如下步骤：
请参阅图3G，在所述初始支撑层340上形成覆盖材料410，所述覆盖材料410上表面为平坦表面。在该步骤中，沉积的覆盖材料410足够厚，以使得所述覆盖材料410上表面为平坦表面，即位于所述外围区域300B的覆盖材料的上表面与位于所述阵列区域300A的覆盖材料的上表面在同一水平位置，从而进一步消除外围区域300B与阵列区域300A形成的补充支撑层420的厚度差。
请参阅图3H，刻蚀部分所述覆盖材料410，形成所述补充支撑层420。在该步骤中，可采用干法刻蚀工艺刻蚀所述覆盖材料410，使得所述覆盖材料410减薄至预设厚度，形成所述补充支撑层420。
在本实施例中，所述补充支撑层420还覆盖所述下电极390的顶部，以在后续图案化所述中间支撑层的步骤中，避免所述下电极390被刻蚀。
在一些实施例中，所述初始支撑层340与所述补充支撑层420的材料相同。例如，两者均为氮化硅层。在一些实施例中，所述初始支撑层340与所述补充支撑层420构成的顶部支撑层430的厚度与所述中间支撑层320的厚度相同。
步骤S25，请参阅图3I，图案化所述顶部支撑层430，并去除所述第二牺牲层330。
具体地说，在该步骤中，图案化所述顶部支撑层430，形成第一开口431；沿所述第一开口431去除所述第二牺牲层330，暴露出所述中间支撑层320。其中，图案化所述顶部支撑层430的工艺可为光刻及干法刻蚀工艺，去除所述第二牺牲层330的方法可为湿法刻蚀工艺。
步骤S26，请参阅图3J，图案化所述中间支撑层320，并去除所述第一牺牲层310。
具体地说，在该步骤中，图案化所述中间支撑层320，形成第二开口321。其中，所述第二开口321与所述第一开口431位置对应。沿所述第二开口321去除所述第一牺牲层310，暴露出所述衬底300。图案化所述中间支撑层320的工艺可为光刻及干法刻蚀工艺，去除所述第一牺牲层310的方法可为湿法刻蚀工艺。
在图案化所述中间支撑层320的步骤中，所述补充支撑层420也被减薄，位于所述下电极390顶部的补充支撑层420被去除，所述下电极390顶部被暴露。在本实施例中，除所述第一牺牲层310后，所述底部支撑层370被暴露。
步骤S27，请参阅图3K，形成介质层440，所述介质层440覆盖所述衬底层300、所述下电极390、所述中间支撑层320、所述顶部支撑层430暴露的表面。
其中，所述介质层440可为高K介质层，以提高柱状电容器的性能。例如，Al 2O 3,HfO 2,Ta 2O 5,ZrO 2，其可利用化学气相沉积(CVD)工艺、原子层沉积(ALD)工艺或金属有机物化学气相淀积(MOCVD)工艺等形成。
步骤S28，请参阅图3L，形成上电极450，所述上电极450覆盖所述介质层440表面。在本具体实施方式中，所述上电极450填充所述底部支撑层370、中间支撑层320及顶部支撑层430之间的空隙，并覆盖所述顶部支撑层430。所上电极450、介质层440及所述下电极390构成柱状电容器。多个所述柱状电容器阵列排布构成柱状电容器阵列结构。
本申请柱状电容器阵列结构的制备方法在去除掩膜层之前先将所述外围区域的掩膜层与所述阵列区域的掩膜层的厚度调整为相同，从而避免由于掩膜层厚度不同而对顶部支撑层的厚度产生影响。另外，本申请制备方法还形成补充支撑层，增加顶部支撑层的厚度，以增大顶部支撑层的支撑力度，从而进一步避免由于顶部支撑层支撑力度不够而导致柱状电容倾斜的情况发生。
本申请还提供一种半导体结构。请参阅图3H，所述半导体结构包括衬底300，在所述衬底300内设置有若干个导电垫301，所述衬底300被划分为阵列区域300A及外围区域300B。
所述衬底300可以包括硅衬底、锗(Ge)衬底、锗化硅(SiGe)衬底、SOI衬底或GOI(Germanium-on-Insulator，绝缘体上锗)衬底等；所述衬底300还可以为包括其他元素半导体或化合物半导体的衬底，例如砷化镓、磷化铟或碳化硅等，所述衬底300还可以为叠层结构，例如硅/锗硅叠层等；另外，所述衬底300可以为进行离子掺杂后的衬底，可以进行P型掺杂，也可以进行N型掺杂；所述衬底300中还可以形成有多个外围器件，如场效应晶体管、电容、电感和/或pn结二极管等。本实施例中，所述衬底300为硅衬底，其内部还包括其他器件结构，例如位线结构，晶体管结构等，但由于与本申请无关，所以不绘示。
在所述衬底300上堆叠设置的第一牺牲层310、中间支撑层320、第二牺牲层330及顶部支撑层430。位于所述阵列区域300A的顶部支撑层430的表面与位于所述外围区域300B的顶部支撑层430的表面平齐。
在本实施例中，所述第一牺牲层310及所述第二牺牲层330的材料可为氧化物，例如氧化硅，所述中间支撑层320的材料可为氮化物，例如氮化硅。
在一些实施例中，所述顶部支撑层430的厚度与所述中间支撑层320的厚度相同。
所述顶部支撑层430包括初始支撑层340及覆盖所述初始支撑层340与补充支撑层420。在一些实施例中，所述初始支撑层340与补充支撑层420的材料相同，均为氮化硅。
在本实施例中，在所述衬底300上还设置有底部支撑层370。所述底部支撑层370覆盖所述衬底300，且暴露出所述导电垫301，所述第一牺牲层310覆盖所述底部支撑层370。所述底部支撑层370的材料可以为氮化物，例如氮化硅。
下电极390设置在所述阵列区域300A，且贯穿所述顶部支撑层430、第二牺牲层330、中间支撑层320及第一牺牲层310，并与所述导电垫301电连接。所述下电极390可为氮化钛电极。所述下电极390的顶部可与所述顶部支撑层430的表面平齐，或者所述顶部支撑层430覆盖所述下电极390的顶部。例 如，在本实施例中，所述顶部支撑层430覆盖所述下电极390的顶部。
本申请半导体结构中，顶部支撑层有初始支撑层与补充支撑层构成，且位于所述阵列区域的顶部支撑层的表面与位于所述外围区域的顶部支撑层的表面平齐，大大增加了所述顶部支撑层的厚度及支撑力度，避免了以所述半导体结构为基础而形成的柱状电容器发生倾斜，提高后续形成的存储器的性能。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (15)

  1. 一种柱状电容器阵列结构的制备方法，包括：
    提供衬底，在所述衬底内设置有若干个导电垫，在所述衬底上堆叠设置有第一牺牲层、中间支撑层、第二牺牲层、初始支撑层及掩膜层，所述衬底被划分为阵列区域及外围区域，位于所述阵列区域的掩膜层的厚度小于位于所述外围区域的掩膜层的厚度，在所述阵列区域，若干个电容孔贯穿所述掩膜层、初始支撑层、第二牺牲层、中间支撑层及第一牺牲层，暴露出所述导电垫；
    在所述电容孔内填充导电材料，形成所述柱状电容器的下电极，所述下电极与所述导电垫电连接；
    在所述外围区域，去除部分掩膜层，使得所述外围区域剩余的掩膜层与所述阵列区域的掩膜层的厚度相同；
    去除所述外围区域剩余的掩膜层及所述阵列区域的掩膜层，暴露出所述初始支撑层；
    在所述初始支撑层上形成补充支撑层，所述初始支撑层与所述补充支撑层共同作为顶部支撑层；
    图案化所述顶部支撑层，并去除所述第二牺牲层；
    图案化所述中间支撑层，并去除所述第一牺牲层；
    形成介质层，所述介质层覆盖所述衬底层、所述下电极、所述中间支撑层、所述顶部支撑层暴露的表面；
    形成上电极，所述上电极覆盖所述介质层表面。
  2. 根据权利要求1所述的柱状电容器阵列结构的制备方法，其中，在所述电容孔内填充导电材料，形成所述柱状电容器的下电极的步骤还包括：所述导电材料还覆盖所述阵列区域及所述外围区域的掩膜层的表面，对所述导电材料进行回刻蚀，暴露出所述掩膜层。
  3. 根据权利要求1所述的柱状电容器阵列结构的制备方法，其中，在所述外围区域，去除部分掩膜层，使得所述外围区域剩余的掩膜层与所述阵列区域的掩膜层的厚度相同的步骤还包括：
    在所述阵列区域，形成光阻层，所述光阻层覆盖所述掩膜层及所述下电极；
    以所述光阻层为掩膜，刻蚀所述外围区域的掩膜层，以去除所述外围区域的部分掩膜层；
    去除所述光阻层。
  4. 根据权利要求3所述的柱状电容器阵列结构的制备方法，其中，以所述光阻层为掩膜，刻蚀所述外围区域的掩膜层的步骤中，刻蚀物质对所述掩膜层的刻蚀速率大于对所述下电极的刻蚀速率。
  5. 根据权利要求1所述的柱状电容器阵列结构的制备方法，其中，去除所述外围区域剩余的掩膜层及所述阵列区域的掩膜层，暴露出所述初始支撑层的步骤中，刻蚀物质对所述掩膜层的刻蚀速率大于对所述下电极的刻蚀速率。
  6. 根据权利要求5所述的柱状电容器阵列结构的制备方法，进一步所述掩膜层为多晶硅掩膜层，所述下电极为氮化钛电极。
  7. 根据权利要求1所述的柱状电容器阵列结构的制备方法，在所述初始支撑层上形成补充支撑层的步 骤进一步包括：
    在所述初始支撑层上形成覆盖材料，所述覆盖材料上表面为平坦表面；
    刻蚀部分所述覆盖材料，形成所述补充支撑层。
  8. 根据权利要求7所述的柱状电容器阵列结构的制备方法，进一步所述初始支撑层与所述补充支撑层材料相同。
  9. 根据权利要求1所述的柱状电容器阵列结构的制备方法，进一步所述顶部支撑层的厚度与所述中间支撑层的厚度相同。
  10. 根据权利要求1所述的柱状电容器阵列结构的制备方法，其中，图案化所述顶部支撑层，并去除所述第二牺牲层的步骤还包括：
    图案化所述顶部支撑层，形成第一开口；
    沿所述第一开口去除所述第二牺牲层，暴露出所述中间支撑层。
  11. 根据权利要求10所述的柱状电容器阵列结构的制备方法，其中，图案化所述中间支撑层，并去除所述第一牺牲层的步骤还包括：
    图案化所述中间支撑层，形成第二开口；
    沿所述第二开口去除所述第一牺牲层，暴露出所述衬底。
  12. 根据权利要求11所述的柱状电容器阵列结构的制备方法，进一步所述第一开口与所述第二开口位置对应。
  13. 根据权利要求1所述的柱状电容器阵列结构的制备方法，还包括底部支撑层，所述底部支撑层覆盖所述衬底，且暴露出所述导电垫，在图案化所述中间支撑层，并去除所述第一牺牲层的步骤之后，所述底部支撑层被暴露。
  14. 一种半导体结构，包括：
    衬底，在所述衬底内设置有若干个导电垫，所述衬底被划分为阵列区域及外围区域；
    在所述衬底上堆叠设置的第一牺牲层、中间支撑层、第二牺牲层及顶部支撑层，位于所述阵列区域的顶部支撑层的表面与位于所述外围区域的顶部支撑层的表面平齐，所述顶部支撑层包括初始支撑层及覆盖所述初始支撑层的补充支撑层；
    下电极，设置在所述阵列区域，且贯穿所述顶部支撑层、第二牺牲层、中间支撑层及第一牺牲层，并与所述导电垫电连接。
  15. 根据权利要求14所述的半导体结构，还包括底部支撑层，所述底部支撑层覆盖所述衬底，且暴露出所述导电垫，所述第一牺牲层覆盖所述底部支撑层。
PCT/CN2022/072658 2021-08-24 2022-01-19 柱状电容器阵列结构的制备方法及半导体结构 WO2023024428A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/951,122 US20230015120A1 (en) 2021-08-24 2022-09-23 Method for fabricating array structure of columnar capacitor and semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110973561.XA CN113707614B (zh) 2021-08-24 2021-08-24 柱状电容器阵列结构的制备方法及半导体结构
CN202110973561.X 2021-08-24

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/951,122 Continuation US20230015120A1 (en) 2021-08-24 2022-09-23 Method for fabricating array structure of columnar capacitor and semiconductor structure

Publications (1)

Publication Number Publication Date
WO2023024428A1 true WO2023024428A1 (zh) 2023-03-02

Family

ID=78654359

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/072658 WO2023024428A1 (zh) 2021-08-24 2022-01-19 柱状电容器阵列结构的制备方法及半导体结构

Country Status (2)

Country Link
CN (1) CN113707614B (zh)
WO (1) WO2023024428A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113707614B (zh) * 2021-08-24 2024-03-29 长鑫存储技术有限公司 柱状电容器阵列结构的制备方法及半导体结构
CN116206969A (zh) * 2021-11-30 2023-06-02 长鑫存储技术有限公司 半导体结构制作方法及半导体结构
CN117320438A (zh) * 2022-06-21 2023-12-29 长鑫存储技术有限公司 半导体结构及其制作方法、存储器
CN117500365B (zh) * 2023-12-29 2024-05-10 长鑫新桥存储技术有限公司 电容器的制备方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140134839A1 (en) * 2012-11-13 2014-05-15 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices with electrode support patterns
US20170345886A1 (en) * 2016-05-27 2017-11-30 Samsung Electronics Co., Ltd. Semiconductor device
CN110010604A (zh) * 2017-12-22 2019-07-12 三星电子株式会社 半导体器件及其制造方法
CN111725139A (zh) * 2019-03-21 2020-09-29 三星电子株式会社 制造具有支撑图案的半导体装置的方法
CN112908968A (zh) * 2019-12-03 2021-06-04 长鑫存储技术有限公司 半导体存储器中的电容及其制备方法
CN112951768A (zh) * 2021-03-17 2021-06-11 长鑫存储技术有限公司 电容阵列及其制造方法和存储器
CN113497187A (zh) * 2020-03-20 2021-10-12 爱思开海力士有限公司 半导体器件及其制造方法
CN113707614A (zh) * 2021-08-24 2021-11-26 长鑫存储技术有限公司 柱状电容器阵列结构的制备方法及半导体结构

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100395767B1 (ko) * 2001-09-13 2003-08-21 삼성전자주식회사 강유전성 메모리 장치 및 그 형성 방법
TWI389260B (zh) * 2009-09-30 2013-03-11 Inotera Memories Inc 半導體記憶體之電容下電極的製備方法
CN109411413B (zh) * 2017-08-16 2020-11-27 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
CN110504284B (zh) * 2018-05-17 2024-06-21 长鑫存储技术有限公司 柱状电容器阵列结构及制备方法
CN110504283A (zh) * 2018-05-17 2019-11-26 长鑫存储技术有限公司 柱状电容器阵列结构及制备方法
CN109148426B (zh) * 2018-09-29 2024-03-29 长鑫存储技术有限公司 电容结构及其形成方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140134839A1 (en) * 2012-11-13 2014-05-15 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices with electrode support patterns
US20170345886A1 (en) * 2016-05-27 2017-11-30 Samsung Electronics Co., Ltd. Semiconductor device
CN110010604A (zh) * 2017-12-22 2019-07-12 三星电子株式会社 半导体器件及其制造方法
CN111725139A (zh) * 2019-03-21 2020-09-29 三星电子株式会社 制造具有支撑图案的半导体装置的方法
CN112908968A (zh) * 2019-12-03 2021-06-04 长鑫存储技术有限公司 半导体存储器中的电容及其制备方法
CN113497187A (zh) * 2020-03-20 2021-10-12 爱思开海力士有限公司 半导体器件及其制造方法
CN112951768A (zh) * 2021-03-17 2021-06-11 长鑫存储技术有限公司 电容阵列及其制造方法和存储器
CN113707614A (zh) * 2021-08-24 2021-11-26 长鑫存储技术有限公司 柱状电容器阵列结构的制备方法及半导体结构

Also Published As

Publication number Publication date
CN113707614B (zh) 2024-03-29
CN113707614A (zh) 2021-11-26

Similar Documents

Publication Publication Date Title
WO2023024428A1 (zh) 柱状电容器阵列结构的制备方法及半导体结构
US7585741B2 (en) Methods of forming capacitors
US8120103B2 (en) Semiconductor device with vertical gate and method for fabricating the same
WO2023024429A1 (zh) 柱状电容器阵列结构制备方法及半导体结构
US8188529B2 (en) Semiconductor device and method for manufacturing the same
US9236427B2 (en) Multi-material structures and capacitor-containing semiconductor constructions
US11011525B2 (en) Landing pad structure and method of manufacturing the same
US9305927B2 (en) Semiconductor device and method of manufacturing the same
WO2023151356A1 (zh) 电容器及其制备方法
KR102462439B1 (ko) 반도체 소자의 제조 방법
US10930654B2 (en) Semiconductor devices
US20010019866A1 (en) Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole
WO2022062495A1 (zh) 电容结构及其形成方法
GB2336942A (en) Method for fabricating a DRAM cell capacitor
US20230223429A1 (en) Semiconductor structure and manufacturing method thereof
US11923449B2 (en) Manufacturing method for semiconductor device
US20230015120A1 (en) Method for fabricating array structure of columnar capacitor and semiconductor structure
WO2022236980A1 (zh) 存储器的制作方法
US11289493B2 (en) Patterning method
CN114361111A (zh) 半导体结构及其制备方法
US9230967B2 (en) Method for forming self-aligned isolation trenches in semiconductor substrate and semiconductor device
JPH10256505A (ja) Ｄｒａｍの製造方法
WO2023159967A1 (zh) 半导体结构及其形成方法、动态随机存储器的制造方法
WO2024041040A1 (zh) 半导体器件及其制备方法
US11778804B2 (en) Capacitor array structure and fabrication method thereof

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE