WO2022062495A1 - 电容结构及其形成方法 - Google Patents

电容结构及其形成方法 Download PDF

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Publication number
WO2022062495A1
WO2022062495A1 PCT/CN2021/100740 CN2021100740W WO2022062495A1 WO 2022062495 A1 WO2022062495 A1 WO 2022062495A1 CN 2021100740 W CN2021100740 W CN 2021100740W WO 2022062495 A1 WO2022062495 A1 WO 2022062495A1
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Prior art keywords
capacitor structure
hole
layer
central
electrode layer
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PCT/CN2021/100740
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English (en)
French (fr)
Inventor
吴秉桓
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长鑫存储技术有限公司
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Priority to US17/579,851 priority Critical patent/US20220149148A1/en
Publication of WO2022062495A1 publication Critical patent/WO2022062495A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/35—Feed-through capacitors or anti-noise capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a capacitor structure and a method for forming the same.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line
  • the data information stored in the capacitor is read, or the data information is written into the capacitor through the bit line for storage.
  • the aspect ratio of the capacitor hole formed in the dielectric layer is also continuously improved. It is always a great challenge for the etching process to challenge the capacitor hole with a high aspect ratio.
  • etching a capacitor hole with a wide ratio there is usually a problem of offset of the capacitor hole, so that the capacitor formed in the capacitor hole cannot be normally connected to the target metal layer, and the capacitance value of the existing capacitor still needs to be improved.
  • the embodiments of the present application propose a capacitor structure and a method for forming the same.
  • the present application provides a method for forming a capacitor structure, including:
  • annular spacer on the base, the annular spacer having a central through hole exposing the surface of the base part;
  • a second capacitor structure connected to the first capacitor structure is formed in the etching hole.
  • the material of the annular spacer is different from the material of the dielectric layer, and when the dielectric layer is etched to form an etching hole communicating with the central through hole, the etching rate of the dielectric layer is higher than that of the dielectric layer.
  • the etch rate of the annular spacer is higher than that of the dielectric layer.
  • a target layer is formed in the substrate, the substrate exposes the surface of the target layer, the annular spacer is formed on the surface of the target layer, and the central through hole exposes part of the surface of the target layer .
  • the forming process of the annular spacer includes: forming a masking material layer on the surface of the substrate and the partial surface of the target layer, and forming a through hole exposing the partial surface of the target layer in the masking material layer ; Form a spacer material layer on the sidewall and bottom surface of the through hole and the surface of the mask material layer; remove the spacer material on the surface of the mask material layer and the bottom surface of the through hole by maskless etching layer, an annular gasket is formed on the sidewall surface of the through hole, and the annular gasket has a central through hole in the middle; after the first capacitor structure is formed, the mask material layer is removed.
  • the top surface of the first capacitor structure is lower than the bottom surface of the annular spacer.
  • the first capacitor structure includes a first electrode layer located on the sidewall and bottom surface of the central through hole, a first dielectric layer located on the first electrode layer, and a second dielectric layer located on the first dielectric layer. electrode layer.
  • the second capacitor structure includes a third electrode layer located on the sidewall and bottom of the etched hole, a second dielectric layer located on the third electrode layer, and a fourth electrode layer located on the second dielectric layer.
  • the third electrode layer is electrically connected with the first electrode layer.
  • an isolation layer is formed on the surface of the second electrode layer.
  • the second capacitor structure includes a third electrode layer located on the sidewall and bottom of the etched hole, a second dielectric layer located on the third electrode layer, and a fourth electrode layer located on the second dielectric layer.
  • the third electrode layer is electrically connected to the second electrode layer.
  • an isolation spacer is formed on the surface of the first electrode layer and the sidewall surface of the central through hole
  • the inner diameter of the annular spacer is greater than or equal to the diameter of the etching hole.
  • one of the etching holes is communicated with a corresponding one of the central through holes, a first capacitor structure is formed in one of the central through holes, a second capacitor structure is formed in one of the etching holes, or a
  • the etching hole is communicated with a plurality of corresponding central through holes, a first capacitor structure is formed in each of the central through holes, a second capacitor structure is formed in one of the etching holes, or a plurality of all the corresponding through holes are formed.
  • the etching hole is communicated with a corresponding one of the central through holes, a first capacitor structure is formed in one of the central through holes, and a second capacitor structure is formed in each of the etching holes.
  • the application also provides a capacitor structure, including:
  • annular spacer located on the base, the annular spacer having a central through hole exposing the surface of the base part in the middle;
  • a second capacitor structure located in the etched hole and connected to the first capacitor structure.
  • the material of the annular spacer is different from the material of the dielectric layer, and when the dielectric layer is etched to form an etching hole communicating with the central through hole, the etching rate of the dielectric layer is higher than that of the dielectric layer.
  • the etch rate of the annular spacer is higher than that of the dielectric layer.
  • the substrate has a target layer therein, the substrate exposes the surface of the target layer, the annular spacer is located on the surface of the target layer, and the central through hole exposes part of the surface of the target layer.
  • the top surface of the first capacitor structure is lower than the bottom surface of the annular spacer.
  • the first capacitor structure includes a first electrode layer located on the sidewall and bottom surface of the central through hole, a first dielectric layer located on the first electrode layer, and a second dielectric layer located on the first dielectric layer. electrode layer.
  • the second capacitor structure includes a third electrode layer located on the sidewall and bottom of the etched hole, a second dielectric layer located on the third electrode layer, and a fourth electrode layer located on the second dielectric layer.
  • the third electrode layer is electrically connected with the first electrode layer.
  • the isolation layer on the surface of the second electrode layer.
  • the second capacitor structure includes a third electrode layer located on the sidewall and bottom of the etched hole, a second dielectric layer located on the third electrode layer, and a fourth electrode layer located on the second dielectric layer.
  • the third electrode layer is electrically connected to the second electrode layer.
  • the method further includes: isolation sidewalls located on the surface of the first electrode layer and the sidewall surface of the central through hole.
  • the inner diameter of the annular spacer is greater than or equal to the diameter of the etching hole.
  • one of the etching holes is communicated with a corresponding one of the central through holes, a first capacitor structure is formed in one of the central through holes, a second capacitor structure is formed in one of the etching holes, or a
  • the etching hole is communicated with a plurality of corresponding central through holes, a first capacitor structure is formed in each of the central through holes, a second capacitor structure is formed in one of the etching holes, or a plurality of all the corresponding through holes are formed.
  • the etching hole is communicated with a corresponding one of the central through holes, a first capacitor structure is formed in one of the central through holes, and a second capacitor structure is formed in each of the etching holes.
  • an annular spacer is formed on a substrate, and after the annular spacer has a central through hole exposing the surface of a part of the substrate, a first capacitor structure is formed in the center through hole; a substrate, an annular gasket and a dielectric layer of the first capacitor structure; etching the dielectric layer, forming an etching hole in the dielectric layer that communicates with the central through hole; forming a connection with the first capacitor structure in the etching hole connected second capacitive structure.
  • the annular spacer when the etching hole is formed in the dielectric layer, when the etching hole is bent or the position is shifted, the annular spacer can prevent the lateral etching of the bottom of the etching hole, so that the The bottom is guided into the central through hole between the annular spacers, so that the bottom of the etched hole is corrected to the correct position, so that the formed capacitor hole (including the connected central through hole and the etched hole) can normally expose the target layer Therefore, the capacitor structure formed in the capacitor hole can be connected to the target layer normally.
  • the existence of the annular spacer can prevent anomalies such as leakage caused by metal diffusion caused by the formation of the first capacitor structure in the central through hole.
  • a first capacitor structure can also be formed in the central through hole in the middle of the annular spacer, and an etching hole in the dielectric layer can form a second capacitor structure connected to the first capacitor structure, and the central through hole and the etching hole constitute a Capacitance hole, the first capacitance structure and the second capacitance structure can be connected in parallel to form a capacitor, so that the capacitance value of the capacitor formed in the capacitance hole increases, because the capacitor is formed in two steps (the first capacitance structure is formed first, and then the second capacitance is formed structure), making it less difficult to form capacitors in capacitor holes with high aspect ratio (it is more difficult to form high-quality electrode layers and dielectric layers in capacitor holes with high aspect ratio).
  • the forming process of the annular spacer includes: forming a masking material layer on the surface of the substrate and part of the target layer, wherein the masking material layer is formed with capacitor holes exposing the surface of the part of the target layer; The sidewall and bottom surface of the capacitor hole and the surface of the mask material layer form a gasket material layer; the surface of the mask material layer and the gasket material layer on the bottom surface of the capacitor hole are removed by maskless etching, An annular spacer is formed on the sidewall surface of the capacitor hole.
  • the size and shape of the annular spacer formed in this way are more precise and have a higher sidewall topography.
  • the top surface of the first capacitor structure is lower than the bottom surface of the annular spacer, so that when etching holes are subsequently formed in the dielectric layer, the annular spacer still has a better effect on the etching process of the etching holes. guiding role.
  • the annular spacer when an etching hole is formed in the dielectric layer through an annular spacer, when the etching hole is bent or the position is shifted, the annular spacer can prevent lateral etching at the bottom of the etching hole, The bottom of the etched hole is guided into the central through hole between the annular spacers, so that the bottom of the etched hole is corrected to the correct position, so that the formed capacitor hole (including the connected central through hole and the etched hole) can be The surface of the target layer is normally exposed, so the capacitor structure formed in the capacitor hole can be normally connected to the target layer.
  • the existence of the annular spacer can prevent anomalies such as leakage caused by metal diffusion caused by the formation of the first capacitor structure in the central through hole.
  • a first capacitor structure can also be formed in the central through hole in the middle of the annular spacer, and an etching hole in the dielectric layer can form a second capacitor structure connected to the first capacitor structure, and the central through hole and the etching hole constitute a Capacitance hole, the first capacitance structure and the second capacitance structure can be connected in parallel to form a capacitor, so that the capacitance value of the capacitor formed in the capacitance hole increases, because the capacitor is formed in two steps (the first capacitance structure is formed first, and then the second capacitance is formed structure), making it less difficult to form capacitors in capacitor holes with high aspect ratio (it is more difficult to form high-quality electrode layers and dielectric layers in capacitor holes with high aspect ratio).
  • 1 is a schematic structural diagram of a conventionally formed capacitor hole
  • FIGS. 2 to 11 are schematic cross-sectional structural diagrams of a process of forming a capacitor structure according to an embodiment of the present application.
  • the etched capacitor hole 104 is easily bent, so that the bottom of the etched capacitor hole deviates from the normal position, so that the surface of the target metal layer cannot be exposed normally. Or, due to the deviation of the over-etching process, the formed etched capacitor hole deviates from the normal position, so that the capacitor formed in the capacitor hole cannot be normally connected to the target metal layer.
  • the present application provides a capacitor structure and a method for forming the same.
  • an annular gasket is formed on a substrate.
  • forming a first capacitor structure in the hole forming a dielectric layer covering the substrate, the annular spacer and the first capacitor structure; etching the dielectric layer, and forming an etching hole in the dielectric layer that communicates with the central through hole;
  • a second capacitor structure connected to the first capacitor structure is formed in the etching hole.
  • the annular spacer when the etching hole is formed in the dielectric layer, when the etching hole is bent or the position is shifted, the annular spacer can prevent the lateral etching of the bottom of the etching hole, so that the The bottom is guided into the central through hole between the annular spacers, so that the bottom of the etched hole is corrected to the correct position, so that the formed capacitor hole (including the connected central through hole and the etched hole) can normally expose the target layer Therefore, the capacitor structure formed in the capacitor hole can be normally electrically connected to the target layer.
  • the existence of the annular spacer can prevent anomalies such as leakage caused by metal diffusion caused by the formation of the first capacitor structure in the central through hole.
  • a first capacitor structure can also be formed in the central through hole in the middle of the annular spacer, and an etching hole in the dielectric layer can form a second capacitor structure connected to the first capacitor structure, and the central through hole and the etching hole constitute a Capacitance hole, the first capacitance structure and the second capacitance structure can be connected in parallel to form a capacitor, so that the capacitance value of the capacitor formed in the capacitance hole increases, because the capacitor is formed in two steps (the first capacitance structure is formed first, and then the second capacitance is formed structure), making it less difficult to form capacitors in capacitor holes with high aspect ratio (it is more difficult to form high-quality electrode layers and dielectric layers in capacitor holes with high aspect ratio).
  • a substrate 201 having a target layer 202 formed therein is provided, and the substrate 201 exposes a surface of the target layer 202 .
  • the substrate 201 may be a semiconductor substrate
  • the target layer 202 may be a doped region (such as a doped region doped with N-type impurity ions or doped with P-type impurity ions) located in the semiconductor substrate. region) or a metal suicide region (such as a nickel suicide region or a cobalt suicide region) in a semiconductor substrate.
  • the material of the semiconductor substrate can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or It can also be other materials, such as III-V group compounds such as gallium arsenide.
  • the target layer may not be formed in the substrate 201, and a ring-shaped gasket may be directly formed on the surface of the substrate subsequently.
  • the base 201 may include a semiconductor substrate and an interlayer dielectric layer in the semiconductor substrate, and the target layer 202 is in the interlayer dielectric layer.
  • the interlayer dielectric layer may be a single-layer or multi-layer stack structure
  • the target layer 202 may be a metal layer
  • the metal layer may be connected to a conductive structure (such as a conductive plug) formed in the underlying dielectric layer.
  • the surface of the target layer 202 may be flush with the surface of the substrate 201 or slightly higher than the surface of the substrate 102 .
  • target layers 202 There may be one or more ( ⁇ 2) target layers 202 formed in the substrate 201. When there are multiple target layers 202, the adjacent target layers are separated. In this embodiment, only the substrate is used.
  • a target layer 202 in 201 is illustrated as an example.
  • a masking material layer 206 is formed on the substrate 201 and a portion of the surface of the target layer 202 , and a masking material layer 206 is formed to expose a portion of the surface of the target layer 202 . Via 207.
  • the material of the mask material layer 206 can be one or more of photoresist, silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, polysilicon, amorphous silicon, amorphous carbon, and low-K dielectric materials. kind.
  • the formation process of the mask material layer 206 may be a chemical vapor deposition process.
  • the material of the mask material layer 206 is photoresist, and through holes 207 are formed in the mask material layer 206 through exposure and development processes.
  • a through hole 207 may be formed in the mask material layer 206 through an etching process.
  • the shape and position of the through hole 207 define the shape and position of the subsequently formed annular spacer.
  • a spacer material layer 208 is formed on the sidewall and bottom surfaces of the through hole 207 and the surface of the mask material layer 206 .
  • the shim material layer 208 is subsequently configured to form an annular shim.
  • the material of the gasket material layer 208 is different from the material of the subsequently formed dielectric layer.
  • the dielectric layer has a high etching selectivity ratio relative to the annular gasket, so that The annular structure can effectively prevent the lateral etching when the through hole is formed by the etching medium layer, and guide the bottom of the etching hole into the central through hole more effectively.
  • the material of the annular spacer material layer 208 may be one or more of silicon nitride, silicon oxide, silicon carbonitride, and silicon oxynitride.
  • the material of the annular spacer material layer 208 is silicon nitride, and a chemical vapor deposition process is used to form the annular spacer material layer.
  • the thickness of the spacer material layer 208 determines the width of the subsequently formed annular spacer. In one embodiment, the thickness of the spacer material layer 208 is 5nm-5um.
  • the surface of the mask material layer 206 and the spacer material layer on the bottom surface of the through hole are removed by maskless etching, and an annular spacer 203 is formed on the sidewall surface of the through hole, and the middle of the annular spacer 203 is formed.
  • a central through hole 213 is formed.
  • the annular spacer 203 when the etching hole is subsequently formed in the dielectric layer, when the etching hole is bent or the position is offset, the annular spacer can prevent the lateral etching of the bottom of the etching hole, so that the etching The bottom of the hole is guided into the central through hole between the annular spacers, so that the bottom of the etched hole is corrected to the correct position, so that the formed capacitor hole (including the connected central through hole and the etched hole) can be exposed normally The surface of the target layer, so the capacitor structure formed in the capacitor hole can be normally electrically connected to the target layer.
  • annular spacer can prevent anomalies such as leakage caused by metal diffusion caused by the formation of the first capacitor structure in the subsequent central through hole.
  • a first capacitor structure can be formed in the central through hole in the middle of the annular spacer, and a second capacitor structure connected to the first capacitor structure can be formed in the etching hole in the dielectric layer.
  • the hole constitutes a capacitance hole
  • the first capacitance structure and the second capacitance structure constitute a capacitor
  • the first capacitance structure and the second capacitance structure can be connected in parallel so that the capacitance value of the capacitor formed in the capacitance hole increases, and because the capacitor divides Two-step formation (the first capacitor structure is formed first and then the second capacitor structure is formed), which reduces the difficulty of forming capacitors in high aspect ratio capacitor holes (high-quality electrode and dielectric layers are formed in high aspect ratio capacitor holes more difficult).
  • the etching of the gasket material layer adopts an anisotropic dry etching process, which may be a plasma etching process.
  • FIG. 5 and FIG. 6 are schematic top views of the annular gasket 203 formed above.
  • the annular gasket 203 shown in FIG. 5 is in the shape of a circular ring, and the annular gasket shown in FIG.
  • the shape of the sheet 203 is an elliptical ring. In other embodiments, the shape of the annular gasket 203 may also be a rectangular annular shape.
  • the inner diameter of the annular gasket 203 may be greater than or equal to the diameter of the etching hole formed in the subsequent dielectric layer. When the etching hole is bent, the bottom of the etching hole can be more easily guided to the middle of the annular gasket 203. in the central through hole.
  • the outer diameter of the annular spacer may be smaller than the diameter of the etching hole formed in the subsequent dielectric layer.
  • FIG. 7 is performed on the basis of FIG. 4 , and a first capacitor structure 219 is formed in the central through hole 213 .
  • the first capacitor structure 219 includes a first electrode layer 216 on the sidewall and bottom surface of the central through hole 213 , a first dielectric layer 217 on the first electrode layer 216 , and a first dielectric layer 217 on the first electrode layer 216 .
  • the second electrode layer 218 on the dielectric layer 217 .
  • the material of the first electrode layer 216 includes a compound formed by one or both of metal nitride and metal silicide, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide) ), titanium silicon nitride (TiSixNy).
  • the material of the first dielectric layer 217 is a high-K dielectric material to improve the capacitance value of the capacitor per unit area, and the high-K dielectric material includes one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx or the above materials A stack formed by two or more of the group consisting of.
  • the material of the second electrode layer 218 includes one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, P-type polysilicon, or two or more of the above materials.
  • the laminate can also include compounds formed by one or both of metal nitrides and metal silicides, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide), silicon nitride (Titanium Nitride) Titanium (TiSixNy) and so on.
  • the forming process of the first capacitor structure 219 includes: sequentially forming a first capacitor on the sidewall and bottom surface of the central through hole 213 , the top surface of the annular gasket 203 and the surface of the mask material layer 206 .
  • first capacitor structure 219 is formed in the central through hole 213, the first capacitor structure 219 includes a first electrode layer 216 on the sidewall and bottom surface of the central through hole 213, A first dielectric layer 217 on an electrode layer 216 and a second electrode layer 218 on the first dielectric layer 217 form the top surface of the first capacitor structure 219 and the top surface of the annular spacer 203 flush.
  • the first capacitor structure 219 is etched back so that the top surface of the remaining first capacitor structure 219 is lower than the bottom surface of the annular spacer 203 , so that the When the etching hole is subsequently formed in the dielectric layer, the annular spacer 203 still has a good guiding effect on the etching process of the etching hole.
  • the second electrode layer 218 is etched back so that the top surface of the second electrode layer 218 is lower than the first electrode layer
  • an isolation layer 220 is formed on the etched back second electrode layer 218, the isolation layer 220 does not cover the first electrode layer 216, and a second capacitor structure is subsequently formed in the etching hole
  • the third electrode layer of the second capacitor structure and the first electrode layer 216 can be electrically connected, so that the first capacitor structure and the second capacitor structure are connected in parallel, thereby increasing the capacitance value of the capacitor formed in the capacitor hole.
  • the isolation layer may also cover part of the first electrode layer 216 and the annular spacer 203 and extend to the surface of the dielectric layer 206 , a rewiring metal layer may be formed in the isolation layer, and the redistribution layer may be formed in the isolation layer.
  • One end of the wiring metal layer is connected to the second electrode layer 218, and the other end extends to the surface of the dielectric layer through the isolation layer.
  • the fourth part of the second capacitor structure can be connected to the dielectric layer on one side of the etching hole by making a metal plug.
  • the electrode layer is electrically connected to the second electrode layer of the first capacitor structure, wherein the first electrode layer 216 and the third electrode layer of the second capacitor structure constitute the upper electrode of the capacitor, and the second electrode layer 218 is connected to the fourth electrode layer of the second capacitor structure.
  • the electrode layer constitutes the lower electrode of the capacitor.
  • the material of the isolation layer 213 is different from the material of the subsequently formed dielectric layer. Specifically, the material of the isolation layer 213 may be the same as the material of the annular gasket 203 .
  • the surface of the first electrode layer 216 and the sidewall surface of the central through hole 213 further have isolation spacers, and the isolation spacers do not cover the second
  • the etching hole connected to the central through hole is subsequently formed in the dielectric layer, when the second capacitance structure is formed in the etching hole, the third electrode layer of the second capacitance structure can be connected with the first capacitance structure.
  • the second electrode layer is electrically connected, that is, the first capacitance structure and the second capacitance structure formed in the capacitance hole are connected in series, and the capacitor in the capacitance hole is formed in two steps (the first capacitance structure is formed first, and then the second capacitance structure is formed), so that It is less difficult to form capacitors in high aspect ratio capacitor holes (high quality electrode and dielectric layers are more difficult to form in high aspect ratio capacitor holes).
  • a dielectric layer 211 covering the substrate 201, the target layer 202, the annular spacer 203 and the first capacitor structure 219 is formed.
  • the mask material layer 206 is removed by a wet etching process (refer to FIG. 8 ). After the mask material layer is removed, a target layer covering the substrate 201 and a target layer are formed. 202 , the annular spacer 203 and the dielectric layer 211 of the first capacitor structure 219 .
  • the mask material layer 206 is an isolation material, which can be configured to electrically isolate devices, for example, when the mask material layer is made of the same material as the dielectric layer to be formed subsequently, when the mask material layer 206 is formed Before the dielectric layer, the mask material layer 206 is retained, and the dielectric layer 211 is directly formed on the mask material layer 206 subsequently, so that no additional steps are required to remove the mask material layer 206 .
  • the material of the dielectric layer 211 may be silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon glass (FSG), low dielectric constant materials, other suitable materials and/or combinations thereof.
  • the dielectric layer 211 is formed by a deposition process, which can be atmospheric pressure chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (Thermal CVD), high density plasma chemical vapor deposition (HDPCVD) ) or atomic layer deposition process.
  • CVD atmospheric pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • Thermal CVD thermal chemical vapor deposition
  • HDPCVD high density plasma chemical vapor deposition
  • the dielectric layer 211 is etched, an etching hole 215 is formed in the dielectric layer 211 and communicated with the central through hole 213 , and the etching hole 215 and the central through hole 213 constitute a capacitor hole.
  • the etching of the dielectric layer 211 to form the etching holes 215 adopts an anisotropic dry etching process, which may be an anisotropic plasma etching process.
  • the formed etching hole 215 may expose all or part of the first electrode layer 216 .
  • the curved etching hole 215 when etching the dielectric layer 211, when the formed etching hole 215 is curved or offset, the curved etching hole 215 can be guided to the central through hole by the annular spacer 203. 213 connection.
  • the etched hole 215 is an etched hole with no complete or offset offset.
  • a second capacitor structure 224 connected to the first capacitor structure 219 is formed in the etching hole 215 (refer to FIG. 10 ).
  • the second capacitor structure 224 includes a third electrode layer 221 located on the sidewall and bottom of the etched hole, a second dielectric layer 222 located on the third electrode layer 221, and a second dielectric layer located on the second dielectric layer 221.
  • the fourth electrode layer 223 on the 222, the third electrode layer 221 is electrically connected to the first electrode layer 216, that is, the first capacitor structure 219 and the second capacitor structure 224 are formed in parallel.
  • the material of the third electrode layer 221 includes a compound formed by one or both of metal nitride and metal silicide, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide) ), titanium silicon nitride (TiSixNy).
  • the material of the second dielectric layer 222 is a high-K dielectric material to increase the capacitance value of the capacitor per unit area, and the high-K dielectric material includes one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx or the above materials A stack formed by two or more of the group consisting of.
  • the material of the fourth electrode layer 223 includes one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, P-type polysilicon, or two or more of the above materials.
  • the laminate can also include compounds formed by one or both of metal nitrides and metal silicides, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide), silicon nitride (Titanium Nitride) Titanium (TiSixNy) and so on.
  • the formation process of the second capacitor structure 224 includes: sequentially forming a third electrode material layer and a second dielectric material on the sidewall and bottom surface of the etched hole and the surface of the dielectric layer 211 layer and the fourth electrode material layer; planarize the third electrode material layer, the second dielectric material layer and the fourth electrode material layer, expose the surface of the dielectric layer 211, and form the third electrode material layer in the etching hole
  • the second capacitor structure 224 includes a third electrode layer 221 on the sidewall and bottom of the etched hole, a second dielectric layer 222 on the third electrode layer 221, and a second dielectric layer 222 on the third electrode layer 221
  • the fourth electrode layer 223 on top of the third electrode layer 221 is electrically connected to the first electrode layer 216 .
  • an etching hole and a corresponding connected central through hole are used as examples.
  • a first capacitor structure is formed in one of the central through holes, and a first capacitor structure is formed in one of the etching holes.
  • a second capacitive structure In other embodiments, one of the etching holes is communicated with a plurality of corresponding central through holes, a first capacitor structure is formed in each of the central through holes, and a second capacitor structure is formed in each of the etching holes. Capacitive structure.
  • a plurality of the etching holes are communicated with a corresponding one of the central through holes, a first capacitor structure is formed in one of the central through holes, and a second capacitor is formed in each of the etching holes structure.
  • An embodiment of the present application further provides a capacitor structure, with reference to FIG. 10 and FIG. 11 , including:
  • a substrate 201 a target layer 202 is formed in the substrate 201, and the substrate 201 exposes the surface of the target layer 202;
  • annular spacer 203 located on the surface of the target layer 202, the annular spacer 203 having a central through hole 213 exposing part of the surface of the target layer 202 in the middle;
  • a second capacitor structure 224 located in the etched hole 215 and connected to the first capacitor structure 219 .
  • the material of the annular gasket 203 is different from the material of the dielectric layer 211 .
  • the dielectric layer 211 is etched to form the etching hole 215 communicating with the central through hole 213 , the The etch rate of layer 211 is greater than the etch rate of the annular spacer 204 .
  • the top surface of the first capacitor structure 219 is lower than the bottom surface of the annular spacer 203 .
  • the first capacitor structure 219 includes a first electrode layer 216 on the sidewall and bottom surface of the central via, a first dielectric layer 217 on the first electrode layer 216, and a first dielectric layer 217 on the first dielectric layer.
  • the second electrode layer 218 on the electrical layer 217 .
  • the second capacitor structure 224 includes a third electrode layer 221 located on the sidewall and bottom of the etched hole, a second dielectric layer 222 located on the third electrode layer 221, and a second dielectric layer located on the second dielectric layer 221.
  • the fourth electrode layer 223 on the 222 is electrically connected to the third electrode layer 221 and the first electrode layer 216 .
  • the surface of the second electrode layer 218 also has an isolation layer 220 .
  • the second capacitor structure includes a third electrode layer on the sidewall and bottom of the etched hole, a second dielectric layer on the third electrode layer, and a third electrode layer on the second dielectric layer Four electrode layers, the third electrode layer is electrically connected to the second electrode layer of the first capacitor structure.
  • the method further includes: isolation sidewalls located on the surface of the first electrode layer and the sidewall surface of the central through hole.
  • the inner diameter of the annular spacer 203 is greater than or equal to the diameter of the etching hole 215 .
  • one of the etching holes is communicated with a corresponding one of the central through holes, a first capacitor structure is formed in one of the central through holes, and a second capacitor structure is formed in one of the etching holes, Or one of the etching holes is communicated with a plurality of the corresponding central through holes, a first capacitor structure is formed in each of the central through holes, a second capacitor structure is formed in one of the etching holes, or more Each of the etching holes is communicated with a corresponding one of the central through holes, a first capacitor structure is formed in one of the central through holes, and a second capacitor structure is formed in each of the etching holes.
  • the substrate 201 may not have the target layer, the annular spacer is directly located on the substrate, and the annular spacer has a central through hole in the middle that exposes the surface of the portion of the substrate.

Abstract

一种电容结构及其形成方法，在基底（201）上形成环形垫片（203），所述环形垫片（203）中间具有暴露出基底（201）部分表面的中央通孔，在所述中央通孔中形成第一电容结构（219）；形成覆盖所述基底（201）、环形垫片（203）和第一电容结构（219）的介质层（211）；刻蚀所述介质层（211），在所述介质层（211）中形成与中央通孔连通的刻蚀孔；在所述刻蚀孔中形成与第一电容结构（219）连接的第二电容结构（224）。

Description

电容结构及其形成方法
相关申请的交叉引用
本申请基于申请号为202011001853.9、申请日为2020年9月22日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及本涉及半导体领域，尤其涉及一种电容结构及其形成方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
在制作DARM的电容器时通常需要现在介质层中形成暴露出目标金属层的电容孔，然后在电容孔中形成电容器结构。
随着器件的集成度越来越高，所述介质层中形成的电容孔的深宽比也不断提高，挑战高深宽比的电容孔对于刻蚀工艺来说一直是非常大的挑战，形成高深宽比的刻蚀电容孔时通常存在电容孔偏移问题，使得电容孔中形成电容器不能正常连接目标金属层，并且现有的电容器的电容值仍有待提高。
发明内容
为解决相关技术问题，本申请实施例提出一种电容结构及其形成方法。本申请提供了一种电容结构的形成方法，包括：
提供基底；
在所述基底上形成环形垫片，所述环形垫片中间具有暴露出基底部分表面的中央通孔；
在所述中央通孔中形成第一电容结构；
形成覆盖所述基底、环形垫片和第一电容结构的介质层；
刻蚀所述介质层，在所述介质层中形成与中央通孔连通的刻蚀孔；
在所述刻蚀孔中形成与第一电容结构连接的第二电容结构。
可选的，所述环形垫片的材料与所述介质层的材料不相同，在刻蚀所述介质层形成与中央通孔连通的刻蚀孔时，对所述介质层的刻蚀速率大于对所述环形垫片的刻蚀速率。
可选的，所述基底中形成有目标层，所述基底露出所述目标层的表面，所述环形垫片形成在所述目标层的表面，所述中央通孔暴露出所述目标层部分表面。
可选的，所述环形垫片的形成过程包括：在所述基底和目标层部分表面上形成掩膜材料层，所述掩膜材料层中形成有暴露出所述目标层部分表面的通孔；在所述通孔的侧壁和底部表面以及所述掩膜材料层的表面形成垫片材料层；无掩膜刻蚀去除所述掩膜材料层的表面以及通孔底部表面的垫片材料层，在所述通孔的侧壁表面形成环形垫片，环形垫片中间具有中央通孔；形成第一电容结构后，去除所述掩膜材料层。
可选的，所述第一电容结构的顶部表面低于所述环形垫片的底部表面。
可选的，所述第一电容结构包括位于中央通孔侧壁和底部表面的第一电极层、位于第一电极层上的第一介电层和位于所述第一介电层上的第二 电极层。
可选的，所述第二电容结构包括位于刻蚀孔侧壁和底部的第三电极层、位于第三电极层上的第二介电层和位于第二介电层上的第四电极层，所述第三电极层与第一电极层电连接。
可选的，在形成所述第二电容结构之前，在所述第二电极层表面形成隔离层。
可选的，所述第二电容结构包括位于刻蚀孔侧壁和底部的第三电极层、位于第三电极层上的第二介电层和位于第二介电层上的第四电极层，所述第三电极层与第二电极层电连接。
可选的，在形成第二电容结构之前，在所述第一电极层表面和中央通孔的侧壁表面形成隔离侧墙
可选的，所述环形垫片的内径大于或等于所述刻蚀孔的直径。
可选的，一个所述刻蚀孔与对应的一个所述中央通孔连通，一个所述中央通孔内形成有一个第一电容结构，一个所述刻蚀孔内形成一个第二电容结构，或者一个所述刻蚀孔与对应的多个所述中央通孔连通，每一个所述中央通孔中相应的形成一个第一电容结构，一个所述刻蚀孔中形成一个第二电容结构，或者多个所述刻蚀孔与对应的一个所述中央通孔连通，一个所述中央通孔中形成一个第一电容结构，每一个所述刻蚀孔中形成一个第二电容结构。
本申请还提供了一种电容结构，包括：
基底；
位于所述基底上的环形垫片，所述环形垫片中间具有暴露出基底部分表面的中央通孔；
位于所述中央通孔中的第一电容结构；
覆盖所述基底、环形垫片和第一电容结构的介质层；
位于所述介质层中的与中央通孔连通的刻蚀孔；
位于所述刻蚀孔中的与第一电容结构连接的第二电容结构。
可选的，所述环形垫片的材料与所述介质层的材料不相同，在刻蚀所述介质层形成与中央通孔连通的刻蚀孔时，对所述介质层的刻蚀速率大于对所述环形垫片的刻蚀速率。
可选的，所述基底中具有目标层，所述基底露出所述目标层的表面，所述环形垫片位于所述目标层的表面，所述中央通孔暴露出所述目标层部分表面。
可选的，所述第一电容结构的顶部表面低于所述环形垫片的底部表面。
可选的，所述第一电容结构包括位于中央通孔侧壁和底部表面的第一电极层、位于第一电极层上的第一介电层和位于所述第一介电层上的第二电极层。
可选的，所述第二电容结构包括位于刻蚀孔侧壁和底部的第三电极层、位于第三电极层上的第二介电层和位于第二介电层上的第四电极层，所述第三电极层与第一电极层电连接。
可选的，所述第二电极层表面的隔离层。
可选的，所述第二电容结构包括位于刻蚀孔侧壁和底部的第三电极层、位于第三电极层上的第二介电层和位于第二介电层上的第四电极层，所述第三电极层与第二电极层电连接。
可选的，还包括：位于所述第一电极层表面和中央通孔的侧壁表面的隔离侧墙。
可选的，所述环形垫片的内径大于或等于所述刻蚀孔的直径。
可选的，一个所述刻蚀孔与对应的一个所述中央通孔连通，一个所述中央通孔内形成有一个第一电容结构，一个所述刻蚀孔内形成一个第二电容结构，或者一个所述刻蚀孔与对应的多个所述中央通孔连通，每一个所 述中央通孔中相应的形成一个第一电容结构，一个所述刻蚀孔中形成一个第二电容结构，或者多个所述刻蚀孔与对应的一个所述中央通孔连通，一个所述中央通孔中形成一个第一电容结构，每一个所述刻蚀孔中形成一个第二电容结构。
与现有技术相比，本申请技术方案具有以下优点：
本申请的电容结构的形成方法，在基底上形成环形垫片，所述环形垫片中间具有暴露出基底部分表面的中央通孔后，在所述中央通孔中形成第一电容结构；形成覆盖所述基底、环形垫片和第一电容结构的介质层；刻蚀所述介质层，在所述介质层中形成与中央通孔连通的刻蚀孔；在所述刻蚀孔中形成与第一电容结构连接的第二电容结构。通过形成环形垫片，在介质层中形成刻蚀孔时，当刻蚀孔存在弯曲或者位置偏移时，所述环形垫片能防止刻蚀孔底部的侧向刻蚀，使得刻蚀孔的底部被导引至环形垫片之间的中央通孔中，因而使得刻蚀孔底部被纠正至正确的位置，使得形成的电容孔(包括连通的中央通孔和刻蚀孔)能正常的暴露目标层表面，因而电容孔中形成的电容结构能正常的与目标层点连接。并且，环形垫片的存在，能防止中央通孔中形成第一电容结构带来的金属扩散而导致的漏电等异常。并且，所述环形垫片中间的中央通孔中还可以形成第一电容结构，介质层中的刻蚀孔可以形成与第一电容结构连接的第二电容结构，所述中央通孔和刻蚀孔构成电容孔，所述第一电容结构和第二电容结构可以并联构成电容器，使得电容孔中形成的电容器的容值增大，由于电容器分两步形成(先形成第一电容结构后形成第二电容结构)，使得在高深宽比的电容孔中形成电容器的难度降低(高深宽比的电容孔中形成高质量的电极层和介电层的难度较大)。
进一步，所述环形垫片的形成过程包括：在所述基底和目标层部分表面上形成掩膜材料层，所述掩膜材料层中形成有暴露出所述目标层部分表 面的电容孔；在所述电容孔的侧壁和底部表面以及所述掩膜材料层的表面形成垫片材料层；无掩膜刻蚀去除所述掩膜材料层的表面以及电容孔底部表面的垫片材料层，在所述电容孔的侧壁表面形成环形垫片。这样方法形成的环形垫片的尺寸和形状的精度较高，并具有较高的侧壁形貌。
进一步，第一电容结构的顶部表面低于所述环形垫片的底部表面，以使得后续在介质层中形成刻蚀孔时，所述环形垫片对刻蚀孔的刻蚀过程仍具有较好的导引作用。
本申请的电容结构，通过环形垫片，在介质层中形成刻蚀孔时，当刻蚀孔存在弯曲或者位置偏移时，所述环形垫片能防止刻蚀孔底部的侧向刻蚀，使得刻蚀孔的底部被导引至环形垫片之间的中央通孔中，因而使得刻蚀孔底部被纠正至正确的位置，使得形成的电容孔(包括连通的中央通孔和刻蚀孔)能正常的暴露目标层表面，因而电容孔中形成的电容结构能正常的与目标层点连接。并且，环形垫片的存在，能防止中央通孔中形成第一电容结构带来的金属扩散而导致的漏电等异常。并且，所述环形垫片中间的中央通孔中还可以形成第一电容结构，介质层中的刻蚀孔可以形成与第一电容结构连接的第二电容结构，所述中央通孔和刻蚀孔构成电容孔，所述第一电容结构和第二电容结构可以并联构成电容器，使得电容孔中形成的电容器的容值增大，由于电容器分两步形成(先形成第一电容结构后形成第二电容结构)，使得在高深宽比的电容孔中形成电容器的难度降低(高深宽比的电容孔中形成高质量的电极层和介电层的难度较大)。
附图说明
图1为现有形成的电容孔的结构示意图；
图2-图11为本申请实施例电容结构的形成过程的剖面结构示意图。
具体实施方式
如背景技术所言，形成高深宽比的刻蚀电容孔时通常存在电容孔偏移问题。
研究发现，参考图1，由于晶圆边缘的磁场偏压较弱所以容易造成刻蚀电容孔104弯曲，使得刻蚀电容孔的底部会偏离正常位置，因而不能正常的暴露目标金属层表面。或者，由于套刻工艺的偏差，使得形成的刻蚀电容孔偏离正常的位置，使得电容孔中形成电容器不能正常连接目标金属层。
为此，本申请提供了一种电容结构及其形成方法，所述形成方法，在基底上形成环形垫片，所述环形垫片中间具有暴露出基底部分表面的中央通孔后，在所述中央通孔中形成第一电容结构；形成覆盖所述基底、环形垫片和第一电容结构的介质层；刻蚀所述介质层，在所述介质层中形成与中央通孔连通的刻蚀孔；在所述刻蚀孔中形成与第一电容结构连接的第二电容结构。通过形成环形垫片，在介质层中形成刻蚀孔时，当刻蚀孔存在弯曲或者位置偏移时，所述环形垫片能防止刻蚀孔底部的侧向刻蚀，使得刻蚀孔的底部被导引至环形垫片之间的中央通孔中，因而使得刻蚀孔底部被纠正至正确的位置，使得形成的电容孔(包括连通的中央通孔和刻蚀孔)能正常的暴露目标层表面，因而电容孔中形成的电容结构能正常的与目标层电连接。并且，环形垫片的存在，能防止中央通孔中形成第一电容结构带来的金属扩散而导致的漏电等异常。并且，所述环形垫片中间的中央通孔中还可以形成第一电容结构，介质层中的刻蚀孔可以形成与第一电容结构连接的第二电容结构，所述中央通孔和刻蚀孔构成电容孔，所述第一电容结构和第二电容结构可以并联构成电容器，使得电容孔中形成的电容器的容值增大，由于电容器分两步形成(先形成第一电容结构后形成第二电容结构)，使得在高深宽比的电容孔中形成电容器的难度降低(高深宽比的电容孔中形成高质量的电极层和介电层的难度较大)。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在详述本申请实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
参考图2，提供基底201，所述基底201中形成有目标层202，所述基底201露出所述目标层202的表面。
在一实施例中，所述基底201可以为半导体衬底，所述目标层202可以为位于半导体衬底中的掺杂区(比如掺杂有N型杂质离子或掺杂有P型杂质离子的区域)或者位于半导体衬底中的金属硅化物区(比如硅化镍区或硅化钴区)。所述半导体衬底的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。在其他实施例中，所述基底201中可以不形成有目标层，后续直接在基底表面形成环形垫片。
在其他实施例中，所述基底201可以包括半导体衬底和位于半导体衬底中的层间介质层，所述目标层202位于层间介质层中。所述层间介质层可以为单层或多层堆叠结构，所述目标层202可以为金属层，所述金属层可以与下层介质层中形成的导电结构(比如导电插塞)连接。
所述目标层202的表面可以与所述基底201的表面齐平，或者略高于所述基底102的表面。
所述基底201中形成目标层202可以为一个或多个(≥2个)，所述目标层202为多个时，相邻目标层之间是分立的，本实施例中仅以所述基底201中具有一个目标层202作为示例进行说明。
所述目标层202上后续需要形成环形垫片。在一实施例中，继续参考图2，在所述基底201和目标层202部分表面上形成掩膜材料层206，所述 掩膜材料层206中形成有暴露出所述目标层202部分表面的通孔207。
所述掩膜材料层206的材料可以为光刻胶、氮化硅、氧化硅、碳氮化硅、氮氧化硅、多晶硅、无定型硅、无定型碳、低K介质材料中一种或几种。所述掩膜材料层206的形成工艺可以为化学气相沉积工艺。
在一实施例中，所述掩膜材料层206的材料为光刻胶，通过曝光和显影工艺在所述掩膜材料层206中形成通孔207。所述掩膜材料层206为其他材料时，可以通过，可以通过刻蚀工艺在所述掩膜材料层206中形成通孔207。
所述通孔207的形状和位置限定后续形成的环形垫片的形状和位置。
参考图3，在所述通孔207的侧壁和底部表面以及所述掩膜材料层206的表面形成垫片材料层208。
所述垫片材料层208后续配置为形成环形垫片。所述垫片材料层208的材料与后续形成的介质层的材料不相同，后续在介质层中形成刻蚀孔时，使得介质层相对于所述环形垫片具有高的刻蚀选择比，从而使得环形结构能有效的防止刻蚀介质层形成通孔时的侧向刻蚀，将刻蚀孔的底部更有效的导引至所述中央通孔中。
所述环形垫片材料层208的材料可以为氮化硅、氧化硅、碳氮化硅、氮氧化硅中的一种或几种。本实施例中，所述环形垫片材料层208的材料为氮化硅，形成所述环形垫片材料层采用化学气相沉积工艺。
所述垫片材料层208的厚度决定后续形成的环形垫片的宽度。在一实施例中，所述垫片材料层208的厚度为5nm-5um。
参考图4，无掩膜刻蚀去除所述掩膜材料层206的表面以及通孔底部表面的垫片材料层，在所述通孔的侧壁表面形成环形垫片203，环形垫片203中间形成中央通孔213。
通过形成环形垫片203，后续在介质层中形成刻蚀孔时，当刻蚀孔存在 弯曲或者位置偏移时，所述环形垫片能防止刻蚀孔底部的侧向刻蚀，使得刻蚀孔的底部被导引至环形垫片之间的中央通孔中，因而使得刻蚀孔底部被纠正至正确的位置，使得形成的电容孔(包括连通的中央通孔和刻蚀孔)能正常的暴露目标层表面，因而电容孔中形成的电容结构能正常的与目标层电连接。并且，环形垫片的存在，能防止后续中央通孔中形成第一电容结构带来的金属扩散而导致的漏电等异常。并且，所述环形垫片中间的中央通孔中后续还可以形成第一电容结构，介质层中的刻蚀孔后续可以形成与第一电容结构连接的第二电容结构，所述中央通孔和刻蚀孔构成电容孔，所述第一电容结构和第二电容结构构成电容器，所述第一电容结构和第二电容结构可以并联连接使得电容孔中形成的电容器的容值增大，并且由于电容器分两步形成(先形成第一电容结构后形成第二电容结构)，使得在高深宽比的电容孔中形成电容器的难度降低(高深宽比的电容孔中形成高质量的电极层和介电层的难度较大)。刻蚀所述垫片材料层采用各项异性的干法刻蚀工艺，可以为等离子体刻蚀工艺。
参考图5和图6，图5和图6为前述形成的环形垫片203的俯视结构示意图，图5中所示的环形垫片203的形状为圆环形，图6中所示的环形垫片203的形状为椭圆环形。在其他实施例中，所述环形垫片203的形状也可以为长方环状。所述环形垫片203的内径可以大于或等于后续介质层中形成的刻蚀孔的直径，当刻蚀孔存在弯曲时，使得刻蚀孔的底部更容易被导引至环形垫片203中间的中央通孔中。在其他实施例中，所述环形垫片的外径可以小于所述后续介质层中形成的刻蚀孔的直径。
参考图7，图7在图4的基础上进行，在所述中央通孔213中形成第一电容结构219。
在一实施例中，所述第一电容结构219包括位于中央通孔213侧壁和底部表面的第一电极层216、位于第一电极层216上的第一介电层217和位 于所述第一介电层217上的第二电极层218。
所述第一电极层216的材料包括金属氮化物及金属硅化物中的一种或两种所形成的化合物，如氮化钛(Titanium Nitride)，硅化钛(Titanium Silicide)，硅化镍(Titanium Silicide)，硅氮化钛(TiSixNy)。
所述第一介电层217的材料为高K介质材料，以提高单位面积电容器的电容值，所述高K介质材料包括ZrOx、HfOx、ZrTiOx、RuOx、SbOx、AlOx中的一种或上述材料所组成群组中的两种以上所形成的叠层。
所述第二电极层218的材料包括钨、钛、镍、铝、铂、氮化钛、N型多晶硅、P型多晶硅中的一种或上述材料所组成群组中的两种以上所形成的叠层，还可以包括金属氮化物及金属硅化物中的一种或两种所形成的化合物，如氮化钛(Titanium Nitride)，硅化钛(Titanium Silicide)，硅化镍(Titanium Silicide)，硅氮化钛(TiSixNy)等。
在一实施例中，所述第一电容结构219的形成过程包括：在所述中央通孔213的侧壁和底部表面、环形垫片203的顶部表面以及掩膜材料层206的表面依次形成第一电极材料层、第一介电材料层和第二电极材料层；平坦化所述第一电极材料层、第一介电材料层和第二电极材料层，暴露出所述掩膜材料层206的表面和环形垫片203的顶部表面，在所述中央通孔213中形成第一电容结构219，所述第一电容结构219包括位于中央通孔213侧壁和底部表面的第一电极层216、位于第一电极层216上的第一介电层217和位于所述第一介电层217上的第二电极层218，形成的第一电容结构219的顶部表面与所述环形垫片203的顶部表面平齐。
在一实施例中，形成第一电容结构219后，回刻蚀所述第一电容结构219，使得剩余的第一电容结构219的顶部表面低于所述环形垫片203的底部表面，以使得后续在介质层中形成刻蚀孔时，所述环形垫片203对刻蚀孔的刻蚀过程仍具有较好的导引作用。
在一实施例中，参考图8，回刻蚀所述第一电容结构219后，回刻蚀所述第二电极层218，使得第二电极层218的顶部表面低于所述第一电极层216的顶部表面，在所述回刻蚀后的第二电极层218上形成隔离层220，所述隔离层220未覆盖所述第一电极层216，后续在刻蚀孔中形成第二电容结构时，使得第二电容结构的第三电极层与第一电极层216能电连接，使得第一电容结构和第二电容结构并联，从而增大了电容孔中形成的电容器的电容值。
在一实施例中，所述隔离层还可以覆盖部分所述第一电极层216以及环形垫片203并延伸至介质层206的表面，所述隔离层中可以形成再布线金属层，所述再布线金属层一端与所述第二电极层218连接，另一端穿过隔离层延伸至介质层表面，后续通过在刻蚀孔一侧的介质层制作金属插塞可以将第二电容结构的第四电极层与第一电容结构的第二电极层电连接，其中第一电极层216与第二电容结构的第三电极层构成电容器的上电极，第二电极层218与第二电容结构的第四电极层构成电容器的下电极。
所述隔离层213的材料与后续形成的介质层的材料不相同，具体的，所述隔离层213的材料可以与环形垫片203的材料相同。
在其他实施例中，回刻蚀所述第一电容结构219后，在所述第一电极层216表面和中央通孔213的侧壁表面还具有隔离侧墙，所述隔离侧墙未覆盖第二电极层的表面，后续在介质层中形成与中央通孔连接的刻蚀孔后，在刻蚀孔中形成第二电容结构时，使得第二电容结构的第三电极层能与第一电容结构的第二电极层电连接，即使得电容孔中形成的第一电容结构和第二电容结构串联，电容孔中的电容器分两步形成(先形成第一电容结构后形成第二电容结构)，使得在高深宽比的电容孔中形成电容器的难度降低(高深宽比的电容孔中形成高质量的电极层和介电层的难度较大)。
参考图9，形成覆盖所述基底201、目标层202、环形垫片203和第一 电容结构219的介质层211。
本实施例中，在形成介质层211之前，通过湿法刻蚀工艺去除所述掩膜材料层206(参考图8)，去除所述掩膜材料层后，形成覆盖所述基底201、目标层202、环形垫片203和第一电容结构219的介质层211。
在另一实施例中，当所述掩膜材料层206为隔离材料，可以配置为器件之间的电学隔离时，比如所述掩膜材料层与后续形成的介质层的材料相同时，在形成介质层之前，保留所述掩膜材料层206，后续在所述掩膜材料层206上直接形成介质层211，从而无需额外的步骤去除所述掩膜材料层206。
所述介质层211的材料可以为氧化硅、氮化硅、氮氧化硅、氟掺杂硅玻璃(FSG)、低介电常数材料、其它适合的材料及/或上述的组合。形成所述介质层211采用沉积工艺，可以为常压化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、热化学气相沉积法(Thermal CVD)、高密度等离子体化学气相沉积(HDPCVD)或原子层沉积工艺。
参考图10，刻蚀所述介质层211，在所述介质层211中形成与中央通孔213连通的刻蚀孔215，所述刻蚀孔215和中央通孔213构成电容孔。
刻蚀所述介质层211形成刻蚀孔215采用各项异性的干法刻蚀工艺，可以为各项异性的等离子体刻蚀工艺。所述形成的刻蚀孔215可以暴露出全部或部分所述第一电极层216。
在一实施例中，在刻蚀介质层211时，当形成的刻蚀孔215存在弯曲或者套刻偏移时，通过环形垫片203能将所述弯曲的刻蚀孔215引导至与中央通孔213连接。本实施例中，所述刻蚀孔215为不存在完全或者套刻偏移的刻蚀孔。
参考图11，在所述刻蚀孔215(参考图10)中形成与第一电容结构219连接的第二电容结构224。
在一实施例中，所述第二电容结构224包括位于刻蚀孔侧壁和底部的第三电极层221、位于第三电极层221上的第二介电层222和位于第二介电层222上的第四电极层223，所述第三电极层221与第一电极层216电连接，即使得形成的第一电容结构219和第二电容结构224并联。
所述第三电极层221的材料包括金属氮化物及金属硅化物中的一种或两种所形成的化合物，如氮化钛(Titanium Nitride)，硅化钛(Titanium Silicide)，硅化镍(Titanium Silicide)，硅氮化钛(TiSixNy)。
所述第二介电层222的材料为高K介质材料，以提高单位面积电容器的电容值，所述高K介质材料包括ZrOx、HfOx、ZrTiOx、RuOx、SbOx、AlOx中的一种或上述材料所组成群组中的两种以上所形成的叠层。
所述第四电极层223的材料包括钨、钛、镍、铝、铂、氮化钛、N型多晶硅、P型多晶硅中的一种或上述材料所组成群组中的两种以上所形成的叠层，还可以包括金属氮化物及金属硅化物中的一种或两种所形成的化合物，如氮化钛(Titanium Nitride)，硅化钛(Titanium Silicide)，硅化镍(Titanium Silicide)，硅氮化钛(TiSixNy)等。
在一实施例中，所述第二电容结构224的形成过程包括：在所述刻蚀孔的侧壁和底部表面、以及介质层211的表面依次形成第三电极材料层、第二介电材料层和第四电极材料层；平坦化所述第三电极材料层、第二介电材料层和第四电极材料层，暴露出所述介质层211的表面，在所述刻蚀孔中形成第二电容结构224，所述第二电容结构224包括位于刻蚀孔侧壁和底部的第三电极层221、位于第三电极层221上的第二介电层222和位于第二介电层222上的第四电极层223，所述第三电极层221与第一电极层216电连接。
需要说明的是，前述实施例中，均是以一个刻蚀孔和对应的连通的一个中央通孔作为示例，一个所述中央通孔内形成有一个第一电容结构，一 个所述刻蚀孔内形成一个第二电容结构。在其他实施例中，一个所述刻蚀孔与对应的多个所述中央通孔连通，每一个所述中央通孔中相应的形成一个第一电容结构，一个所述刻蚀孔中形成一个第二电容结构。在另一实施例中，多个所述刻蚀孔与对应的一个所述中央通孔连通，一个所述中央通孔中形成一个第一电容结构，每一个所述刻蚀孔中形成一个第二电容结构。
本申请一实施例还提供了一种电容结构，结合参考图10和图11，包括：
基底201，所述基底201中形成有目标层202，所述基底201露出所述目标层202的表面；
位于所述目标层202表面上的环形垫片203，所述环形垫片203中间具有暴露出目标层202部分表面的中央通孔213；
位于所述中央通孔213中的第一电容结构219；
覆盖所述基底201、目标层202、环形垫片203和第一电容结构219的介质层211；
位于所述介质层211中的与中央通孔213连通的刻蚀孔215；
位于所述刻蚀孔215中的与第一电容结构219连接的第二电容结构224。
在一实施例中，所述环形垫片203的材料与所述介质层211的材料不相同，在刻蚀所述介质层211形成与中央通孔213连通的刻蚀孔215时，对所述介质层211的刻蚀速率大于对所述环形垫片204的刻蚀速率。
在一实施例中，所述第一电容结构219的顶部表面低于所述环形垫片203的底部表面。
在一实施例中，所述第一电容结构219包括位于中央通孔侧壁和底部表面的第一电极层216、位于第一电极层216上的第一介电层217和位于所述第一介电层217上的第二电极层218。
在一实施例中，所述第二电容结构224包括位于刻蚀孔侧壁和底部的 第三电极层221、位于第三电极层221上的第二介电层222和位于第二介电层222上的第四电极层223，所述第三电极层221与第一电极层216电连接。相应的，所述第二电极层218表面还具有隔离层220。
在另一实施例中，所述第二电容结构包括位于刻蚀孔侧壁和底部的第三电极层、位于第三电极层上的第二介电层和位于第二介电层上的第四电极层，所述第三电极层与第一电容结构的第二电极层电连接。相应的，还包括：位于所述第一电极层表面和中央通孔的侧壁表面的隔离侧墙。
在一实施例中，所述环形垫片203的内径大于或等于所述刻蚀孔215的直径。
在一实施例中，一个所述刻蚀孔与对应的一个所述中央通孔连通，一个所述中央通孔内形成有一个第一电容结构，一个所述刻蚀孔内形成一个第二电容结构，或者一个所述刻蚀孔与对应的多个所述中央通孔连通，每一个所述中央通孔中相应的形成一个第一电容结构，一个所述刻蚀孔中形成一个第二电容结构，或者多个所述刻蚀孔与对应的一个所述中央通孔连通，一个所述中央通孔中形成一个第一电容结构，每一个所述刻蚀孔中形成一个第二电容结构。
在其他实施例中，所述基底201可以不具有目标层，所述环形垫片直接位于位于所述基底上，所述环形垫片中间具有暴露出基底部分表面的中央通孔。
需要说明的是，本实施例中(电容结构)与前述实施例中(电容结构的形成过程)中相似或相同结构的限定或描述，在本实施例中不再限定，具体请参考前述实施例相应部分的限定或描述。
本申请虽然已以较佳实施例公开如上，但其并不是用来限定本申请，任何本领域技术人员在不脱离本申请的精神和范围内，都可以利用上述揭示的方法和技术内容对本申请技术方案做出可能的变动和修改，因此，凡 是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本申请技术方案的保护范围。

Claims (23)

  1. 一种电容结构的形成方法，包括：
    提供基底，在所述基底上形成环形垫片，所述环形垫片中间具有暴露出基底部分表面的中央通孔；
    在所述中央通孔中形成第一电容结构；
    形成覆盖所述基底、环形垫片和第一电容结构的介质层；
    刻蚀所述介质层，在所述介质层中形成与中央通孔连通的刻蚀孔；
    在所述刻蚀孔中形成与第一电容结构连接的第二电容结构。
  2. 如权利要求1所述的电容结构的形成方法，其中，所述环形垫片的材料与所述介质层的材料不相同，在刻蚀所述介质层形成与中央通孔连通的刻蚀孔时，对所述介质层的刻蚀速率大于对所述环形垫片的刻蚀速率。
  3. 如权利要求1所述的电容结构的形成方法，其中，所述基底中形成有目标层，所述基底露出所述目标层的表面，所述环形垫片形成在所述目标层的表面，所述中央通孔暴露出所述目标层部分表面。
  4. 如权利要求3所述的电容结构的形成方法，其中，所述环形垫片的形成过程包括：在所述基底和目标层部分表面上形成掩膜材料层，所述掩膜材料层中形成有暴露出所述目标层部分表面的通孔；在所述通孔的侧壁和底部表面以及所述掩膜材料层的表面形成垫片材料层；无掩膜刻蚀去除所述掩膜材料层的表面以及通孔底部表面的垫片材料层，在所述通孔的侧壁表面形成环形垫片，环形垫片中间具有中央通孔；形成第一电容结构后，去除所述掩膜材料层。
  5. 如权利要求1所述的电容结构的形成方法，其中，所述第一电容结构的顶部表面低于所述环形垫片的顶部表面。
  6. 如权利要求1或4所述的电容结构的形成方法，其中，所述第一 电容结构包括位于中央通孔侧壁和底部表面的第一电极层、位于第一电极层上的第一介电层和位于所述第一介电层上的第二电极层。
  7. 如权利要求5所述的电容结构的形成方法，其中，所述第二电容结构包括位于刻蚀孔侧壁和底部的第三电极层、位于第三电极层上的第二介电层和位于第二介电层上的第四电极层，所述第三电极层与第一电极层电连接。
  8. 如权利要求5所述的电容结构的形成方法，其中，在形成所述第二电容结构之前，在所述第二电极层表面形成隔离层。
  9. 如权利要求5所述的电容结构的形成方法，其中，所述第二电容结构包括位于刻蚀孔侧壁和底部的第三电极层、位于第三电极层上的第二介电层和位于第二介电层上的第四电极层，所述第三电极层与第二电极层电连接。
  10. 如权利要求9所述的电容结构的形成方法，其中，在形成第二电容结构之前，在所述第一电极层表面和中央通孔的侧壁表面形成隔离侧墙。
  11. 如权利要求1所述的电容结构的形成方法，其中，所述环形垫片的内径大于或等于所述刻蚀孔的直径。
  12. 如权利要求1所述的电容结构的形成方法，其中，一个所述刻蚀孔与对应的一个所述中央通孔连通，一个所述中央通孔内形成有一个第一电容结构，一个所述刻蚀孔内形成一个第二电容结构，或者一个所述刻蚀孔与对应的多个所述中央通孔连通，每一个所述中央通孔中相应的形成一个第一电容结构，一个所述刻蚀孔中形成一个第二电容结构，或者多个所述刻蚀孔与对应的一个所述中央通孔连通，一个所述中央通孔中形成一个第一电容结构，每一个所述刻蚀孔中形成一个第二电容结构。
  13. 一种电容结构，包括：
    基底；
    位于所述基底上的环形垫片，所述环形垫片中间具有暴露出基底部分表面的中央通孔；
    位于所述中央通孔中的第一电容结构；
    覆盖所述基底、环形垫片和第一电容结构的介质层；
    位于所述介质层中的与中央通孔连通的刻蚀孔；
    位于所述刻蚀孔中的与第一电容结构连接的第二电容结构。
  14. 如权利要求13所述的电容结构，其中，所述环形垫片的材料与所述介质层的材料不相同，在刻蚀所述介质层形成与中央通孔连通的刻蚀孔时，对所述介质层的刻蚀速率大于对所述环形垫片的刻蚀速率。
  15. 如权利要求13所述的电容结构，其中，所述基底中具有目标层，所述基底露出所述目标层的表面，所述环形垫片位于所述目标层的表面，所述中央通孔暴露出所述目标层部分表面。
  16. 如权利要求13所述的电容结构，其中，所述第一电容结构的顶部表面低于所述环形垫片的顶部表面。
  17. 如权利要求13或16所述的电容结构，其中，所述第一电容结构包括位于中央通孔侧壁和底部表面的第一电极层、位于第一电极层上的第一介电层和位于所述第一介电层上的第二电极层。
  18. 如权利要求17所述的电容结构，其中，所述第二电容结构包括位于刻蚀孔侧壁和底部的第三电极层、位于第三电极层上的第二介电层和位于第二介电层上的第四电极层，所述第三电极层与第一电极层电连接。
  19. 如权利要求18所述的电容结构，其中，还包括：位于所述第二电极层表面的隔离层。
  20. 如权利要求17所述的电容结构，其中，所述第二电容结构包括位于刻蚀孔侧壁和底部的第三电极层、位于第三电极层上的第二介电层和 位于第二介电层上的第四电极层，所述第三电极层与第二电极层电连接。
  21. 如权利要求20所述的电容结构，其中，还包括：位于所述第一电极层表面和中央通孔的侧壁表面的隔离侧墙。
  22. 如权利要求13所述的电容结构，其中，所述环形垫片的内径大于或等于所述刻蚀孔的直径。
  23. 如权利要求13所述的电容结构，其中，一个所述刻蚀孔与对应的一个所述中央通孔连通，一个所述中央通孔内形成有一个第一电容结构，一个所述刻蚀孔内形成一个第二电容结构，或者一个所述刻蚀孔与对应的多个所述中央通孔连通，每一个所述中央通孔中相应的形成一个第一电容结构，一个所述刻蚀孔中形成一个第二电容结构，或者多个所述刻蚀孔与对应的一个所述中央通孔连通，一个所述中央通孔中形成一个第一电容结构，每一个所述刻蚀孔中形成一个第二电容结构。
PCT/CN2021/100740 2020-09-22 2021-06-17 电容结构及其形成方法 WO2022062495A1 (zh)

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