WO2023024429A1 - 柱状电容器阵列结构制备方法及半导体结构 - Google Patents

柱状电容器阵列结构制备方法及半导体结构 Download PDF

Info

Publication number
WO2023024429A1
WO2023024429A1 PCT/CN2022/072659 CN2022072659W WO2023024429A1 WO 2023024429 A1 WO2023024429 A1 WO 2023024429A1 CN 2022072659 W CN2022072659 W CN 2022072659W WO 2023024429 A1 WO2023024429 A1 WO 2023024429A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
sacrificial
sacrificial layer
top support
mask
Prior art date
Application number
PCT/CN2022/072659
Other languages
English (en)
French (fr)
Inventor
宛强
占康澍
夏军
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US18/151,469 priority Critical patent/US20230298899A1/en
Publication of WO2023024429A1 publication Critical patent/WO2023024429A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

Definitions

  • the present application relates to the field of semiconductor technology, in particular to a method for preparing a columnar capacitor array structure and a semiconductor structure.
  • DRAM Dynamic random access memory
  • DRAM Dynamic Random Access Memory
  • the capacitor is a vertical cylindrical capacitor with a high aspect ratio.
  • the columnar capacitor Since the columnar capacitor has a high aspect ratio, in order to increase the stability of the columnar capacitor, it is generally necessary to provide a support layer to support the columnar capacitor.
  • the disadvantage of the existing method for manufacturing pillar capacitors is that the support layer on the top is easily worn out, and the supporting force of the top support layer is insufficient, which may cause the pillar capacitor to tilt or even peel off, affecting the performance of the pillar capacitor.
  • the embodiment of the present application provides a method for preparing a columnar capacitor array structure and a semiconductor structure, which can avoid the loss of the top support layer, thereby ensuring the thickness and support strength of the top support layer, avoiding the tilt of the columnar capacitors, and improving the performance of the columnar capacitor array structure , thereby improving the yield of the memory.
  • the present application provides a method for preparing a columnar capacitor array structure, including:
  • a substrate is provided, a plurality of conductive pads are arranged in the substrate, and a first sacrificial layer, a middle support layer, a second sacrificial layer, a top support layer and a mask layer are stacked on the substrate, and the The substrate is divided into an array area and a peripheral area, the thickness of the mask layer located in the array area is smaller than the thickness of the mask layer located in the peripheral area, and in the array area, several capacitance holes penetrate the mask Layer, top support layer, second sacrificial layer, middle support layer and first sacrificial layer, exposing the conductive pad; forming a photoresist layer, the photoresist layer fills the capacitor hole, and covers the array
  • the step of forming a photoresist layer, the photoresist layer filling the capacitance hole, and covering the mask layer of the array area further includes: forming a photoresist material layer, the photoresist material layer filling the Capacitor holes, and cover the array area and the mask layer of the peripheral area; etch back the photoresist material layer to expose the mask layer of the peripheral area, so as to form the photoresist layer.
  • the step of forming a photoresist layer, the photoresist layer filling the capacitance hole, and covering the mask layer of the array region further includes: forming a photoresist material layer, the photoresist The glue material layer fills the capacitor hole and covers the mask layer in the array region and the peripheral region; etching back the photoresist material layer exposes the mask layer in the peripheral region to form the mask layer in the peripheral region. the photoresist layer.
  • the upper surface of the photoresist layer is flush with the upper surface of the mask layer in the peripheral region.
  • the photoresist layer on the surface of the mask layer is removed, and the top support layer is used as an etching stop layer.
  • the etching material is The etch rate of the membrane layer is greater than the etch rate of the top support layer.
  • the mask layer is a polysilicon layer
  • the top support layer is a silicon nitride layer
  • a third sacrificial layer is formed, and in the step of covering the top support layer, the third sacrificial layer is formed by using a spin coating deposition process.
  • the third sacrificial layer is an oxide layer.
  • the step of forming a third sacrificial layer, the third sacrificial layer covering the top supporting layer further includes: forming a third sacrificial material layer, the third sacrificial material layer covering the top supporting layer and The photoresist layer; thinning the third sacrificial material layer to expose the photoresist layer to form the third sacrificial layer.
  • the step of electrically connecting the lower electrode to the conductive pad further includes: forming a lower electrode material layer, and the lower electrode material layer fills the lower electrode the capacitance hole and cover the third sacrificial layer; thinning the lower electrode material layer to expose the third sacrificial layer to form the lower electrode.
  • the step of patterning the auxiliary layer, the third sacrificial layer and the top support layer, and removing the third sacrificial layer and the second sacrificial layer further includes: patterning the auxiliary layer, the second sacrificial layer Three sacrificial layers and a top support layer, forming a first opening, the first opening exposing the third sacrificial layer and the second sacrificial layer; removing the third sacrificial layer and the second sacrificial layer along the first opening a sacrificial layer exposing the intermediate support layer.
  • the step of patterning the intermediate support layer and removing the first sacrificial layer and the auxiliary layer further includes: patterning the intermediate support layer to form a second opening; Opening removes the first sacrificial layer, exposing the substrate; removing the auxiliary layer.
  • the first opening corresponds to the second opening.
  • it also includes a bottom support layer, the bottom support layer covers the substrate, and exposes the conductive pad, and the step of patterning the middle support layer and removing the first sacrificial layer Afterwards, the bottom support layer is exposed
  • another aspect of the present application also provides a semiconductor structure, which includes: a substrate, a plurality of conductive pads are arranged in the substrate, and the substrate is divided into an array area and a peripheral area.
  • area the first sacrificial layer, the middle support layer, the second sacrificial layer, the top support layer and the third sacrificial layer stacked on the substrate, the surface of the top support layer in the array area and the periphery The surface of the top support layer in the area is even; the lower electrode is arranged in the array area, and runs through the third sacrificial layer, the top support layer, the second sacrificial layer, the middle support layer and the first sacrificial layer, and is connected with the The conductive pad is electrically connected; the auxiliary layer covers the third sacrificial layer and the lower electrode.
  • the surface of the lower electrode is flush with the surface of the third sacrificial layer.
  • a bottom support layer is further included, the bottom support layer covers the substrate and exposes the conductive pad, and the first sacrificial layer covers the bottom support layer.
  • the preparation method of the columnar capacitor array structure of the present application uses the filling of the photoresist layer before removing the mask layer, and adjusts the thickness of the mask layer in the peripheral region and the mask layer in the array region to be the same, thereby avoiding the The difference in thickness of the mask layer affects the thickness of the top support layer, resulting in loss of the top support layer.
  • the preparation method of the present application also forms a third sacrificial layer and an auxiliary layer to double protect the top support layer, prevent the top support layer from being thinned in the subsequent process, and increase the support strength of the top support layer. In this way, it is further avoided that the columnar capacitance is tilted due to insufficient support of the top support layer.
  • FIGS. 1A to 1D are schematic cross-sectional views of the semiconductor structure corresponding to the main process of forming the lower electrode of the columnar capacitor array structure provided by the first embodiment of the present application;
  • Fig. 2 is a schematic diagram of the steps of the method for manufacturing the columnar capacitor array structure provided by the second embodiment of the present application;
  • 3A to 3L are schematic cross-sectional views of main semiconductor structures formed by the preparation method provided in the second embodiment of the present application.
  • FIGS. 1A to 1D are schematic cross-sectional views of a semiconductor structure corresponding to the main process of forming the lower electrode of the columnar capacitor array structure provided by the first embodiment of the present application.
  • a substrate 100 is provided. Several conductive pads 101 are disposed in the substrate 100 .
  • a first sacrificial layer 110 , a middle support layer 120 , a second sacrificial layer 130 , a top support layer 140 and a mask layer 150 are stacked on the substrate 100 .
  • the substrate 100 is divided into an array area 100A and a peripheral area 100B. The thickness of the mask layer 150 located in the array area 100A is smaller than that of the mask layer 150 located in the peripheral area 100B.
  • a plurality of capacitive holes 160 penetrate the mask layer 150 , the top supporting layer 140 , the second sacrificial layer 130 , the middle supporting layer 120 and the first sacrificial layer 110 , exposing the conductive pads 101 .
  • the mask layer 150 is removed.
  • the thickness of the mask layer 150 in the peripheral region 100B is greater than the thickness of the mask layer 150 in the array region 100A, if the mask layer 150 in the peripheral region 100B is completely removed, the As a result, the top support layer 140 in the array area 100A is lost, and the thickness becomes thinner than that in the peripheral area 100B.
  • the conductive material 170 is filled.
  • the conductive material 170 fills the capacitor hole 160 and covers the surface of the top support layer 140 .
  • the thickness of the conductive material 170 deposited in the peripheral region 100B is greater than the thickness of the conductive material deposited in the array region 100A.
  • the conductive material 170 on the surface of the top support layer 140B is removed, and a lower electrode 180 is formed in the capacitor hole 160 .
  • the top layer of the array region 100A will be The thickness of the support layer 140 is further thinned, and even the top support layer 140 of the array region 100A will be completely removed, which makes the support strength of the top of the subsequently formed columnar capacitors insufficient, prone to tilting, and affects the performance of the columnar capacitor array structure. Furthermore, the performance of the memory will be affected, and the yield rate of the memory will be reduced.
  • the second embodiment of the present application also provides a method for preparing a columnar capacitor array structure, which can avoid the loss of the top support layer, ensure the thickness and support strength of the top support layer, avoid its inclination, and improve The performance of the columnar capacitor, thereby improving the yield rate of the memory.
  • the preparation method of the columnar capacitor array structure of the present application uses the filling of the photoresist layer before removing the mask layer, and adjusts the thickness of the mask layer in the peripheral region and the mask layer in the array region to be the same , so as to avoid the impact on the thickness of the top support layer due to the different thickness of the mask layer, resulting in the loss of the top support layer.
  • the preparation method of the present application also forms a third sacrificial layer and an auxiliary layer to double protect the top support layer, prevent the top support layer from being thinned in the subsequent process, and increase the support strength of the top support layer.
  • a third sacrificial layer and an auxiliary layer to double protect the top support layer, prevent the top support layer from being thinned in the subsequent process, and increase the support strength of the top support layer.
  • Fig. 2 is a schematic diagram of the steps of the preparation method of the columnar capacitor array structure provided by the second embodiment of the present application, please refer to Fig. 2, the preparation method includes the following steps: step S20, providing a substrate, and setting a substrate in the substrate Several conductive pads are stacked with a first sacrificial layer, an intermediate support layer, a second sacrificial layer, a top support layer and a mask layer on the substrate, and the substrate is divided into an array area and a peripheral area, located at The thickness of the mask layer in the array area is smaller than the thickness of the mask layer located in the peripheral area.
  • step S21 forming a photoresist layer, the photoresist layer fills the capacitor hole, and covers the mask layer of the array area
  • step S22 In the peripheral area, part of the mask layer is removed, and the upper surface of the remaining mask layer in the peripheral area is flush with the upper surface of the mask layer in the array area
  • step S23 removing the mask layer on the surface of the mask layer photoresist layer, and using the top support layer as an etching stop layer, etch the mask layer
  • step S24 forming a third sacrificial layer, and the third sacrificial layer covers the top support layer
  • step S25 remove the photoresist layer
  • step S26 fill the conductive material in the capacitor hole to form a lower electrode, and the lower electrode is electrically connected to the conductive pad
  • step S27 form
  • 3A to 3L are schematic cross-sectional views of main semiconductor structures formed by the preparation method provided in the second embodiment of the present application.
  • Step S20 please refer to FIG. 3A , providing a substrate 300 .
  • Several conductive pads 301 are disposed in the substrate 300 .
  • a first sacrificial layer 310 , a middle support layer 320 , a second sacrificial layer 330 , a top support layer 340 and a mask layer 350 are stacked on the substrate 300 .
  • the substrate 300 is divided into an array area 300A and a peripheral area 300B.
  • the thickness of the mask layer 350 located in the array area 300A is smaller than that of the mask layer 350 located in the peripheral area 300B.
  • a plurality of capacitive holes 360 penetrate the mask layer 350 , the top supporting layer 340 , the second sacrificial layer 330 , the middle supporting layer 320 and the first sacrificial layer 310 , exposing the conductive pad 301 .
  • the substrate 300 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate or a GOI (Germanium-on-Insulator, germanium-on-insulator) substrate, etc.; the substrate The bottom 300 can also be a substrate including other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc., and the substrate 300 can also be a stacked structure, such as a silicon/germanium silicon stack, etc.; In addition, the substrate 300 can be ion-doped, and can be doped with P-type or N-type doped; multiple peripheral devices can also be formed in the substrate 300, such as field Effect transistors, capacitors, inductors and/or pn junction diodes, etc. In this embodiment, the substrate 300 is a silicon substrate, which also includes other device structures, such as bit line structures, transistor structures, etc., but are not shown because they are irrelevant to this
  • the material of the first sacrificial layer 310 and the second sacrificial layer 330 can be oxide, such as silicon oxide, and the material of the middle support layer 320 and the top support layer 340 can be nitrogen. compounds such as silicon nitride.
  • the material of the mask layer 350 may be polysilicon.
  • a bottom support layer 370 is further disposed on the substrate 300 .
  • the bottom supporting layer 370 covers the substrate 300 and exposes the conductive pad 301 , and the first sacrificial layer 310 covers the bottom supporting layer 370 .
  • the material of the bottom supporting layer 370 may be nitride, such as silicon nitride.
  • Step S21 please refer to FIG. 3B , forming a photoresist layer 380 , the photoresist layer 380 fills the capacitor hole 360 and covers the mask layer 350 of the array region 300A.
  • the upper surface of the photoresist layer 380 is flush with the upper surface of the mask layer 350 of the peripheral region 300B.
  • the capacitor hole 360 is filled with a photoresist layer 380 and the mask layer 350 of the array region 300A is protected.
  • the photoresist material layer is formed first, and then the photoresist material layer is etched back to form the photoresist layer 380 .
  • a photoresist material layer is formed, and the photoresist material layer fills the capacitor hole 360 and covers the mask layer 350 of the array region 300A and the peripheral region 300B;
  • the resist material layer exposes the mask layer 350 of the peripheral region 300B, and the remaining photoresist material layer serves as the photoresist layer 380 .
  • Step S22 please refer to FIG. 3C , in the peripheral region 300B, part of the mask layer 350 is removed, and the remaining upper surface of the mask layer 350 in the peripheral region 300B is in contact with the upper surface of the mask layer 350 in the array region 300A. flush.
  • the photoresist layer 380 serves as a shielding layer for the mask layer 350 of the array region 300A, and the mask layer 350 of the peripheral region 300B is not blocked by the photoresist layer 380, then
  • the mask layer 3500 of the peripheral region 300B may be etched and thinned, so that the remaining upper surface of the mask layer 350 of the peripheral region 300B is flush with the upper surface of the mask layer 350 of the array region 300A.
  • the photoresist layer 380 is also partially removed, that is, the photoresist layer 380 is also thinned.
  • the etching rate of the etching substance on the mask layer 350 is greater than that on the photoresist layer 380 , so as to prevent the photoresist layer 380 from being completely etched.
  • at least one of HBr and NF 3 is used as an etching gas to perform dry etching on the mask layer 350, and the etching rate of the HBr and NF 3 etching gas to the mask layer 350 is greater than The etching rate of the photoresist layer 380.
  • This step is to eliminate the height difference between the peripheral region 300B and the mask layer 350 of the array region 300A.
  • the remaining mask layer 350 of the peripheral region 300B has the same thickness as the mask layer 350 of the array region 300A, so that when the mask layer 350 is subsequently removed, there is no Masking layer 350, and the situation that causes loss of the top support layer 340 of the array region 300A occurs (as shown in FIG. 1B ), avoiding that the thickness of the top support layer 340 of the array region 300A is smaller than the thickness of the top support layer 340 of the peripheral region 300B.
  • step S23 please refer to FIG. 3D , removing the photoresist layer 380 on the surface of the mask layer 350 , and etching the mask layer 350 using the top support layer 340 as an etching stop layer.
  • the photoresist layer 380 on the surface of the mask layer 350 is removed to expose the mask layer 350 , and then the mask layer 350 is etched until the top support layer 340 is exposed.
  • the mask layer 350 is removed by a dry etching process.
  • the etch rate of the etching substance on the mask layer 350 is greater than the etch rate of the photoresist layer 380 and the top support layer 340, so as to prevent the photoresist layer 380 and the top layer from The support layer 340 is etched.
  • the mask layer 350 is a polysilicon mask layer
  • the top support layer 340 is a silicon nitride layer
  • at least one of HBr and NF 3 can be used as the etching gas, dry etching Etching the mask layer 350 to remove the mask layer 350.
  • the etching rate of HBr and NF 3 for etching gas on polysilicon is greater than that on silicon nitride.
  • the thickness of the top support layer 340 in the peripheral region 300B and the array region 300A is reduced to a degree The same, so that after this step, the thickness of the exposed top support layer 340 in the peripheral region 300B and the array region 300A is also the same.
  • Step S24 please refer to FIG. 3E , forming a third sacrificial layer 390 covering the top support layer 340 .
  • the third sacrificial layer 390 is formed by depositing on the surface of the top support layer 340 .
  • the deposition method may be an atomic layer deposition process, a chemical vapor deposition process, a spin coating deposition process, and the like.
  • the third sacrificial layer 390 not only covers the surface of the top support layer 340 , but also covers the top of the photoresist layer 380 .
  • the third sacrificial layer 390 can be an oxide layer, such as a silicon oxide layer, and the material of the third sacrificial layer 390 can be the same as that of the first sacrificial layer 310 and the second sacrificial layer 330 .
  • the method for forming the third sacrificial layer 390 includes the following steps: forming a third sacrificial material layer, the third sacrificial material layer covering the top support layer 340 and the photoresist layer 380; The third sacrificial material layer is thinned to expose the photoresist layer 380 to form the third sacrificial layer 390 .
  • the method for forming the third sacrificial material layer may be an atomic layer deposition process, a chemical vapor deposition process, a spin coating deposition process, or the like.
  • Step S25 please refer to FIG. 3F , removing the photoresist layer 380 .
  • the third sacrificial layer 390 also covers the top of the photoresist layer 380, in this step, the third sacrificial layer 390 is first thinned to expose the photoresist layer 380, and then the photoresist layer 380 is removed.
  • the above photoresist layer 380 Wherein, the photoresist layer 380 may be removed by an ashing process.
  • Step S26 please refer to FIG. 3G , filling the capacitor hole 360 with a conductive material to form a lower electrode 400 , and the lower electrode 400 is electrically connected to the conductive pad 301 .
  • the conductive material can be titanium nitride material or other materials that can be used as the bottom electrode of the columnar capacitor.
  • the conductive material may be deposited by atomic layer deposition to form the lower electrode 400 .
  • the conductive material not only fills the capacitor hole 360 , but also covers the surface of the third sacrificial layer 390 in the array region 300A and the peripheral region 300B.
  • the following steps are also included: forming a lower electrode material layer, the lower electrode material layer not only fills the capacitor hole 360, but also covers the third sacrificial layer 390; thinning the lower electrode material layer, The third sacrificial layer 390 is exposed, and the remaining material layer of the lower electrode serves as the lower electrode 400 .
  • the method of thinning the lower electrode material layer may be etching back to expose the third sacrificial layer 390 and only retain the conductive material in the capacitor hole 360 to form the lower electrode 400 .
  • Step S27 please refer to FIG. 3H , forming an auxiliary layer 410 covering the third sacrificial layer 390 and the lower electrode 400 .
  • an auxiliary layer 410 is deposited on the surface of the third sacrificial layer 390 and the top of the bottom electrode 400 .
  • the auxiliary layer 410 can be a nitride layer, such as a silicon nitride layer.
  • the auxiliary layer 410 and the third sacrificial layer 390 serve as a double protection layer for the top support layer 340 to prevent the top support layer 340 from being thinned in subsequent processes.
  • the auxiliary layer 410 can also protect the lower electrode 400 from being damaged in the subsequent process.
  • Step S28 please refer to FIG. 3I , pattern the auxiliary layer 410 , the third sacrificial layer 390 and the top support layer 340 , and remove the third sacrificial layer 390 and the second sacrificial layer 330 .
  • the auxiliary layer 410, the third sacrificial layer 390 and the top support layer 340 are patterned to form the first opening 341; the third sacrificial layer 390 and the third sacrificial layer 390 are removed along the first opening 341
  • the second sacrificial layer 330 exposes the middle supporting layer 320 .
  • the process of patterning the auxiliary layer 410, the third sacrificial layer 390 and the top support layer 340 can be a photolithography and dry etching process, and the third sacrificial layer 390 and the second sacrificial layer 330 are removed.
  • the method may be a wet etching process.
  • Step S29 referring to FIG. 3J , patterning the intermediate support layer 320 , and removing the first sacrificial layer 310 and the auxiliary layer 410 .
  • the intermediate support layer 320 is patterned to form the second opening 321 .
  • the position of the second opening 321 corresponds to that of the first opening 341 .
  • the first sacrificial layer 310 is removed along the second opening 321 to expose the substrate 300 .
  • the process of patterning the intermediate support layer 320 may be a photolithography and dry etching process, and the method of removing the first sacrificial layer 310 may be a wet etching process.
  • the intermediate support layer 320 is made of the same material as the auxiliary layer 410, and in the step of patterning the intermediate support layer 320, the auxiliary layer 410 can be removed simultaneously to expose the lower electrode. 400 top.
  • the bottom supporting layer 370 is exposed.
  • Step S30 please refer to FIG. 3K , forming a dielectric layer 420 covering exposed surfaces of the substrate 300 , the lower electrode 400 , the middle support layer 320 , and the top support layer 340 .
  • the dielectric layer 420 may be a high-K dielectric layer to improve the performance of the columnar capacitor.
  • the dielectric layer 420 may be a high-K dielectric layer to improve the performance of the columnar capacitor.
  • Al 2 O 3 , HfO 2 , Ta 2 O 5 , ZrO 2 which can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or metal organic chemical vapor deposition (MOCVD).
  • Step S31 please refer to FIG. 3L , forming an upper electrode 430 covering the surface of the dielectric layer 420 .
  • the upper electrode 430 fills the gap among the bottom support layer 370 , the middle support layer 320 and the top support layer 340 , and covers the top support layer 340 .
  • the upper electrode 430, the dielectric layer 420 and the lower electrode 400 form a columnar capacitor.
  • a plurality of columnar capacitor arrays are arranged to form a columnar capacitor array structure.
  • the thicknesses of the mask layer 350 in the peripheral region 300B and the mask layer 350 in the array region 300A are adjusted to be The same, so as to avoid the impact on the thickness of the top support layer 340 due to the different thickness of the mask layer 350 .
  • the preparation method of the present application also forms the third sacrificial layer 390 and the auxiliary layer 410 to provide double protection for the top support layer 340, prevent the top support layer 340 from being thinned in the subsequent process, and increase the thickness of the top support layer. 340, so as to further avoid the inclination of the columnar capacitor due to insufficient support of the top support layer 340.
  • the present application also provides a semiconductor structure.
  • the semiconductor structure includes a substrate 300 in which several conductive pads 301 are disposed, and the substrate is divided into an array area 300A and a peripheral area 300B.
  • the substrate 300 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate or a GOI (Germanium-on-Insulator, germanium-on-insulator) substrate, etc.; the substrate The bottom 300 can also be a substrate including other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc., and the substrate 300 can also be a stacked structure, such as a silicon/germanium silicon stack, etc.; In addition, the substrate 300 can be ion-doped, and can be doped with P-type or N-type doped; multiple peripheral devices can also be formed in the substrate 300, such as field Effect transistors, capacitors, inductors and/or pn junction diodes, etc. In this embodiment, the substrate 300 is a silicon substrate, which also includes other device structures, such as bit line structures, transistor structures, etc., but are not shown because they are irrelevant to this
  • the first sacrificial layer 310 , the middle support layer 320 , the second sacrificial layer 330 , the top support layer 340 and the third sacrificial layer 390 are stacked on the substrate 300 .
  • the surface of the top support layer 340 located in the array area 300A is flush with the surface of the top support layer 340 located in the peripheral area 300B.
  • the material of the first sacrificial layer 310 , the second sacrificial layer 330 and the third sacrificial layer 390 may be oxide, such as silicon oxide.
  • the material of the middle support layer 320 and the top support layer 340 may be nitride, such as silicon nitride.
  • a bottom support layer 370 is further disposed on the substrate 300 .
  • the bottom supporting layer 370 covers the substrate 300 and exposes the conductive pad 301 , and the first sacrificial layer 310 covers the bottom supporting layer 370 .
  • the material of the bottom supporting layer 370 may be nitride, such as silicon nitride.
  • the lower electrode 400 is disposed in the array area 300A, and runs through the third sacrificial layer 390 , the top supporting layer 340 , the second sacrificial layer 330 , the middle supporting layer 320 and the first sacrificial layer 310 , and is connected to the conductive pad 301 electrical connection.
  • the bottom electrode 400 may be a titanium nitride electrode.
  • the top of the lower electrode 390 may be flush with the surface of the third sacrificial layer 390 .
  • the auxiliary layer 410 covers the third sacrificial layer 390 and the bottom electrode 400 .
  • the auxiliary layer 410 can be a nitride layer, such as a silicon nitride layer.
  • the auxiliary layer 410 and the third sacrificial layer 390 serve as a double protection layer for the top support layer 340 to prevent the top support layer 340 from being thinned in subsequent processes.
  • the auxiliary layer 410 can also protect the lower electrode 400 from being damaged in the subsequent process.
  • the surface of the top support layer 340 located in the array area 300A is flush with the surface of the top support layer 340 located in the peripheral area 300B, and the auxiliary layer 410 and the third sacrificial layer 390
  • a double protective layer of the top support layer 340 it prevents the top support layer 340 from being thinned in the subsequent process, ensures the thickness and support strength of the top support layer 340, and avoids the use of the semiconductor structure
  • the columnar capacitors formed as the base are tilted to improve the performance of the subsequently formed memory.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本申请提供一种柱状电容器阵列结构的制备方法及半导体结构，所述制备方法在去除掩膜层之前利用光刻胶层的填充，将所述外围区域的掩膜层与所述阵列区域的掩膜层的厚度调整为相同，从而避免由于掩膜层厚度不同而对顶层支撑层的厚度产生影响，造成顶层支撑层的损失。另外，本申请制备方法还形成第三牺牲层及辅助层，以对顶层支撑层进行双重保护，防止所述顶层支撑层在后续工艺过程中被减薄，以增大顶层支撑层的支撑力度，从而进一步避免由于顶层支撑层支撑力度不够而导致柱状电容倾斜的情况发生。

Description

柱状电容器阵列结构制备方法及半导体结构
相关申请引用说明
本申请要求于2021年08月24日递交的中国专利申请号202110973338.5、申请名为“柱状电容器阵列结构制备方法及半导体结构”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体技术领域，尤其涉及一种柱状电容器阵列结构制备方法及半导体结构。
背景技术
动态随机存储器(Dynamic Random Access Memory，简称：DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。在20nm以下的DRAM制程中，DRAM大多采用堆栈式的电容构造，其电容器(Capacitor)是垂直的高深宽比的圆柱体形状的柱状电容器。
由于所述柱状电容器具有高深宽比，为了增加所述柱状电容器的稳定性，通常需要提供支撑层，以支撑所述柱状电容器。现有的柱子电容器的制造方法的缺点在于，顶部的支撑层易被损耗，顶部的支撑层支撑力不足，可能会导致柱状电容的倾斜、甚至剥离，影响柱状电容器的性能。
因此，如何提供一种柱状电容器阵列结构的制备方法，以解决现有技术中顶部的支撑层易损耗等问题实属必要。
发明内容
本申请实施例提供一种柱状电容器阵列结构制备方法及半导体结构，其能够避免顶层支撑层的损失，进而保证顶部支撑层的厚度及支撑力度，避免柱状电容器发生倾斜，提高柱状电容器阵列结构的性能，进而提高存储器的良率。
根据本申请的一些实施例，本申请一方面提供了一种柱状电容器阵列结构的制备方法，包括：
提供衬底，在所述衬底内设置有若干个导电垫，在所述衬底上堆叠设置有第一牺牲层、中间支撑层、第二牺牲层、顶层支撑层及掩膜层，所述衬底被划分为阵列区域及外围区域，位于所述阵列区域的掩膜层的厚度小于位于所述外围区域的掩膜层的厚度，在所述阵列区域，若干个电容孔贯穿所述掩膜层、顶层支撑层、第二牺牲层、中间支撑层及第一牺牲层，暴露出所述导电垫；形成光刻胶层，所述光刻胶层填充所述电容孔，且覆盖所述阵列区域的掩膜层；在所述外围区域，去除部分所述掩膜层，所述外围区域剩余的掩膜层上表面与所述阵列区域的掩膜层上表面平齐；去除所述掩膜层表面的光刻胶层，并以所述顶层支撑 层为刻蚀停止层，刻蚀所述掩膜层；形成第三牺牲层，所述第三牺牲层覆盖所述顶层支撑层；去除所述光刻胶层；在所述电容孔内填充导电材料，形成下电极，所述下电极与所述导电垫电连接；形成辅助层，所述辅助层覆盖所述第三牺牲层及所述下电极；图案化所述辅助层、第三牺牲层及顶层支撑层，并去除所述第三牺牲层及所述第二牺牲层；图案化所述中间支撑层，并去除所述第一牺牲层及所述辅助层；形成介质层，所述介质层覆盖所述衬底、所述下电极、所述中间支撑层、所述顶层支撑层暴露的表面；形成上电极，所述上电极覆盖所述介质层表面。形成光刻胶层，所述光刻胶层填充所述电容孔，且覆盖所述阵列区域的掩膜层的步骤还包括：形成光刻胶材料层，所述光刻胶材料层填充所述电容孔，且覆盖所述阵列区域及所述外围区域的掩膜层；回刻蚀所述光刻胶材料层，暴露出所述外围区域的掩膜层，以形成所述光刻胶层。
在一实施例中，形成光刻胶层，所述光刻胶层填充所述电容孔，且覆盖所述阵列区域的掩膜层的步骤还包括：形成光刻胶材料层，所述光刻胶材料层填充所述电容孔，且覆盖所述阵列区域及所述外围区域的掩膜层；回刻蚀所述光刻胶材料层，暴露出所述外围区域的掩膜层，以形成所述光刻胶层。
在一实施例中，所述光刻胶层上表面与所述外围区域的掩膜层上表面平齐。
在一实施例中，去除所述掩膜层表面的光刻胶层，并以所述顶层支撑层为刻蚀停止层，刻蚀所述掩膜层的步骤中，刻蚀物质对所述掩膜层的刻蚀速率大于对所述顶层支撑层的刻蚀速率。
在一实施例中，所述掩膜层为多晶硅层，所述顶层支撑层为氮化硅层。
在一实施例中，形成第三牺牲层，所述第三牺牲层覆盖所述顶层支撑层的步骤中，采用旋涂沉积工艺形成所述第三牺牲层。
在一实施例中，所述第三牺牲层为氧化物层。
在一实施例中，形成第三牺牲层，所述第三牺牲层覆盖所述顶层支撑层的步骤还包括：形成第三牺牲材料层，所述第三牺牲材料层覆盖所述顶层支撑层及所述光刻胶层；减薄所述第三牺牲材料层，暴露出所述光刻胶层，以形成所述第三牺牲层。
在一实施例中，在所述电容孔内填充导电材料，形成下电极，所述下电极与所述导电垫电连接的步骤还包括：形成下电极材料层，所述下电极材料层填充所述电容孔，且覆盖所述第三牺牲层；减薄所述下电极材料层，暴露出所述第三牺牲层，以形成所述下电极。
在一实施例中，图案化所述辅助层、第三牺牲层及顶层支撑层，并去除所述第三牺牲层及所述第二牺牲层的步骤还包括：图案化所述辅助层、第三牺牲层及顶层支撑层，形成第一开口，所述第一开口暴露出所述第三牺牲层及所述第二牺牲层；沿所述第一开口去除 所述第三牺牲层及第二牺牲层，暴露出所述中间支撑层。
在一实施例中，图案化所述中间支撑层，并去除所述第一牺牲层及所述辅助层的步骤还包括：图案化所述中间支撑层，形成第二开口；沿所述第二开口去除所述第一牺牲层，暴露出所述衬底；去除所述辅助层。
在一实施例中，所述第一开口与所述第二开口位置对应。
在一实施例中，还包括底部支撑层，所述底部支撑层覆盖所述衬底，且暴露出所述导电垫，在图案化所述中间支撑层，并去除所述第一牺牲层的步骤之后，所述底部支撑层被暴露
根据本申请的一些实施例，本申请另一方面还提供一种半导体结构，其包括：衬底，在所述衬底内设置有若干个导电垫，所述衬底被划分为阵列区域及外围区域；在所述衬底上堆叠设置的第一牺牲层、中间支撑层、第二牺牲层、顶层支撑层及第三牺牲层，位于所述阵列区域的顶层支撑层的表面与位于所述外围区域的顶层支撑层的表面平齐；下电极，设置在所述阵列区域，且贯穿所述第三牺牲层、顶层支撑层、第二牺牲层、中间支撑层及第一牺牲层，并与所述导电垫电连接；辅助层，覆盖所述第三牺牲层及所述下电极。
在一实施例中，所述下电极的表面与所述第三牺牲层的表面平齐。
在一实施例中，还包括底部支撑层，所述底部支撑层覆盖所述衬底，且暴露出所述导电垫，所述第一牺牲层覆盖所述底部支撑层。
本申请柱状电容器阵列结构的制备方法在去除掩膜层之前利用光刻胶层的填充，将所述外围区域的掩膜层与所述阵列区域的掩膜层的厚度调整为相同，从而避免由于掩膜层厚度不同而对顶层支撑层的厚度产生影响，造成顶层支撑层的损失。另外，本申请制备方法还形成第三牺牲层及辅助层，以对顶层支撑层进行双重保护，防止所述顶层支撑层在后续工艺过程中被减薄，以增大顶层支撑层的支撑力度，从而进一步避免由于顶层支撑层支撑力度不够而导致柱状电容倾斜的情况发生。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A～图1D是本申请第一实施例提供的形成柱状电容器阵列结构下电极的主要工艺对应的半导体结构的截面示意图；
图2是本申请第二实施例提供的柱状电容器阵列结构的制备方法的步骤示意图；
图3A～图3L是本申请第二实施例提供的制备方法形成的主要的半导体结构截面示意图。
具体实施方式
为了使本申请的目的、技术手段及其效果更加清楚明确，以下将结合附图对本申请作进一步地阐述。应当理解，此处所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例，并不用于限定本申请。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图1A～图1D是本申请第一实施例提供的形成柱状电容器阵列结构下电极的主要工艺对应的半导体结构的截面示意图。
请参阅图1A，提供衬底100。在所述衬底100内设置有若干个导电垫101。在所述衬底100上堆叠设置有第一牺牲层110、中间支撑层120、第二牺牲层130、顶层支撑层140及掩膜层150。所述衬底100被划分为阵列区域100A及外围区域100B，位于所述阵列区域100A的掩膜层150的厚度小于位于所述外围区域100B的掩膜层150的厚度。在所述阵列区域100A，若干个电容孔160贯穿所述掩膜层150、顶层支撑层140、第二牺牲层130、中间支撑层120及第一牺牲层110，暴露出所述导电垫101。
请参阅图1B，去除所述掩膜层150。在该步骤中，由于位于所述外围区域100B的掩膜层150的厚度大于位于所述阵列区域100A的掩膜层150的厚度，若完全去除所述外围区域100B所述掩膜层150，会导致阵列区域100A的顶层支撑层140损失，厚度相较于外围区域100B变薄。
请参阅图1C，填充导电材料170。所述导电材料170填充所述电容孔160并覆盖所述顶层支撑层140表面。在该步骤中，外围区域100B沉积的导电材料170的厚度大于所述阵列区域100A沉积的导电材料的厚度。
请参阅图1D，去除所述顶层支撑层140B表面的导电材料170，在所述电容孔160内形成下电极180。在该步骤中，由于外围区域100B沉积的导电材料170的厚度大于所述阵列区域100A沉积的导电材料的厚度，若完全去除所述外围区域100B的导电材料，会导致所述阵列区域100A的顶层支撑层140的厚度被进一步减薄，甚至所述阵列区域100A的顶层支撑层140会被完全去除，这使得后续形成的柱状电容器顶部支撑力度不够，易发生倾斜，影响柱状电容器阵列结构的性能，进而会影响存储器的性能，降低存储器的良率。
为了解决上述技术问题，本申请第二实施例还提供了一种柱状电容器阵列结构的制备方法，其能够避免顶层支撑层的损失，保证顶层支撑层的厚度及支撑力度，避免其发生倾斜，提高柱状电容器的性能，进而提高存储器的良率。具体地说，本申请柱状电容器阵列 结构的制备方法在去除掩膜层之前利用光刻胶层的填充，将所述外围区域的掩膜层与所述阵列区域的掩膜层的厚度调整为相同，从而避免由于掩膜层厚度不同而对顶层支撑层的厚度产生影响，造成顶层支撑层的损失。另外，本申请制备方法还形成第三牺牲层及辅助层，以对顶层支撑层进行双重保护，防止所述顶层支撑层在后续工艺过程中被减薄，以增大顶层支撑层的支撑力度，从而进一步避免由于顶层支撑层支撑力度不够而导致柱状电容倾斜的情况发生
图2是本申请第二实施例提供的柱状电容器阵列结构的制备方法的步骤示意图，请参阅图2，所述制备方法包括如下步骤：步骤S20，提供衬底，在所述衬底内设置有若干个导电垫，在所述衬底上堆叠设置有第一牺牲层、中间支撑层、第二牺牲层、顶层支撑层及掩膜层，所述衬底被划分为阵列区域及外围区域，位于所述阵列区域的掩膜层的厚度小于位于所述外围区域的掩膜层的厚度，在所述阵列区域，若干个电容孔贯穿所述掩膜层、顶层支撑层、第二牺牲层、中间支撑层及第一牺牲层，暴露出所述导电垫；步骤S21，形成光刻胶层，所述光刻胶层填充所述电容孔，且覆盖所述阵列区域的掩膜层；步骤S22，在所述外围区域，去除部分所述掩膜层，所述外围区域剩余的掩膜层上表面与所述阵列区域的掩膜层上表面平齐；步骤S23，去除所述掩膜层表面的光刻胶层，并以所述顶层支撑层为刻蚀停止层，刻蚀所述掩膜层；步骤S24，形成第三牺牲层，所述第三牺牲层覆盖所述顶层支撑层；步骤S25，去除所述光刻胶层；步骤S26，在所述电容孔内填充导电材料，形成下电极，所述下电极与所述导电垫电连接；步骤S27，形成辅助层，所述辅助层覆盖所述第三牺牲层及所述下电极；步骤S28，图案化所述辅助层、第三牺牲层及顶层支撑层，并去除所述第三牺牲层及所述第二牺牲层；步骤S29，图案化所述中间支撑层，并去除所述第一牺牲层及所述辅助层；步骤S30，形成介质层，所述介质层覆盖所述衬底、所述下电极、所述中间支撑层、所述顶层支撑层暴露的表面；步骤S31，形成上电极，所述上电极覆盖所述介质层表面。
图3A～图3L是本申请第二实施例提供的制备方法形成的主要的半导体结构截面示意图。
步骤S20，请参阅图3A，提供衬底300。在所述衬底300内设置有若干个导电垫301。在所述衬底300上堆叠设置有第一牺牲层310、中间支撑层320、第二牺牲层330、顶层支撑层340及掩膜层350。所述衬底300被划分为阵列区域300A及外围区域300B，位于所述阵列区域300A的掩膜层350的厚度小于位于所述外围区域300B的掩膜层350的厚度。在所述阵列区域300A，若干个电容孔360贯穿所述掩膜层350、顶层支撑层340、第二牺牲层330、中间支撑层320及第一牺牲层310，暴露出所述导电垫301。
所述衬底300可以包括硅衬底、锗(Ge)衬底、锗化硅(SiGe)衬底、SOI衬底或 GOI(Germanium-on-Insulator，绝缘体上锗)衬底等；所述衬底300还可以为包括其他元素半导体或化合物半导体的衬底，例如砷化镓、磷化铟或碳化硅等，所述衬底300还可以为叠层结构，例如硅/锗硅叠层等；另外，所述衬底300可以为进行离子掺杂后的衬底，可以进行P型掺杂，也可以进行N型掺杂；所述衬底300中还可以形成有多个外围器件，如场效应晶体管、电容、电感和/或pn结二极管等。本实施例中，所述衬底300为硅衬底，其内部还包括其他器件结构，例如位线结构，晶体管结构等，但由于与本申请无关，所以不绘示。
在本实施例中，所述第一牺牲层310及所述第二牺牲层330的材料可为氧化物，例如氧化硅，所述中间支撑层320及所述顶层支撑层340的材料可为氮化物，例如氮化硅。所述掩膜层350的材料可为多晶硅。
在本实施例中，在所述衬底300上还设置有底部支撑层370。所述底部支撑层370覆盖所述衬底300，且暴露出所述导电垫301，所述第一牺牲层310覆盖所述底部支撑层370。所述底部支撑层370的材料可以为氮化物，例如氮化硅。
步骤S21，请参阅图3B，形成光刻胶层380，所述光刻胶层380填充所述电容孔360，且覆盖所述阵列区域300A的掩膜层350。在本实施例中，所述光刻胶层380上表面与所述外围区域300B的掩膜层350上表面平齐。
在该步骤中，利用光刻胶层380填充所述电容孔360，且保护阵列区域300A的掩膜层350。在一些实施例中，先形成光刻胶材料层，再回刻蚀所述光刻胶材料层，形成所述光刻胶层380。具体地说，形成光刻胶材料层，所述光刻胶材料层填充所述电容孔360，且覆盖所述阵列区域300A及所述外围区域300B的掩膜层350；回刻蚀所述光刻胶材料层，暴露出所述外围区域300B的掩膜层350，剩余的所述光刻材料层作为所述光刻胶层380。
步骤S22，请参阅图3C，在所述外围区域300B，去除部分所述掩膜层350，所述外围区域300B剩余的掩膜层350上表面与所述阵列区域300A的掩膜层350上表面平齐。
在该步骤中，所述光刻胶层380作为所述阵列区域300A的掩膜层350的遮挡层，所述外围区域300B的掩膜层350并未被所述光刻胶层380遮挡，则可刻蚀减薄所述外围区域300B的掩膜层3500，使所述外围区域300B剩余的掩膜层350上表面与所述阵列区域300A的掩膜层350上表面平齐。在本申请一些实施例中，受限于实际工艺，在去除所述外围区域300B的所述掩膜层350时，所述光刻胶层380也被部分去除，即所述光刻胶层380也被减薄。
在该步骤中，刻蚀物质对所述掩膜层350的刻蚀速率大于对所述光刻胶层380的刻蚀速率，以避免所述光刻胶层380被全部刻蚀。例如，采用HBr与NF 3中的至少一种作为刻蚀气体对所述掩膜层350进行干法刻蚀，所述HBr与NF 3刻蚀气体对所述掩膜层350的刻 蚀速率大于对所述光刻胶层380的刻蚀速率。
该步骤的目的在于，消除外围区域300B与阵列区域300A的掩膜层350的高度差。所述外围区域300B剩余的掩膜层350与所述阵列区域300A的掩膜层350的厚度相同，使得在后续去除所述掩膜层350时，不存在为了完全去除所述外围区域300B所述掩膜层350，而导致阵列区域300A的顶层支撑层340损失的情况发生(如图1B所示)，避免阵列区域300A的顶层支撑层340的厚度小于外围区域300B的顶层支撑层340的厚度。
步骤S23，请参阅图3D，去除所述掩膜层350表面的光刻胶层380，并以所述顶层支撑层340为刻蚀停止层，刻蚀所述掩膜层350。
在该步骤中，去除所述掩膜层350表面的光刻胶层380，暴露出所述掩膜层350，再刻蚀所述掩膜层350，直至暴露出所述顶层支撑层340。
在该步骤中，采用干法刻蚀工艺去除所述掩膜层350。其中，刻蚀物质对所述掩膜层350的刻蚀速率大于对所述光刻胶层380及所述顶层支撑层340的刻蚀速率，以避免所述光刻胶层380及所述顶层支撑层340被刻蚀。在本实施例中，所述掩膜层350为多晶硅掩膜层，所述顶层支撑层340为氮化硅层，则可采用HBr与NF 3中的至少一种作为刻蚀气体，干法刻蚀所述掩膜层350，以去除所述掩膜层350。HBr与NF 3对刻蚀气体对多晶硅的刻蚀速率大于对氮化硅的刻蚀速率。
在该步骤中，由于所述外围区域300B剩余的掩膜层350与所述阵列区域300A的掩膜层350的厚度相同，则外围区域300B与阵列区域300A的所述顶层支撑层340减薄程度相同，使得在该步骤之后，外围区域300B与阵列区域300A暴露的顶层支撑层340的厚度也相同。
步骤S24，请参阅图3E，形成第三牺牲层390，所述第三牺牲层390覆盖所述顶层支撑层340。
在该步骤中，在所述顶层支撑层340表面沉积形成所述第三牺牲层390。沉积方法可为原子层沉积工艺、化学气相沉积工艺、旋涂沉积工艺等。在一些实施例中，受限于实际工艺，所述第三牺牲层390不仅覆盖所述顶层支撑层340的表面，还覆盖所述光刻胶层380的顶部。所述第三牺牲层390可为氧化物层，例如氧化硅层，所述第三牺牲层390可与所述第一牺牲层310及第二牺牲层330的材料相同。
在一些实施例中，形成所述第三牺牲层390的方法包括如下步骤：形成第三牺牲材料层，所述第三牺牲材料层覆盖所述顶层支撑层340及所述光刻胶层380；减薄所述第三牺牲材料层，暴露出所述光刻胶层380，以形成所述第三牺牲层390。形成所述第三牺牲材料层的方法可为原子层沉积工艺、化学气相沉积工艺、旋涂沉积工艺等。
步骤S25，请参阅图3F，去除所述光刻胶层380。
由于所述第三牺牲层390还覆盖所述光刻胶层380的顶部，则在该步骤中，首先减薄所述第三牺牲层390，暴露出所述光刻胶层380，再去除所述光刻胶层380。其中，可采用灰化工艺去除所述光刻胶层380。
步骤S26，请参阅图3G，在所述电容孔360内填充导电材料，形成下电极400，所述下电极400与所述导电垫301电连接。
所述导电材料可为氮化钛材料或者其他能够作为柱状电容器下电极的材料。在该步骤中，可采用原子层沉积工艺沉积所述导电材料，形成所述下电极400。在一些实施例中，受限于实际工艺，所述导电材料不仅填充所述电容孔360，还覆盖所述阵列区域300A及所述外围区域300B的第三牺牲层390的表面。则在该步骤中，还包括如下步骤：形成下电极材料层，所述下电极材料层不仅填充所述电容孔360，还覆盖所述第三牺牲层390；减薄所述下电极材料层，暴露出所述第三牺牲层390，剩余的所述下电极材料层作为所述下电极400。减薄所述下电极材料层的方法可为回刻蚀，暴露出所述第三牺牲层390，仅保留位于所述电容孔360内的导电材料，形成所述下电极400。
步骤S27，请参阅图3H，形成辅助层410，所述辅助层410覆盖所述第三牺牲层390及所述下电极400。
在该步骤中，在所述第三牺牲层390表面及所述下电极400顶部沉积辅助层410。所述辅助层410可为氮化物层，例如氮化硅层。所述辅助层410与所述第三牺牲层390作为所述顶层支撑层340的双重保护层，防止所述顶层支撑层340在后续工艺过程中被减薄。另外，所述辅助层410还可保护所述下电极400，避免其在后续工艺过程中被损伤。
步骤S28，请参阅图3I，图案化所述辅助层410、第三牺牲层390及顶层支撑层340，并去除所述第三牺牲层390及所述第二牺牲层330。
具体地说，在该步骤中，图案化所述辅助层410、第三牺牲层390及顶层支撑层340，形成第一开口341；沿所述第一开口341去除所述第三牺牲层390及所述第二牺牲层330，暴露出所述中间支撑层320。其中，图案化所述辅助层410、第三牺牲层390及顶层支撑层340的工艺可为光刻及干法刻蚀工艺，去除所述第三牺牲层390及所述第二牺牲层330的方法可为湿法刻蚀工艺。
步骤S29，请参阅图3J，图案化所述中间支撑层320，并去除所述第一牺牲层310及所述辅助层410。
具体地说，在该步骤中，图案化所述中间支撑层320，形成第二开口321。其中，所述第二开口321与所述第一开口341位置对应。沿所述第二开口321去除所述第一牺牲层310， 暴露出所述衬底300。图案化所述中间支撑层320的工艺可为光刻及干法刻蚀工艺，去除所述第一牺牲层310的方法可为湿法刻蚀工艺。
在该步骤中，所述中间支撑层320与所述辅助层410的材料相同，则在图案化所述中间支撑层320的步骤中，可同步去除所述辅助层410，暴露出所述下电极400的顶部。
在本实施例中，去除所述第一牺牲层310后，所述底部支撑层370被暴露。
步骤S30，请参阅图3K，形成介质层420，所述介质层420覆盖所述衬底300、所述下电极400、所述中间支撑层320、所述顶层支撑层340暴露的表面。
其中，所述介质层420可为高K介质层，以提高柱状电容器的性能。例如，Al 2O 3,HfO 2,Ta 2O 5,ZrO 2，其可利用化学气相沉积(CVD)工艺、原子层沉积(ALD)工艺或金属有机物化学气相淀积(MOCVD)工艺等形成。
步骤S31，请参阅图3L，形成上电极430，所述上电极430覆盖所述介质层420表面。
在本实施例中，所述上电极430填充所述底部支撑层370、中间支撑层320及顶层支撑层340之间的空隙，并覆盖所述顶层支撑层340。所上电极430、介质层420及所述下电极400构成柱状电容器。多个所述柱状电容器阵列排布构成柱状电容器阵列结构。
本申请柱状电容器阵列结构的制备方法在去除掩膜层之前利用光刻胶层380的填充，将所述外围区域300B的掩膜层350与所述阵列区域300A的掩膜层350的厚度调整为相同，从而避免由于掩膜层350厚度不同而对顶层支撑层340的厚度产生影响。另外，本申请制备方法还形成第三牺牲层390及辅助层410，以对顶层支撑层340进行双重保护，防止所述顶层支撑层340在后续工艺过程中被减薄，以增大顶层支撑层340的支撑力度，从而进一步避免由于顶层支撑层340支撑力度不够而导致柱状电容倾斜的情况发生。
本申请还提供一种半导体结构。请参阅图3H，所述半导体结构包括衬底300，在所述衬底300内设置有若干个导电垫301，所述衬底被划分为阵列区域300A及外围区域300B。
所述衬底300可以包括硅衬底、锗(Ge)衬底、锗化硅(SiGe)衬底、SOI衬底或GOI(Germanium-on-Insulator，绝缘体上锗)衬底等；所述衬底300还可以为包括其他元素半导体或化合物半导体的衬底，例如砷化镓、磷化铟或碳化硅等，所述衬底300还可以为叠层结构，例如硅/锗硅叠层等；另外，所述衬底300可以为进行离子掺杂后的衬底，可以进行P型掺杂，也可以进行N型掺杂；所述衬底300中还可以形成有多个外围器件，如场效应晶体管、电容、电感和/或pn结二极管等。本实施例中，所述衬底300为硅衬底，其内部还包括其他器件结构，例如位线结构，晶体管结构等，但由于与本申请无关，所以不绘示。
在所述衬底300上堆叠设置的第一牺牲层310、中间支撑层320、第二牺牲层330、顶层支撑层340及第三牺牲层390。位于所述阵列区域300A的顶层支撑层340的表面与位于 所述外围区域300B的顶层支撑层340的表面平齐。
在本实施例中，所述第一牺牲层310、所述第二牺牲层330及所述第三牺牲层390的材料可为氧化物，例如氧化硅。所述中间支撑层320及所述顶层支撑鞥340的材料可为氮化物，例如氮化硅。
在本实施例中，在所述衬底300上还设置有底部支撑层370。所述底部支撑层370覆盖所述衬底300，且暴露出所述导电垫301，所述第一牺牲层310覆盖所述底部支撑层370。所述底部支撑层370的材料可以为氮化物，例如氮化硅。
下电极400设置在所述阵列区域300A，且贯穿所述第三牺牲层390、顶层支撑层340、第二牺牲层330、中间支撑层320及第一牺牲层310，并与所述导电垫301电连接。所述下电极400可为氮化钛电极。所述下电极390的顶部可与所述第三牺牲层390的表面平齐。
所述辅助层410覆盖所述第三牺牲层390及所述下电极400。所述辅助层410可为氮化物层，例如氮化硅层。所述辅助层410与所述第三牺牲层390作为所述顶层支撑层340的双重保护层，防止所述顶层支撑层340在后续工艺过程中被减薄。另外，所述辅助层410还可保护所述下电极400，避免其在后续工艺过程中被损伤。
在本申请半导体结构中，位于所述阵列区域300A的顶层支撑层340的表面与位于所述外围区域300B的顶层支撑层340的表面平齐，所述辅助层410与所述第三牺牲层390作为所述顶层支撑层340的双重保护层，防止所述顶层支撑层340在后续工艺过程中被减薄，保证了所述顶层支撑层340的厚度及支撑力度，且避免了以所述半导体结构为基础而形成的柱状电容器发生倾斜，提高后续形成的存储器的性能。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (16)

  1. 一种柱状电容器阵列结构的制备方法，包括：
    提供衬底，在所述衬底内设置有若干个导电垫，在所述衬底上堆叠设置有第一牺牲层、中间支撑层、第二牺牲层、顶层支撑层及掩膜层，所述衬底被划分为阵列区域及外围区域，位于所述阵列区域的掩膜层的厚度小于位于所述外围区域的掩膜层的厚度，在所述阵列区域，若干个电容孔贯穿所述掩膜层、顶层支撑层、第二牺牲层、中间支撑层及第一牺牲层，暴露出所述导电垫；
    形成光刻胶层，所述光刻胶层填充所述电容孔，且覆盖所述阵列区域的掩膜层；
    在所述外围区域，去除部分所述掩膜层，所述外围区域剩余的掩膜层上表面与所述阵列区域的掩膜层上表面平齐；
    去除所述掩膜层表面的光刻胶层，并以所述顶层支撑层为刻蚀停止层，刻蚀所述掩膜层；
    形成第三牺牲层，所述第三牺牲层覆盖所述顶层支撑层；
    去除所述光刻胶层；
    在所述电容孔内填充导电材料，形成下电极，所述下电极与所述导电垫电连接；
    形成辅助层，所述辅助层覆盖所述第三牺牲层及所述下电极；
    图案化所述辅助层、第三牺牲层及顶层支撑层，并去除所述第三牺牲层及所述第二牺牲层；
    图案化所述中间支撑层，并去除所述第一牺牲层及所述辅助层；
    形成介质层，所述介质层覆盖所述衬底、所述下电极、所述中间支撑层、所述顶层支撑层暴露的表面；
    形成上电极，所述上电极覆盖所述介质层表面。
  2. 根据权利要求1所述的柱状电容器阵列结构的制备方法，其中，形成光刻胶层，所述光刻胶层填充所述电容孔，且覆盖所述阵列区域的掩膜层的步骤还包括：
    形成光刻胶材料层，所述光刻胶材料层填充所述电容孔，且覆盖所述阵列区域及所述外围区域的掩膜层；
    回刻蚀所述光刻胶材料层，暴露出所述外围区域的掩膜层，以形成所述光刻胶层。
  3. 根据权利要求2所述的柱状电容器阵列结构的制备方法，进一步，所述光刻胶层上表面与所述外围区域的掩膜层上表面平齐。
  4. 根据权利要求1所述的柱状电容器阵列结构的制备方法，其中，去除所述掩膜层表面的光刻胶层，并以所述顶层支撑层为刻蚀停止层，刻蚀所述掩膜层的步骤中，刻蚀物质对所述掩膜层的刻蚀速率大于对所述顶层支撑层的刻蚀速率。
  5. 根据权利要求4所述的柱状电容器阵列结构的制备方法，进一步，所述掩膜层为多晶硅 层，所述顶层支撑层为氮化硅层。
  6. 根据权利要求1所述的柱状电容器阵列结构的制备方法，其中，形成第三牺牲层，所述第三牺牲层覆盖所述顶层支撑层的步骤中，采用旋涂沉积工艺形成所述第三牺牲层。
  7. 根据权利要求6所述的柱状电容器阵列结构的制备方法，其中，所述第三牺牲层为氧化物层。
  8. 根据权利要求1所述的柱状电容器阵列结构的制备方法，其中，形成第三牺牲层，所述第三牺牲层覆盖所述顶层支撑层的步骤还包括：
    形成第三牺牲材料层，所述第三牺牲材料层覆盖所述顶层支撑层及所述光刻胶层；
    减薄所述第三牺牲材料层，暴露出所述光刻胶层，以形成所述第三牺牲层。
  9. 根据权利要求1所述的柱状电容器阵列结构的制备方法，其中，在所述电容孔内填充导电材料，形成下电极，所述下电极与所述导电垫电连接的步骤还包括：
    形成下电极材料层，所述下电极材料层填充所述电容孔，且覆盖所述第三牺牲层；
    减薄所述下电极材料层，暴露出所述第三牺牲层，以形成所述下电极。
  10. 根据权利要求1所述的柱状电容器阵列结构的制备方法，其中，图案化所述辅助层、第三牺牲层及顶层支撑层，并去除所述第三牺牲层及所述第二牺牲层的步骤还包括：
    图案化所述辅助层、第三牺牲层及顶层支撑层，形成第一开口，所述第一开口暴露出所述第三牺牲层及所述第二牺牲层；
    沿所述第一开口去除所述第三牺牲层及第二牺牲层，暴露出所述中间支撑层。
  11. 根据权利要求10所述的柱状电容器阵列结构的制备方法，其中，图案化所述中间支撑层，并去除所述第一牺牲层及所述辅助层的步骤还包括：图案化所述中间支撑层，形成第二开口；
    沿所述第二开口去除所述第一牺牲层，暴露出所述衬底；
    去除所述辅助层。
  12. 根据权利要求11所述的柱状电容器阵列结构的制备方法，其中，所述第一开口与所述第二开口位置对应。
  13. 根据权利要求1所述的柱状电容器阵列结构的制备方法，还包括底部支撑层，所述底部支撑层覆盖所述衬底，且暴露出所述导电垫，在图案化所述中间支撑层，并去除所述第一牺牲层的步骤之后，所述底部支撑层被暴露。
  14. 一种半导体结构，包括：
    衬底，在所述衬底内设置有若干个导电垫，所述衬底被划分为阵列区域及外围区域；
    在所述衬底上堆叠设置的第一牺牲层、中间支撑层、第二牺牲层、顶层支撑层及第三牺 牲层，位于所述阵列区域的顶层支撑层的表面与位于所述外围区域的顶层支撑层的表面平齐；
    下电极，设置在所述阵列区域，且贯穿所述第三牺牲层、顶层支撑层、第二牺牲层、中间支撑层及第一牺牲层，并与所述导电垫电连接；
    辅助层，覆盖所述第三牺牲层及所述下电极。
  15. 根据权利要求14所述的半导体结构，其中，所述下电极的表面与所述第三牺牲层的表面平齐。
  16. 根据权利要求14所述的半导体结构，还包括底部支撑层，所述底部支撑层覆盖所述衬底，且暴露出所述导电垫，所述第一牺牲层覆盖所述底部支撑层。
PCT/CN2022/072659 2021-08-24 2022-01-19 柱状电容器阵列结构制备方法及半导体结构 WO2023024429A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/151,469 US20230298899A1 (en) 2021-08-24 2023-01-09 Method for fabricating array structure of columnar capacitor and semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110973338.5 2021-08-24
CN202110973338.5A CN116133376A (zh) 2021-08-24 2021-08-24 柱状电容器阵列结构制备方法及半导体结构

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/151,469 Continuation US20230298899A1 (en) 2021-08-24 2023-01-09 Method for fabricating array structure of columnar capacitor and semiconductor structure

Publications (1)

Publication Number Publication Date
WO2023024429A1 true WO2023024429A1 (zh) 2023-03-02

Family

ID=85321498

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/072659 WO2023024429A1 (zh) 2021-08-24 2022-01-19 柱状电容器阵列结构制备方法及半导体结构

Country Status (3)

Country Link
US (1) US20230298899A1 (zh)
CN (1) CN116133376A (zh)
WO (1) WO2023024429A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115955840A (zh) * 2023-03-09 2023-04-11 长鑫存储技术有限公司 半导体结构及其形成方法
CN116033748A (zh) * 2023-03-24 2023-04-28 长鑫存储技术有限公司 半导体结构及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120050327A (ko) * 2010-11-10 2012-05-18 에스케이하이닉스 주식회사 커패시터의 스토리지노드 형성 방법
CN103681676A (zh) * 2012-08-29 2014-03-26 三星电子株式会社 包括用于电极的支撑件的半导体器件及其形成方法
US20170077102A1 (en) * 2015-09-11 2017-03-16 Samsung Electronics Co., Ltd. Semiconductor device having supporters and method of manufacturing the same
CN110010604A (zh) * 2017-12-22 2019-07-12 三星电子株式会社 半导体器件及其制造方法
CN111725139A (zh) * 2019-03-21 2020-09-29 三星电子株式会社 制造具有支撑图案的半导体装置的方法
US20210151439A1 (en) * 2019-11-19 2021-05-20 Samsung Electronics Co., Ltd. Semiconductor device including storage node electrode having filler and method for manufacturing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120050327A (ko) * 2010-11-10 2012-05-18 에스케이하이닉스 주식회사 커패시터의 스토리지노드 형성 방법
CN103681676A (zh) * 2012-08-29 2014-03-26 三星电子株式会社 包括用于电极的支撑件的半导体器件及其形成方法
US20170077102A1 (en) * 2015-09-11 2017-03-16 Samsung Electronics Co., Ltd. Semiconductor device having supporters and method of manufacturing the same
CN110010604A (zh) * 2017-12-22 2019-07-12 三星电子株式会社 半导体器件及其制造方法
CN111725139A (zh) * 2019-03-21 2020-09-29 三星电子株式会社 制造具有支撑图案的半导体装置的方法
US20210151439A1 (en) * 2019-11-19 2021-05-20 Samsung Electronics Co., Ltd. Semiconductor device including storage node electrode having filler and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115955840A (zh) * 2023-03-09 2023-04-11 长鑫存储技术有限公司 半导体结构及其形成方法
CN115955840B (zh) * 2023-03-09 2023-06-02 长鑫存储技术有限公司 半导体结构及其形成方法
CN116033748A (zh) * 2023-03-24 2023-04-28 长鑫存储技术有限公司 半导体结构及其制备方法
CN116033748B (zh) * 2023-03-24 2023-09-15 长鑫存储技术有限公司 半导体结构及其制备方法

Also Published As

Publication number Publication date
US20230298899A1 (en) 2023-09-21
CN116133376A (zh) 2023-05-16

Similar Documents

Publication Publication Date Title
WO2023024428A1 (zh) 柱状电容器阵列结构的制备方法及半导体结构
US7387939B2 (en) Methods of forming semiconductor structures and capacitor devices
WO2023024429A1 (zh) 柱状电容器阵列结构制备方法及半导体结构
US8878272B2 (en) Semiconductor device having stacked storage nodes of capacitors in cell region separated from peripheral region
US8691680B2 (en) Method for fabricating memory device with buried digit lines and buried word lines
US9337089B2 (en) Method for fabricating a semiconductor device having a bit line contact
US11011525B2 (en) Landing pad structure and method of manufacturing the same
US9236427B2 (en) Multi-material structures and capacitor-containing semiconductor constructions
US20090179246A1 (en) Semiconductor device and method for manufacturing the same
US9305927B2 (en) Semiconductor device and method of manufacturing the same
WO2023151356A1 (zh) 电容器及其制备方法
KR102462439B1 (ko) 반도체 소자의 제조 방법
CN112397384A (zh) 制造半导体器件的方法
US6221714B1 (en) Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole
US20230223429A1 (en) Semiconductor structure and manufacturing method thereof
WO2022236980A1 (zh) 存储器的制作方法
US11289493B2 (en) Patterning method
US20230015120A1 (en) Method for fabricating array structure of columnar capacitor and semiconductor structure
CN114361111A (zh) 半导体结构及其制备方法
WO2020125515A1 (zh) 半导体结构及其形成方法
US20240032283A1 (en) Semiconductor device with air gap and method for preparing the same
WO2023159967A1 (zh) 半导体结构及其形成方法、动态随机存储器的制造方法
WO2024041040A1 (zh) 半导体器件及其制备方法
US20220044940A1 (en) Semiconductor structure and manufacturing method thereof
WO2023133996A1 (zh) 半导体结构及半导体结构的制造方法

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE