WO2023022179A1 - 半導体モジュールおよびその製造方法、電子装置、電子モジュール、ならびに電子装置の製造方法 - Google Patents

半導体モジュールおよびその製造方法、電子装置、電子モジュール、ならびに電子装置の製造方法 Download PDF

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Publication number
WO2023022179A1
WO2023022179A1 PCT/JP2022/031116 JP2022031116W WO2023022179A1 WO 2023022179 A1 WO2023022179 A1 WO 2023022179A1 JP 2022031116 W JP2022031116 W JP 2022031116W WO 2023022179 A1 WO2023022179 A1 WO 2023022179A1
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Prior art keywords
die
bridge
electrode
chip
connection portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/JP2022/031116
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English (en)
French (fr)
Japanese (ja)
Inventor
洋一郎 栗田
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Aoi Electronics Co Ltd
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Aoi Electronics Co Ltd
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Filing date
Publication date
Application filed by Aoi Electronics Co Ltd filed Critical Aoi Electronics Co Ltd
Priority to JP2023542430A priority Critical patent/JP7496942B2/ja
Priority to KR1020247004921A priority patent/KR20240046499A/ko
Priority to CN202280054608.5A priority patent/CN117769896A/zh
Priority to US18/684,440 priority patent/US20250015002A1/en
Publication of WO2023022179A1 publication Critical patent/WO2023022179A1/ja
Anticipated expiration legal-status Critical
Priority to JP2024085925A priority patent/JP7832985B2/ja
Priority to JP2025252176A priority patent/JP2026031831A/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H10W74/473—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins containing a filler
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4204—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms
    • G02B6/4214—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4246—Bidirectionally operating package structures
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4274—Electrical aspects
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/733—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a semiconductor module and its manufacturing method.
  • Patent Literature 1 describes a semiconductor package in which two IC chips are connected by a bridge (nested component) molded together with an interposer.
  • Patent Document 2 describes a semiconductor package in which two IC chips are electrically connected via a bridge integrally formed with an interposer via an underfill material.
  • the inventors of the present application have studied a semiconductor package having a plurality of IC chips connected via a bridge and a semiconductor module using the same, and found that there is room for improvement in the above-described semiconductor package and semiconductor module. I found out. For example, when electrically connecting two IC chips via a bridge integrated with an interposer, it is difficult to precisely align the terminals of the two IC chips with the terminals of the bridge. In this case, the density of the terminal portion electrically connecting the IC chip and the bridge is restricted.
  • the present invention has been made in such a situation, and one of the exemplary purposes of certain aspects thereof is to provide a technology that enables bonding of IC chips and bridges at a higher density.
  • a method of manufacturing a semiconductor module includes: (a) a first connection portion including a first columnar connection portion extending in an out-of-plane direction of the first support on a first surface of a first support; (b) a first IC chip and a first die electrode connected to the first IC chip; providing a semiconductor die and a second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip, wherein the first die electrode is disposed on the first connection portion; (c) mounting each of the first semiconductor die and the second semiconductor die on the first support such that the second die electrode is disposed on the second connection portion; (b) after the step, sealing the first semiconductor die, the second semiconductor die, the first connection portion, and the second connection portion with a first sealing body; (d) the (c) (e) removing the first supporting member and exposing a portion of the first columnar connection portion and a portion of the second columnar connection portion from the first sealing member after the step;
  • a bridge including a first bridge electrode connected to one
  • a method of manufacturing a semiconductor module includes: (a) forming a first insulating layer on a first surface of a first support; (b) forming an opening; (b) a first connecting portion including a first columnar connecting portion formed within the first opening; (c) a first semiconductor die having a first IC chip, a first die electrode connected to the first IC chip, and a second insulating layer encapsulating the first die electrode; a second semiconductor die having a second IC chip, a second die electrode connected to the second IC chip, and a third insulating layer sealing the second die electrode; each of the first semiconductor die and the second semiconductor die is first supported such that the first die electrode is disposed thereon and the second die electrode is disposed on the second connection portion; (d) encapsulating the first semiconductor die and the second semiconductor die with a first sealing body after the step (c); (e) the step (d) (f) removing the first support and exposing a portion of the first columnar connection portion and a portion of the
  • the first insulating layer and the second insulating layer are bonded together, and the first die electrode is encapsulated by the first insulating layer and the second insulating layer.
  • the first insulating layer and the third insulating layer are bonded together, and the second die electrode is encapsulated by the first insulating layer and the third insulating layer.
  • a semiconductor module includes a first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip, a second IC chip and a second die connected to the second IC chip.
  • a second semiconductor die having an electrode; a first connection electrically connected to the first die electrode; a second connection electrically connected to the second die electrode; and the first connection.
  • a bridge having a first bridge electrode connected to and a second bridge electrode connected to the second connection; a first encapsulant encapsulating the first semiconductor die and the second semiconductor die; Prepare.
  • the first connecting portion includes a first columnar connecting portion disposed between the first semiconductor die and the bridge and extending in a direction from one of the first semiconductor die and the bridge toward the other.
  • the first connection portion is disposed between the first semiconductor die and the bridge and includes a second columnar connection portion extending in a direction from one of the first semiconductor die and the bridge to the other.
  • the first bridge electrode and the second bridge electrode are exposed from the first sealing body.
  • Each of the first columnar connection portion and the second columnar connection portion is sealed with the first sealing body.
  • An electronic device includes a first die having a first electrode, a second die having a second electrode, a first connection electrically connected to the first electrode, and a second electrode. and a bridge electrically connected to the first connection and the second connection.
  • the first connection has a columnar connection facing from the bridge to the first die.
  • the electronic module includes the electronic device described above, a wiring layer in which wiring is provided, and a columnar connection portion that electrically connects the wiring and the electronic device.
  • a method for manufacturing an electronic device includes a forming step of forming a first connection portion including a columnar connection portion protruding from the columnar support on a support, and a second connection portion; a die bonding step of bonding a first electrode of the first die to the portion and bonding a second electrode of the second die to the second connection portion; It includes a sealing step of sealing the first connecting portion with resin, and a bridge connecting step of connecting a bridge to a lower portion of the first connecting portion and a lower portion of the second connecting portion.
  • the IC chip and the bridge can be bonded with higher density.
  • FIG. 1 is a schematic diagram of a chip integrated system according to one embodiment
  • FIG. 2 is a perspective view showing a configuration example of the chip integrated body shown in FIG. 1
  • FIG. 3 is an explanatory diagram showing a configuration example of the chip integrated body shown in FIG. 2
  • FIG. 4 is an enlarged cross-sectional view showing a configuration example of a part of the chip integrated module shown in FIG. 3
  • FIG. 4 is an explanatory diagram schematically showing a configuration example of the optical module shown in FIG. 3
  • FIG. FIG. 10 is an explanatory diagram showing an outline of a manufacturing method of a chip integrated module as a study example for one embodiment
  • 5 is an explanatory diagram showing an outline of a manufacturing process of the chip integrated module shown in FIG. 4;
  • FIG. 8 is an enlarged cross-sectional view showing details of a connecting portion forming step shown in FIG. 7;
  • FIG. 9 is an enlarged cross-sectional view showing the details of the connecting portion forming step following FIG. 8 ;
  • FIG. 10 is an enlarged cross-sectional view showing the details of the connecting portion forming step subsequent to FIG. 9;
  • FIG. 11 is an enlarged cross-sectional view showing the details of the connecting portion forming step following FIG. 10 ;
  • FIG. 12 is an enlarged cross-sectional view showing the details of the connecting portion forming step subsequent to FIG. 11;
  • 8 is an enlarged cross-sectional view showing details of a semiconductor die mounting step shown in FIG. 7;
  • FIG. 14 is an enlarged cross-sectional view showing the details of the semiconductor die mounting process following FIG. 13;
  • FIG. 13 is an enlarged cross-sectional view showing the details of the semiconductor die mounting process following FIG. 13;
  • FIG. 13 is an enlarged cross-sectional view showing the details of the semiconductor die mounting process
  • FIG. 15 is an enlarged cross-sectional view showing the details of the semiconductor die mounting process following FIG. 14;
  • FIG. 8 is an enlarged cross-sectional view showing details of the first sealing step shown in FIG. 7;
  • FIG. 8 is an enlarged cross-sectional view showing the details of the support removing step shown in FIG. 7;
  • FIG. 8 is an enlarged cross-sectional view showing the details of the connecting portion exposing step shown in FIG. 7;
  • FIG. 19 is an enlarged cross-sectional view showing the details of the connecting portion exposing step following FIG. 18 ;
  • FIG. 8 is an enlarged sectional view showing the details of the bridge mounting process shown in FIG. 7;
  • FIG. 21 is an enlarged cross-sectional view showing the details of the bridge mounting step following FIG. 20;
  • FIG. 22 is an enlarged cross-sectional view showing the details of the bridge mounting step following FIG. 21;
  • FIG. 8 is an enlarged cross-sectional view showing details of a second sealing step shown in FIG. 7;
  • FIG. 24 is an enlarged sectional view showing a modified example with respect to FIG. 23;
  • FIG. 5 is an enlarged cross-sectional view showing a modified example of the sealing body shown in FIG. 4;
  • 5 is an enlarged sectional view showing another modified example of the sealing body shown in FIG. 4;
  • FIG. 5 is an enlarged sectional view showing another modified example of the sealing body shown in FIG. 4;
  • FIG. FIG. 5 is an enlarged cross-sectional view of a chip integrated module that is a modified example of FIG. 4;
  • FIG. 29 is an explanatory diagram showing an outline of a manufacturing process of the chip integrated module shown in FIG. 28;
  • 30 is an enlarged cross-sectional view showing the details of the insulating layer forming step shown in FIG. 29;
  • FIG. 31 is an enlarged cross-sectional view showing the details of the insulating layer forming step following FIG. 30;
  • FIG. FIG. 30 is an enlarged cross-sectional view showing details of a connecting portion forming step shown in FIG. 29;
  • 30 is an enlarged cross-sectional view showing details of the semiconductor die mounting process shown in FIG. 29;
  • 34 is an enlarged cross-sectional view showing the details of the semiconductor die mounting process following FIG. 33;
  • FIG. 35 is an enlarged cross-sectional view showing the details of the semiconductor die mounting step subsequent to FIG.
  • FIG. 30 is an enlarged cross-sectional view showing details of the sealing step shown in FIG. 29;
  • FIG. 30 is an enlarged cross-sectional view showing the details of the connecting portion exposing step shown in FIG. 29;
  • FIG. 38 is an enlarged cross-sectional view showing the details of the connecting portion exposing step following FIG. 37;
  • FIG. 30 is an enlarged sectional view showing the details of the bridge mounting step shown in FIG. 29;
  • FIG. 40 is an enlarged cross-sectional view showing the details of the bridge mounting process following FIG. 39;
  • FIG. 41 is an enlarged cross-sectional view showing the details of the bridge mounting step following FIG. 40;
  • FIG. 4 is an explanatory diagram showing a modified example of the chip integrated body shown in FIG. 3;
  • FIG. 4 is an explanatory diagram showing another modified example of the chip integrated body shown in FIG. 3;
  • FIG. 5 is a cross-sectional view showing a modification to the bridge shown in FIG. 4;
  • FIG. 45 is a cross-sectional view showing an outline of a wiring layer forming step in the manufacturing steps of the bridge shown in FIG. 44;
  • FIG. 45 is a cross-sectional view showing an outline of a wiring layer transfer step in the manufacturing steps of the bridge shown in FIG. 44;
  • FIG. 45 is a cross-sectional view showing an outline of a support removing step in the manufacturing steps of the bridge shown in FIG. 44;
  • FIG. 5 is an explanatory diagram showing another modified example of the bridge shown in FIG.
  • FIG. 4; 5 is a diagram showing a configuration of part of a chip integrated module that is a modified example of FIG. 4;
  • FIG. FIG. 50 is a diagram showing the configuration of a chip integrated module according to a first modified example of the chip integrated module shown in FIG. 49; 50 is a diagram showing the configuration of a chip integrated module according to a second modification of the chip integrated module shown in FIG. 49;
  • FIG. FIG. 50 is a diagram showing the configuration of a chip integrated module according to a third modified example of the chip integrated module shown in FIG. 49;
  • FIG. 50 is a diagram showing the configuration of a chip integrated module according to a fourth modified example of the chip integrated module shown in FIG. 49;
  • FIG. 50 is a diagram showing the configuration of a chip integrated module according to a fifth modified example of the chip integrated module shown in FIG. 49; It is a figure for demonstrating the manufacturing method of the chip integrated module which concerns on other embodiment. It is a figure for demonstrating the manufacturing method of the chip integrated module which concerns on the same embodiment. It is a figure for demonstrating the manufacturing method of the chip integrated module which concerns on the same embodiment. It is a figure for demonstrating the manufacturing method of the chip integrated module which concerns on the same embodiment. It is a figure for demonstrating the manufacturing method of the chip integrated module which concerns on the same embodiment. It is a figure for demonstrating the manufacturing method of the chip integrated module which concerns on the same embodiment. It is a figure for demonstrating the manufacturing method of the chip integrated module which concerns on the same embodiment. FIG.
  • FIG. 61 is a diagram for explaining a method of manufacturing a chip integrated module according to a sixth modification of the method of manufacturing a chip integrated module shown in FIGS. 55 to 60;
  • FIG. FIG. 61 is a diagram for explaining a method of manufacturing a chip integrated module according to a sixth modification of the method of manufacturing a chip integrated module shown in FIGS. 55 to 60;
  • FIG. FIG. 61 is a diagram for explaining a method of manufacturing a chip integrated module according to a sixth modification of the method of manufacturing a chip integrated module shown in FIGS. 55 to 60;
  • FIG. FIG. 61 is a diagram for explaining a method of manufacturing a chip integrated module according to a sixth modification of the method of manufacturing a chip integrated module shown in FIGS. 55 to 60;
  • FIG. FIG. 61 is a diagram for explaining a method of manufacturing a chip integrated module according to a sixth modification of the method of manufacturing a chip integrated module shown in FIGS. 55 to 60;
  • FIG. 61 is a diagram for explaining a method of manufacturing a chip integrated module according to a seventh modification of the method of manufacturing a chip integrated module shown in FIGS. 55 to 60;
  • FIG. FIG. 61 is a diagram for explaining a method of manufacturing a chip integrated module according to a seventh modification of the method of manufacturing a chip integrated module shown in FIGS. 55 to 60;
  • FIG. FIG. 61 is a diagram for explaining a method of manufacturing a chip integrated module according to an eighth modified example of the method of manufacturing a chip integrated module shown in FIGS. 55 to 60;
  • FIG. FIG. 61 is a diagram for explaining a method of manufacturing a chip integrated module according to an eighth modified example of the method of manufacturing a chip integrated module shown in FIGS. 55 to 60;
  • FIG. FIG. 61 is a diagram for explaining a method of manufacturing a chip integrated module according to an eighth modified example of the method of manufacturing a chip integrated module shown in FIGS. 55 to 60;
  • FIG. 61 is a diagram for explaining a method of manufacturing a chip integrated module according to an eighth modified example of the method of manufacturing a chip integrated module shown in FIGS. 55 to 60;
  • FIG. It is a figure for demonstrating the manufacturing method of the optical module which concerns on one Embodiment. It is a figure for demonstrating the manufacturing method of the optical module which concerns on the same embodiment. It is a figure for demonstrating the manufacturing method of the optical module which concerns on the same embodiment. It is a figure for demonstrating the manufacturing method of the optical module which concerns on the same embodiment. It is a figure for demonstrating the manufacturing method of the optical module which concerns on the same embodiment. It is a figure for demonstrating the manufacturing method of the optical module which concerns on the same embodiment. It is a figure for demonstrating the manufacturing method of the chip integrated body which concerns on other embodiment.
  • FIG. 1 is a diagram showing a configuration example of an integrated circuit chip according to an embodiment
  • IC chip a structure in which circuit elements such as transistors and wiring are formed on a semiconductor substrate is called an IC chip.
  • the IC chip includes a superconducting integrated circuit (quantum computer) and the like.
  • a structure comprising wiring layers stacked on the main surface of an IC chip is called a semiconductor die.
  • a rewiring layer may be further formed on the IC chip, in which case the rewiring layer is included in the wiring layer.
  • a structure in which a plurality of semiconductor dies are sealed with a sealing body and integrated is called a chip integrated module.
  • Chip integrated modules also include bridges that electrically connect multiple semiconductor dies together.
  • Chip integrated bodies may include modules such as optical modules in addition to chip integrated modules.
  • a chip stack may include multiple chip integrated modules.
  • the chip integrated body may include a wide area wiring layer electrically connecting a plurality of modules, and a heat dissipation mechanism or heat dissipation member having a function of dissipating heat generated in each module to the outside.
  • a portion of the chip integrated body excluding the heat-dissipating components is called an integrated layer.
  • a chip integrated module is taken up as an example of a semiconductor module.
  • an integrated layer is taken as an example of a semiconductor package.
  • the chip integrated body 10 is one electronic component (module) incorporated in the chip integrated system 1 .
  • the chip integrated body 10 can be considered as a semiconductor module incorporated in the chip integrated system 1.
  • FIG. 1 each of the chip integrated module, integrated layer, and chip integrated body described below may include an IC chip and be distributed as a packaged semiconductor package. Therefore, each aspect of the chip integrated module, the integrated layer, and the chip integrated body can be considered as a semiconductor package.
  • FIG. 1 is a schematic diagram of a chip integrated system according to one embodiment of the present invention.
  • a chip integrated system 1 includes a plurality of chip integrated bodies 10 . These chip integrated bodies 10 are connected to each other by optical wiring 110 .
  • the optical wiring may connect different chip integrated bodies, and if the scale of the chip integrated body is large, it may also be used to connect different parts within the chip integrated body.
  • the chip integrated system 1 can be used, for example, in an artificial intelligence system in which various processors and memories are highly integrated. Although two chip integrated bodies 10a and 10b are shown in FIG. 1, the chip integrated system 1 may include three or more chip integrated bodies 10, or the chip integrated system 1 may include , may consist of only one chip assembly 10 .
  • the chip integrated body 10 is an integrated body having a plurality of chip integrated modules inside.
  • the size of the chip integrated module is not particularly limited, for example, a size of about 50 mm square to about 300 mm square can be exemplified.
  • the chip integrated module is a semiconductor module provided with a plurality of IC chips.
  • FIG. 1 a region where chip integrated modules are arranged in the chip integrated body 10 is indicated by a broken line.
  • eight chip integrated modules are arranged vertically and eight horizontally, and the chip integrated body 10 has a total of 64 chip integrated modules.
  • the number of chip modules included in the chip integrated body 10 is not limited to this, and may be 63 or less, or 65 or more.
  • the chip integrated body 10 includes an optical transceiver module (hereinafter referred to as "optical module”).
  • the chip integrated body 10 according to this embodiment includes, for example, six optical modules.
  • the chip integrated body 10a includes optical modules 11a, 12a, 13a, 14a, 15a, and 16a.
  • the chip integrated body 10b includes optical modules 11b, 12b, 13b, 14b, 15b, and 16b.
  • the optical modules 11a to 16a and the optical modules 11b to 16b shown in FIG. 1 respectively correspond to the optical modules 11 to 16 shown in FIG. 2 which will be described later.
  • These optical modules are connected to optical modules provided in the same chip integrated body 10 or optical modules provided in other chip integrated bodies 10 by optical wiring 110 .
  • a typical example of optical wiring is an optical fiber, but the present invention is not limited to this.
  • a planar panel or sheet provided with an optical waveguide, or an optical wiring using free space can also be used.
  • the signal in the chip integrated body 10 is transmitted by light, so the signal is transmitted at a higher speed than when the signal is transmitted only by an electrical signal.
  • FIG. 2 is a perspective view showing a configuration example of the chip integrated body shown in FIG.
  • a chip integrated body 10 according to the present embodiment includes an integrated layer (also referred to as a semiconductor package or an electronic module) 100, optical modules 11 to 16 arranged on the upper surface of the integrated layer 100, and optical modules 11 to 16 arranged on the upper surface of the integrated layer 100. and an external terminal 30 arranged on the lower surface of the integrated layer 100 .
  • the integrated layer 100 is a layer having a laminated structure and having a plurality of chip integrated modules (also called semiconductor modules or electronic devices). A detailed configuration of the integrated layer 100 will be described later with reference to FIG.
  • the heat dissipation mechanism 20 is a mechanism for dissipating heat generated in the chip integrated body 10 .
  • the heat dissipation mechanism 20 has a function of dissipating heat generated by, for example, the plurality of IC chips built in the integrated layer 100 and the IC chips of the optical modules 11 to 16 during operation.
  • the heat dissipation mechanism 20 can dissipate heat generated by the integrated circuit chips of the integrated layer 100 and the integrated circuit chips of the optical modules 11 to 16 (see FIG. 2) during operation.
  • the external terminal 30 is a terminal electrically connected to one of the optical modules 11 to 16 or a chip integrated module 40 (see FIG. 3, which will be described later).
  • the external terminal 30 is a solder ball and constitutes a part of the transmission path of the electrical signal.
  • the external terminal 30 can be used to supply power to the optical module or chip integrated module, or to input/output electrical signals to/from the outside.
  • the shape of the external terminal may be spherical as shown in FIG. 2, or may be various shapes such as a pin shape or a pad shape.
  • FIG. 3 is an explanatory diagram showing a configuration example of the chip integrated body shown in FIG.
  • FIG. 3 is a diagram showing the cross-sectional structure of the chip integrated body, but hatching is omitted for clarity. 3 shows two of the 64 chip integrated modules shown in FIG.
  • Each of the plurality of optical modules 11-16 shown in FIG. 2 includes an optical transceiver, a connector, and a heat dissipation member.
  • the optical module 13 shown in FIG. 3 includes an optical transceiver 130 , a connector 132 and a heat dissipation member 136 .
  • the heat dissipation member 136 includes a support plate (heat spreader) fixed on the optical transceiver 130 and a plurality of heat dissipation fins fixed on the support plate and projecting away from the optical transceiver 130 .
  • the optical transceiver 130 has a function of converting an optical signal received via the optical wiring 110 (see FIG. 1) into an electrical signal, and converting the electrical signal into an optical signal and transmitting the optical signal to the outside via the optical wiring 110. It is a photoelectric conversion component with the function of A connector 132 is connected to the bottom surface of the optical transceiver 130 . The connector 132 is also connected to an electrode 140 formed on the surface of the integrated layer 100 via solder 138 . Optical transceiver 130 can transmit and receive electrical signals to and from integrated layer 100 via connector 132 . The use of the connector enables easy attachment and detachment of the optical transceiver, and enables quick replacement of the optical transceiver, for example, in the event of failure.
  • a heat dissipation member 136 is arranged on the upper surface of the optical transceiver 130 .
  • the heat dissipation member 136 can dissipate the heat of the optical transceiver 130, for example.
  • the heat dissipating member 136 has a heat spreader provided with heat dissipating fins on the upper surface to realize a large surface area with a small volume.
  • the heat sink fins can dissipate the heat of the optical transceiver 130, for example.
  • the heat dissipation mechanism 20 is supported by a support member 210 arranged on the surface of the integrated layer 100 .
  • the heat dissipation mechanism 20 includes a support plate fixed to the support member 210 and a plurality of heat dissipation fins fixed on the support plate and projecting away from the chip integrated module 40 .
  • the heat dissipation mechanism 20 is thermally connected to the chip integrated module 40 (in other words, each of the plurality of IC chips) arranged inside the integrated layer 100 (more specifically, inside the chip layer 104) via the support member 210.
  • the support member 210 is, for example, a thermal interface material (TIM) and is thermally connected to an IC chip arranged inside the integrated layer 100 .
  • TIM thermal interface material
  • the integrated layer 100 shown in FIG. 3 includes a wide area wiring layer 102, a chip layer 104 and a connection layer 106.
  • the wide area wiring layer 102 is a layer having a laminated structure composed of a plurality of layers. Each of the multiple layers of the wide-area wiring layer 102 includes a conductor pattern such as wiring and an insulating layer covering the conductor pattern.
  • the insulating layer is made of, for example, an insulating resin.
  • a conductor pattern such as wiring is formed on the underlying insulating layer. Two wirings provided in layers adjacent to each other in the thickness direction are electrically connected by a conductor via.
  • the wide-area wiring layer 102 has four layers. formed. Wirings provided in the uppermost layer (the layer closest to the chip layer 104 ) of the wide area wiring layer 102 are electrically connected to electrodes provided in the chip layer 104 .
  • the chip layer 104 is a layer comprising an insulating sealing body 105 and various conductors and functional devices embedded in the sealing body 105 .
  • conductor posts 146 and a plurality of chip integrated modules 40 are embedded in the sealing body 105 .
  • an electrode 148 is provided on the lower surface of the conductor post 146
  • the conductor post 146 is a wiring layer disposed on the top layer of the wide-area wiring layer 102 via the electrode 148 . is electrically connected to
  • the chip integrated module 40 is electrically connected to wiring arranged in the uppermost layer of the wide-area wiring layer 102 via conductor tall pillars 401 and electrodes 403 . Details of the configuration of the chip integrated module 40 will be described later with reference to FIG.
  • connection layer 106 is a layer that connects the components arranged on the surface of the integrated layer 100 and the chip layer 104 .
  • connection layer 106 has conductive vias 142 and electrodes 144 that connect optical transceiver 130 to conductive posts 146 of chip layer 104 and electrodes 140 electrically connected to optical transceiver 130 .
  • connection layer 106 also has metal contact portions 222 thermally connected to each of the plurality of chip integrated modules 40 , and the contact portions 222 are provided inside the support member 210 of the heat dissipation mechanism 20 . 220 .
  • the chip integrated module 40 according to this embodiment is thermally connected to the heat dissipation mechanism 20 via the contact portion 222 and the coupling portion 220 .
  • FIG. 4 is an enlarged cross-sectional view showing a configuration example of part of the chip integrated module shown in FIG.
  • a chip integrated module 40 according to this embodiment includes a semiconductor die 41, a semiconductor die 42, and a sealing body 45 that seals the semiconductor die 41 and the semiconductor die 42.
  • the chip integrated module 40 also includes a bridge 43 that electrically connects the semiconductor die 41 and the semiconductor die 42 .
  • the chip integrated module 40 includes a connecting portion 47 that electrically connects the semiconductor die 41 and the bridge 43 and a connecting portion 48 that electrically connects the semiconductor die 42 and the bridge 43 .
  • Each of the connection portion 47 and the connection portion 48 is sealed with a sealing body 45 .
  • the semiconductor die 41 is electrically connected to the outside of the chip integrated module 40 (for example, the external terminals 30 shown in FIG. 3) via the connecting portion 49 .
  • the semiconductor die 41 has an IC chip 411 having a main surface 411t and an insulating layer 412 and an insulating layer 413 laminated on the main surface 411t of the IC chip 411.
  • Semiconductor die 41 has wiring 414 and wiring 415 electrically connected to IC chip 411 .
  • Semiconductor die 41 also has die electrode 416 connected to wire 414 and die electrode 417 connected to wire 415 .
  • the semiconductor die 41 has two insulating layers 412 and 413 .
  • the total number of insulating layers that the semiconductor die 41 has is not limited to two layers, and may have three or more insulating layers, for example.
  • the IC chip 411 includes a semiconductor substrate such as silicon and circuit elements such as transistors and diodes. Various forms of integration of the circuit elements in the IC chip 411 are possible. , the semiconductor substrate itself is laminated in multiple layers, circuit elements are formed in each layer, and various types can be assumed, such as those connected by vias (TSV: Through Silicon Via) penetrating the semiconductor substrate.
  • TSV Through Silicon Via
  • the semiconductor die 42 has an IC chip 421 having a main surface 421t and an insulating layer 422 and an insulating layer 423 laminated on the main surface 421t of the IC chip 421.
  • the semiconductor die 42 has wires 425 electrically connected to the IC chip 421 .
  • Semiconductor die 42 also has a die electrode 427 connected to wiring 425 .
  • the semiconductor die 42 has two insulating layers 422 and 423 .
  • the total number of insulating layers that the semiconductor die 42 has is not limited to two layers, and may have, for example, three or more insulating layers and two or more wiring layers.
  • the structure of the semiconductor die 42 is similar to the structure of the semiconductor die 41 described above, for example.
  • the bridge 43 has a chip 431 having a main surface 431 t and an insulating layer 432 and an insulating layer 433 laminated on the main surface 431 t of the chip 431 .
  • Bridge 43 has wiring 434 formed on insulating layer 432 .
  • the chip 431 is made of a semiconductor substrate such as a silicon wafer, but may be made of an inorganic material such as glass as a modification. However, the total number of insulating layers that the bridge 43 has is not limited to two layers, and may have, for example, three or more insulating layers and two or more wiring layers. Moreover, when the chip 431 has a circuit, it may be electrically connected to the wiring 434 .
  • the bridge 43 has a bridge electrode 436 connected to the connection portion 47 and a bridge electrode 437 connected to the connection portion 48 . The bridge electrode 436 and the bridge electrode 437 are electrically connected to each other through the wiring 434 .
  • the bridge 43 according to the present embodiment is a pillar suspended bridge.
  • the wiring 434 according to this embodiment mode is electrically connected to the chip 431, and the wiring 434 and the chip 431 function together as a bridge.
  • the bridge 43 can function as a bridge circuit if it has a function of electrically connecting the semiconductor die 41 and the semiconductor die 42 . Therefore, as a modification, there is a case where the chip 431 is not provided, or a case where the chip 431 and the wiring 434 are not electrically connected.
  • the bridge 43 has two insulating layers 432 and 433 .
  • the total number of insulating layers that the bridge 43 has is not limited to two layers, and may have three or more insulating layers, for example.
  • the connecting portion 47 includes a columnar connecting portion 472 .
  • the connection portion 47 includes a columnar connection portion 472, a solder layer 473 that connects the columnar connection portion 472 and the die electrode 417, a solder layer 474 that connects the columnar connection portion 472 and the bridge electrode 436, have.
  • the connecting portion 48 includes a columnar connecting portion 482 .
  • the connection portion 48 includes a columnar connection portion 482, a solder layer 483 that connects the columnar connection portion 482 and the die electrode 427, a solder layer 484 that connects the columnar connection portion 482 and the bridge electrode 437, have.
  • each of the columnar connection portion 472 and the columnar connection portion 482 is a ⁇ m-sized columnar conductor (also referred to as a "micropillar").
  • the body portions of the columnar connection portion 472 and the columnar connection portion 482 are each made of a metal material containing copper as a main component, for example.
  • the bonding interface between the columnar connection portion 472 and the solder layer 473 and the bonding interface between the columnar connection portion 472 and the solder layer 474 each have a higher oxidation resistance than the main body portion, in other words, the free energy of metal oxide formation.
  • a large alloy layer of a metallic material such as gold and a solder containing tin as a main component is formed.
  • the alloy layer was formed by a eutectic reaction between the metal film formed at the bonding interface between the columnar connection portion and the solder layer and the solder layer when the columnar connection portion 472 was joined to the solder layers 473 and 474. layer. Details of the alloy layer will be described later.
  • the bonding interface between the columnar connection portion 482 and the solder layer 483 and the bonding interface between the columnar connection portion 482 and the solder layer 484 are each made of a metal material such as gold, which has higher oxidation resistance than the main body portion.
  • a bonding film is formed.
  • an alloy layer with the solder layers 483 and 484 is formed in the vicinity of the bonding film, and the original constituents of the bonding film are contained in the solder layer. In some cases, it is in a state of being diffused.
  • the connecting portion 49 has an electrode 492 connected to the tall pillar 401 and a solder layer 493 connecting the electrode 492 and the die electrode 426 .
  • the tall pillar 401 connected to the electrode 492 is not included in the chip integrated module 40, so it is indicated by a dotted line.
  • the tall pillar 401 can be regarded as part of the chip integrated module 40 .
  • each of the bridge electrodes 436 and 437 is sealed in the sealing body 44 formed separately from the sealing body 45 .
  • the sealing body 44 is, for example, an underfill resin.
  • a sealing body that seals the chip 431 and the bridge electrodes 436 and 437 together can also be used.
  • the portion of the sealing body 44 may be replaced with the sealing body 105 shown in FIG.
  • the structure in which the connecting portion 47 and the connecting portion 48 are sealed in the sealing body 45 and the bridge 43 is exposed from the sealing body 45 is the same as the manufacturing method of the chip integrated module 40 described below. is the structure obtained by The details of why the structure shown in FIG. 4 is obtained will be described later.
  • each of the connection portion 47 and the connection portion 48 has one columnar connection portion 472 , 482 .
  • each of the connecting portions 47 and 48 may have two or more stacked columnar connecting portions. The cross-sectional shape and cross-sectional area of the laminated columnar connection parts may be different.
  • FIG. 5 is an explanatory diagram schematically showing a configuration example of the optical module shown in FIG.
  • the optical module 13 mainly includes an optical system mechanism 131 , an optical transceiver 130 and a connector 132 .
  • the optical module 13 includes a mechanism for transmitting an optical signal to the outside (hereinafter also referred to as a "transmitting mechanism 13T”) and a mechanism for receiving an optical signal from the outside (hereinafter also referred to as a "receiving mechanism 13R").
  • the transmitting mechanism 13T is shown on the left side of the paper and the receiving mechanism 13R is shown on the right side, but there are various modifications other than the mode shown in FIG. be.
  • the structure of the transmission mechanism 13T will be taken up and explained, and the explanation of the part common to the structure of the transmission mechanism 13T in the structure of the reception mechanism 13R may be omitted.
  • the optical system mechanism 131 of the transmission mechanism 13T includes an optical fiber 600, a lens 601, a reflection mechanism (reflection mirror in FIG. 5) 602, and a lens 603.
  • Light incident on the lens 603 from the optical transceiver 130 passes through the lens 603 and is reflected by the reflecting mechanism 602 .
  • the reflected light passes through lens 601 and enters optical fiber 600 .
  • the optical signal is transmitted to the outside through the optical fiber 600 .
  • the optical system mechanism 131 of the receiving mechanism 13R includes an optical fiber 610, a lens 611, a reflecting mechanism (a reflecting mirror in FIG. 5) 612, and a lens 613.
  • Light emitted from the optical fiber 610 passes through the lens 611 and is reflected by the reflecting mechanism 612 .
  • the reflected light passes through lens 613 and enters optical transceiver 130 .
  • the optical signal received by the optical fiber 610 is converted into an electrical signal, and various types of processing are performed.
  • Lenses and reflection mechanisms that make up the optical system mechanism 131 can be added or deleted as appropriate based on design requirements. Depending on the configuration, there may be a configuration in which they are directly coupled to the light-emitting element or the light-receiving element.
  • the optical transceiver 130 mainly includes a chip layer 620 , a wiring layer 630 , two optical element chips 605 and 615 arranged on the wiring layer 630 , a light emitting element 606 and a light receiving element 616 .
  • the two optical element chips 605 and 615, the light emitting element 606 and the light receiving element 616 are electrically connected to the wiring layer 630, and the connecting portion is sealed with the underfill resin 607 or the like.
  • the two optical element chips 605 and 615, the light emitting element 606 and the light receiving element 616 are fixed by a fixing member (underfill resin 607) made of resin or the like.
  • the wiring layer 630 has, for example, a two-layer structure. Conductor patterns such as wiring and electrodes are formed in each layer of wiring layer 630 .
  • the chip layer 620 also includes an optical element driving chip 621 and an optical element driving chip 622 .
  • the optical element driving chips 621 and 622 are chips for controlling the driving of the optical element chip 605 and the optical element chip 615, respectively.
  • the optical element driver chips 621 and 622 have the function of converting the electric signal level (voltage, current) required for the optical element to properly convert light/electricity and the electric signal level input/output from the outside of the optical transceiver. etc. may be included.
  • the light emitting element 606 of the transmission mechanism is provided on the surface of the optical element chip 605 and is an element that emits an optical signal according to the electrical signal transmitted from the optical element chip 605 .
  • a light signal emitted by the light emitting element 606 is incident on the lens 603 of the optical system mechanism 131 .
  • the optical element chip 605 is connected to an electrode 631 formed on the upper layer of the wiring layer 630 via an electrode terminal 608 and a solder layer 609, and the optical element driver chip 621 is connected to an electrode terminal 623 and a solder layer. 634 to an electrode 633 formed in a layer below the wiring layer 630 . Therefore, the optical element chip 605 and the optical drive element chip 621 are electrically connected via the wiring layer 630 .
  • This structure can realize multiple parallel and short-distance connections by substantially vertical electrical connections in the wiring layer 630 between the optical element chip and the optical element driving chip. This enables broadband signal transmission between the optical element group arranged in a two-dimensional array and the optical element driving chip.
  • solder layer 634 may not necessarily be required depending on the method of manufacturing the optical transceiver.
  • the electrode terminals 608, the conductor vias 632, and the electrode terminals 623 are arranged substantially on a straight line, the length of the electrical connection path between the optical element chip and the optical drive element chip is minimized, and an excellent electrical connection with small parasitic impedance is achieved. It is possible to connect.
  • a metal layer 629 made of metal is formed on the lower surface of the optical element driving chip 621 .
  • Metal layer 629 is thermally connected to conductor via 641 provided in connector 132 via coupling member 640 .
  • the heat generated when the optical element driving chip 621 is driven is dissipated through the coupling member 640 in the direction of the arrow schematically shown in FIG. 5 (direction from the metal layer 629 to the connector 132).
  • the metal layer 629 it is desirable for the metal layer 629 to be present for heat radiation, the effect can be obtained even if it is not necessarily present.
  • a conductor via 641 of the connector 132 is connected to the electrode 140 formed on the surface of the connection layer 106 via a solder layer 642 . Also, as shown in FIG. 3, the electrode 140 is connected through a conductor via 142 to an electrode 148 that is connected to a conductor post 146 formed on the chip layer 104 . Thus, heat dissipated in connector 132 is dissipated through conductor posts 146 .
  • An electrode terminal 624 is formed on the upper surface of the optical element driver chip 621 , and this electrode terminal 624 is connected to an electrode 626 formed below the wiring layer 630 via a solder layer or conductor connection portion 625 . It is connected.
  • a wiring 635 is formed in the wiring layer 630 . The wiring 635 is connected via a conductor via 636 to an electrode 626 electrically connected to the optical element driver chip 621 . Also, the wiring 635 is connected through a conductor via 637 to an electrode 627 coupled to a conductor post 628 formed on the chip layer 620 .
  • the conductor post 628 is electrically connected to the conductor via 644 of the connector 132 via the coupling member 643 .
  • coupling member 643 allows electrical signals between, for example, optical transceiver 130 and connector 132 to be transmitted to each other.
  • the electrical signal transmission direction between the optical transceiver 130 and the connector 132 may be one direction. That is, an electrical signal is transmitted from the connector 132 to the optical transceiver 130 in the case of the transmitting mechanism 13T, and an electrical signal is transmitted from the optical transceiver 130 to the connector 132 in the case of the receiving mechanism 13R.
  • FIG. 6 is an explanatory diagram showing an outline of a manufacturing method of a chip integrated module, which is a study example for this embodiment.
  • the bridge structure 52 is a structure in which a plurality of bridges 520 and a plurality of connection portions 521 are each sealed with a sealing body 523 to be integrated.
  • a plurality of tall pillars 401 are sealed with a sealing body 523 together with a plurality of bridges 520 .
  • the manufacturing method of the chip integrated module according to the present embodiment prepares a structure in which a plurality of semiconductor dies and a plurality of connection portions are integrated with a sealing body, and then prepares a general structure. It has multiple bridges on its body.
  • the volume of the encapsulant in the structure integrating the multiple semiconductor dies and the multiple connections can be smaller than the volume of the encapsulant 523 in the bridge structure 52 shown in FIG.
  • the manufacturing method of the chip integrated module according to the present embodiment it is possible to improve the positional accuracy of each of the plurality of connecting portions. High density is feasible.
  • FIG. 7 is an explanatory diagram showing an overview of the manufacturing process of the chip integrated module shown in FIG.
  • the manufacturing method of the chip integrated module according to the present embodiment includes a connecting portion forming step, a semiconductor die mounting step, a first sealing step, a support removing step, a connecting portion exposing step, a bridge mounting step, and a second sealing step.
  • the connecting part forming process shown in FIG. 7 includes each process shown in FIGS. 8 to 12 are enlarged cross-sectional views showing the details of the connecting portion forming process shown in FIG.
  • the connection portion forming step as shown in FIG. 11, on the upper surface 70t of the support 70, the connection portion 47 including the columnar connection portion 472 extending in the out-of-plane direction of the upper surface 70t and the columnar connection portion 472 extending in the out-of-plane direction of the upper surface 70t are formed.
  • a support 70 having an upper surface 70t is prepared.
  • a release layer 71 and a seed layer 72 are formed in advance on the upper surface 70t of the support 70 .
  • the material of the support 70 is not particularly limited as long as it is a plate having rigidity to the extent that workability is not impaired in each process up to the support removing process shown in FIG.
  • a semiconductor substrate such as a silicon wafer, a plate made of an inorganic material such as a glass or sapphire substrate, or a resin plate can be used.
  • the peeling layer 71 is a functional layer having the function of enabling the support 70 to be peeled off in the support removing step shown in FIG.
  • the seed layer 72 is a seed film as a base for forming conductive members such as the connection portions 47, 48 and 49 by plating.
  • the seed layer 72 can be formed, for example, by depositing copper on the release layer 71 by sputtering.
  • a resist mask 73 is formed on the upper surface 70t of the support 70, more specifically, on the seed layer 72. Then, as shown in FIG. A plurality of openings 73H are formed in the resist mask 73 using, for example, a photolithographic technique.
  • connection portion 47, a connection portion 48, and a connection portion 49 are formed by depositing a metal film in the openings 73H of the resist mask 73 by plating or the like. Since the seed layer 72 is formed in advance on the top surface 70t of the support 70, the columnar connection portion 472 that is part of the connection portion 47, the columnar connection portion 482 that is part of the connection portion 48, and the connection portion 482 are formed by plating, for example. An electrode 492 that is part of portion 49 can be formed.
  • the columnar connection portion 472 includes a body portion 472A and a metal film 472B.
  • the columnar connection portion 482 includes a body portion 482A and a metal film 482B.
  • Electrode 492 includes body portion 492A and metal film 492B.
  • Each of the body portions 472A, 482A, 492A is made of copper, for example, and each of the metal films 472B, 482B, 492B is made of a metal material, such as gold, which has higher oxidation resistance than copper.
  • Each of the metal films 472B, 482B, 492B prevents oxidation of the bonding surface of each of the main body portions 472A, 482A, 492A made of copper, and enables fluxless solder bonding in the semiconductor die mounting process, which will be described later. It has functionality.
  • the resist mask 73 (see FIG. 10) is removed.
  • the side surfaces of the connection portions 47, 48 and 49 and part of the upper surface of the seed layer 72 are exposed.
  • the step of forming is included.
  • the oxide film 72A before the semiconductor die mounting process, it is possible to prevent the solder from spreading on the side surface of the connecting portion and making the joint shape unstable in the semiconductor die mounting process.
  • the step of forming an oxide film 72A on each side surface of the connection portions 47, 48, 49 and the exposed surface of the seed layer 72 is included, as shown in FIG. are covered with an oxide film 72A. In this step, when the oxide film 72A is not formed, the oxide film 72A shown in FIG. 4 may not be formed as shown in FIG. 24 described later.
  • Examples of methods for forming the oxide film 72A include the following methods. For example, there is a method in which the resist mask 73 shown in FIG. 10 is removed and exposed to an atmosphere containing oxygen until the oxide film 72A shown in FIG. 12 is formed. Further, as a method of forming the oxide film 72A in a shorter time, there is a method of heating the side surfaces of the connection portions 47, 48 and 49 and the exposed surface of the seed layer 72 in an atmosphere containing oxygen. Although the oxide film 72A is shown thick in FIG. 12 for ease of viewing, the oxide film 72A should be thinly formed on the side surfaces of the connection portions 47, 48, and 49 and the exposed surface of the seed layer 72. Enough.
  • the semiconductor die mounting process shown in FIG. 7 includes each process shown in FIGS. 13 to 15 are enlarged cross-sectional views showing details of the semiconductor die mounting process shown in FIG.
  • a semiconductor die 41 having an IC chip 411 and a die electrode 417 connected to the IC chip 411, and an IC chip 421 and a die electrode 427 connected to the IC chip 421.
  • a semiconductor die 42 is provided.
  • each of the semiconductor die 41 and the semiconductor die 42 is mounted on the support 70 so that the die electrode 417 is arranged on the connecting portion 47 and the die electrode 427 is arranged on the connecting portion 48 . Mount on top.
  • a semiconductor die 41 and a semiconductor die 42 are prepared as shown in FIG.
  • the detailed structures of the semiconductor die 41 and the semiconductor die 42 have already been described with reference to FIG. 4, and redundant description will be omitted.
  • each of the semiconductor die 41 and the semiconductor die 42 is arranged such that the die electrode 417 is arranged on the connecting portion 47 and the die electrode 427 is arranged on the connecting portion 48 , and Alignment with the support 70 is performed.
  • a solder layer 473 is formed on the die electrode 417 of the semiconductor die 41 .
  • a solder layer 493 is formed on the die electrode 416 of the semiconductor die 41 .
  • a solder layer 483 is formed on the die electrode 427 of the semiconductor die 42 .
  • the die electrode 417 of the semiconductor die 41 is pressed against the connection portion 47 via the solder layer 473 .
  • the die electrode 416 of the semiconductor die 41 is pressed against the connecting portion 49 via the solder layer 493 .
  • die electrode 427 of semiconductor die 42 is pressed against connection 48 via solder layer 483 .
  • the solder layer 473 and the columnar connection portion 472 of the connection portion 47 are temporarily bonded by solid-phase diffusion bonding.
  • the solder layer 493 and the electrode 492 of the connection portion 49 are temporarily joined by solid phase diffusion joining.
  • the solder layer 483 and the columnar connection portion 482 of the connection portion 48 are temporarily bonded by solid phase diffusion bonding.
  • the bonding interface between the solder layer 473 and the metal film 472B of the columnar connection portion 472, the bonding interface between the solder layer 493 and the metal film 492B of the electrode 492, and the metal of the solder layer 483 and the columnar connection portion 482 Each bonding interface with the film 482B is heated to the melting temperature of the solder and held. Thereby, a liquid phase can be generated at each bonding interface. As shown in FIG. 15, an alloy layer 472D, an alloy layer 482D, and an alloy layer 492D are formed at each bonding interface. When the temperature at which the liquid phase is generated is maintained, the melting point of the liquid phase rises due to the diffusion of the elements in the liquid phase toward the alloy layer.
  • liquid phase diffusion bonding Such a bonding method is called liquid phase diffusion bonding.
  • a strong and thermally stable bonding state is achieved without using flux in the bonding process using solder. can be realized.
  • flux residue there is a high possibility that flux residue will remain around the bonding portion in fine bonding as in this embodiment.
  • the step of cleaning it can be omitted. Further, the process of cleaning and removing the flux residue becomes difficult as the connecting portion becomes finer and denser.
  • solder component of each solder layer it is preferable to prevent the solder component of each solder layer from wetting and spreading on the side surface of the columnar connection when soldering. This is because if the solder component wets and spreads on the side surface of the columnar connection portion and the upper surface of the seed layer 72, the shape of the joint portion will not be stable, or the seed layer and the release layer are likely to be adversely affected by the solder.
  • the oxide film 72A is formed on the side surface of the columnar connection portion and the exposed surface of the seed layer 72 . In this case, the wetting and spreading of the solder component can be suppressed, so that the die electrode and the connection portion can be joined with a small amount of solder.
  • FIG. 16 is an enlarged sectional view showing details of the first sealing step shown in FIG. 7.
  • FIG. 16 the semiconductor die 41 , the semiconductor die 42 , the connecting portion 47 and the connecting portion 48 are integrated with the sealing body 45 .
  • the connecting portion 49 is also sealed with the sealing body 45 .
  • the sealing body 45 can be exemplified by a resin material including, for example, a thermosetting resin. As a modified example of the sealing body 45, a large number of inorganic filler particles may be contained in the resin, as will be described later.
  • the distance between the semiconductor die 41 and the semiconductor die 42 is narrow.
  • the separation distance G1 between the semiconductor die 41 and the semiconductor die 42 is shorter than the shortest distance G2 from the upper surface 70t of the support 70 to the portion of the semiconductor die 41 excluding the die electrodes 416 and 417.
  • the IC chip occupying most of the semiconductor die 41 and the semiconductor die 42 is made of a semiconductor material having a very low coefficient of linear expansion compared to the sealing body 45 . Therefore, even if the encapsulant 45 thermally expands or contracts, the positions of the die electrodes 416, 417, and 427 are less likely to be affected.
  • each of the connections 47, 48, 49 has already been fixed to the semiconductor die 41 or the semiconductor die 42 before the first encapsulation process. Therefore, each of the connecting portions 47 , 48 , 49 can maintain high positional accuracy even when sealed with the sealing body 45 . Therefore, the problem that it is difficult to improve the positional accuracy of each of the plurality of connecting portions 521 of the bridge structure 52 described with reference to FIG. 6 hardly occurs in the case of the present embodiment.
  • FIG. 17 is an enlarged cross-sectional view showing details of the support removing step shown in FIG.
  • the release layer 71 is decomposed (ablated) by applying energy to the release layer 71 with a laser or the like, thereby greatly reducing the adhesion of the release layer 71 to the support. can be easily peeled off.
  • the support removing step it is also possible to separate the release layer by mechanical stress.
  • FIG. 18 is an enlarged cross-sectional view showing details of the step of exposing the connecting portion shown in FIG. 7.
  • the peeling layer 71 and the seed layer 72 shown in FIG. 17 are removed by etching, for example.
  • the portion of the oxide film 72A shown in FIG. 17 formed on the upper surface of the seed layer 72 is removed.
  • a portion (lower surface) of the electrode 492 is also exposed from the sealing body 45 in this step.
  • FIG. 19 is an enlarged cross-sectional view showing the details of the connecting portion exposing step subsequent to FIG.
  • a metal film 472C is formed on the surface of the columnar connection portion 472 exposed from the sealing body 45 .
  • a metal film 482 ⁇ /b>C is formed on the surface of the columnar connection portion 482 exposed from the sealing body 45 .
  • a metal film 492 ⁇ /b>C is formed on the exposed surface of the electrode 492 from the sealing body 45 .
  • Each of the metal films 472C, 482C, and 492C has a function of preventing oxidation of the bonding surface of each of the main body portions 472A, 482A, and 492A made of copper, and also has a function of using solder containing tin as a main component in a semiconductor die mounting process, which will be described later.
  • the eutectic reaction between them has the function of enabling bonding in a low-temperature process.
  • each of the metal films 472C, 482C, and 492C is made of a metal material (for example, gold) having higher oxidation resistance than the material of the body portions 472A, 482A, and 492A, similarly to each of the metal films 472B, 482B, and 492B.
  • Gold can be exemplified as an example of the metal material having the above functions.
  • the bridge mounting process shown in FIG. 7 includes each process shown in FIGS. 20 to 22 are enlarged cross-sectional views showing details of the bridge mounting process shown in FIG.
  • the bridge 43 including the bridge electrode 436 connected to the connection portion 47 and the bridge electrode 437 connected to the connection portion 48 is prepared.
  • the bridge 43 is sealed so that the bridge electrode 436 is arranged on the columnar connection portion 472 and the bridge electrode 437 is arranged on the columnar connection portion 482 . It is mounted on a structure sealed with body 45 .
  • the bridge 43 is prepared as shown in FIG.
  • the detailed structure of the bridge 43 has already been described with reference to FIG. 4, so redundant description will be omitted.
  • the bridge 43 and the sealing body 45 are sealed together so that the bridge electrode 436 is arranged on the columnar connection portion 472 and the bridge electrode 437 is arranged on the columnar connection portion 482 . Align with the stopped structure.
  • a solder layer 474 is formed on the bridge electrode 436 .
  • a solder layer 484 is formed on the bridge electrode 437 .
  • the bridge electrode 436 of the bridge 43 is pressed against the columnar connection portion 472 of the connection portion 47 via the solder layer 474 .
  • the bridge electrode 437 of the bridge 43 is pressed against the columnar connection portion 482 of the connection portion 48 via the solder layer 484 .
  • the solder layer 474 and the columnar connection portion 472 of the connection portion 47 (specifically, the metal film 472C of the columnar connection portion 472) are temporarily joined by solid-phase diffusion bonding.
  • the solder layer 484 and the columnar connection portion 482 of the connection portion 48 are temporarily joined by solid-phase diffusion bonding.
  • liquid phase diffusion bonding can bond the interface between the solder layer 474 and the columnar connection portion 472 and the interface between the solder layer 484 and the columnar connection portion 482 at a temperature lower than the melting point of the solder layers 473 and 483 .
  • FIG. 23 is an enlarged sectional view showing details of the second sealing step shown in FIG. 7.
  • the encapsulant 44 is an underfill resin embedded between the bridge 43 and the encapsulant 45 .
  • the second sealing step shown in FIG. 7 may be omitted and the semiconductor module in the state shown in FIG. 22 may be shipped as a product.
  • the bridge electrode 436 and the bridge electrode 437 may be sealed together with the conductive tall pillar 401 by the sealing body 105 .
  • This encapsulation process is commonly referred to as mold underfill (MUF).
  • a step of forming tall pillars 401 is required before the second sealing step.
  • the step of forming the tall pillars is preferably performed after the connection exposing step and before the bridge mounting step.
  • the formation method of the tall pillar 401 can be performed in the same manner as the connecting portion forming step described with reference to FIGS. That is, a resist mask is formed on the lower surface 45b of the sealing body 45 shown in FIG. The resist mask is formed with an opening at a position overlapping with a portion of the connecting portion 49 .
  • the tall pillars 401 are formed by depositing a metal film in the openings of this mask by plating or the like. In this case, tall pillar 401 is formed directly on electrode 492 .
  • the entire chip layer 104, the integrated layer 100, or the chip integrated body 10 shown in FIG. 3 can be regarded as a semiconductor module.
  • each of the plurality of die electrodes and the plurality of connection portions are formed with high positional accuracy. , so that the IC chips and bridges can be bonded with higher density.
  • a chip integrated module 40A shown in FIG. 25 differs from the chip integrated module 40 shown in FIG. 4 in a sealing body 45A and a sealing body 44A.
  • the sealing body 45A contains a plurality of filler particles 451 and the sealing body 44A contains a plurality of filler particles 441 .
  • the average particle size of the plurality of filler particles 451 is larger than the average particle size of the plurality of filler particles 441 . Since the sealing body 45A includes a plurality of filler particles 451 having a large average particle size as in this modification, the linear expansion coefficient of the sealing body 45A as a whole can be reduced. As a result, it is possible to further improve the positional accuracy of the connection portions 47 and 48 in the bridge mounting process described with reference to FIGS.
  • the plurality of filler particles 451 are mixed in advance in the sealing resin used in the first sealing step used in FIG.
  • a plurality of filler particles 441 are premixed in the sealing resin used in the second sealing step shown in FIG.
  • a chip integrated module 40B shown in FIG. 26 differs from the chip integrated module 40 shown in FIG. 4 in a sealing body 45B and a sealing body 44B.
  • the encapsulant 45B includes a plurality of filler particles 452 and the encapsulant 44 includes a plurality of filler particles 442.
  • the filling rate of the plurality of filler particles 452 in the sealing body 45B is higher than the filling rate of the plurality of filler particles 442 in the sealing body 44B.
  • the “filling rate of the filler particles 452 ” is defined as the total volume of the plurality of filler particles 452 included in the volume of the entire sealing body 45 ⁇ /b>B including the resin 453 and the plurality of filler particles 452 .
  • the “filling rate of the filler particles 442 ” is defined as the total volume of the plurality of filler particles 442 included in the volume of the entire sealing body 44 ⁇ /b>B including the insulating resin 443 and the plurality of filler particles 442 .
  • the sealing body 45A when calculating the filling rate, for example, cross sections of two or more randomly determined regions of the sealing body 45A are imaged, and in each of the imaged ranges, the sealing body 45A By measuring the ratio of the cross-sectional area of the filler particles 452 to the cross-sectional area of , the average value of each region can be regarded as the "filling rate of the filler particles 452". The same applies to the "filler particle 442 filling rate". By increasing the filling rate of the plurality of filler particles 452 in the sealing body 45B as in this modification, the linear expansion coefficient of the sealing body 45B as a whole can be reduced.
  • the plurality of filler particles 452 are mixed in advance in the sealing resin used in the first sealing step used in FIG.
  • a plurality of filler particles 442 are pre-mixed in the sealing resin used in the second sealing step shown in FIG.
  • a chip integrated module 40C shown in FIG. 27 differs from the chip integrated module 40 shown in FIG. 4 in a sealing body 45B.
  • the sealing body 45B contains a plurality of filler particles 452, and the sealing body 44 is an insulating resin 443 that does not contain filler particles.
  • the sealing body 45B contains filler particles, the linear expansion coefficient of the sealing body 45B as a whole can be reduced. can be done. As a result, it is possible to further improve the positional accuracy of the connection portions 47 and 48 in the bridge mounting process described with reference to FIGS. 7 and 20 to 22 .
  • FIG. 28 is an enlarged cross-sectional view of a chip integrated module that is another modified example of FIG.
  • the connecting portion 47 and the connecting portion 48 are sealed with the insulating layer 81, and the die electrodes 416 and 417 of the semiconductor die 41 and the die electrode 427 of the semiconductor die 42 are each sealed with the insulating layer 81. It is different from the chip integrated module 40 shown in FIG. Chip integrated module 40D differs from chip integrated module 40 shown in FIG. do.
  • FIG. 29A and 29B are explanatory diagrams showing an overview of the manufacturing process of the chip integrated module shown in FIG.
  • the manufacturing method of the chip integrated module of this modified example includes an insulating layer forming step, a connecting portion forming step, a semiconductor die mounting step, a sealing step, a support removing step, a connecting portion exposing step, and a bridge. Includes mounting process.
  • the insulating layer forming process shown in FIG. 29 includes each process shown in FIGS. 30 and 31 are enlarged cross-sectional views showing details of the insulating layer forming step shown in FIG.
  • an insulating layer 81 is formed on the upper surface 70t of the support 70, and then, as shown in FIG. do.
  • an opening 81H3 for forming the connecting portion 49 shown in FIG. 28 is also formed.
  • the insulating layer 81 is bonded to the insulating layer 82 shown in FIG. 28 in a semiconductor die mounting process to be described later.
  • the insulating material used for the insulating layer 82 is preferably a material having high heat resistance as well as electrical insulating properties.
  • examples of such materials include organic insulating materials such as polyimide and PBO (polybenzoxazole).
  • the support 70, release layer 71, and seed layer 72 shown in FIGS. 30 and 31 have already been described with reference to FIG. 8, and redundant description will be omitted.
  • FIG. 32 is an enlarged cross-sectional view showing details of the connecting portion forming step shown in FIG.
  • an electrode 492 forming the connecting portion 49 is formed in the opening 81H3.
  • This modification differs from the manufacturing method described with reference to FIG. 10 in that an insulating layer 81 is used as a mask instead of the resist mask 73 described with reference to FIG.
  • the structure of each of the columnar connection portions 472, 482 and the electrode 492 is the same as described with reference to FIG. 10, so redundant description will be omitted.
  • connection portions 47, 48, and 49 are formed using the insulating layer 81 as a mask. Therefore, the step of removing resist mask 73 described with reference to FIG. 11 and the step of forming oxide film 72A described with reference to FIG. 12 are not applied to this modification.
  • the semiconductor die mounting process shown in FIG. 29 includes each process shown in FIGS. 33 to 35 are enlarged cross-sectional views showing details of the semiconductor die mounting process shown in FIG.
  • a semiconductor die 41 having an IC chip 411 and a die electrode 417 connected to the IC chip 411, and an IC chip 421 and a die electrode 427 connected to the IC chip 421.
  • a semiconductor die 42 is provided.
  • each of the semiconductor die 41 and the semiconductor die 42 is mounted on the support 70 so that the die electrode 417 is arranged on the connecting portion 47 and the die electrode 427 is arranged on the connecting portion 48 . Mount on top.
  • a semiconductor die 41 and a semiconductor die 42 are prepared as shown in FIG.
  • an insulating layer 82 is formed on the upper surface (die electrode forming surface) of the semiconductor die 41
  • an insulating layer 83 is formed on the upper surface (die electrode forming surface) of the semiconductor die 42.
  • the insulating layer 82 is an insulating layer that is bonded to the insulating layer 81 in this step. It is particularly preferable that the insulating layers 82 and 83 are made of the same material as the insulating layer 81 in consideration of the bondability with the insulating layer 81 .
  • the detailed structures of the semiconductor die 41 and the semiconductor die 42 other than the above-described differences are already explained with reference to FIG. 4, so overlapping explanations are omitted.
  • each of the semiconductor die 41 and the semiconductor die 42 is arranged such that the die electrode 417 is arranged on the connecting portion 47 and the die electrode 427 is arranged on the connecting portion 48 , and Alignment with the support 70 is performed.
  • a solder layer 473 is formed on the die electrode 417 of the semiconductor die 41 .
  • a solder layer 483 is formed on the die electrode 427 of the semiconductor die 42 .
  • the sealing body 45 does not come into contact with each of the connecting portions 47, 48, and 49 in the sealing step illustrated in FIG. Therefore, it is preferable that the solder layer 493 is formed on the bonding surface of the electrode 492 having a relatively large area compared to the die electrode 416 .
  • the volume of the void around the solder layer 493 can be reduced after the semiconductor die mounting process.
  • the die electrode 416 also have a solder layer formed thereon.
  • the die electrode 417 of the semiconductor die 41 is pressed against the connection portion 47 via the solder layer 473 .
  • the die electrode 416 of the semiconductor die 41 is pressed against the solder layer 493 .
  • die electrode 427 of semiconductor die 42 is pressed against connection 48 via solder layer 483 .
  • the solder layer 473 and the columnar connection portion 472 of the connection portion 47 are temporarily bonded by solid-phase diffusion bonding.
  • the solder layer 493 and the electrode 492 of the connection portion 49 are temporarily joined by solid phase diffusion joining.
  • the solder layer 483 and the columnar connection portion 482 of the connection portion 48 are temporarily bonded by solid phase diffusion bonding.
  • insulating layer 81 is in contact with insulating layer 82 and insulating layer 83, respectively, but is not yet bonded.
  • each bonding interface with the film 482B is bonded by the liquid phase diffusion bonding described above.
  • an alloy layer 472D, an alloy layer 482D, and an alloy layer 492D are formed at each bonding interface by eutectic reaction.
  • the details of the liquid phase diffusion bonding have already been explained, so overlapping explanations will be omitted.
  • the insulating layers 81 and 82 are bonded to each other and the die electrode 417 is sealed with the insulating layers 81 and 82 in the semiconductor die mounting process.
  • the insulating layer 81 and the insulating layer 83 are bonded to each other, and the die electrode 427 is sealed by the insulating layer 81 and the insulating layer 83 .
  • the timing at which the insulating layer 81 is bonded to each of the insulating layers 82 and 83 may be substantially the same as the timing at which the liquid phase diffusion bonding is performed. That is, when the solder layer 473 and the metal film 472B shown in FIG.
  • the insulating layers 81, 82, and 83 are also heated together.
  • the materials forming the insulating layers 81, 82, 83 are softened and their contact interfaces are bonded.
  • bonding principle between the insulating layers bonding by dehydration polymerization of hydroxyl groups on the surfaces of the insulating layers (fusion bonding) can be used, and depending on the material, bonding by softening or melting can also be used.
  • fusion bonding bonding by dehydration polymerization of hydroxyl groups on the surfaces of the insulating layers
  • connection portion 47 the periphery of the connection portion 47 , the connection portion 48 , and the connection portion 49 is surrounded by an insulating layer 81 . Therefore, it is possible to suppress the wetting and spreading of the solder component when performing the liquid phase diffusion bonding. Therefore, also in this modification, the die electrode and the connection portion can be joined with a small amount of solder.
  • FIG. 29 is an enlarged sectional view showing details of the sealing step shown in FIG. 29.
  • FIG. 29 the semiconductor die 41 and the semiconductor die 42 are integrated with the sealing body 45 .
  • the connecting portion 47, the connecting portion 48, and the connecting portion 49 are already sealed, strictly speaking, the semiconductor die 41 and the semiconductor die 42 are integrated with each other via the insulating layer 81. has been made In this step, the rigidity of the structure in which the semiconductor die 41 and the semiconductor die 42 are integrated is improved by sealing with the sealing body 45 .
  • the volume of the sealing body 45 is even smaller than the volume of the sealing body 45 shown in FIG. Therefore, even when the sealing body 45 thermally expands or contracts, each of the connecting portions 47 , 48 , 49 can maintain high positional accuracy even when sealed with the sealing body 45 .
  • the support 70 shown in FIG. 36 is removed after the sealing process. Since the method of removing the support 70 is the same as the support removal step described with reference to FIG. 17, redundant description will be omitted.
  • FIG. 37 is an enlarged cross-sectional view showing the details of the connecting portion exposing step shown in FIG. In this step, the separation layer 71 and the seed layer 72 shown in FIG. 36 are removed by etching, for example. In the example shown in FIG. 37, a portion (lower surface) of the electrode 492 is also exposed from the insulating layer 81 in this step.
  • FIG. 38 is an enlarged cross-sectional view showing the details of the connecting portion exposing step subsequent to FIG.
  • a metal film 472C is formed on the surface of the columnar connection portion 472 exposed from the sealing body 45 .
  • a metal film 482 ⁇ /b>C is formed on the surface of the columnar connection portion 482 exposed from the sealing body 45 .
  • a metal film 492 ⁇ /b>C is formed on the exposed surface of the electrode 492 from the sealing body 45 .
  • the details of the metal films 472C, 482C, and 492C have already been described with reference to FIG. 19, and redundant description will be omitted.
  • the bridge mounting process shown in FIG. 29 includes each process shown in FIGS. 39 to 41 are enlarged cross-sectional views showing details of the bridge mounting process shown in FIG.
  • the bridge 43 including the bridge electrode 436 connected to the connection portion 47 and the bridge electrode 437 connected to the connection portion 48 is prepared.
  • the bridge 43 is sealed so that the bridge electrode 436 is arranged on the columnar connection portion 472 and the bridge electrode 437 is arranged on the columnar connection portion 482 . It is mounted on a structure sealed with body 45 .
  • the bridge 43 is prepared as shown in FIG.
  • an insulating layer 84 is formed on the top surface of the bridge 43 (bridge electrode forming surface), and the bridge electrodes 436 and 437 are each sealed by the insulating layer 84.
  • 15 is different from the semiconductor die mounting process described with reference to FIG.
  • the detailed structure of the bridge 43, except for the above differences, has already been explained with reference to FIG. 4, so redundant explanation will be omitted.
  • a bridge electrode 436 is arranged on the columnar connection portion 472 and a bridge electrode 437 is arranged on the columnar connection portion 482 . Align with the stopped structure.
  • a solder layer 474 is formed on the bridge electrode 436 .
  • a solder layer 484 is formed on the bridge electrode 437 .
  • the bridge electrode 436 of the bridge 43 is pressed against the columnar connection portion 472 of the connection portion 47 via the solder layer 474 .
  • the bridge electrode 437 of the bridge 43 is pressed against the columnar connection portion 482 of the connection portion 48 via the solder layer 484 .
  • the solder layer 474 and the columnar connection portion 472 of the connection portion 47 (specifically, the metal film 472C of the columnar connection portion 472) are temporarily joined by solid-phase diffusion bonding.
  • the solder layer 484 and the columnar connection portion 482 of the connection portion 48 are temporarily joined by solid-phase diffusion bonding.
  • the insulating layer 81 and the insulating layer 84 are in contact with each other. At this point, however, the insulating layer 81 and the insulating layer 84 have not yet been bonded.
  • each of the metal films 472C and 482C shown in FIG. 40 has an alloy layer 472E formed by a eutectic reaction between tin, which is the main component of the solder layer, and the material of the metal film (for example, gold). , 482E (see FIG. 41).
  • the insulating layer 81 and the insulating layer 84 are bonded to each other in the bridge mounting process.
  • the timing at which the insulating layer 81 and the insulating layer 84 are bonded to each other is the timing at which the liquid phase diffusion bonding is performed. That is, when the solder layer 474 and the metal film 472C shown in FIG. 40 are heated to the temperature at which the eutectic reaction occurs, the insulating layers 81 and 84 are also heated together. As a result, the materials forming the insulating layers 81 and 84 are softened and their contact interfaces are bonded.
  • the bonding principle between the insulating layers the above-described bonding (fusion bonding) by dehydration polymerization of the hydroxyl groups on the surfaces of the insulating layers can be used.
  • each of the bridge electrodes 436 and 437 may be sealed with the sealing body 44 shown in FIG. 4 or the sealing body 105 shown in FIG. be.
  • the insulating layer 84 may not be formed.
  • NCF Non-Conductive Film
  • a wide area wiring layer 102 is formed on a support (not shown).
  • a method for forming the wide-area wiring layer 102 is not particularly limited, and for example, a build-up method can be used.
  • a plurality of electrodes 403 and tall pillars 401 are formed on the wide area wiring layer 102 .
  • the method of forming the electrode 403 and the tall pillar 401 can be applied by applying the connecting portion forming process described with reference to FIGS.
  • Electrodes 148 and conductor posts 146 are also formed in this step. If the electrode 148 and the electrode 403 have the same thickness, they can be collectively formed at the same timing. On the other hand, since the conductor post 146 and the tall pillar 401 have different thicknesses, they are formed separately.
  • the chip integrated module 40 is mounted on the tall pillar 401 .
  • the tall pillar 401 is connected to the connecting portion 49 shown in FIG.
  • the method of connecting the tall pillar 401 and the connecting portion 49 is not particularly limited, but they can be connected via a solder layer (not shown), for example. At this time, from the viewpoint of preventing the solder layer in the chip integrated module 40 from remelting, it is preferable to use liquid phase diffusion bonding.
  • various members formed on the chip layer 104 are sealed with a sealing body 105 .
  • the conductor posts 146, the electrodes 148, the chip integrated module 40, the tall pillars 401, and the electrodes 403 are each sealed with the sealing body 105.
  • the support (not shown) is removed from the wide area wiring layer 102 .
  • the upper portion of the sealing body 105 is ground so that the conductor posts 146 and the chip integrated module 40 are exposed.
  • connection layer 106 is formed on the sealing body 105 . More specifically, the connection layer 106 is formed on the sealing body 105 so that the wiring included in the connection layer 106 is connected to the exposed portion of the conductor post 146 or the exposed portion of the chip integrated module 40 . do.
  • electrodes 140 formed on connection layer 106 are connected to conductor posts 146 through conductor vias 142 .
  • the heat dissipation mechanism 20 is mounted on the contact portion 222 . Furthermore, the electrode 140 is connected to the optical module 13 to which the optical fiber 600 (see FIG. 5) and the optical fiber 610 (see FIG. 5) are connected. The heat dissipation member 136 is connected to the optical module 13 in advance. Next, by mounting a plurality of external terminals 30 on the wide area wiring layer 102, the chip integrated body 10 shown in FIG. 3 is obtained.
  • FIG. 42 and 43 are explanatory diagrams showing modifications to the chip integrated body shown in FIG.
  • a chip integrated body 10A shown in FIG. 42 differs from the chip integrated body 10 shown in FIG. Specifically, the connector 132 portion of the optical module 13 is sealed with the sealing body 105 . Connector 132 and electrode 148 are connected via conductor via 142 .
  • the connector 132 portion is embedded in the chip layer 104, the height of the entire chip integrated body 10A can be reduced, and the distance from the chip integrated module to the optical transceiver can be shortened compared to the case of FIG. This can improve signal transmission characteristics.
  • the optical transceiver 130 since the optical transceiver 130 is exposed from the chip layer 104 and the connection layer 106, the optical transceiver 130 can be easily attached and detached.
  • a chip integrated body 10B shown in FIG. 43 differs from the chip integrated body 10 shown in FIG.
  • the integrated layer 100 has a front surface 100f on which the heat dissipation mechanism 20 is mounted and a rear surface 100b opposite to the front surface 100f.
  • the optical module 13 is mounted on the rear surface 100b side. By arranging the optical module 13 on the rear surface 100b, the separation distance between the heat dissipation mechanism 20 and the optical module 13 is increased, so that the heat effect from the heat dissipation mechanism 20 can be reduced.
  • the optical module 13 is arranged at a position overlapping the chip integrated module 40 in the thickness direction of the integrated layer 100 . In this case, since the distance between the chip integrated module 40 and the optical module 13 is shortened, the transmission efficiency of electrical signals can be improved.
  • a bridge 43A shown in FIG. 44 is different from the bridge 43 shown in FIG. 4 in that an insulating layer 438 is further provided between the insulating layer 432 and the chip 431. Other points are the same as the bridge 43 shown in FIG.
  • the bridge 43A is sandwiched between a chip 431, an insulating layer 438, an insulating layer 432, and an insulating layer 433, which are sequentially laminated on the chip 431, and an insulating layer 432 and an insulating layer 438. and wiring 434 connected to each of 437 .
  • the insulating layer 438 is a thick film insulating layer. The thickness of the insulating layer 438 is thicker than the thickness of the insulating layers 432 and 433 .
  • the insulating layer 438 has a surface 438 t bonded to the insulating layer 432 and a surface 438 b bonded to the chip 431 .
  • Each of the surfaces 438t and 438b has an adhesive function, and the insulating layer 438 is adhesively fixed to the insulating layer 432 and the chip 431 via the adhesive functions of the surfaces 438t and 438b.
  • the entire insulating layer 438 may be an adhesive layer.
  • the separation distance between the wiring 434 and the chip 431 can be increased.
  • the parasitic capacitance generated between the chip 431 and the wiring 434 can be reduced.
  • Warp deformation of the bridge occurs due to film forming stress (curing shrinkage or heat shrinkage of resin) that occurs when the insulating layer 438 is formed. From the viewpoint of reducing this warp deformation, it is desirable to use a material with a low elastic modulus for the insulating layer 438 . In addition, from the same point of view, it is preferable to use a resin material whose curing temperature and thermal decomposition temperature are lower than those of the insulating layers 432 and 433 .
  • the insulating layer 438 has a lower curing temperature and a lower thermal decomposition temperature than the insulating layers 432 and 433. Since it is made of a resin material, warp deformation of the bridge 43A can be suppressed.
  • the bridge 43A shown in FIG. 44 is manufactured, for example, as follows.
  • 45 to 47 are cross-sectional views showing the outline of the manufacturing process of the bridge shown in FIG.
  • a method of manufacturing the bridge 43A includes a wiring layer forming step shown in FIG. 45, a wiring layer transferring step shown in FIG. 46, a support removing step shown in FIG. 47, and a bridge electrode forming step shown in FIG.
  • the insulating layer 433, the wiring 434, and the insulating layer 432 are formed in this order on the support 80 shown in FIG.
  • a support 80 shown in FIG. 45 is prepared.
  • a release layer 81A and a seed layer 82A are formed in advance on the upper surface 80t of the support 80.
  • the material of the support 80 is not particularly limited as long as it is a plate having rigidity to the extent that workability is not impaired in each process up to the support removing process described later.
  • a semiconductor substrate such as a silicon wafer, a plate made of an inorganic material such as a glass or sapphire substrate, or a resin plate can be used.
  • the release layer 81A is the same as the release layer 71 described using FIG. 8, and the seed layer 82A is the same as the seed layer 72 described using FIG.
  • the insulating layer 433 is deposited on the seed layer 82A.
  • an opening is formed in part of the insulating layer 433 and a wiring 434 is formed in the opening.
  • the method of forming the opening and the method of forming the wiring 434 in the opening can be formed by the method using the photolithography technique described with reference to FIGS. 9 and 10 .
  • the structure shown in FIG. 45 is obtained.
  • FIG. 46 illustrates an example in which individualized chips 431 are attached.
  • a silicon wafer before singulation, a glass substrate before singulation, or a sapphire substrate before singulation may be attached.
  • a singulation step of obtaining a plurality of bridges 43A (see FIG. 44) by dicing the substrate is performed after the bridge electrode forming step.
  • this step can be expressed as follows. That is, in the wiring layer transfer step, the insulating layer 432 on the support 80 and the substrate are bonded with the insulating layer 438 interposed therebetween.
  • the "substrate” used herein includes, in addition to the chip shown in FIG. 46, a semiconductor substrate such as a silicon wafer before singulation, a glass substrate before singulation, a sapphire substrate before singulation, and the like. As described with reference to FIG. 44, each of the surfaces 438t and 438b of the insulating layer 438 has an adhesive function.
  • the chip 431 and the wiring 434 are not electrically connected.
  • the chip 431 portion shown in FIG. 44 may be replaced with a substrate (for example, a semiconductor substrate, a glass substrate, etc.) on which no integrated circuit is formed. Alternatively, as will be described later, it may be a bridge with a portion of chip 431 removed.
  • the support removing step energy is applied to the release layer 81A (see FIG. 46) to decompose the release layer 81A.
  • the conductor portions connected to the bridge electrode 437 and the bridge electrode 436 (the conductor portion 437A connected to the bridge electrode 437 and the conductor portion 436A connected to the bridge electrode 436) are exposed.
  • Each of the conductor portion 436A and the conductor portion 437A functions as a contactor for electrically connecting the wiring board and the bridge electrode.
  • the release layer 81A and the seed layer 82A shown in FIG. 46 are removed by etching, for example.
  • a bridge electrode 437 is formed on the conductor portion 437A connected to the wiring 434, and a bridge electrode 436 is formed on the conductor portion 436A connected to the wiring 434. do. Also, in this step, a solder layer 474 is formed on the tip surface of the bridge electrode 436 and a solder layer 484 is formed on the tip of the bridge electrode 437 .
  • the bridge 43A shown in FIG. 44 can be formed.
  • the bridge 43A can be used in place of the bridge 43 shown in FIG. 4, for example. Replacing the bridge 43 with the bridge 43A reduces the parasitic capacitance between the chip 431 and the wiring 434, which is particularly suitable for high-speed signal transmission.
  • a bridge 43A shown in FIG. 44 and a bridge 43B shown in FIG. 48 which will be described later, will be described as modified examples of the bridge 43 shown in FIG. 25, chip integrated module 40B shown in FIG. 26, chip integrated module 40C shown in FIG. 27, and chip integrated module 40D shown in FIG. can be replaced with the bridge 43 that is
  • FIG. 48 is a cross-sectional view showing another modified example of the bridge shown in FIG. A bridge 43B shown in FIG. 48 differs from the bridge 43 shown in FIG. 4 in that a portion corresponding to the chip 431 is removed. In the case of the bridge 43B, since the chip 431 is not arranged near the wiring 434, the influence of the parasitic capacitance on the wiring 434 can be further reduced.
  • the bridge 43B has lower rigidity than the bridge 43 shown in FIG. 4 and the bridge 43A shown in FIG. Therefore, in the manufacturing process of the chip integrated module 40E, the semiconductor die 41 and the semiconductor die 42 are joined to the bridge 43B, and the periphery of the bridge electrode 436 and the bridge electrode 437 is sealed. Each step is preferably performed in the same manner as the manufacturing method described with reference to FIGS. After that, the manufacturing method of removing the chip 431 in the state shown in FIG. 23 is preferable. As a method for removing the chip 431, for example, if the chip 431 is made of silicon, it can be removed by dry etching or the like.
  • a method can be used in which a peeling layer is interposed between the chip 433 and the layer 433 and the chip 431 is removed by decomposing (ablating) the peeling layer with an energy beam such as a laser.
  • an energy beam such as a laser.
  • FIG. 49 is a diagram showing a partial configuration of a chip integrated module that is a modification of FIG.
  • a chip integrated module 40E according to this embodiment includes a first die 41E, a second die 42E, a bridge 43E, and sealing members 45E and 46E for sealing these.
  • a first die 41E is connected to the bridge 43E via a first connection 47E.
  • the bridge 43E is connected to the second die 42E via a second connection 48E.
  • the first die 41E is connected to the outside of the chip integrated module 40E via a third connection portion 49E.
  • the first die 41E includes a first integrated circuit chip 402E, die electrodes 408E and 410E, wires 404E and 406E connected to the first integrated circuit chip 402E, and an insulating layer in which the wires 404E and 406E are embedded. 412E, 414E.
  • the wirings 404E and 406E are wirings separate from the wiring layer included in the first integrated circuit chip 402E. More specifically, the wirings 404E and 406E may be thick film wirings using an organic (inorganic) resin insulating film, and are so-called redistribution layers (RDLs). Note that the wiring included in the second die and bridge is also called rewiring.
  • a second integrated circuit chip 420 and a third integrated circuit chip 442E, which will be described later, may also have the same configuration as the first integrated circuit chip 402E.
  • the second die 42E includes a second integrated circuit chip 420E, die electrodes 424E, wiring 422E connected to the second integrated circuit chip 420E, and insulating layers 426E and 428E in which the wiring 422E is embedded.
  • the bridge 43E includes a third integrated circuit chip 442E, bridge electrodes 446E and 448E, wiring 444E connected to the third integrated circuit chip 442E, and insulating layers 450E and 452E in which the wiring 444E is embedded.
  • the wiring 444E forms part of a bridge electrically connected to the first connection portion 47E and the second connection portion 48E.
  • the bridge according to this embodiment is a pillar suspended bridge.
  • the wiring 444E according to this embodiment is electrically connected to the third integrated circuit chip 442E, and the wiring 444E and the third integrated circuit chip 442E are integrated to function as a bridge.
  • the first connecting portion 47E includes columnar connecting portions 474E and 472E.
  • the columnar connection portion is a ⁇ m-sized columnar conductor (also referred to as a “micropillar”).
  • the columnar connection portions 472E and 474E are columnar conductors formed so as to extend from the bridge 43E toward the first die 41E.
  • the cross-sectional area of the portion of the columnar connection portion 472E that is connected to the columnar connection portion 474E is larger than the cross-sectional area of the portion of the columnar connection portion 474E that is connected to the columnar connection portion 472E.
  • the columnar connection portion 474E is connected to the die electrode 408E via solder 478E.
  • the columnar connection portion 472E is connected to the bridge electrode 446E via solder 476E.
  • the second connecting portion 48E includes columnar connecting portions 480E and 482E.
  • the columnar connection portions 480E and 482E are columnar conductors formed from the bridge 43E toward the second die 42E.
  • the cross-sectional area of the portion of the columnar connection portion 480E connected to the columnar connection portion 482E is larger than the cross-sectional area of the portion of the columnar connection portion 482E connected to the columnar connection portion 480E.
  • the columnar connection portion 482E is connected to the die electrode 424E via solder 486E.
  • the columnar connection portion 480E is connected to the bridge electrode 448E via solder 484E.
  • the third connecting portion 49E includes a columnar connecting portion 492E.
  • the columnar connection portion 492E is a columnar conductor that extends outward from the first die 41E.
  • the columnar connection portion 492E is connected to the die electrode 410E via solder 490E.
  • the columnar connection portion 492E is connected to an electrode pad 494E that is connected to the outside (for example, the wide area wiring layer 102, etc.).
  • the third connecting portion 49E may have various structures in addition to (or instead of) the structure shown in FIG.
  • the third connection portion 49E includes various structures that can be connected to the wide area wiring layer 102 (see FIG. 3) such as deep vias, tall pillars, and columnar connection portions provided below the electrode pads 494E. OK.
  • the bridge is a die including an integrated circuit chip
  • the bridge may not include an integrated circuit chip and may be mainly composed of wiring and an insulating layer in which the wiring is embedded.
  • the die and the bridge are connected by two columnar connection portions having different diameters. Not limited to this, the die and the bridge may be connected by one columnar connection portion, or may be connected by three or more columnar connection portions.
  • (First modification) 50 is a diagram showing the configuration of a chip integrated module according to a first modification of the chip integrated module shown in FIG. 49.
  • a chip integrated module 40F according to the first modified example differs from the above-described chip integrated module 40E (see FIG. 49) in the configurations of the first connection portion, the second connection portion, and the third connection portion.
  • the columnar connection portion or electrode pad is directly connected to another electrode or wiring without solder.
  • the columnar connecting portion 502F is connected to the die electrode 408E and the bridge electrode 446E.
  • the columnar connection portion 504 is connected to the die electrode 424E and the bridge electrode 448E.
  • the electrode pad 494E is connected to the die electrode 410E.
  • the columnar connection portion and the die electrode or the bridge electrode, or the die electrode and the electrode pad may be connected by various known techniques related to hybrid bonding.
  • various conductors are embedded in the insulator.
  • the die electrodes 408E, 410E, 424E are embedded in the insulating film 510F.
  • the electrode pad 494E and the columnar connection portions 502F and 504F are embedded in the insulating layer 512F.
  • the bridge electrodes 446E and 448E are embedded in the insulating film 514F.
  • the first die 41E and the second die 42E are sealed with an insulating resin 506F.
  • the bridge electrodes 446E and 448E and the insulating layer 512F, and the insulating film 514F and the insulating layer 512F can be connected and joined.
  • the bridge electrodes 446E and 448E and the insulating layer 512F, and the insulating film 514F and the insulating layer 512F can be connected and joined in the same manner.
  • the bridge may not include an integrated circuit chip.
  • the bridges may include solid chips made of various materials such as silicon and glass.
  • (Second modification) 51 is a diagram showing the configuration of a chip integrated module according to a second modification of the chip integrated module shown in FIG. 49.
  • FIG. In the chip integrated module 40G according to the second modification, a deep via 520G is formed in the insulating resin 524G that seals the bridge 43E, and the first die 41E is electrically connected to the external conductor through the deep via 520G.
  • a deep via 520G may be connected to the electrode pad 494E connected to the bridge 43E, and a solder 522G connected to an external conductor may be formed at the end of the deep via 520G.
  • the deep via 520G may be formed so that the diameter increases from the electrode pad 494E toward the solder 522G.
  • the lower surface of the third integrated circuit chip 442E may be exposed.
  • bridges including the bridge 43E are sealed with an insulating resin 524G. Therefore, in the second modified example, the bridge is protected by the insulating resin 524G. It is also possible to seal (underfill) the connecting portion between the bridge and another member at the same time as sealing the bridge. Furthermore, by flattening the portion of the die where the terminals are formed, it is possible to narrow the pitch of the connection portion with the wide area wiring layer.
  • (Third modification) 52 is a diagram for explaining a chip integrated module according to a third modification of the chip integrated module shown in FIG. 49.
  • FIG. FIG. 52 shows the vicinity of part of the deep via 520G and the third integrated circuit chip 442E of a chip integrated module H which is a modification of the chip integrated module 40G shown in FIG.
  • the chip integrated module according to the third modified example may have the configuration of the chip integrated module 40G according to the second modified example. That is, the configuration not shown in FIG. 52 may be substantially the same as the configuration shown in FIG.
  • the lower surface of the third integrated circuit chip 442E is not exposed. More specifically, the lower side of the third integrated circuit chip 442E is covered with an insulating resin 525G.
  • FIG. 53 is a diagram showing a chip integrated module according to a fourth modification of the chip integrated module shown in FIG. 49.
  • the wiring layer 570K according to the fourth modification has various conductors embedded in the insulating layer, and specifically has wiring 578K and electrodes 576 embedded in the insulating layers 572K and 574K. there is These wires 578K and electrodes 576K may be electrically connected to external conductors. According to the fourth modification, for example, it is possible to arrange the terminals in the bridge. It is also possible, for example, to supply power directly to the bridge from the outside.
  • a third integrated circuit chip 564K according to the fourth modification includes functional elements 566K having various functions in a region surrounded by broken lines.
  • This functional element 566K is connected to electrodes 576K formed on the wiring layer 570K through vias 568K formed inside the third integrated circuit chip 564K.
  • the bridge electrode 446E is connected to the wiring 443K
  • the bridge electrode 448E is connected to the wiring 444E.
  • the first die 41E and the second die 42E are connected via the functional element 566K.
  • the electrode pad 494E electrically connected to the first die 41E is connected to the wiring 578K of the wiring layer 570K through the tall pillar 560K.
  • the tall pillar 560K may have a substantially constant cross-sectional area from the electrode pad 494E to the wiring 578K.
  • (Fifth modification) 54 is a diagram showing a chip integrated module according to a fifth modified example of the chip integrated module shown in FIG. 49.
  • FIG. In the chip integrated module 40M according to the fifth modified example, the bridge mainly includes wiring.
  • the bridge 580M according to the fifth modification has various wirings and an insulating layer in which the wirings are embedded, but does not have an integrated circuit chip.
  • the bridge 580M has wiring 588M embedded in the insulating layer 582M, and this wiring 588M is connected to the bridge electrodes 446E, 448E.
  • Wirings 589M and 590 are embedded in the insulating layers 582M, 584M and 586M. These wirings 589M and 590M are connected to electrodes 576 of the wiring layer 570K through contact vias 592M.
  • a flat support 800 having a release film 802 formed on its surface as shown in FIG. 55 is prepared.
  • Various conductors are formed on the release film 802 (formation step).
  • Various materials such as glass, silicon, and metal can be appropriately used as the support.
  • columnar connection portions 806 and 808 protruding from the surface of the support 800 are formed on the release film 802 .
  • electrode pads 804 and 809 may be formed on the release film 802 .
  • a plurality of dies including a first die 81E and a second die 82E are bonded to various conductors formed on the release film 802.
  • the first die 81E has a first integrated circuit chip 810, a wiring layer 812 formed on its surface, and various electrodes including die electrodes 814 and 816 formed on its surface.
  • the second die 82E also has a second integrated circuit chip 820, a wiring layer 822 formed on its surface, and various electrodes including die electrodes 824 and 826 formed on its surface.
  • the die electrodes formed on the die are bonded to various conductors (die bonding process).
  • die electrode 814 and die electrode 816 of first die 81E are coupled to electrode pad 804 and post connection 806, respectively.
  • die electrode 824 and die electrode 826 of second die 82E are coupled to electrode pad 809 and post connection 808, respectively.
  • the die electrodes may be connected to the electrode pads or the columnar connection portions via solder, or may be bonded by hybrid bonding without solder.
  • various conductors and a plurality of dies formed on the release film 802 are sealed with a resin 818 (sealing member) (sealing step).
  • a resin 818 (sealing member)
  • the resin 818 for example, injection and curing (capillary underfill) using a liquid underfill resin using capillary action, NCF ( It may be pre-sealed with an insulating resin such as a non-conductive film), or may be simultaneously sealed in the sealing process with the resin 818 (Mold Underfill). This secures the plurality of dies coupled to the pillars and metal pads.
  • the peeling film 802 and the support 800 are removed, and the peeling film remaining on the electrode pads and the like is removed.
  • a method for removing the support there are various methods such as a method of mechanically peeling the support, a method of peeling by irradiating the peeling film with a laser beam, and a method of removing the support by grinding or etching in some cases. can be used. In the case of a method using grinding or etching, the peeling film may not be necessary in some cases.
  • the resin 818 on the surface side of the die is ground. This allows the die to be exposed.
  • various conductors and a plurality of dies are embedded as shown in FIG. 58 by the method described with reference to FIGS.
  • bridge joining step each of the plurality of dies including the bridge 83E is used as a bridge, and the bridge is coupled to the lower portion of each of the plurality of columnar connection portions.
  • the bridge 83E has a third integrated circuit chip 830, a wiring layer 832 formed on its surface, and bridge electrodes (including bridge electrodes 834 and 836) formed thereon.
  • a bridge electrode 834 that the bridge 83E has is coupled to the columnar connection portion 806 that is connected to the first die 81E. Furthermore, the bridge electrode 836 of the bridge 83E is joined to the columnar connection portion 808 connected to the second die 82E. Bridge 83E thereby functions as a bridge that is electrically connected to first die 81E and second die 82E, forming a structure that characterizes a suspended bridge with pillars. In addition, the bridge electrode may be coupled to the columnar connection portion via solder, or may be coupled by hybrid bonding without solder.
  • each chip integrated module 80 is individually formed.
  • the manufacturing method of the chip integrated module according to the present embodiment as described with reference to FIG. is carried out. Therefore, in subsequent processes, the positional relationship of the plurality of dies is not deviated, and the integrated circuit chips can be connected to each other with higher accuracy. In addition, simpler steps and handling are possible. Furthermore, it becomes possible to form the external terminals directly under the integrated circuit chip, and excellent characteristics can be expected in terms of power integrity (PI) and signal integrity (SI). In addition, since stable relative positional accuracy of the die can be ensured without depending on the size of the module, according to the present embodiment, it is easy to develop Panel-Scale large-scale chip integration.
  • PI power integrity
  • SI signal integrity
  • FIGS. 55 to 60 are diagrams for explaining a chip integrated module manufacturing method according to a sixth modification of the chip integrated module manufacturing method shown in FIGS. 55 to 60.
  • FIG. In the sixth modified example a method of manufacturing a chip integrated module having the same configuration as the chip integrated module 40F according to the second modified example described with reference to FIG. 50 will be described.
  • a bridge is connected to the columnar connection portion.
  • a bridge according to the sixth modification has a wiring layer 946 and an integrated circuit chip 948 .
  • the wiring layer 946 has wiring (not shown in FIG. 61), and this wiring is connected to a plurality of bridge electrodes.
  • This bridge electrode is connected to the columnar connection portion.
  • bridge electrode 942 is connected to post connection 806 and bridge electrode 944 is connected to post connection 808 .
  • the bridge electrodes 942 and 944, the wiring layer 946 and the integrated circuit chip function as a bridge.
  • the bottom surface of the integrated circuit chip is covered with resin 940 . Grind the bottom surface of the integrated circuit chip and the resin 940 on the bottom surface. This exposes the bottom surface of the integrated circuit chip, as shown in FIG.
  • openings 950 are formed in the resin 940 in which the integrated circuit chip is embedded.
  • openings 950 may be formed in the resin 940 by irradiating the resin 940 with a laser. Openings 950 may be formed, for example, to expose electrode pads 809 connected to the integrated circuit chip. Also, the via opening 950 to be formed may be formed so that the diameter increases downward from the electrode pad 809 .
  • a metal is formed in the opening formed in the resin 940 by, for example, plating, and solder is provided at the end of the metal.
  • solder is provided at the end of the metal.
  • a deep via 952 having solder 954 at its end is formed in the resin 940 .
  • a bridge according to the seventh modification has a wiring layer 964 and an integrated circuit chip 966 .
  • the wiring layer 964 has wiring, and functions as a bridge by connecting bridge electrodes provided on the surface of this wiring to the columnar connection portions 806 and 808, for example.
  • the resin 960 encapsulating the tall pillars and bridges, the tall pillars and the integrated circuit chip are ground.
  • the surfaces of the tall pillars and the integrated circuit chip are exposed on the surface of the resin 960, as shown in FIG.
  • a chip integrated module of a desired size can be produced.
  • a bridge according to the eighth modification has a wiring layer 986 and an integrated circuit chip 988 .
  • the wiring layer 986 has wiring.
  • the wiring layer 986 and the bridge electrodes formed on the wiring layer 986 are sealed with resin. Thereby, as shown in FIG. 67, the bridges are connected to the columnar connection portions while the die electrodes and wiring layers 986 are fixed by the resin 980 .
  • integrated circuit chip 988 is removed from wiring layer 986 . Furthermore, by cutting the resin 818, a chip integrated module of a desired size can be produced.
  • a release layer 996 is provided between the integrated circuit chip 988 and the insulating layer 994 of the wiring layer.
  • energy particles 981 for example, laser light
  • the peeling layer 996 can be entirely decomposed. This allows the integrated circuit chip 988 to be removed from the insulating layer 994 .
  • the separation layer 996 is decomposed by scanning the region irradiated with energetic particles.
  • the present invention is not limited to this, and the entire separation layer 996 is irradiated with energetic particles at once without scanning. You can irradiate.
  • a support 850 having a release layer 852 formed on its surface is prepared.
  • a wiring layer 860 is formed on the surface of the release layer 852 .
  • This wiring layer 860 may have a two-layer structure, and more specifically, may have substantially the same configuration as the wiring layer 630 described with reference to FIG.
  • a plurality of conductor vias are formed in the upper layer of the wiring layer 630, and an electrode is coupled to each conductor via.
  • the conductor via 861 is coupled with an electrode 862 to which a conductor post is connected
  • the conductor via 863 is coupled with an electrode 864 to which an optical element driving chip is connected.
  • a conductor post 870 and an optical element driver chip 880 are coupled to the electrodes.
  • conductor post 870 is coupled to electrode 862 .
  • the optical element driver chip 880 has a plurality of electrode terminals 874 .
  • the electrode terminal 874 is connected via solder 782 to the electrode 872 formed on the surface of the wiring layer 860 .
  • the multiple conductor posts 870 and the optical element driving chip 880 are sealed with a resin 882 . Thereby, the plurality of conductor posts 870 and the optical element driving chip 880 are fixed.
  • the peeling layer 852 and the support 850 are removed, and the peeling layer 852 remaining on the lower surface of the wiring layer 860 is removed. Further, the upper surface of the resin 882 is ground to form a metal layer 884 on the upper surface of the optical element driving chip 880 as shown in FIG.
  • the optical element chip 890 is provided with a light emitting element 892 , a light receiving element 894 and a plurality of electrode terminals 896 .
  • the optical element chip 890 is joined to the wiring layer 860 by joining each of the plurality of electrode terminals 896 to the electrodes 866 of the wiring layer 860 via solder 868 .
  • the lower side of the optical element chip 890 , the light emitting element 892 , the light receiving element 894 and the plurality of electrode terminals 896 are sealed with a resin 898 .
  • an optical module 89 is produced.
  • a support 900 having a release layer 902 formed on its surface is prepared, and various conductors are formed on the surface of the release layer 902 .
  • electrodes 906 to which conductor posts are connected, columnar connection portions 908 (toll pillars) to which a chip integrated module is connected, and the like are formed.
  • various members are formed on various conductors formed on the release layer 902 .
  • conductor posts 907 may be formed on electrodes 906, and chip integrated modules 909 may be connected to columnar connection portions 908.
  • FIG. The chip integrated module 909 may be connected to the columnar connection portion 908 by solder provided on the columnar connection portion 908 . If the thickness of the bridge of the chip integrated module is sufficiently thin, the columnar connection portion 908 can be replaced by a solder bump having a relatively low height.
  • the formed various members are sealed with resin.
  • the conductor post 907 , the columnar connection portion 908 , the chip integrated module 909 and the like may be sealed with the resin 914 .
  • the support 900 is removed from the wiring layer 904 together with the release layer 902 .
  • the resin 914 is ground so that the conductor post 907 and the chip integrated module 909 are exposed.
  • wiring layer 912 is formed on resin 914 . More specifically, the wiring layer 912 is formed on the resin 914 so that the wiring included in the wiring layer 912 is connected to the exposed portion of the conductor post 907 or the exposed portion of the chip integrated module 909 .
  • electrodes 916 formed on wiring layer 912 may be connected to conductor posts 907 through conductor vias.
  • the contact metal 918 may be connected to the chip integrated module 909 through conductor vias.
  • a heat dissipation mechanism 922 is mounted on the contact metal 918. Furthermore, an optical module 917 to which an optical wiring 920 is connected is connected to the electrode 916 . Thus, the chip integrated body according to this embodiment is produced.
  • FIG. 80 is a diagram showing a configuration example of an integrated circuit chip according to one embodiment.
  • the integrated circuit chip 35 includes a wiring layer 350 , a transistor 370 , and a connection layer 390 connecting the wiring layer 350 and the transistor 370 .
  • the wiring layer 350 has a laminated structure of five layers, and each layer has a film for insulating between layers, wiring embedded in the film, and vias for connecting wirings of layers adjacent to each other vertically.
  • a second layer wiring 352 and a third layer wiring 354 are connected via vias 353 , and the wiring 354 is embedded in an insulating film 356 .
  • the film included in each layer may be made of, for example, BPSG (Boron-Phosphorous Silicate Glass).
  • the wiring included in each layer may be made of metal such as copper.
  • the wiring in the upper layers serves as a power source or ground, so it does not have to be finer than the wiring in the other layers.
  • the various columnar connection portions are oriented substantially perpendicular to the surface of the die.
  • the various columnar connection portions may be formed in any direction as long as they extend in a direction toward another die.
  • the dimensions, cross-sectional shape, and aspect ratio (the ratio of the dimension in the cross-sectional direction to the dimension in the direction perpendicular to the cross-sectional direction) of the columnar connection part are determined according to the requirements of performance, reliability, etc., and the manufacturing process that can be selected. It can be set as appropriate.
  • the bridge when the bridge includes the chip, the example in which the bridge mainly includes wiring and the chip is connected to the bridge electrode via this wiring has been described.
  • the bridge may not include wiring and the chip may be directly connected to the bridge electrode.
  • examples were mainly described in which various dies (for example, the first die and the second die, etc.) included wiring.
  • the die may not include wiring.
  • the integrated circuit chip that the die has may be directly connected to the die electrodes.
  • a thin film wiring layer formed on the support 900 is used as the wiring 904, but the wiring 904 is not limited to this, and various known interposers and wiring substrates can be used.
  • the present invention is widely applicable to semiconductor modules and the like.

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
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  • Physics & Mathematics (AREA)
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  • Lead Frames For Integrated Circuits (AREA)
PCT/JP2022/031116 2021-08-20 2022-08-17 半導体モジュールおよびその製造方法、電子装置、電子モジュール、ならびに電子装置の製造方法 Ceased WO2023022179A1 (ja)

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JP2023542430A JP7496942B2 (ja) 2021-08-20 2022-08-17 半導体モジュールおよびその製造方法、電子装置、電子モジュール、ならびに電子装置の製造方法
KR1020247004921A KR20240046499A (ko) 2021-08-20 2022-08-17 반도체 모듈 및 그 제조 방법, 전자 장치, 전자 모듈, 및 전자 장치의 제조 방법
CN202280054608.5A CN117769896A (zh) 2021-08-20 2022-08-17 半导体模块及其制造方法、电子装置、电子模块以及电子装置的制造方法
US18/684,440 US20250015002A1 (en) 2021-08-20 2022-08-17 Semiconductor module, method of manufacturing the same, electronic apparatus, electronic module, and method of manufacturing electronic apparatus
JP2024085925A JP7832985B2 (ja) 2021-08-20 2024-05-28 半導体モジュールおよび電子装置
JP2025252176A JP2026031831A (ja) 2021-08-20 2025-12-16 半導体モジュールおよび電子装置

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024219502A1 (ja) * 2023-04-19 2024-10-24 Ｈｄマイクロシステムズ株式会社 絶縁膜形成材料、半導体装置の製造方法及び半導体装置
US20240429142A1 (en) * 2023-06-26 2024-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
WO2025070181A1 (ja) * 2023-09-27 2025-04-03 古河電気工業株式会社 基板アセンブリ

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021182529A1 (ja) 2020-03-10 2021-09-16 日本製鉄株式会社 曲げ加工装置、鋼矢板の製造設備、曲げ加工方法、及び、鋼矢板の製造方法
US20250006644A1 (en) * 2023-06-29 2025-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160293572A1 (en) * 2015-03-30 2016-10-06 Qualcomm Incorporated Cavity bridge connection for die split architecture
JP2019125779A (ja) * 2017-12-08 2019-07-25 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ ウエハレベルのダイブリッジのための方法及び装置
US20200176384A1 (en) * 2018-11-29 2020-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method of manufacturing the same
JP2020528220A (ja) * 2017-08-11 2020-09-17 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 成形チップの組み合わせ
JP2020529742A (ja) * 2017-08-10 2020-10-08 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ チップを相互接続する構造を含む基板、電子デバイス、およびその製作する方法
US20210091005A1 (en) * 2019-09-25 2021-03-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US20210134728A1 (en) * 2019-11-06 2021-05-06 International Business Machines Corporation Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers
US20210175174A1 (en) * 2019-12-04 2021-06-10 International Business Machines Corporation Cu-Cu Bonding for Interconnects on Bridge Chip Attached to Chips and Packaging Substrate

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090059504A (ko) * 2007-12-06 2009-06-11 삼성전자주식회사 반도체 장치 및 그 제조방법들
US8637392B2 (en) * 2010-02-05 2014-01-28 International Business Machines Corporation Solder interconnect with non-wettable sidewall pillars and methods of manufacture
JP2014236188A (ja) * 2013-06-05 2014-12-15 イビデン株式会社 配線板及びその製造方法
US10340253B2 (en) * 2017-09-26 2019-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US10797022B2 (en) * 2017-10-06 2020-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11735533B2 (en) 2019-06-11 2023-08-22 Intel Corporation Heterogeneous nested interposer package for IC chips
US20210005542A1 (en) 2019-07-03 2021-01-07 Intel Corporation Nested interposer package for ic chips
JP2021040012A (ja) * 2019-09-02 2021-03-11 キオクシア株式会社 半導体装置の製造方法
US11574872B2 (en) * 2019-12-18 2023-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US11276620B2 (en) * 2019-12-30 2022-03-15 Advanced Semiconductor Engineering, Inc. Package structure and method for manufacturing the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160293572A1 (en) * 2015-03-30 2016-10-06 Qualcomm Incorporated Cavity bridge connection for die split architecture
JP2020529742A (ja) * 2017-08-10 2020-10-08 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ チップを相互接続する構造を含む基板、電子デバイス、およびその製作する方法
JP2020528220A (ja) * 2017-08-11 2020-09-17 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 成形チップの組み合わせ
JP2019125779A (ja) * 2017-12-08 2019-07-25 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ ウエハレベルのダイブリッジのための方法及び装置
US20200176384A1 (en) * 2018-11-29 2020-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method of manufacturing the same
US20210091005A1 (en) * 2019-09-25 2021-03-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US20210134728A1 (en) * 2019-11-06 2021-05-06 International Business Machines Corporation Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers
US20210175174A1 (en) * 2019-12-04 2021-06-10 International Business Machines Corporation Cu-Cu Bonding for Interconnects on Bridge Chip Attached to Chips and Packaging Substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024219502A1 (ja) * 2023-04-19 2024-10-24 Ｈｄマイクロシステムズ株式会社 絶縁膜形成材料、半導体装置の製造方法及び半導体装置
US20240429142A1 (en) * 2023-06-26 2024-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
WO2025070181A1 (ja) * 2023-09-27 2025-04-03 古河電気工業株式会社 基板アセンブリ

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