WO2023005396A1 - 一种芯片封装用底部填充胶及芯片封装结构 - Google Patents

一种芯片封装用底部填充胶及芯片封装结构 Download PDF

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Publication number
WO2023005396A1
WO2023005396A1 PCT/CN2022/095506 CN2022095506W WO2023005396A1 WO 2023005396 A1 WO2023005396 A1 WO 2023005396A1 CN 2022095506 W CN2022095506 W CN 2022095506W WO 2023005396 A1 WO2023005396 A1 WO 2023005396A1
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Prior art keywords
underfill
xylene
epoxy resin
chip
chip packaging
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PCT/CN2022/095506
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English (en)
French (fr)
Inventor
伍得
王圣权
王�义
廖述杭
苏峻兴
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武汉市三选科技有限公司
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Publication of WO2023005396A1 publication Critical patent/WO2023005396A1/zh
Priority to US18/307,569 priority Critical patent/US11804463B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J163/00—Adhesives based on epoxy resins; Adhesives based on derivatives of epoxy resins
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08G—MACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONS ONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS
    • C08G59/00—Polycondensates containing more than one epoxy group per molecule; Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups
    • C08G59/18—Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing
    • C08G59/40—Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing characterised by the curing agents used
    • C08G59/4007—Curing agents not provided for by the groups C08G59/42 - C08G59/66
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08G—MACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONS ONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS
    • C08G59/00—Polycondensates containing more than one epoxy group per molecule; Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups
    • C08G59/18—Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing
    • C08G59/40—Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing characterised by the curing agents used
    • C08G59/62—Alcohols or phenols
    • C08G59/621—Phenols
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08L—COMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L63/00—Compositions of epoxy resins; Compositions of derivatives of epoxy resins
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J11/00—Features of adhesives not provided for in group C09J9/00, e.g. additives
    • C09J11/02—Non-macromolecular additives
    • C09J11/04—Non-macromolecular additives inorganic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/29387—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin

Definitions

  • the present application relates to the technical field of semiconductor packaging, in particular to an underfill glue and a chip package structure using the underfill glue.
  • Flip chip is to turn the semiconductor chip over and connect the solder joints to the substrate by welding to realize the conduction of the circuit.
  • This method is different from the traditional method, which is to wire around the chip and connect it to the circuit board through gold wires or copper wires.
  • the advantage of flip chip is that the chip size is small, because the solder joint is shorter than the traditional gold wire, the transmission loss is reduced, the signal transmission is faster, and the heat conduction effect is better.
  • underfill is a material suitable for flip-chip underfill technology. It usually uses the principle of capillary action to penetrate into the gap between the chip and the substrate, and then gradually solidifies through thermal curing and fills it between the chip and the substrate. In the gap between them, the high-density soldering bumps and chips between the chip and the substrate are protected.
  • the use of underfill glue for chip bottom packaging can reduce the expansion coefficient mismatch between the chip and the substrate, and protect the chip from harmful operating environments such as mechanical stretching, shearing, twisting, vibration, etc., thereby improving the reliability and reliability of the chip. long-term usability. As such, underfills are required to have excellent electrical, physical and mechanical properties.
  • the underfill material is bonded to the chip, the substrate, and the solder bumps between the chip and the substrate, thereby protecting the chip, substrate and Solder bumps are protected.
  • the adhesion between the underfill material formed after curing of the existing underfill adhesive and the chip, substrate, and solder bumps is not strong enough, and the underfill material often cracks or breaks from the chip, substrate, and/or solder bumps. If the chip is peeled off, the chip cannot be protected and the chip is damaged.
  • the present application provides an underfill adhesive for chip packaging and a chip packaging junction.
  • the embodiment of the present application provides an underfill adhesive for chip packaging, including epoxy resin with a mass percentage of 19-25%, filler with a mass percentage of 55-60%, and a mass percentage of 15-25% curing agent, and a accelerator with a mass percentage of 0.5-0.8%,
  • the curing agent includes a polycondensate of p-xylene and dihydroxynaphthalene and a polycondensate of p-xylene and naphthol, wherein,
  • condensation polymer of p-xylene and dihydroxynaphthalene has the following structural formula:
  • condensation polymer of p-xylene and naphthol has the following structural formula:
  • the mass ratio of the polycondensate of p-xylene and dihydroxynaphthalene to the polycondensate of p-xylene and naphthol ranges from (1:0.5) to (1 :2).
  • the hydroxyl equivalent of the condensation polymer of p-xylene and dihydroxynaphthalene is in the range of 150-300, and the hydroxyl equivalent of the condensation polymer of p-xylene and naphthol is The range is 100-200.
  • the epoxy resin has a hydroxyl equivalent in the range of 50-100.
  • the epoxy resin is selected from bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin and hydrogenated bisphenol A type epoxy resin One or more of epoxy resins.
  • the filler is silicon dioxide.
  • the average particle diameter of the silicon dioxide is 0.1-100 ⁇ m.
  • the accelerator is selected from one or more of imidazole latent accelerators and amine latent accelerators.
  • the underfill further includes a pigment with a mass percentage of 0.1-0.3%.
  • the embodiment of the present application also provides a chip packaging structure, including a substrate, a chip arranged on the substrate, and a plurality of welding bumps arranged at intervals formed between the substrate and the chip, and the gap between the substrate and the chip is The gaps between the welding bumps are filled with an underfill material, and the underfill material is formed after the above underfill glue is cured.
  • the curing agent of the underfill adhesive for chip packaging of the present application includes the condensation polymer of p-xylene and dihydroxynaphthalene and the condensation polymer of p-xylene and naphthol, so that the underfill adhesive has a strong of stickiness.
  • the underfill has strong adhesion through the synergistic effect of the components in a specific ratio. Therefore, the underfill material formed after the underfill glue is cured has strong adhesion between the chip, the substrate, and the soldering bumps, and there will be no cracking, and the underfill material can be better fixed and protected. chip, so that the chip has high reliability and long-term usability.
  • FIG. 1 is a schematic structural diagram of a chip packaging structure provided by an embodiment of the present application.
  • the embodiment of the present application provides a quantum dot light-emitting diode and a preparation method thereof. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments. In addition, in the description of the present application, the term “including” means “including but not limited to”.
  • expressions such as “one or more” refer to one or more of the listed items, and “multiple” refers to any combination of two or more of these items, including single items (species) ) or any combination of plural items (species), for example, "at least one (species) of a, b, or c" or "at least one (species) of a, b, and c" can mean: a ,b,c,a-b (that is, a and b),a-c,b-c, or a-b-c, where a,b,c can be single or multiple.
  • the embodiment of the present application provides an underfill adhesive for chip packaging, including epoxy resin with a mass percentage of 19-25%, filler with a mass percentage of 55-60%, and a mass percentage of 15-25%
  • epoxy resin with a mass percentage of 19-25%
  • filler with a mass percentage of 55-60%
  • mass percentage of 15-25%
  • the curing agent, the pigment with a mass percentage of 0.1-0.3%, and the accelerator with a mass percentage of 0.5-0.8%.
  • the epoxy resin can be selected from but not limited to one or more of bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, hydrogenated bisphenol A type epoxy resin .
  • the epoxy resin contains hydroxyl groups, and the range of hydroxyl equivalents is 50-100, such as 50-80, or 60-90, or 80-100; Within the range of the hydroxyl equivalent, the epoxy resin has strong adhesion.
  • the filler may be silica.
  • the average particle diameter of the silicon dioxide is 0.1-100 ⁇ m. It can be understood that modified silicon dioxide with different particle sizes can be selected and used according to the size of the gap between the chip and the packaging substrate and/or between the soldering bumps.
  • the particle size of the modified silicon dioxide is preferably 0.1-5 ⁇ m; when the gap between the chip and the packaging substrate is in the range of 50-100 ⁇ m, the modified The particle size of silicon dioxide is preferably 0.1-2 ⁇ m; when the gap between the chip and the packaging substrate is in the range of 15-50 ⁇ m, the particle size of the modified silicon dioxide is preferably 0.1-0.5 ⁇ m; When the gap between the substrates is in the range of 6-15 ⁇ m, the particle size of the modified silica is preferably 0.1-0.3 ⁇ m.
  • the curing agent includes a polycondensate of p-xylene and dihydroxynaphthalene (curing agent (1)) and a polycondensate of p-xylene and naphthol (curing agent (2)).
  • the polycondensate of p-xylene and dihydroxynaphthalene has the following structural formula:
  • the polycondensate of p-xylene and naphthol has the following structural formula:
  • the hydroxyl equivalent of the curing agent (1) ranges from 150-300, for example, 150-200, or 180-250, or 160-300.
  • the hydroxyl equivalent of the curing agent (2) ranges from 100-200, for example, 100-150, or 120-180, or 160-200.
  • the addition of the curing agent (1) and the curing agent (2) makes the underfill adhesive have stronger adhesion after curing.
  • the range of the mass ratio of the curing agent (1) to the curing agent (2) is (1:0.5)-(1:2), such as (1:0.5)-(1:1), or (1:0.8 )-(1:1.2), or (1:1.1)-(1:1.6), or (1:1.5)-(1:2).
  • the underfill has strong adhesion.
  • the pigments are pigments known in the art for underfills, such as carbon black and the like.
  • the pigments can give the underfill a different appearance.
  • the accelerator may be selected from but not limited to one or more of imidazole latent accelerators and amine latent accelerators.
  • the amine latent accelerator may be benzyldimethylamine or the like.
  • the accelerator has the functions of lowering the curing temperature and prolonging the storage performance of the material, and can ensure that the multifunctional epoxy resin does not react at normal temperature, and makes the multifunctional epoxy resin have the greatest adhesion after heating.
  • the curing agent with the underfill adhesive for chip packaging of the present application includes the curing agent (1) and the curing agent (2), so that the underfill adhesive has strong adhesion after curing.
  • the underfill with strong adhesive force further enhances the adhesive force of the underfill through the synergistic effect of the components in a specific ratio.
  • the preparation method of the underfill with strong adhesion comprises the following steps:
  • Step S1 Add epoxy resin, filler, curing agent, pigment and accelerator into the mixing cup according to a certain proportion;
  • Step S2 Use a centrifugal mixer to stir for 90-300s at a speed of 800r/min in rotation and 1200r/min in revolution to obtain a mixture;
  • Step S3 Put the mixture into a three-roll mill, and roll mill to obtain a uniformly dispersed bottom filler, wherein, the feeding gap of the three rollers of the three-roll mill is 30-60 ⁇ m, and the discharging gap is 10- 30 ⁇ m.
  • Step S4 Use a centrifugal mixer to perform vacuum defoaming on the evenly dispersed underfill glue, wherein the vacuum defoaming time is 30-60s, the rotation speed of the centrifugal mixer is 800r/min, and the revolution speed is 1200r/min.
  • the embodiment of the present application also provides a chip packaging structure 100, including a substrate 10, a chip 20 disposed on the substrate 10, and a plurality of welding bumps arranged at intervals between the substrate 10 and the chip 20. 30.
  • the gap between the solder bumps 30 between the substrate 10 and the chip 20 is filled with an underfill material 40 .
  • the underfill material 40 is formed by curing the underfill glue for chip packaging.
  • the solder bump 30 is a solder bump made of a high-copper material, that is, the mass percentage of copper in the material of the solder bump 30 ranges from 1.4-1.8%.
  • the underfill material 40 filled in the gaps between the soldering bumps 30 of the chip packaging structure 100 is formed by curing the underfill glue for chip packaging, because the underfill glue for chip packaging has strong adhesion. Therefore, the underfill material 40 has strong adhesion between the chip 20, the substrate 10 and the soldering bump 30, and there will be no cracking, and the underfill material 40 can be better fixed and The chip 20 is protected so that the chip 20 has high reliability and long-term usability.
  • the model of curing agent (1) polycondensate of p-xylene and dihydroxynaphthalene is Nippon Steel Chemical Co., Ltd. SN-395
  • the model of curing agent (2) polycondensate of p-xylene and naphthol is : Nippon Steel Chemical Co., Ltd. SN-485.
  • MSL3 and TCB1000 (-55°C to -125°C) mean: Under the condition of moisture sensitivity level 3, the high and low temperature thermal cycle of -55°C to -125°C is 1000 times.
  • MSL3 and TCC200 (-65°C to -150°C) mean: Under the condition of moisture sensitivity level 3, the high and low temperature thermal cycle of -65°C to -150°C is 1000 times.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Polymers & Plastics (AREA)
  • Medicinal Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Inorganic Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Compositions Of Macromolecular Compounds (AREA)

Abstract

本申请公开一种芯片封装用底部填充胶及芯片封装结构，底部填充胶包括质量百分含量为19-25％的环氧树脂、质量百分含量为55-60％的填料、质量百分含量为15-25％的固化剂、及质量百分含量为0.5-0.8％的促进剂，所述固化剂包括对二甲苯与二羟基萘的缩聚物及对二甲苯与萘酚的缩聚物。

Description

一种芯片封装用底部填充胶及芯片封装结构
本申请要求于2021年07月27日在中国专利局提交的、申请号为202110849534.1、申请名称为“一种芯片封装用底部填充胶及芯片封装结”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体封装技术领域，尤其涉及一种底部填充胶、及使用所述底部填充胶的芯片封装结构。
背景技术
倒装芯片是将半导体芯片翻转后，通过焊接将焊点连接到基板上实现电路的导通。这种方法不同于传统方式，传统方式是在芯片四周打线，通过金线或铜线等连接到线路板上。倒装芯片的优点是芯片尺寸小，由于焊点与传统金线相比更短，减少的传输损耗，使得信号传输更快，同时导热效果更好。
为了能够满足电子器件可靠性的要求，倒装芯片一般采用底部填充技术。底部填充胶(Underfill)是一种适用于倒装芯片底部填充技术的材料，通常是利用毛细作用原理渗透到芯片与基板之间的间隙中，再通过热固化逐渐凝固并填充在芯片与基板之间的间隙中，保护芯片与基板之间的高密度焊接凸点及芯片。使用底部填充胶进行芯片底部封装可以降低芯片与基板之间的膨胀系数不匹配，保护芯片免受机械拉伸、剪切、扭曲、振动等有害的操作环境的影响，从而提高芯片的可靠性及长期使用性。如此，就要求底部填充胶具有优异的电、物理和机械性能。
底部填充胶填充在芯片与基板之间的间隙中并固化形成底部填充材料后，底部填充材料粘接在芯片、基板、及位于芯片与基板之间的焊接凸点上，从而对芯片、基板及焊接凸点进行保护。然而，现有的底部填充胶固化后形成的底部填充材料与芯片、基板及焊接凸点之间的粘着力不够强，经常会出现底部填充材料龟裂或从芯片、基板和/或焊接凸点上剥离的情况，而不能继续对芯片进行保护，而使芯片受损。
技术问题
因此，现有技术中的底部填充胶的粘着力有待进一步提高。
技术解决方案
因此，本申请提供一种芯片封装用底部填充胶及芯片封装结。
本申请实施例提供一种芯片封装用底部填充胶，包括质量百分含量为19-25％的环氧树脂、质量百分含量为55-60％的填料、质量百分含量为15-25％的固化剂、及质量百分含量为0.5-0.8％的促进剂，所述固化剂包括对二甲苯与二羟基萘的缩聚物及对二甲苯与萘酚的缩聚物，其中，
对二甲苯与二羟基萘的缩聚物具有以下结构式：
Figure PCTCN2022095506-appb-000001
对二甲苯与萘酚的缩聚物具有以下结构式：
Figure PCTCN2022095506-appb-000002
可选的，在本申请的一些实施例中，所述对二甲苯与二羟基萘的缩聚物与所述对二甲苯与萘酚的缩聚物质量比的范围为(1:0.5)-(1:2)。
可选的，在本申请的一些实施例中，所述对二甲苯与二羟基萘的缩聚物的羟基当量的范围为150-300，所述对二甲苯与萘酚的缩聚物的羟基当量的范围为100-200。
可选的，在本申请的一些实施例中，所述环氧树脂的羟基当量的范围为50-100。
可选的，在本申请的一些实施例中，所述环氧树脂选自双酚A型环氧树脂、双酚F型环氧树脂、双酚S型环氧树脂及氢化双酚A型环氧树脂中的一 种或多种。
可选的，在本申请的一些实施例中，所述填料为二氧化硅。
可选的，在本申请的一些实施例中，所述二氧化硅的平均粒径为0.1-100μm。
可选的，在本申请的一些实施例中，所述促进剂选自咪唑类潜伏性促进剂及胺类潜伏性促进剂中的一种或多种。
可选的，在本申请的一些实施例中，所述底部填充胶还包括质量百分含量为0.1-0.3％的颜料。
相应的，本申请实施例还提供一种芯片封装结构，包括基板、设置在基板上的芯片、及形成在基板与芯片之间的多个间隔设置的焊接凸点，所述基板与芯片之间的焊接凸点之间的间隙中填充有底部填充材料，所述底部填充材料由上述底部填充胶固化后形成。
有益效果
本申请的芯片封装用底部填充胶的固化剂包括所述对二甲苯与二羟基萘的缩聚物及所述对二甲苯与萘酚的缩聚物，使得所述底部填充胶完成固化后具有较强的粘着性。此外，所述底部填充胶通过特定配比的组分之间的协同作用，而具有较强的粘着力。因此，所述底部填充胶固化后形成的底部填充材料与芯片、基板及焊接凸点之间具有较强的粘着力，不会出现开裂的情况，所述底部填充材料可以较好的固定并保护芯片，使芯片具有高可靠性及长期使用性。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供一种芯片封装结构的结构示意图。
本申请的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
本申请实施例提供一种量子点发光二极管及其制备方法。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。另外，在本申请的描述中，术语“包括”是指“包括但不限于”。本申请中“一种或多种”等表述，是指所列举多项中的一种或者多种，“多种”是指这些项中两种或两种以上的任意组合，包括单项(种)或复数项(种)的任意组合，例如，“a、b或c中的至少一项(种)”或“a、b和c中的至少一项(种)”，均可以表示：a,b,c,a-b(即a和b),a-c,b-c,或a-b-c，其中a,b,c分别可以是单个，也可以是多个。本申请的各种实施例可以以一个范围的型式存在；应当理解，以一范围型式的描述仅仅是因为方便及简洁，不应理解为对本申请范围的硬性限制；因此，应当认为所述的范围描述已经具体公开所有可能的子范围以及该范围内的单一数值。例如，应当认为从1到6的范围描述已经具体公开子范围，例如从1到3，从1到4，从1到5，从2到4，从2到6，从3到6等，以及所述范围内的单一数字，例如1、2、3、4、5及6，此不管范围为何皆适用。另外，每当在本文中指出数值范围，是指包括所指范围内的任何引用的数字(分数或整数)。
本申请实施例提供一种芯片封装用底部填充胶，包括质量百分含量为19-25％的环氧树脂、质量百分含量为55-60％的填料、质量百分含量为15-25％的固化剂、质量百分含量为0.1-0.3％的颜料、质量百分含量为0.5-0.8％的促进剂。
所述环氧树脂可以选自但不限于双酚A型环氧树脂、双酚F型环氧树脂、双酚S型环氧树脂、氢化双酚A型环氧树脂中的一种或多种。所述环氧树脂中包含羟基，且羟基当量的范围为50-100，例如可以为50-80，或者60-90，或者80-100；作为示例可以为50、60、85、90、100。在所述羟基当量的范围内，所述环氧树脂具有较强的粘着力。
所述填料可以为二氧化硅。所述二氧化硅的平均粒径为0.1-100μm。可以理解，可以根据芯片与封装基板之间和/或焊接凸点之间的间隙大小选择使用不同粒径的改性二氧化硅。作为列举，在所述间隙为100μm范围内时，所述改性二氧化硅的粒径优选为0.1-5μm；在芯片与封装基板之间的间隙在50-100μm范围内时，所述改性二氧化硅的粒径优选为0.1-2μm；在芯片与封装基板之间的间隙在15-50μm范围内时，所述改性二氧化硅的粒径优选为0.1-0.5μm；在芯片与封装基板之间的间隙在6-15μm范围内时，所述改性二氧化硅的粒径优选为0.1-0.3μm。
所述固化剂包括对二甲苯与二羟基萘的缩聚物(固化剂(1))及对二甲苯与萘酚的缩聚物(固化剂(2))。
所述对二甲苯与二羟基萘的缩聚物具有以下结构式：
Figure PCTCN2022095506-appb-000003
所述对二甲苯与萘酚的缩聚物具有以下结构式：
Figure PCTCN2022095506-appb-000004
所述固化剂(1)的羟基当量的范围为150-300，例如可以为150-200，或者180-250，或者160-300。所述固化剂(2)的羟基当量的范围为100-200，例如可以为100-150，或者120-180，或者160-200。所述固化剂(1)及固化剂(2)的添加使得所述底部填充胶完成固化后具有较强的粘着性。
所述固化剂(1)与固化剂(2)质量比的范围为(1:0.5)-(1:2)，例如可以为(1:0.5)-(1:1)，或者(1:0.8)-(1:1.2)，或者(1:1.1)-(1:1.6)，或者(1:1.5)-(1:2)。在所述比例范围内，所述底部填充胶具有较强的粘着性。
所述颜料为本领域已知用于底部填充胶的颜料，如炭黑等。所述颜料可以使底部填充胶呈现不同的外观。
所述促进剂可以选自但不限于咪唑类潜伏性促进剂、胺类潜伏性促进剂中的一种或多种。作为列举，所述胺类潜伏性促进剂可以为苄基二甲胺等。所述促进剂具有降低固化温度，延长材料存储性的功能，能够保证多官能团环氧树脂在常温下不发生反应，而在加热后使多官能团环氧树脂具有最大的粘着力。
本申请的具有芯片封装用底部填充胶的固化剂包括所述固化剂(1)及固化剂(2)，使得所述底部填充胶完成固化后具有较强的粘着性。此外，所述具有强粘着力的底部填充胶通过特定配比的组分之间的协同作用，进一步增强了底部填充胶的粘着力。
在至少一实施例中，所述具有强粘着力的底部填充胶的制备方法包括如下步骤：
步骤S1：按照一定的配比将环氧树脂、填料、固化剂、颜料及促进剂加入搅拌杯中；
步骤S2：采用离心搅拌机，以自转800r/min、公转1200r/min的速度搅拌90-300s，得到混合物；
步骤S3：将所述混合物加入三辊研磨机中，辊磨，得到分散均匀的底部填充胶，其中，三辊研磨机的三辊筒的入料间隙为30-60μm，出料间隙为10-30μm。
步骤S4：使用离心搅拌机对所述分散均匀的底部填充胶进行真空脱泡，其中，真空脱泡时间为30-60s，离心搅拌机的自转速度为800r/min，公转速度为1200r/min。
请参阅图1，本申请实施例还提供一种芯片封装结构100，包括基板10、设置在基板10上的芯片20、及形成在基板10与芯片20之间的多个间隔设置的焊接凸点30。所述基板10与芯片20之间的焊接凸点30之间的间隙中填充有底部填充材料40。所述底部填充材料40由所述芯片封装用底部填充胶固化后形成。
在至少一实施例中，所述焊接凸点30为高铜材质的焊接凸点，即所述焊接凸点30的材质中铜的质量百分含量范围为1.4-1.8％。
所述芯片封装结构100的焊接凸点30之间的间隙中填充的底部填充材料40由所述芯片封装用底部填充胶固化后形成，因所述芯片封装用底部填充胶 具有较强的粘着力，因此，所述底部填充材料40与所述芯片20、基板10及焊接凸点30之间具有较强的粘着力，不会出现开裂的情况，所述底部填充材料40可以较好的固定并保护芯片20，使芯片20具有高可靠性及长期使用性。
下面通过具体实施例来对本申请进行具体说明，以下实施例仅是本申请的部分实施例，不是对本申请的限定。
以下实施例中，固化剂(1)对二甲苯与二羟基萘的缩聚物的型号为新日铁化学株式会社SN-395，固化剂(2)对二甲苯与萘酚的缩聚物的型号为：新日铁化学株式会社SN-485。
实施例1
Figure PCTCN2022095506-appb-000005
实施例2
Figure PCTCN2022095506-appb-000006
实施例3
Figure PCTCN2022095506-appb-000007
实施例4
Figure PCTCN2022095506-appb-000008
实施例5
Figure PCTCN2022095506-appb-000009
实施例6
Figure PCTCN2022095506-appb-000010
实施例7
Figure PCTCN2022095506-appb-000011
实施例8
Figure PCTCN2022095506-appb-000012
实施例9
Figure PCTCN2022095506-appb-000013
对比例1
Figure PCTCN2022095506-appb-000014
对比例2
Figure PCTCN2022095506-appb-000015
对比例3
Figure PCTCN2022095506-appb-000016
对比例4
Figure PCTCN2022095506-appb-000017
对比例5
Figure PCTCN2022095506-appb-000018
对所述实施例1-9的芯片封装用底部填充胶及对比例1-5的底部填充胶进行铜粘着力测试。测试方法为：在长5cm、宽1cm、厚0.1cm的铜片上，用聚四氟乙烯胶带贴成一个4×4mm的正方形格，将配制好的胶均匀涂覆在正方形格内，使用另一个新的铜片与之贴合，并用夹子固定，在150℃温度下热固化1h后，在万能拉伸试验机上测试底部填充胶对铜材质的粘接强度，测试结果参下表一。
表一：
Figure PCTCN2022095506-appb-000019
其中，RH表示相对湿度。atm表示标准大气压。MSL3及TCB1000(-55℃至-125℃)表示：湿气敏感性等级3条件下-55℃至-125℃高低温热循环一千次。MSL3及TCC200(-65℃至-150℃)表示：湿气敏感性等级3条件下-65℃至-150℃高低温热循环一千次。
由上表可知，实施例1-3的芯片封装用底部填充胶相较于实施例4-9的芯片封装用底部填充胶具有更强的粘着力。
实施例1-9的芯片封装用底部填充胶相较于对比例1-5的底部填充胶具有更强的粘着力，且不会从基板上分离及龟裂。
以上对本申请实施例所提供的芯片封装用底部填充胶进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (16)

  1. 一种芯片封装用底部填充胶，其中，包括质量百分含量为19-25％的环氧树脂、质量百分含量为55-60％的填料、质量百分含量为15-25％的固化剂、及质量百分含量为0.5-0.8％的促进剂，所述固化剂包括对二甲苯与二羟基萘的缩聚物及对二甲苯与萘酚的缩聚物，且对二甲苯与二羟基萘的缩聚物与对二甲苯与萘酚的缩聚物的质量比的范围为(1:0.5)-(1:2)，其中，
    对二甲苯与二羟基萘的缩聚物具有以下结构式：
    Figure PCTCN2022095506-appb-100001
    对二甲苯与萘酚的缩聚物具有以下结构式：
    Figure PCTCN2022095506-appb-100002
  2. 如权利要求1所述的底部填充胶，其中，所述对二甲苯与二羟基萘的缩聚物的羟基当量的范围为150-300，所述对二甲苯与萘酚的缩聚物的羟基当量的范围为100-200。
  3. 如权利要求1所述的底部填充胶，其中，所述环氧树脂的羟基当量的范围为50-100。
  4. 如权利要求1所述的底部填充胶，其中，所述环氧树脂选自双酚A型环氧树脂、双酚F型环氧树脂、双酚S型环氧树脂及氢化双酚A型环氧树脂中的一种或多种。
  5. 如权利要求1所述的底部填充胶，其中，所述填料为二氧化硅。
  6. 如权利要求5所述的底部填充胶，其中，所述二氧化硅的平均粒径为0.1-100μm。
  7. 如权利要求1所述的底部填充胶，其中，所述促进剂选自咪唑类潜伏性促进剂及胺类潜伏性促进剂中的一种或多种。
  8. 如权利要求1所述的底部填充胶，其中，所述底部填充胶还包括颜料，所述底部填充胶中，所述颜料的质量百分含量为0.1-0.3％。
  9. 一种芯片封装结构，包括基板、设置在基板上的芯片、及形成在基板与芯片之间的多个间隔设置的焊接凸点，所述基板与芯片之间的焊接凸点之间的间隙中填充有底部填充材料，其中，所述底部填充材料由芯片封装用底部填充胶固化后形成，所述底部填充胶包括质量百分含量为19-25％的环氧树脂、质量百分含量为55-60％的填料、质量百分含量为15-25％的固化剂、及质量百分含量为0.5-0.8％的促进剂，所述固化剂包括对二甲苯与二羟基萘的缩聚物及对二甲苯与萘酚的缩聚物，且对二甲苯与二羟基萘的缩聚物与对二甲苯与萘酚的缩聚物的质量比的范围为(1:0.5)-(1:2)，其中，
    对二甲苯与二羟基萘的缩聚物具有以下结构式：
    Figure PCTCN2022095506-appb-100003
    对二甲苯与萘酚的缩聚物具有以下结构式：
    Figure PCTCN2022095506-appb-100004
  10. 如权利要求9所述的芯片封装结构，其中，所述对二甲苯与二羟基萘的缩聚物的羟基当量的范围为150-300，所述对二甲苯与萘酚的缩聚物的羟基当量的范围为100-200。
  11. 如权利要求9所述的芯片封装结构，其中，所述环氧树脂的羟基当量的范围为50-100。
  12. 如权利要求9所述的芯片封装结构，其中，所述环氧树脂选自双酚A型环氧树脂、双酚F型环氧树脂、双酚S型环氧树脂及氢化双酚A型环氧树脂中的一种或多种。
  13. 如权利要求9所述的芯片封装结构，其中，所述填料为二氧化硅。
  14. 如权利要求13所述的芯片封装结构，其中，所述二氧化硅的平均粒径为0.1-100μm。
  15. 如权利要求9所述的芯片封装结构，其中，所述促进剂选自咪唑类潜伏性促进剂及胺类潜伏性促进剂中的一种或多种。
  16. 如权利要求9所述的芯片封装结构，其中，所述底部填充胶还包括颜料，所述底部填充胶中，所述颜料的质量百分含量为0.1-0.3％。
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