WO2022255048A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- WO2022255048A1 WO2022255048A1 PCT/JP2022/019913 JP2022019913W WO2022255048A1 WO 2022255048 A1 WO2022255048 A1 WO 2022255048A1 JP 2022019913 W JP2022019913 W JP 2022019913W WO 2022255048 A1 WO2022255048 A1 WO 2022255048A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- semiconductor device
- terminal
- metal layer
- semiconductor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 230
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 229910052751 metal Inorganic materials 0.000 claims description 118
- 239000002184 metal Substances 0.000 claims description 118
- 239000000463 material Substances 0.000 claims description 34
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 239000010949 copper Substances 0.000 claims description 18
- 229910052802 copper Inorganic materials 0.000 claims description 17
- 229910052709 silver Inorganic materials 0.000 claims description 8
- 239000004332 silver Substances 0.000 claims description 8
- 238000001514 detection method Methods 0.000 description 78
- 239000000470 constituent Substances 0.000 description 22
- 229920005989 resin Polymers 0.000 description 12
- 239000011347 resin Substances 0.000 description 12
- 238000007789 sealing Methods 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 7
- 229910000881 Cu alloy Inorganic materials 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000007769 metal material Substances 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000004734 Polyphenylene sulfide Substances 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229920000069 polyphenylene sulfide Polymers 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
Definitions
- the present disclosure relates to semiconductor devices.
- Patent Document 1 discloses an example of a semiconductor device mounted with a plurality of semiconductor elements such as MOSFETs.
- a metal layer composed of a metal thin film such as a copper foil is arranged on a substrate (insulation layer) composed of an electrical insulation member.
- a plurality of semiconductor elements are conductively joined to the metal layer via a conductive joining layer such as solder.
- the semiconductor device can easily cope with large current flow by increasing the number of semiconductor elements.
- the present disclosure has been conceived under the circumstances described above, and aims to provide a semiconductor device that is suitable for efficiently dissipating heat generated by a plurality of semiconductor elements and allowing a large amount of current to flow. Let it be the first issue.
- a semiconductor device provided by the present disclosure includes a substrate having a main surface facing one side in the thickness direction, and a plurality of semiconductor elements positioned on one side in the thickness direction with respect to the substrate and having a switching function. a conductive first layer located between the main surface and the plurality of semiconductor elements in the thickness direction, and a second layer electrically connecting the main surface and the first layer; and a third layer electrically connecting the first layer and the plurality of semiconductor elements.
- the semiconductor device of the present disclosure it is possible to efficiently dissipate heat generated by a plurality of semiconductor elements.
- FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure
- FIG. 2 is a plan view of the semiconductor device shown in FIG. 1
- FIG. FIG. 2 is a perspective view of the semiconductor device shown in FIG. 1 (seeing through a sealing resin and wires);
- 2 is a plan view (transmissive through a sealing resin) of the semiconductor device shown in FIG. 1;
- FIG. 2 is a front view of the semiconductor device shown in FIG. 1;
- FIG. 2 is a right side view of the semiconductor device shown in FIG. 1;
- FIG. 2 is a left side view of the semiconductor device shown in FIG. 1;
- FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1;
- FIG. FIG. 5 is an enlarged view of the right side of FIG. 4;
- FIG. 5 is an enlarged view of the left side of FIG. 4; 5 is a cross-sectional view along line XI-XI of FIG. 4; FIG. 5 is a cross-sectional view along line XII-XII in FIG. 4; FIG. FIG. 5 is a cross-sectional view along line XIII-XIII of FIG. 4; 5 is a cross-sectional view along line XIV-XIV in FIG. 4; FIG. FIG. 10 is a partially enlarged view (periphery of the first element) of FIG. 9; FIG. 16 is a cross-sectional view along line XVI-XVI of FIG. 15; FIG. 10 is a partially enlarged view (periphery of a second element) of FIG. 9; FIG.
- FIG. 18 is a cross-sectional view along line XVIII-XVIII in FIG. 17;
- FIG. 11 is a plan view (transmissive through a sealing resin) showing a semiconductor device according to a modification of the first embodiment;
- 20 is a partially enlarged view (periphery of the first element) of FIG. 19;
- FIG. 21 is a cross-sectional view along line XXI-XXI of FIG. 20;
- FIG. 20 is a partially enlarged view (periphery of a second element) of FIG. 19;
- FIG. FIG. 23 is a cross-sectional view along line XXIII-XXIII of FIG. 22;
- FIG. 10 is a plan view (transmissive through a sealing resin) showing a semiconductor device according to a second embodiment of the present disclosure
- FIG. 25 is an enlarged view of the right side of FIG. 24
- FIG. 25 is a cross-sectional view along line XXVI-XXVI of FIG. 24;
- a certain entity A is formed on a certain entity B” and “a certain entity A is formed on a certain entity B” mean “a certain entity A is formed on a certain entity B”. It includes "being directly formed in entity B” and “being formed in entity B while another entity is interposed between entity A and entity B”.
- ⁇ an entity A is placed on an entity B'' and ⁇ an entity A is located on an entity B'' mean ⁇ an entity A is located on an entity B.'' It includes "directly placed on B” and "some entity A is placed on an entity B while another entity is interposed between an entity A and an entity B.”
- ⁇ an object A is located on an object B'' means ⁇ an object A is adjacent to an object B and an object A is positioned on an object B. and "the thing A is positioned on the thing B while another thing is interposed between the thing A and the thing B".
- ⁇ an object A overlaps an object B when viewed in a certain direction'' means ⁇ an object A overlaps all of an object B'' and ⁇ an object A overlaps an object B.'' It includes "overlapping a part of a certain thing B".
- a semiconductor device A10 includes a substrate 10, a first layer 20, a second layer 21, a third layer 22, and a plurality of semiconductor elements 30. As shown in FIG. In this embodiment, the semiconductor device A10 includes a plurality of power supply terminals 23, an output terminal 24, a plurality of gate terminals 25, a plurality of element current detection terminals 26, a plurality of conduction members 40, a case 60, and a sealing resin 70. .
- FIG. 3 shows the sealing resin 70 and wires described later.
- FIG. 4 is transparent through the sealing resin 70 .
- the semiconductor device A10 shown in FIG. 1 is a power module.
- the semiconductor device A10 is used for inverters such as various electric appliances and hybrid vehicles.
- the semiconductor device A10 has a rectangular shape (or a substantially rectangular shape) when viewed in the thickness direction z of the substrate 10 .
- the direction orthogonal to the thickness direction z is called the first direction x.
- a direction orthogonal to both the thickness direction z and the first direction x is called a second direction y.
- the semiconductor device A10 is elongated along the first direction x, but the present disclosure is not limited thereto.
- the substrate 10 has a first metal layer 11, a second metal layer 12 and an insulating layer 13, as shown in FIG.
- the insulating layer 13 is located between the first metal layer 11 and the second metal layer 12 in the thickness direction z.
- the insulating layer 13 has electrical insulation.
- a constituent material of the insulating layer 13 is, for example, ceramic epoxy.
- the first metal layer 11 is laminated on the insulating layer 13 .
- the first metal layer 11 includes a primary surface 11A.
- the main surface 11A faces one side in the thickness direction z (upper side in FIG. 11).
- the first metal layer 11 is made of a metal material having conductivity, and is made of, for example, a metal foil made of copper (Cu) or a copper alloy.
- the second metal layer 12 is located on the side opposite to the first metal layer 11 (the other side in the thickness direction z) with respect to the insulating layer 13, and the insulating layer 13 is laminated on the second metal layer 12. .
- the second metal layer 12 is made of a conductive metal material like the first metal layer 11, and is made of, for example, a metal plate made of copper or a copper alloy.
- the thickness of the first metal layer 11 is 0.1 mm to 2.0 mm
- the thickness of the second metal layer 12 is 0.3 mm to 2.0 mm
- the thickness of the insulating layer 13 is 0.12 mm to 0.18 mm.
- an insulated metal substrate may be used as the substrate 10 of the present embodiment.
- a substrate 10 made of an insulating metal substrate is configured by laminating an insulating layer 13 and a first metal layer 11 on a metal plate (second metal layer 12).
- a DBC (Direct Bonded Copper) substrate may be used instead of the insulating metal substrate.
- the DBC substrate is composed of a ceramic plate (insulating layer 13) and a pair of copper foils (first metal layer 11 and second metal layer 12) laminated on the ceramic plate on both sides in the thickness direction z.
- the first metal layer 11 includes a first element mounting portion 111, a second element mounting portion 112, a first conductive portion 113, a first gate portion 114, a first detection portion 115, and a pair of thermistor mounting portions 116. , a second gate section 117 and a second detection section 118 .
- Each part constituting the first metal layer 11 is formed, for example, by partially removing the copper foil laminated on the insulating layer 13 by wet etching.
- the surface of each portion of the first metal layer 11 may be plated with silver (Ag).
- a plurality of semiconductor elements 30 are mounted on the first element mounting portion 111.
- the plurality of semiconductor elements 30 mounted on the first element mounting portion 111 will be referred to as "plurality of first elements 31".
- the first element mounting portion 111 is positioned on one end side of the substrate 10 in the second direction y (upper side in FIG. 4).
- the first element mounting portion 111 has a strip shape extending in the first direction x.
- ten first elements 31 are mounted on the first element mounting portion 111, but the number of first elements 31 is not limited to this.
- a strip-shaped first power supply pad 111a extending in the second direction y is formed at one end (right side in FIG. 4) of the first element mounting portion 111 in the first direction x.
- a plurality of semiconductor elements 30 are mounted on the second element mounting portion 112.
- FIG. 4 the plurality of semiconductor elements 30 mounted on the second element mounting portion 112 will be referred to as "a plurality of second elements 32".
- the second element mounting portion 112 is positioned between the first element mounting portion 111 and the first conductive portion 113 in the second direction y.
- the second element mounting portion 112 has a strip shape extending in the first direction x.
- ten second elements 32 are mounted on the second element mounting portion 112, but the number of second elements 32 is not limited to this.
- a strip-shaped output pad 112a extending in the second direction y is formed at one end (left side in FIG. 4) of the second element mounting portion 112 in the first direction x.
- a part of the output pad 112a located on one side (upper side in FIG. 4) of the second element mounting portion 112 in the second direction y is located next to the first element mounting portion 111 in the first direction x.
- a portion of the output pad 112a located on the other side (lower side in FIG. 4) of the second element mounting portion 112 in the second direction y is located next to the first conductive portion 113 in the first direction x.
- the first conductive portion 113 is electrically connected to both the multiple first elements 31 and the multiple second elements 32 .
- the first conductive portion 113 is located on the side opposite to the first element mounting portion 111 with respect to the second element mounting portion 112 in the second direction y.
- the first conductive portion 113 has a strip shape extending in the first direction x.
- a strip-shaped second power supply pad 113a extending in the second direction y is formed at one end (right side in FIG. 4) of the first conductive portion 113 in the first direction x.
- the first conductive portion 113 is formed with a notch 113b extending in the first direction x.
- the notch 113b is located in the center of the first conductive portion 113 in the second direction y and extends from one end (the right end in FIG. 4) in the first direction x to the center in the first direction x.
- the first gate section 114 is electrically connected to the plurality of first elements 31, as shown in FIGS.
- the first gate portion 114 has a strip shape extending in the first direction x.
- the first gate portion 114 is positioned between the first element mounting portion 111 and the case 60 in the second direction y.
- the first gate portions 114 are folded at one end portion (the right end portion in FIG. 4) in the first direction x, and are formed in two rows in the second direction y.
- the width (dimension in the second direction y) of the first gate portion 114 is smaller than the widths of the first element mounting portion 111 , the second element mounting portion 112 and the first conductive portion 113 .
- the first detector 115 is electrically connected to the plurality of first elements 31, as shown in FIGS.
- the first detection unit 115 has a strip shape extending in the first direction x.
- the first detection portion 115 is positioned between the first element mounting portion 111 and the case 60 in the second direction y.
- the first detectors 115 are folded at one end (the left end in FIG. 4) in the first direction x, and formed in two rows in the second direction y.
- the width of the first detection section 115 (dimension in the second direction y) is the same as the width of the first gate section 114 .
- the pair of thermistor mounting portions 116 are separated from each other in the second direction y and mount the thermistor 33 thereon.
- a pair of thermistor mounting portions 116 are positioned near the corners of the substrate 10 .
- a first element mounting portion 111 , a first gate portion 114 and a first detection portion 115 are positioned around the pair of thermistor mounting portions 116 .
- the second gate section 117 is electrically connected to the plurality of second elements 32, as shown in FIGS.
- the second gate portion 117 has a strip shape extending in the first direction x.
- the second gate portion 117 is positioned between the first conductive portion 113 and the case 60 in the second direction y.
- the second gate portions 117 are folded at one end (the left end in FIG. 4) in the first direction x, and formed in two rows in the second direction y.
- the width (dimension in the second direction y) of the second gate portion 117 is smaller than the widths of the first element mounting portion 111 , the second element mounting portion 112 and the first conductive portion 113 .
- the second detector 118 is electrically connected to the plurality of second elements 32, as shown in FIGS.
- the second detector 118 has a strip shape extending in the first direction x.
- the second detection section 118 is positioned between the first conductive section 113 and the case 60 in the second direction y.
- the second detectors 118 are folded at one end (the right end in FIG. 4) in the first direction x, and formed in two rows in the second direction y.
- the width of the second detection section 118 (dimension in the second direction y) is the same as the width of the second gate section 117 .
- the plurality of power supply terminals 23 are part of the external connection terminals provided on the semiconductor device A10, as shown in FIGS.
- a plurality of power supply terminals 23 are connected to a DC power supply arranged outside the semiconductor device A10.
- the power terminals 23 are supported by the case 60 .
- the plurality of power supply terminals 23 are made of metal plates.
- a constituent material of the metal plate is, for example, copper.
- the thickness of the plurality of power supply terminals 23 is, for example, approximately 1.0 mm.
- the plurality of power terminals 23 include a first power terminal 23a and a second power terminal 23b.
- the first power terminal 23a is a positive electrode (P terminal).
- the first power terminal 23 a is connected to the first power pad 111 a of the first element mounting portion 111 .
- the second power terminal 23b is a negative electrode (N terminal).
- the second power supply terminal 23b is connected to the second power supply pad 113a of the first conductive portion 113 .
- the first power terminal 23a and the second power terminal 23b are separated from each other in the second direction y.
- each of the first power terminal 23 a and the second power terminal 23 b has an external connection portion 231 , an internal connection portion 232 and an intermediate portion 233 .
- the external connection part 231 has a flat plate shape exposed from the semiconductor device A10 and orthogonal to the thickness direction z.
- a DC power cable or the like is connected to the external connection portion 231 .
- the external connection portion 231 is supported by the case 60 .
- the external connection portion 231 is provided with a connection hole 231a penetrating in the thickness direction z.
- a fastening member such as a bolt is inserted into the connection hole 231a.
- the surface of the external connection portion 231 may be plated with nickel (Ni).
- the internal connection portion 232 is connected to the first power pad 111a of the first element mounting portion 111 at the first power terminal 23a, and is connected to the second power pad 113a of the first conductive portion 113 at the second power terminal 23b. It is dentate.
- the internal connection portion 232 has three teeth, and these multiple teeth are arranged along the second direction y. A plurality of teeth are bent in the thickness direction z. Therefore, the plurality of teeth are hook-shaped when viewed in the second direction y. The plurality of teeth are all connected to the first power supply pad 111a and the second power supply pad 113a by ultrasonic bonding.
- the intermediate portion 233 connects the external connection portion 231 and the internal connection portion 232 to each other.
- the intermediate portion 233 has an L-shaped cross section with respect to the first direction x.
- the intermediate portion 233 has a base portion 233a and an upright portion 233b.
- the base 233a extends along the first direction x and the second direction y.
- One end of the base portion 233 a in the first direction x is connected to the internal connection portion 232 .
- the standing portion 233b stands up in the thickness direction z from the base portion 233a.
- One end of the standing portion 233 b in the thickness direction z is connected to the external connection portion 231 .
- the output terminals 24 are part of the external connection terminals provided on the semiconductor device A10, as shown in FIGS.
- the output terminal 24 is connected to a power supply object (such as a motor) arranged outside the semiconductor device A10.
- the output terminal 24 is supported by the case 60 and positioned on the opposite side of the substrate 10 from the plurality of power supply terminals 23 in the first direction x.
- the output terminal 24 is made of a metal plate.
- a constituent material of the metal plate is, for example, copper.
- the thickness of the output terminal 24 is 1.0 mm.
- the output terminal 24 is separated into two, a first terminal portion 24a and a second terminal portion 24b.
- the output terminal 24 may be a single member that is not separated like the semiconductor device A10.
- the first terminal portion 24 a and the second terminal portion 24 b are connected in parallel to the output pad 112 a of the second element mounting portion 112 . Therefore, the output terminal 24 is connected to the second element mounting portion 112 .
- the first terminal portion 24a and the second terminal portion 24b are separated from each other in the second direction y.
- each of the first terminal portion 24a and the second terminal portion 24b has an external connection portion 241, an internal connection portion 242 and an intermediate portion 243.
- the external connection part 241 has a flat plate shape exposed from the semiconductor device A10 and perpendicular to the thickness direction z. A cable or the like that conducts to a power supply target is connected to the external connection portion 241 .
- the external connection portion 241 is supported by the case 60 .
- the external connection portion 241 is provided with a connection hole 241a penetrating in the thickness direction z. A fastening member such as a bolt is inserted into the connection hole 241a. Note that the surface of the external connection portion 241 may be plated with nickel.
- the internal connection portion 242 has a comb shape connected to the output pad 112 a of the second element mounting portion 112 .
- the internal connection portion 242 has three teeth, and these multiple teeth are arranged along the second direction y.
- a plurality of teeth are bent in the thickness direction z. Therefore, the plurality of teeth are hook-shaped when viewed in the second direction y. All of the teeth are connected to the output pad 112a by ultrasonic bonding.
- the intermediate portion 243 connects the external connection portion 241 and the internal connection portion 242 to each other.
- the intermediate portion 243 has an L-shaped cross section with respect to the first direction x.
- the intermediate portion 243 has a base portion 243a and an upright portion 243b.
- the base 243a extends along the first direction x and the second direction y.
- One end of the base portion 243 a in the first direction x is connected to the internal connection portion 242 .
- the standing portion 243b stands up in the thickness direction z from the base portion 243a.
- One end of the standing portion 243 b in the thickness direction z is connected to the external connection portion 241 .
- the plurality of gate terminals 25 are part of the external connection terminals provided on the semiconductor device A10, as shown in FIGS.
- a plurality of gate terminals 25 are electrically connected to either the first gate section 114 or the second gate section 117 .
- the plurality of gate terminals 25 are connected to a driving circuit (eg, gate driver) of the semiconductor device A10 arranged outside.
- a plurality of gate terminals 25 are supported by the case 60 .
- a plurality of gate terminals 25 are composed of metal rods.
- a constituent material of the metal bar is, for example, copper.
- the surfaces of the plurality of gate terminals 25 may be plated with tin (Sn) or nickel and tin. As shown in FIG.
- the plurality of gate terminals 25 has an L-shaped cross section with respect to the first direction x. A part of each of the plurality of gate terminals 25 protrudes from the case 60 toward the main surface 11A of the first metal layer 11 (substrate 10) in the thickness direction z.
- the multiple gate terminals 25 include a first gate terminal 25a and a second gate terminal 25b.
- the first gate terminal 25a is close to the first gate portion 114 in the second direction y, as shown in FIG.
- the second gate terminal 25b is located on the opposite side of the first metal layer 11 (substrate 10) from the first gate terminal 25a in the second direction y, as shown in FIG.
- the second gate terminal 25b is close to the second gate section 117 .
- the plurality of device current detection terminals 26 are part of the external connection terminals provided on the semiconductor device A10, as shown in FIGS.
- a plurality of device current detection terminals 26 are electrically connected to either the first detection section 115 or the second detection section 118 .
- a plurality of device current detection terminals 26 are connected to a control circuit of the semiconductor device A10 arranged outside.
- a plurality of device current detection terminals 26 are supported by a case 60 .
- the plurality of device current detection terminals 26 are made of metal rods.
- a constituent material of the metal rod is, for example, copper.
- the surfaces of the plurality of device current detection terminals 26 may be tinned, or nickel-plated and tin-plated. As shown in FIG.
- the plurality of device current detection terminals 26 have an L-shaped cross section with respect to the first direction x. A part of each of the plurality of device current detection terminals 26 protrudes from the case 60 toward the main surface 11A of the first metal layer 11 (substrate 10) in the thickness direction z.
- the plurality of element current detection terminals 26 include a first detection terminal 26a and a second detection terminal 26b.
- the first detection terminal 26a is located next to the first gate terminal 25a in the first direction x, as shown in FIG.
- the second detection terminal 26b is positioned next to the second gate terminal 25b in the first direction x, as shown in FIG.
- the semiconductor device A10 has a power supply current detection terminal 27.
- the power supply current detection terminal 27 is part of the external connection terminals provided on the semiconductor device A10.
- the power supply current detection terminal 27 is connected to the control circuit of the semiconductor device A10 arranged outside.
- the power supply current detection terminal 27 is supported by the case 60 .
- the power supply current detection terminal 27 is composed of a metal rod.
- a constituent material of the metal rod is, for example, copper.
- the surface of the power supply current detection terminal 27 may be tin-plated, or nickel-plated and tin-plated.
- the shape of the power supply current detection terminal 27 is the same as that of the plurality of gate terminals 25 shown in FIG.
- a portion of the power supply current detection terminal 27 protrudes from the case 60 toward the main surface 11A of the first metal layer 11 (substrate 10) in the thickness direction z, like the gate terminal 25 shown in FIG. In the second direction y, the position of the power supply current detection terminal 27 is the same as the position of the first gate terminal 25a.
- the power supply current detection terminal 27 is separated from the first gate terminal 25a toward the first terminal portion 24a (output terminal 24) in the first direction x.
- the semiconductor device A10 includes a power supply current detection wire 45.
- the power current detection wire 45 is a conductive member connected to the power current detection terminal 27 and the first element mounting portion 111 .
- the power supply current detection terminal 27 is electrically connected to the first element mounting portion 111 .
- the constituent material of the power supply current detection wire 45 is, for example, aluminum.
- the semiconductor device A10 has a pair of thermistor terminals 28.
- the pair of thermistor terminals 28 are part of the external connection terminals provided on the semiconductor device A10.
- a pair of thermistor terminals 28 are connected to a control circuit of the semiconductor device A10 arranged outside.
- a pair of thermistor terminals 28 are supported by a case 60 .
- a pair of thermistor terminals 28 are composed of metal rods.
- a constituent material of the metal rod is, for example, copper.
- the surfaces of the pair of thermistor terminals 28 may be tin-plated, or nickel-plated and tin-plated.
- the shape of the pair of thermistor terminals 28 is the same as that of the plurality of gate terminals 25 shown in FIG. A part of the pair of thermistor terminals 28 protrudes from the case 60 toward the main surface 11A of the first metal layer 11 (substrate 10) in the thickness direction z, like the gate terminals 25 shown in FIG. In the second direction y, the position of the pair of thermistor terminals 28 is the same as the position of the first gate terminal 25a.
- the pair of thermistor terminals 28 are separated from the first gate terminal 25a toward the first power supply terminal 23a in the first direction x.
- the pair of thermistor terminals 28 are separated from each other in the first direction x.
- the semiconductor device A10 includes a pair of thermistor wires 46.
- the pair of thermistor wires 46 are conductive members individually connected to the pair of thermistor terminals 28 and the pair of thermistor mounting portions 116 .
- the pair of thermistor terminals 28 are electrically connected to the pair of thermistor mounting portions 116 .
- the constituent material of the pair of thermistor wires 46 is, for example, aluminum.
- Each of the plurality of semiconductor elements 30 (the plurality of first elements 31 and the plurality of second elements 32) has a semiconductor layer containing, for example, silicon carbide (SiC) and has a switching function.
- the plurality of semiconductor elements 30 are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) configured using a semiconductor material mainly composed of silicon carbide.
- the semiconductor element 30 is not limited to a MOSFET, and may be an IGBT (Insulated Gate Bipolar Transistor). In the semiconductor device A10, a case where the plurality of semiconductor elements 30 are MOSFETs will be described. As shown in FIGS.
- the semiconductor element 30 has a rectangular shape (square shape in the semiconductor device A10) when viewed in the thickness direction z.
- the thickness of semiconductor element 30 is, for example, 400 ⁇ m or less, and more preferably 150 ⁇ m or less.
- each of the plurality of semiconductor elements 30 has a source electrode 301, a drain electrode 302 and a gate electrode 303.
- FIG. The source electrode 301 is provided at the upper end of the semiconductor element 30 located on the side facing the main surface 11A of the first metal layer 11 (substrate 10) in the thickness direction z.
- a source current flows from the inside of the semiconductor element 30 to the source electrode 301 .
- the drain electrode 302 is provided at the lower end of the semiconductor element 30 located on the side opposite to the main surface 11A of the first metal layer 11 (substrate 10) in the thickness direction z. A drain current flows through the drain electrode 302 toward the inside of the semiconductor element 30 .
- the gate electrode 303 is provided at the upper end of the semiconductor element 30 located on the side facing the main surface 11A of the first metal layer 11 (substrate 10) in the thickness direction z.
- a gate voltage for driving the semiconductor element 30 is applied to the gate electrode 303 .
- the area of the gate electrode 303 is smaller than the area of the source electrode 301 when viewed in the thickness direction z.
- the multiple semiconductor elements 30 include multiple first elements 31 and multiple second elements 32 .
- the plurality of first elements 31 are mounted on the first element mounting portions 111 respectively.
- the plurality of first elements 31 are arranged at predetermined intervals in the first direction x.
- the plurality of second elements 32 are mounted on the second element mounting portions 112 respectively.
- the plurality of second elements 32 are arranged at predetermined intervals in the first direction x.
- the first layer 20 is the main portion of the first metal layer 11 (the first element mounting portion 111 and the second element mounting portion 112) in the thickness direction z. It is positioned between the surface 11A and the plurality of semiconductor elements 30 .
- the first layer 20 is made of a conductive metal material.
- the first layer 20 is made of a material having the same thermal conductivity as that of the second metal layer 12 or a material having a higher thermal conductivity than that of the second metal layer 12 .
- the first layer 20 is made of copper or a copper alloy, for example. When the constituent material of the first layer 20 is copper, the thermal conductivity of the first layer 20 is 398 W/mk.
- the constituent material of the first layer 20 examples include aluminum, iron, and carbon, in addition to copper and copper alloys.
- the thickness of the first layer 20 is greater than the thickness of the second metal layer 12 .
- the thickness of the first layer 20 is between 1 and 10 times the thickness of the second metal layer 12 .
- An example of the thickness of the first layer 20 is 1 mm to 4 mm, more preferably 2 mm to 3 mm.
- the first layer 20 includes a plurality of individual parts 201 separated from each other.
- the plurality of individual portions 201 are arranged individually corresponding to the plurality of semiconductor elements 30, respectively.
- Each of the plurality of semiconductor elements 30 is supported by one of the plurality of individual portions 201 .
- the plurality of individual portions 201 corresponding to the plurality of first elements 31 are supported by the first element mounting portion 111 and arranged at intervals in the first direction x.
- the plurality of individual portions 201 corresponding to the plurality of second elements 32 are supported by the second element mounting portion 112 and arranged at intervals in the first direction x.
- Each individual portion 201 is larger than the semiconductor element 30 when viewed in the thickness direction z.
- the individual portion 201 has a rectangular shape (square shape in the semiconductor device A10) when viewed in the thickness direction z.
- the second layer 21 is positioned between the first metal layer 11 (the first element mounting portion 111 and the second element mounting portion 112) and the first layer 20 (the plurality of individual portions 201) in the thickness direction z. do.
- the second layer 21 has conductivity, and conducts and joins the main surface 11A of each of the first element mounting portion 111 and the second element mounting portion 112 and the plurality of individual portions 201 .
- the constituent material of the second layer 21 is, for example, lead-free solder containing tin as a main component.
- the thickness of the second layer 21 is, for example, 0.02 mm to 0.20 mm.
- the second layer 21 has a plurality of regions separated from each other.
- the plurality of regions of the second layer 21 individually correspond to the plurality of individual portions 201, respectively.
- the second layer 21 may be configured to have a region common to some of the plurality of individual portions 201 .
- the second layer 21 includes a region common to the plurality of individual portions 201 supported by the first element mounting portion 111, a region common to the plurality of individual portions 201 supported by the second element mounting portion 112, may be a configuration having
- the third layer 22 is located between the first layer 20 (the plurality of individual parts 201) and the plurality of semiconductor elements 30 in the thickness direction z.
- the third layer 22 has electrical conductivity and electrically connects the plurality of individual portions 201 and the plurality of semiconductor elements 30 . More specifically, the third layer 22 electrically connects the drain electrode 302 of each semiconductor element 30 and the first layer 20 (individual portion 201 ).
- the third layer 22 is made of a bonding material containing a metal material. In the semiconductor device A10, the constituent material of the third layer 22 contains silver. In the semiconductor device A10, the third layer 22 is sintered silver.
- the third layer 22 may be made of a sintered metal containing a metal other than silver (for example, sintered copper), solid-phase diffusion-bonded aluminum, solder, or a metal paste material.
- the thickness of the third layer 22 is, for example, 0.02 mm to 0.20 mm.
- the plurality of conductive members 40 are connected to the source electrodes 301 of the plurality of semiconductor elements 30 and either the second element mounting portion 112 or the first conductive portion 113. It is
- the plurality of conducting members 40 are made of metal plates. The metal in question is copper or a copper alloy.
- the plurality of conduction members 40 are metal plate members that are bent.
- the plurality of conducting members 40 includes a plurality of first conducting members 41 and a plurality of second conducting members 42 .
- Each of the multiple first conductive members 41 is joined to the source electrode 301 of one of the multiple first elements 31 and the second element mounting portion 112 .
- the first conductive member 41 and the second element mounting portion 112 are bonded via the conductive member bonding layer 48 .
- the first conductive member 41 and the source electrode 301 of each first element 31 are bonded via the conductive member bonding layer 49 .
- Conductive member bonding layer 48 and conductive member bonding layer 49 bonded to first conductive member 41 are, for example, solder, metal paste material, or sintered metal.
- Each of the plurality of second conductive members 42 is joined to the source electrode 301 of one of the plurality of second elements 32 and the first conductive portion 113 .
- the second conductive member 42 and the first conductive portion 113 are bonded via the conductive member bonding layer 48 .
- the second conductive member 42 and the source electrode 301 of each second element 32 are bonded via the conductive member bonding layer 49 .
- Conductive member bonding layer 48 and conductive member bonding layer 49 bonded to second conductive member 42 are, for example, solder, metal paste material, or sintered metal.
- the semiconductor device A10 includes a thermistor 33, as shown in FIGS.
- the thermistor 33 is electrically connected to the pair of thermistor mounting portions 116 .
- the thermistor 33 is an NTC (Negative Temperature Coefficient) thermistor.
- An NTC thermistor has a characteristic that its resistance gradually decreases with temperature rise.
- the thermistor 33 is used as a temperature detection sensor for the semiconductor device A10.
- the thermistor 33 is electrically connected to the pair of thermistor terminals 28 via the pair of thermistor mounting portions 116 and the pair of thermistor wires 46 .
- the semiconductor device A10 includes a plurality of first gate wires 431, a plurality of second gate wires 432, a third gate wire 433 and a fourth gate wire 434.
- Each of the plurality of first gate wires 431 is a conductive member having one end connected to the gate electrode 303 of one of the plurality of first elements 31 and the other end connected to the first gate section 114 .
- Each of the plurality of second gate wires 432 is a conductive member having one end connected to the gate electrode 303 of one of the plurality of second elements 32 and the other end connected to the second gate section 117 .
- the constituent material of the plurality of first gate wires 431 and the plurality of second gate wires 432 is aluminum, for example.
- the third gate wire 433 is a conductive member connected to the first gate terminal 25 a and the first gate section 114 .
- the first gate terminal 25 a is electrically connected to the gate electrodes 303 of the plurality of first elements 31 mounted on the first element mounting portion 111 .
- a fourth gate wire 434 is a conductive member connected to the second gate terminal 25 b and the second gate portion 117 .
- the second gate terminal 25 b is electrically connected to the gate electrodes 303 of the plurality of second elements 32 mounted on the second element mounting portion 112 .
- the constituent material of the third gate wire 433 and the fourth gate wire 434 is aluminum, for example.
- the semiconductor device A10 includes a plurality of first detection wires 441, a plurality of second detection wires 442, a third detection wire 443 and a fourth detection wire 444.
- Each of the plurality of first detection wires 441 is a conductive member having one end connected to the source electrode 301 of one of the plurality of first elements 31 and the other end connected to the first detection section 115 .
- Each of the plurality of second detection wires 442 is a conductive member having one end connected to the source electrode 301 of one of the plurality of second elements 32 and the other end connected to the second detection section 118 .
- a constituent material of the plurality of first detection wires 441 and the plurality of second detection wires 442 is, for example, aluminum.
- the third detection wire 443 is a conductive member connected to the first detection terminal 26 a and the first detection section 115 .
- the first detection terminals 26 a are electrically connected to the source electrodes 301 of the plurality of first elements 31 mounted on the first element mounting portion 111 .
- a fourth detection wire 444 is a conductive member connected to the second detection terminal 26 b and the second detection section 118 .
- the second detection terminals 26 b are electrically connected to the source electrodes 301 of the plurality of second elements 32 mounted on the second element mounting portion 112 .
- the constituent material of the third detection wire 443 and the fourth detection wire 444 is, for example, aluminum.
- the case 60 is an electrically insulating member surrounding the first metal layer 11 (substrate 10) when viewed in the thickness direction z, as shown in FIGS.
- a constituent material of the case 60 is a synthetic resin having excellent heat resistance, such as PPS (polyphenylene sulfide).
- the case 60 has a pair of first side walls 611 , a pair of second side walls 612 , a plurality of mounting portions 62 , a power terminal block 63 and an output terminal block 64 .
- the pair of first side walls 611 are separated from each other in the first direction x.
- a pair of first side walls 611 are arranged along both the second direction y and the thickness direction z.
- the pair of second side walls 612 are separated from each other in the second direction y.
- a pair of second side walls 612 are arranged along both the first direction x and the thickness direction z. Both ends of the pair of second side walls 612 in the first direction x are connected to the pair of first side walls 611 .
- a first gate terminal 25 a , a first detection terminal 26 a , a power supply current detection terminal 27 and a pair of thermistor terminals 28 are arranged inside one of the second side walls 612 .
- a second gate terminal 25b and a second detection terminal 26b are arranged inside the other second side wall 612.
- the ends of these terminals that are close to the first metal layer 11 (substrate 10) in the thickness direction z are supported by a pair of second sidewalls 612.
- FIGS. 9 the ends of these terminals that are close to the first metal layer 11 (substrate 10) in the thickness direction z are supported by a pair of second sidewalls 612.
- the plurality of mounting portions 62 are portions provided at the four corners of the case 60 when viewed in the thickness direction z.
- Each of the plurality of mounting portions 62 is formed with a through-hole penetrating in the thickness direction z, and a mounting member 621 is fitted in each of the through-holes.
- Each mounting member 621 is provided with a mounting hole 621a penetrating in the thickness direction z.
- a heat dissipating member for example, a heat sink
- the power terminal block 63 protrudes outward in the first direction x from one first side wall 611 .
- a plurality of power terminals 23 are supported on the power terminal block 63 .
- the power terminal block 63 has a first terminal block 631 and a second terminal block 632 .
- the first terminal block 631 and the second terminal block 632 are separated from each other in the second direction y.
- the first terminal block 631 supports the first power terminal 23a.
- the external connection portion 231 of the first power terminal 23 a is exposed from the first terminal block 631 .
- the second terminal block 632 supports the second power terminal 23b.
- the external connection portion 231 of the second power terminal 23b is exposed from the second terminal block 632.
- a plurality of grooves 633 extending in the first direction x are formed between the first terminal block 631 and the second terminal block 632 .
- a pair of nuts 634 and a pair of intermediate members 635 are arranged inside the first terminal block 631 and the second terminal block 632 .
- the intermediate member 635 is located on the other side of the nut 634 in the thickness direction z (lower side in FIG. 13) and is in contact with the nut 634 .
- One nut 634 and intermediate member 635 are locked to the external connection portion 231 and intermediate portion 233 of the first power terminal 23a.
- the other nut 634 and intermediate member 635 are engaged with the external connection portion 231 and intermediate portion 233 of the second power terminal 23b.
- a part of each of the pair of intermediate members 635 is exposed from the power terminal block 63 .
- a pair of nuts 634 correspond to a pair of connection holes 231a provided in the first power terminal 23a and the second power terminal 23b. Fastening members such as bolts inserted into the pair of connection holes 231 a are fitted to the pair of nuts 634 .
- the output terminal block 64 protrudes outward in the first direction x from the other first side wall 611 .
- the output terminal block 64 supports the output terminals 24 .
- the output terminal block 64 has a first terminal block 641 and a second terminal block 642 .
- the first terminal block 641 and the second terminal block 642 are separated from each other in the second direction y.
- the first terminal block 641 supports the first terminal portion 24 a of the output terminal 24 .
- the external connection portion 241 of the first terminal portion 24 a is exposed from the first terminal block 641 .
- the second terminal block 642 supports the second terminal portion 24 b of the output terminal 24 .
- the external connection portion 241 of the second terminal portion 24 b is exposed from the second terminal block 642 .
- a plurality of grooves 643 extending in the first direction x are formed between the first terminal block 641 and the second terminal block 642 .
- a pair of nuts 644 and a pair of intermediate members 645 are arranged inside the first terminal block 641 and the second terminal block 642 .
- the intermediate member 645 is located on the other side of the nut 644 in the thickness direction z (lower side in FIG. 14) and is in contact with the nut 644 .
- One nut 644 and intermediate member 645 are engaged with the external connection portion 241 and intermediate portion 243 of the first terminal portion 24a.
- the other nut 644 and intermediate member 645 are engaged with the external connection portion 241 and intermediate portion 243 of the second terminal portion 24b.
- a part of each of the pair of intermediate members 645 is exposed from the output terminal block 64 .
- a pair of nuts 644 correspond to a pair of connection holes 241a provided in the first terminal portion 24a and the second terminal portion 24b. Fastening members such as bolts inserted into the pair of connection holes 241 a are fitted to the pair of nuts 644 .
- the sealing resin 70 is housed in a region surrounded by the case 60 and the substrate 10, as shown in FIGS.
- a sealing resin 70 covers the plurality of semiconductor elements 30 .
- a constituent material of the sealing resin 70 is, for example, a black epoxy resin. Note that other materials such as silicone gel may be selected as the constituent material of the sealing resin 70 .
- the semiconductor device A10 includes two switching circuits, an upper arm circuit and a lower arm circuit.
- the upper arm circuit is composed of a first element mounting portion 111 and a plurality of first elements 31 mounted on the first element mounting portion 111 . All of the plurality of first elements 31 mounted on the first element mounting portion 111 are connected in parallel between the first power terminal 23a and the output terminal 24 .
- the gate electrodes 303 of the plurality of first elements 31 in the upper arm circuit are all connected in parallel to the first gate terminal 25a.
- a driving circuit such as a gate driver arranged outside the semiconductor device A10 applies a gate voltage to the first gate terminal 25a, thereby simultaneously driving the plurality of first elements 31 in the upper arm circuit.
- the source electrodes 301 of the plurality of first elements 31 in the upper arm circuit are all connected in parallel to the first detection terminal 26a. Source currents flowing through the plurality of first elements 31 in the upper arm circuit are input to the control circuit of the semiconductor device A10 arranged outside the semiconductor device A10 via the first detection terminals 26a.
- the lower arm circuit is composed of a second element mounting portion 112 and a plurality of second elements 32 mounted on the second element mounting portion 112 . All of the plurality of second elements 32 mounted on the second element mounting portion 112 are connected in parallel between the output terminal 24 and the second power terminal 23b.
- the gate electrodes 303 of the plurality of second elements 32 in the lower arm circuit are all connected in parallel to the second gate terminal 25b.
- a driving circuit such as a gate driver arranged outside the semiconductor device A10 applies a gate voltage to the second gate terminal 25b, thereby simultaneously driving the plurality of second elements 32 in the lower arm circuit.
- the source electrodes 301 of the plurality of second elements 32 in the lower arm circuit are all connected in parallel to the second detection terminal 26b. Source currents flowing through the plurality of second elements 32 in the lower arm circuit are input to the control circuit of the semiconductor device A10 arranged outside the semiconductor device A10 via the second detection terminals 26b.
- a DC power supply is connected to the first power supply terminal 23a and the second power supply terminal 23b, and the plurality of semiconductor elements 30 (the plurality of first elements 31 and the plurality of second elements 32) in the upper arm circuit and the lower arm circuit are driven.
- AC voltages of various frequencies are output from the output terminal 24 .
- the AC voltage output from the output terminal 24 is supplied to a power supply target such as a motor.
- the semiconductor device A10 includes a first layer 20, a second layer 21 and a third layer 22.
- the first layer 20 is located between the main surface 11A of the first metal layer 11 (the first element mounting portion 111 and the second element mounting portion 112) and the plurality of semiconductor elements 30, and has conductivity.
- the second layer 21 conducts and joins the main surface 11A of the first metal layer 11 (the first element mounting portion 111 and the second element mounting portion 112 ) and the plurality of semiconductor elements 30 .
- the third layer 22 electrically connects the first layer 20 and the plurality of semiconductor elements 30 . According to the configuration including such a first layer 20, it is possible to increase the heat capacity of the portion between the semiconductor element 30 and the substrate 10, and it is possible to suppress the heat saturation of the portion. can.
- the semiconductor device A10 can efficiently release the heat generated by the plurality of semiconductor elements 30 .
- the semiconductor device A10 it is possible to suppress the temperature rise around the plurality of semiconductor elements 30, and it is suitable even when a large current is applied to the semiconductor device A10.
- a substrate 10 on which a plurality of semiconductor elements 30 are mounted has a first metal layer 11, a second metal layer 12 and an insulating layer 13.
- the first metal layer 11 includes a main surface 11A facing one side in the thickness direction z.
- the second metal layer 12 is located on the other side of the first metal layer 11 in the thickness direction z.
- the insulating layer 13 is interposed between the first metal layer 11 and the second metal layer 12 .
- the substrate 10 has a configuration in which a second metal layer 12, an insulating layer 13 and a first metal layer 11 are laminated in this order.
- the first metal layer 11 (first element mounting portion 111 and second element mounting portion 112) functions as a circuit layer on which a plurality of semiconductor elements 30 are mounted, and has a relatively small thickness.
- the heat generated in the plurality of semiconductor elements 30 can be quickly dissipated in the first layer 20 located between the plurality of semiconductor elements 30 and the first metal layer 11. FIG. Therefore, in the first metal layer 11 laminated on the insulating layer 13, heat retention from the plurality of semiconductor elements 30 can be suppressed.
- the first layer 20 includes a plurality of individual parts 201 separated from each other.
- Each of the plurality of semiconductor elements 30 is supported by one of the plurality of individual portions 201 . According to such a configuration, the heat generated by the plurality of semiconductor elements 30 can be prevented from interfering with each other.
- the constituent material of the first layer 20 contains copper.
- the thickness of the first layer 20 is greater than the thickness of the second metal layer 12 . According to such a configuration, thermal conductivity and heat dissipation in the first layer 20 can be enhanced. Also, as a preferred example, the thickness of the first layer 20 is 2 mm to 3 mm, which is 1 to 10 times the thickness of the second metal layer 12 . According to such a configuration, heat dissipation in the first layer 20 can be further enhanced.
- the constituent material of the third layer 22 contains silver.
- the third layer 22 is sintered silver (sintered metal). With such a configuration, the third layer 22 has excellent thermal conductivity. As a result, the heat generated by the plurality of semiconductor elements 30 is quickly transferred to the second layer 21 via the third layer 22 . This is more preferable in terms of efficiently releasing the heat generated by the plurality of semiconductor elements 30 .
- the semiconductor device A11 of this modified example differs from the semiconductor device A10 of the above embodiment mainly in the configuration of the first layer 20 .
- each of the plurality of individual portions 201 constituting the first layer 20 has a larger dimension in the second direction y than in the above-described embodiment, and has an elongated rectangular shape when viewed in the thickness direction z. .
- the dimension L2 in the second direction y is larger than the dimension L1 in the first direction x.
- the dimension L2 of the individual portion 201 in the second direction y is greater than the dimension L1 in the first direction x, but the dimension L2 is not necessarily greater than the dimension L1.
- the above dimensions L1 and L2 are restricted by the package size of the semiconductor device A11.
- the plane size of the semiconductor element 30 must be adjusted to the dimension L1 in the first direction x and the dimension L1 in the second direction within the limits of the package size. It is desirable to increase both of the y dimensions L2.
- the dimension L2 of the individual portion 201 in the second direction y is 0.5 to 2.0 times the dimension L1 of the individual portion 201 in the first direction x.
- the dimension L2 of the individual portion 201 in the second direction y is 1.2 to 4.0 times the dimension of the semiconductor element 30 in the second direction y.
- the semiconductor device A11 of this modified example also has the same effects as the semiconductor device A10 of the above-described embodiment.
- the dimension L2 in the second direction y is larger than the dimension L1 in the first direction x in which the plurality of semiconductor elements 30 are arranged.
- the volume of the first layer 20 (the plurality of individual portions 201) is increased, and the heat capacity of the first layer 20 can be further increased.
- the heat generated by the plurality of semiconductor elements 30 can be diffused in the second direction y in the plurality of individual portions 201 and released more efficiently.
- the semiconductor device A20 of the present embodiment differs from the semiconductor device A10 of the first embodiment mainly in the configuration of the first layer 20. As shown in FIG.
- the first layer 20 includes a plurality of individual parts 201 separated from each other, as in the first embodiment.
- each of the plurality of individual parts 201 has a larger dimension in the first direction x than in the first embodiment.
- Each of the plurality of individual parts 201 supports the plurality of semiconductor elements 30 .
- one individual portion 201 supports two semiconductor elements 30 adjacent in the first direction x. Note that one individual portion 201 may support three or more semiconductor elements 30 .
- the semiconductor device A20 of this embodiment also has the same effects as the semiconductor device A10 of the first embodiment. Further, in the semiconductor device A20, the volume of the first layer 20 is increased by the portion corresponding to the gap between the individual portions 201 adjacent in the first direction x in the semiconductor device A10. Therefore, it is possible to further increase the heat capacity of the first layer 20 . As a result, the heat generated by the plurality of semiconductor elements 30 can be diffused in the first direction x in the first layer 20 and released more efficiently.
- the semiconductor device according to the present disclosure is not limited to the above-described embodiments.
- the specific configuration of each part of the semiconductor device according to the present disclosure can be changed in various ways.
- Appendix 1 a substrate having a main surface facing one side in the thickness direction; a plurality of semiconductor elements positioned on one side of the substrate in the thickness direction and having a switching function; a first layer located between the main surface and the plurality of semiconductor elements in the thickness direction and having conductivity; a second layer electrically connecting the main surface and the first layer; A semiconductor device, comprising: a third layer electrically connecting the first layer and the plurality of semiconductor elements.
- the substrate includes a first metal layer including the main surface, a second metal layer located on the other side of the first metal layer in the thickness direction, the first metal layer and the second metal layer.
- the semiconductor device according to appendix 1 further comprising an insulating layer interposed between and. Appendix 3. 3.
- the semiconductor device according to appendix 2 wherein the first layer includes a plurality of individual parts separated from each other. Appendix 4.
- the plurality of semiconductor elements are arranged at intervals in a first direction orthogonal to the thickness direction, 5.
- the semiconductor device according to appendix 4, wherein each of the plurality of individual parts has a dimension in a second direction orthogonal to both the thickness direction and the first direction that is larger than a dimension in the first direction.
- Appendix 6. 6.
- the semiconductor device according to any one of appendices 2 to 11, wherein the first layer is made of a material having the same thermal conductivity as that of the second metal layer or a material having a higher thermal conductivity than that of the second metal layer.
- Appendix 13. 13 The semiconductor device according to any one of Appendixes 1 to 12, wherein the third layer contains silver. Appendix 14. 14. The semiconductor device according to any one of Appendixes 1 to 13, wherein the third layer includes sintered metal.
- Appendix 15. 15.
- the semiconductor device according to any one of Appendixes 1 to 14, wherein each of the plurality of semiconductor elements has a semiconductor layer containing SiC. Appendix 16. each of the plurality of semiconductor elements has a gate electrode, a source electrode and a drain electrode; 16. The semiconductor device according to any one of appendices 1 to 15, wherein the drain electrode and the first layer are conductively joined by the third layer.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Dispersion Chemistry (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
厚さ方向の一方側を向く主面を有する基板と、
前記基板に対して前記厚さ方向の一方側に位置し、かつスイッチング機能を有する複数の半導体素子と、
前記厚さ方向において、前記主面と前記複数の半導体素子との間に位置し、かつ導電性を有する第1層と、
前記主面と前記第1層とを導通接合する第2層と、
前記第1層と前記複数の半導体素子とを導通接合する第3層と、を備える、半導体装置。
付記2.
前記基板は、前記主面を含む第1金属層と、前記第1金属層に対して前記厚さ方向の他方側に位置する第2金属層と、前記第1金属層と前記第2金属層との間に介在する絶縁層と、を有する、付記1に記載の半導体装置。
付記3.
前記第1層は、互いに分離した複数の個別部を含む、付記2に記載の半導体装置。
付記4.
前記複数の半導体素子の各々は、前記複数の個別部のいずれかに支持されている、付記3に記載の半導体装置。
付記5.
前記複数の半導体素子は、前記厚さ方向に対して直交する第1方向に間隔を隔てて配列されており、
前記複数の個別部の各々は、前記厚さ方向および前記第1方向の双方に直交する第2方向における寸法が、前記第1方向における寸法よりも大である、付記4に記載の半導体装置。
付記6.
前記第1層は、銅を含有する、付記2ないし5のいずれかに記載の半導体装置。
付記7.
前記第1層の厚さは、前記第2金属層の厚さよりも大である、付記2ないし6のいずれかに記載の半導体装置。
付記8.
前記第1層の厚さは、前記第2金属層の厚さの10倍以下である、付記7に記載の半導体装置。
付記9.
前記第1層の厚さは、2mm~3mmである、付記7または8に記載の半導体装置。
付記10.
前記第2金属層の厚さは、0.3mm~2.0mmである、付記9に記載の半導体装置。
付記11.
前記第1金属層の厚さは、0.1mm~2.0mmである、付記2ないし10のいずれかに記載の半導体装置。
付記12.
前記第1層は、前記第2金属層と熱伝導率が同一の材料または前記第2金属層よりも熱伝導率が大きい材料からなる、付記2ないし11のいずれかに記載の半導体装置。
付記13.
前記第3層は、銀を含有する、付記1ないし12のいずれかに記載の半導体装置。
付記14.
前記第3層は、焼結金属を含む、付記1ないし13のいずれかに記載の半導体装置。
付記15.
前記複数の半導体素子の各々は、SiCを含む半導体層を有する、付記1ないし14のいずれかに記載の半導体装置。
付記16.
前記複数の半導体素子の各々は、ゲート電極、ソース電極およびドレイン電極を有し、
前記ドレイン電極と前記第1層とが、前記第3層によって導通接合されている、付記1ないし15のいずれかに記載の半導体装置。
11:第1金属層 11A:主面
111:第1素子搭載部 111a:第1電源パッド
112:第2素子搭載部 112a:出力パッド
113:第1導電部 113a:第2電源パッド
113b:切欠き 114:第1ゲート部
115:第1検出部 116:サーミスタ搭載部
117:第2ゲート部 118:第2検出部
12:第2金属層 13:絶縁層 20:第1層
201:個別部 21:第2層 22:第3層
23:電源端子 23a:第1電源端子23a
23b:第2電源端子23b 231:外部接続部
231a:接続孔 232:内部接続部
233:中間部 233a:基部 233b:起立部
24:出力端子 24a:第1端子部 24b:第2端子部
241:外部接続部 241a:接続孔 242:内部接続部
243:中間部 243a:基部 243b:起立部
25:ゲート端子 25a:第1ゲート端子
25b:第2ゲート端子 26:素子電流検出端子
26a:第1検出端子 26b:第2検出端子
27:電源電流検出端子 28:サーミスタ端子
30:半導体素子 301:ソース電極 302:ドレイン電極
303:ゲート電極 31:第1素子 32:第2素子
40:導通部材 41:第1導通部材 42:第2導通部材
431:第1ゲートワイヤ 432:第2ゲートワイヤ
433:第3ゲートワイヤ 434:第4ゲートワイヤ
441:第1検出ワイヤ 442:第2検出ワイヤ
443:第3検出ワイヤ 444:第4検出ワイヤ
45:電源電流検出ワイヤ 46:サーミスタワイヤ
48,49:導通部材接合層 60:ケース 611:第1側壁
612:第2側壁 62:取付け部 621:取付け部材
621a:取付け孔 63:電源端子台 631:第1端子台
632:第2端子台 633:溝部 634:ナット
635:中間部材 64:電源端子台 641:第1端子台
642:第2端子台 643:溝部 644:ナット
645:中間部材 70:封止樹脂
L1:寸法(個別部の第1方向における寸法)
L2:寸法(個別部の第2方向における寸法)
x:第1方向 y:第2方向 z:厚さ方向
Claims (16)
- 厚さ方向の一方側を向く主面を有する基板と、
前記基板に対して前記厚さ方向の一方側に位置し、かつスイッチング機能を有する複数の半導体素子と、
前記厚さ方向において、前記主面と前記複数の半導体素子との間に位置し、かつ導電性を有する第1層と、
前記主面と前記第1層とを導通接合する第2層と、
前記第1層と前記複数の半導体素子とを導通接合する第3層と、を備える、半導体装置。 - 前記基板は、前記主面を含む第1金属層と、前記第1金属層に対して前記厚さ方向の他方側に位置する第2金属層と、前記第1金属層と前記第2金属層との間に介在する絶縁層と、を有する、請求項1に記載の半導体装置。
- 前記第1層は、互いに分離した複数の個別部を含む、請求項2に記載の半導体装置。
- 前記複数の半導体素子の各々は、前記複数の個別部のいずれかに支持されている、請求項3に記載の半導体装置。
- 前記複数の半導体素子は、前記厚さ方向に対して直交する第1方向に間隔を隔てて配列されており、
前記複数の個別部の各々は、前記厚さ方向および前記第1方向の双方に直交する第2方向における寸法が、前記第1方向における寸法よりも大である、請求項4に記載の半導体装置。 - 前記第1層は、銅を含有する、請求項2ないし5のいずれかに記載の半導体装置。
- 前記第1層の厚さは、前記第2金属層の厚さよりも大である、請求項2ないし6のいずれかに記載の半導体装置。
- 前記第1層の厚さは、前記第2金属層の厚さの10倍以下である、請求項7に記載の半導体装置。
- 前記第1層の厚さは、2mm~3mmである、請求項7または8に記載の半導体装置。
- 前記第2金属層の厚さは、0.3mm~2.0mmである、請求項9に記載の半導体装置。
- 前記第1金属層の厚さは、0.1mm~2.0mmである、請求項2ないし10のいずれかに記載の半導体装置。
- 前記第1層は、前記第2金属層と熱伝導率が同一の材料または前記第2金属層よりも熱伝導率が大きい材料からなる、請求項2ないし11のいずれかに記載の半導体装置。
- 前記第3層は、銀を含有する、請求項1ないし12のいずれかに記載の半導体装置。
- 前記第3層は、焼結金属を含む、請求項1ないし13のいずれかに記載の半導体装置。
- 前記複数の半導体素子の各々は、SiCを含む半導体層を有する、請求項1ないし14のいずれかに記載の半導体装置。
- 前記複数の半導体素子の各々は、ゲート電極、ソース電極およびドレイン電極を有し、
前記ドレイン電極と前記第1層とが、前記第3層によって導通接合されている、請求項1ないし15のいずれかに記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202280039506.6A CN117425957A (zh) | 2021-06-02 | 2022-05-11 | 半导体装置 |
DE112022002459.3T DE112022002459T5 (de) | 2021-06-02 | 2022-05-11 | Halbleiterbauteil |
JP2023525690A JPWO2022255048A1 (ja) | 2021-06-02 | 2022-05-11 | |
US18/491,332 US20240047432A1 (en) | 2021-06-02 | 2023-10-20 | Semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2021093072 | 2021-06-02 | ||
JP2021-093072 | 2021-06-02 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US18/491,332 Continuation US20240047432A1 (en) | 2021-06-02 | 2023-10-20 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2022255048A1 true WO2022255048A1 (ja) | 2022-12-08 |
Family
ID=84324307
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2022/019913 WO2022255048A1 (ja) | 2021-06-02 | 2022-05-11 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20240047432A1 (ja) |
JP (1) | JPWO2022255048A1 (ja) |
CN (1) | CN117425957A (ja) |
DE (1) | DE112022002459T5 (ja) |
WO (1) | WO2022255048A1 (ja) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010087432A1 (ja) * | 2009-01-29 | 2010-08-05 | 株式会社オクテック | 放熱基体およびこれを用いた電子装置 |
WO2019189612A1 (ja) * | 2018-03-28 | 2019-10-03 | 京セラ株式会社 | 電子素子搭載用基板、電子装置および電子モジュール |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7163054B2 (ja) | 2017-04-20 | 2022-10-31 | ローム株式会社 | 半導体装置 |
-
2022
- 2022-05-11 CN CN202280039506.6A patent/CN117425957A/zh active Pending
- 2022-05-11 JP JP2023525690A patent/JPWO2022255048A1/ja active Pending
- 2022-05-11 WO PCT/JP2022/019913 patent/WO2022255048A1/ja active Application Filing
- 2022-05-11 DE DE112022002459.3T patent/DE112022002459T5/de active Pending
-
2023
- 2023-10-20 US US18/491,332 patent/US20240047432A1/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010087432A1 (ja) * | 2009-01-29 | 2010-08-05 | 株式会社オクテック | 放熱基体およびこれを用いた電子装置 |
WO2019189612A1 (ja) * | 2018-03-28 | 2019-10-03 | 京セラ株式会社 | 電子素子搭載用基板、電子装置および電子モジュール |
Also Published As
Publication number | Publication date |
---|---|
DE112022002459T5 (de) | 2024-02-22 |
US20240047432A1 (en) | 2024-02-08 |
CN117425957A (zh) | 2024-01-19 |
JPWO2022255048A1 (ja) | 2022-12-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2690658B1 (en) | Power semiconductor module and power unit device | |
JP7143277B2 (ja) | 半導体装置 | |
JP4935220B2 (ja) | パワーモジュール装置 | |
JP7228587B2 (ja) | 半導体モジュール | |
JP4492695B2 (ja) | 半導体モジュールの実装構造 | |
JP5217884B2 (ja) | 半導体装置 | |
JP7204779B2 (ja) | 半導体装置 | |
WO2005119896A1 (ja) | インバータ装置 | |
JP2020080348A (ja) | 半導体装置 | |
JP2007068302A (ja) | 電力用半導体素子及び半導体電力変換装置 | |
JP2004186504A (ja) | 半導体装置 | |
US6583981B2 (en) | Ceramic condenser module | |
TW201803049A (zh) | 半導體裝置的散熱結構 | |
WO2021005915A1 (ja) | 半導体装置 | |
WO2020218298A1 (ja) | 半導体装置 | |
WO2022255048A1 (ja) | 半導体装置 | |
JP2022189515A (ja) | 接合構造、半導体装置および接合方法 | |
US12002794B2 (en) | Semiconductor device | |
JP3855726B2 (ja) | パワーモジュール | |
JP5621812B2 (ja) | 半導体装置 | |
JP2022188699A (ja) | 半導体装置および半導体装置の製造方法 | |
JP2004128264A (ja) | 半導体モジュールおよび板状リード | |
WO2022259873A1 (ja) | 半導体装置 | |
WO2024029274A1 (ja) | 半導体装置 | |
JP6973023B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 22815803 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2023525690 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 202280039506.6 Country of ref document: CN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 112022002459 Country of ref document: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 22815803 Country of ref document: EP Kind code of ref document: A1 |