WO2022252297A1 - 驱动电路及显示装置 - Google Patents

驱动电路及显示装置 Download PDF

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Publication number
WO2022252297A1
WO2022252297A1 PCT/CN2021/100788 CN2021100788W WO2022252297A1 WO 2022252297 A1 WO2022252297 A1 WO 2022252297A1 CN 2021100788 W CN2021100788 W CN 2021100788W WO 2022252297 A1 WO2022252297 A1 WO 2022252297A1
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WO
WIPO (PCT)
Prior art keywords
control signal
timing control
level shifter
clock signal
signal
Prior art date
Application number
PCT/CN2021/100788
Other languages
English (en)
French (fr)
Inventor
傅鑫博
陈若峤
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/435,724 priority Critical patent/US20240013702A1/en
Publication of WO2022252297A1 publication Critical patent/WO2022252297A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present application relates to the field of display technology, in particular to a driving circuit and a display device.
  • GOA Gate Driver on Array, array substrate row driving technology
  • GOA is a technology that directly fabricates the gate drive circuit on the array substrate, which has the advantages of narrow frame, low cost, and high yield.
  • the driving of GOA requires a level shifter.
  • the level shifter amplifies the timing control signal sent by the front-end timing controller to the positive and negative voltages that can turn the transistors in the GOA circuit on and off, so as to control the GOA circuit to open step by step.
  • the timing controller sends out many timing control signals, which occupy a large wiring space; at the same time, the I/O ports of the timing controller and the level shifter are occupied more .
  • the present application provides a driving circuit and a display device, which can reduce the number of timing control signals sent by the timing controller, thereby saving wiring space and reducing the number of occupied I/O ports of the timing controller and level shifters.
  • the present application provides a driving circuit, which includes:
  • a timing controller configured to output the first timing control signal and the second timing control signal
  • the first level shifter connected to the timing controller, the first level shifter is configured to output a first clock signal group according to the first timing control signal and the second timing control signal;
  • the first clock signal group includes a plurality of first clock signals
  • the first level shifter determines the starting moment of the rising edge of each of the first clock signals according to the first timing control signal
  • the first level shifter determines the start time of each falling edge of the first clock signal according to the second timing control signal.
  • the start time of the m-th rising edge of the n-th first clock signal is the same as the start time of the n+(m-1)*k-th rising edge of the first timing control signal
  • the starting moment of the m-th falling edge of the nth first clock signal corresponds to the starting moment of the n+(m-1)*k-th rising edge of the second timing control signal
  • both n and m are integers greater than 0
  • k is the number of the first clock signal.
  • the first level shifter determines each The pulse width of the first clock signal.
  • the pulse width of each of the first clock signals is equal to the starting moment of the rising edge corresponding to the first timing control signal and the starting moment of the falling edge corresponding to the second timing control signal. difference between the starting times.
  • the first level shifter determines the chamfer width corresponding to the rising edge of the first clock signal according to the pulse width of the first timing control signal.
  • the pulse width of the first timing control signal is equal to the chamfer width corresponding to the rising edge of the first clock signal.
  • the first level shifter determines the chamfer width corresponding to the falling edge of the first clock signal according to the pulse width of the second timing control signal.
  • the pulse width of the second timing control signal is equal to the chamfer width corresponding to the falling edge of the first clock signal.
  • the timing controller is further configured to output a third timing control signal and a fourth timing control signal
  • the drive circuit further includes a second level shifter, the second level shifter is connected to the timing controller, and the second level shifter is used to control the signal according to the third timing and the first timing controller.
  • the four timing control signals output the second clock signal group;
  • the second clock signal group includes a plurality of second clock signals, the second level shifter determines the start time of each rising edge of the second clock signal according to the third timing control signal, the The second level shifter determines the start time of each falling edge of the second clock signal according to the fourth timing control signal.
  • the first timing control signal, the second timing control signal, the third timing control signal, and the fourth timing control signal have the same period and have a preset phase difference signal of.
  • the first timing control signal and the third timing control signal are the same signal, and the second timing control signal and the fourth timing control signal are the same signal.
  • the timing controller is further configured to output a third timing control signal and a fourth timing control signal
  • the first level shifter is further configured to output a second clock signal group according to the third timing control signal and the fourth timing control signal;
  • the second clock signal group includes a plurality of second clock signals
  • the first level shifter determines the start time of each rising edge of the second clock signal according to the third timing control signal
  • the The second level shifter determines the start time of each falling edge of the second clock signal according to the fourth timing control signal.
  • the timing controller is further configured to output a start control signal and a reset control signal
  • the first level shifter is also used for outputting a start signal according to the start control signal; the first level shifter is also used for outputting a reset signal according to the reset control signal.
  • the starting moment of the rising edge of the first clock signal is equal to the starting moment of the rising edge corresponding to the first timing control signal, and the starting moment of the falling edge of the first clock signal The starting moment is equal to the starting moment of the rising edge corresponding to the second timing control signal.
  • the present application also provides a display device, which includes a display panel and a control board connected to the display panel, the control board includes a driving circuit, and the driving circuit includes:
  • a timing controller configured to output the first timing control signal and the second timing control signal
  • the first level shifter connected to the timing controller, the first level shifter is configured to output a first clock signal group according to the first timing control signal and the second timing control signal;
  • the first clock signal group includes a plurality of first clock signals
  • the first level shifter determines the starting moment of the rising edge of each of the first clock signals according to the first timing control signal
  • the first level shifter determines the start time of each falling edge of the first clock signal according to the second timing control signal.
  • the start time of the m-th rising edge of the n-th first clock signal is the same as the start time of the n+(m-1)*k-th rising edge of the first timing control signal
  • the starting moment of the m-th falling edge of the nth first clock signal corresponds to the starting moment of the n+(m-1)*k-th rising edge of the second timing control signal
  • both n and m are integers greater than 0
  • k is the number of the first clock signal.
  • the first level shifter determines each The pulse width of the first clock signal.
  • the first level shifter determines the chamfer width corresponding to the rising edge of the first clock signal according to the pulse width of the first timing control signal.
  • the first level shifter determines the chamfer width corresponding to the falling edge of the first clock signal according to the pulse width of the second timing control signal.
  • the timing controller is further configured to output a third timing control signal and a fourth timing control signal
  • the drive circuit further includes a second level shifter, the second level shifter is connected to the timing controller, and the second level shifter is used to control the signal according to the third timing and the first timing controller.
  • the four timing control signals output the second clock signal group;
  • the second clock signal group includes a plurality of second clock signals, the second level shifter determines the start time of each rising edge of the second clock signal according to the third timing control signal, the The second level shifter determines the start time of each falling edge of the second clock signal according to the fourth timing control signal.
  • the first level shifter generates a plurality of first clock signals through the first timing control signal and the second timing control signal output by the timing controller in combination with the timing logic relationship.
  • the embodiment of the present application can generate multiple first clock signals by using fewer timing control signals, thereby reducing the number of timing control signals sent by the timing controller, saving wiring and wiring space, and reducing the number of timing controllers. And the number of occupied I/O ports of the level shifter.
  • FIG. 1 is a first structural schematic diagram of a driving circuit provided in an embodiment of the present application
  • FIG. 2 is a timing diagram of the driving circuit shown in FIG. 1;
  • FIG. 3 is a second structural schematic diagram of the driving circuit provided by the embodiment of the present application.
  • FIG. 4 is a timing diagram of the driving circuit shown in FIG. 3;
  • FIG. 5 is another timing diagram of the driving circuit shown in FIG. 3;
  • FIG. 6 is a schematic diagram of a third structure of a driving circuit provided in an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • Embodiments of the present application provide a driving circuit and a display device, which will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • FIG. 1 is a schematic diagram of a first structure of a driving circuit provided by an embodiment of the present application.
  • the driving circuit 100 provided in the embodiment of the present application includes a timing controller 101 and a first level shifter 102 .
  • the timing controller 101 is connected to the first level shifter 102 .
  • the timing controller 101 is used for outputting a first timing control signal CPV1 and a second timing control signal CPV2 .
  • the first level shifter 102 is used for outputting the first clock signal group CKA according to the first timing control signal CPV1 and the second timing control signal CPV2 .
  • the first clock signal group CKA includes a plurality of first clock signals CKa. It should be noted that the number of the first clock signal CKa can be set according to actual needs.
  • the first level shifter 102 generates a plurality of first clock signals CKa by combining the first timing control signal CPV1 and the second timing control signal CPV2 outputted by the timing controller 101 in combination with the timing logic relationship.
  • multiple first clock signals CKa can be generated by using fewer timing control signals, thereby reducing the number of timing control signals sent by the timing controller 101, saving wiring and wiring space, and reducing the timing controller 101 and the number of first clock signals. The number of occupied I/O ports of the level converter 102.
  • FIG. 2 is a timing diagram of the driving circuit shown in FIG. 1 .
  • the first level shifter 102 determines the start time t1 of each rising edge of the first clock signal CKa according to the first timing control signal CPV1 .
  • the first level shifter 102 determines the start time t2 of each falling edge of the first clock signal CKa according to the second timing control signal CPV2 .
  • first timing control signal CPV1 determines the starting moment t1 of the rising edge of the first clock signal CKa
  • the second timing control signal CPV2 determines the starting moment t2 of the falling edge of the first clock signal CKa
  • a plurality of first clock signals CKa can be generated through the sequential logic relationship.
  • the starting time t1 of the rising edge of the first clock signal CKa may be equal to the starting time t11 of the rising edge corresponding to the first timing control signal CPV1 .
  • the starting time t2 of the falling edge of the first clock signal CKa may be equal to the starting time t22 of the rising edge corresponding to the second timing control signal CPV1 .
  • the starting time t1 of the rising edge of the first clock signal CKa may not be equal to the starting time t11 of the corresponding rising edge of the first timing control signal CPV1 .
  • the starting time t2 of the falling edge of the first clock signal CKa may not be equal to the starting time t22 of the rising edge corresponding to the second timing control signal CPV2 . That is, the start time t1 of the rising edge of the first clock signal CKa is approximately equal to the start time t11 of the corresponding rising edge of the first timing control signal CPV1 . The starting time t2 of the falling edge of the first clock signal CKa is approximately equal to the starting time t22 of the corresponding rising edge of the second timing control signal CPV2 .
  • the start time t1 of the m-th rising edge of the n-th first clock signal CKa corresponds to the start time t11 of the n+(m-1)*k-th rising edge of the first timing control signal CPV1 .
  • the starting time t2 of the m-th falling edge of the n-th first clock signal CKa corresponds to the starting time t22 of the n+(m-1)*k-th rising edge of the second timing control signal CPV2, and both n and m is an integer greater than 0, and k is the number of the first clock signal CKa.
  • the correspondence here means that the start time t1 of the m-th rising edge of the n-th first clock signal CKa is equal to or nearly equal to the n+(m-1)th of the first timing control signal CPV1 *The start time t11 of the k rising edges; the start time t2 of the m-th falling edge of the n-th first clock signal CKa is equal to or nearly equal to the n+(m-1)*k of the second timing control signal CPV2 The starting time t22 of a rising edge.
  • the start time t1 of the first rising edge of the first first clock signal CKa and the start time t1 of the first rising edge of the first timing control signal CPV1 corresponds to the start time t11; the start time t2 of the first falling edge of the first clock signal CKa corresponds to the start time t22 of the first rising edge of the second timing control signal CPV2.
  • the start time t1 of the second rising edge of the first first clock signal CKa and the start time t1 of the seventh rising edge of the first timing control signal CPV1 The starting time t11 corresponds; the starting time t2 of the second falling edge of the first first clock signal CKa corresponds to the starting time t22 of the seventh rising edge of the second timing control signal CPV2.
  • the first level shifter 102 determines the pulse width of each first clock signal CKa according to the starting time t11 of the rising edge of the first timing control signal CPV1 and the starting time t22 of the falling edge of the second timing control signal CPV2 d.
  • the pulse width d of each first clock signal CKa may be equal to the interval between the rising edge time t11 corresponding to the first timing control signal CPV1 and the starting time t11 corresponding to the falling edge of the second timing control signal CPV2. difference.
  • the pulse width d of each first clock signal CKa may not be equal to the start time of the rising edge time t11 corresponding to the first timing control signal CPV1 and the falling edge corresponding to the second timing control signal CPV2 the difference between.
  • each first clock signal CKa is approximately equal to the difference between the rising edge time t11 corresponding to the first timing control signal CPV1 and the starting time t11 corresponding to the falling edge of the second timing control signal CPV2 .
  • the first level shifter 102 determines the chamfer width d11 corresponding to the rising edge of the first clock signal CKa according to the pulse width d1 of the first timing control signal CPV1 .
  • the first level shifter 102 determines the chamfer width d22 corresponding to the falling edge of the first clock signal CKa according to the pulse width d2 of the second timing control signal CPV2 .
  • the pulse width d1 of the first timing control signal CPV1 may be equal to the chamfer width d11 corresponding to the rising edge of the first clock signal CKa.
  • the pulse width d1 of the first timing control signal CPV1 may not be equal to the chamfer width d11 corresponding to the rising edge of the first clock signal CKa. That is, the pulse width d1 of the first timing control signal CPV1 is nearly equal to the chamfer width d11 corresponding to the rising edge of the first clock signal CKa.
  • the pulse width d2 of the second timing control signal CPV2 may be equal to the chamfer width d22 corresponding to the falling edge of the first clock signal CKa.
  • the pulse width d2 of the second timing control signal CPV2 may not be equal to the chamfer width d22 corresponding to the falling edge of the first clock signal CKa. That is, the pulse width d2 of the second timing control signal CPV2 is nearly equal to the chamfer width d22 corresponding to the falling edge of the first clock signal CKa.
  • the timing controller 101 is also used to output the start control signal STV1 and the reset control signal RES1; the first level shifter 102 is also used to output the start signal STV2 according to the start control signal STV1; The level converter 102 is also used for outputting the reset signal RES2 according to the reset control signal RES1 .
  • the start control signal STV1 corresponds to the start signal STV2.
  • the reset control signal RES1 corresponds to the reset signal RES2.
  • FIG. 3 is a second structural schematic diagram of the driving circuit provided by the embodiment of the present application.
  • the timing controller 101 is also used to output the third timing control signal CPV3 and the fourth timing Control signal CPV4;
  • the driving circuit 200 also includes a second level shifter 103, the second level shifter 103 is connected to the timing controller 101, and the second level shifter 103 is used to control the signal CPV3 and the fourth timing according to the third timing
  • the timing control signal CPV4 outputs the second clock signal group CKB.
  • the second clock signal group CKB includes a plurality of second clock signals CKb. It should be noted that the number of the second clock signal CKb can be set according to actual needs.
  • the first level shifter 102 passes the first timing control signal CPV1 and the second timing control signal CPV2 output by the timing controller 101
  • the second level shifter 103 passes the timing control signal CPV2 output by the timing controller 101 .
  • the three timing control signals CPV3 and the fourth timing control signal CPV4 are combined with the timing logic relationship to generate a plurality of first clock signals CKa and a plurality of second clock signals CKb.
  • multiple first clock signals CKa and multiple second clock signals CKb can be generated by using fewer timing control signals, thereby reducing the number of timing control signals sent by the timing controller 101, saving wiring space, and reducing The number of occupied I/O ports of the timing controller 101 , the first level shifter 102 and the second level shifter 103 .
  • FIG. 4 is a timing schematic diagram of the driving circuit shown in FIG. 3 .
  • the second level shifter 103 determines the start time T1 of each rising edge of the second clock signal CKb according to the third timing control signal CPV3 .
  • the second level shifter determines the start time T2 of each falling edge of the second clock signal CKb according to the fourth timing control signal CPV4 .
  • the third timing control signal CPV3 determines the starting moment T1 of the rising edge of the second clock signal CKb
  • the fourth timing control signal CPV4 determines the starting moment T2 of the falling edge of the second clock signal CKb
  • a plurality of second clock signals CKb can be generated through the timing logic relationship.
  • the starting time T1 of the rising edge of the second clock signal CKb may be equal to the starting time T11 of the rising edge corresponding to the third timing control signal CPV3 .
  • the starting time T2 of the falling edge of the second clock signal CKb may be equal to the starting time T22 of the corresponding rising edge of the fourth timing control signal CPV4 .
  • the starting time T1 of the rising edge of the second clock signal CKb may not be equal to the starting time T11 of the corresponding rising edge of the third timing control signal CPV3 .
  • the starting time T2 of the falling edge of the second clock signal CKb may not be equal to the starting time T22 of the rising edge corresponding to the fourth timing control signal CPV4 . That is, the start time T1 of the rising edge of the second clock signal CKb is approximately equal to the start time T11 of the corresponding rising edge of the third timing control signal CPV3 . The starting time T2 of the falling edge of the second clock signal CKb is approximately equal to the starting time T22 of the corresponding rising edge of the fourth timing control signal CPV4 .
  • the starting time T1 of the m-th rising edge of the n-th second clock signal CKb corresponds to the starting time T11 of the n+(m-1)*k-th rising edge of the third timing control signal CPV3 .
  • the starting time T2 of the m-th falling edge of the n-th second clock signal CKb corresponds to the starting time T22 of the n+(m-1)*k-th rising edge of the fourth timing control signal CPV4, and both n and m is an integer greater than 0, and k is the number of second clock signals.
  • the correspondence here means that the start time T1 of the m-th rising edge of the n-th second clock signal CKb is equal to or nearly equal to the n+(m-1)th rising edge of the third timing control signal CPV3 *The start time T11 of the k rising edge; the start time T2 of the m-th falling edge of the n-th second clock signal CKb is equal to or nearly equal to the n+(m-1)*k of the fourth timing control signal CPV4 The starting time T22 of a rising edge.
  • the second level shifter 103 determines the pulse width D of each second clock signal according to the starting time T11 of the rising edge of the third timing control signal CPV3 and the starting timing T22 of the rising edge of the fourth timing control signal CPV4 .
  • the pulse width D of each second clock signal CKb may be equal to the interval between the rising edge time T11 corresponding to the third timing control signal CPV3 and the starting time of the falling edge corresponding to the fourth timing control signal CPV4. difference.
  • the pulse width D of each second clock signal CKb may not be equal to the start time of the rising edge time T11 corresponding to the third timing control signal CPV3 and the falling edge corresponding to the fourth timing control signal CPV4 the difference between. That is, the pulse width D of each second clock signal CKb is approximately equal to the difference between the rising edge timing T11 corresponding to the third timing control signal CPV3 and the starting timing of the falling edge corresponding to the fourth timing control signal CPV4 .
  • the second level shifter 103 determines the chamfering width D11 corresponding to the rising edge of the second clock signal CKb according to the pulse width D1 of the third timing control signal CPV3 .
  • the second level shifter determines the chamfer width D22 corresponding to the falling edge of the second clock signal CKb according to the pulse width D2 of the fourth timing control signal CPV4 .
  • the pulse width D1 of the third timing control signal CPV3 may be equal to the chamfer width D11 corresponding to the rising edge of the second clock signal CKb.
  • the pulse width D1 of the third timing control signal CPV3 may not be equal to the chamfer width D11 corresponding to the rising edge of the second clock signal CKb. That is, the pulse width D1 of the third timing control signal CPV3 is nearly equal to the chamfer width D11 corresponding to the rising edge of the second clock signal CKb.
  • the pulse width D2 of the fourth timing control signal CPV4 may be equal to the chamfer width D22 corresponding to the falling edge of the second clock signal CKb.
  • the pulse width D2 of the fourth timing control signal CPV4 may not be equal to the chamfer width D22 corresponding to the falling edge of the second clock signal CKb. That is, the pulse width D2 of the fourth timing control signal CPV4 is nearly equal to the chamfer width D22 corresponding to the falling edge of the second clock signal CKb.
  • the first timing control signal CPV1 , the second timing control signal CPV2 , the third timing control signal CPV3 , and the fourth timing control signal CPV4 are signals with the same period and a preset phase difference.
  • the GOA circuit needs 12 clock signals CK1 ⁇ CK12.
  • the plurality of first clock signals CKa are sequentially CK1, CK3, CK5, CK7, CK9, and CK11.
  • the plurality of second clock signals CKb are sequentially CK2, CK3, CK6, CK8, CK10, and CK12.
  • FIG. 5 is another timing diagram of the driving circuit shown in FIG. 3 .
  • the first timing control signal CPV1 and the third timing control signal CPV3 are the same signal
  • the second timing control signal CPV2 and the fourth timing control signal CPV4 are the same signal.
  • the GOA circuit needs 12 clock signals CK1 ⁇ CK12.
  • the plurality of first clock signals CKa are CK1, CK3, CK5, CK7, CK9, CK11.
  • the plurality of second clock signals are CK2, CK3, CK6, CK8, CK10, CK12.
  • the timing controller 101 is provided with 4 timing control signal output terminals, and the first level converter 102 and the second level converter 103 are both provided with 2 timing control signal output terminals and 6 clock signal output terminals, and the boost
  • the utilization rate of the I/O ports of the timing controller 101, the first level shifter 102, and the second level shifter 103 is improved, the number of signal lines is simplified, and the wiring space is saved; and the single level shifter is effectively controlled. converter size and cost.
  • the driving circuit 200 provided in the embodiment of the present application puts the driving of the first clock signals CK1, CK3, CK5, CK7, CK9, and CK11 in the first level shifter 102, and puts the driving of the second clock signals CK2, CK3, CK6,
  • the driving of CK8, CK10, and CK12 is placed in the second level shifter 103, which disperses the power consumption of the level shifter and is beneficial to improve the temperature rise of the level shifter.
  • the corner cutting function of the clock signal can be realized, and the control method is simple.
  • a timing controller 101 needs to output 12 timing control signals to a level shifter, and the level shifter generates 12 clock signals according to the 12 timing control signals in one-to-one correspondence.
  • multiple timing control signals occupy a large wiring space, and occupy more I/O ports of the timing controller 101 and the level shifter; in addition, the timing of each timing control signal needs to be adjusted separately.
  • Debugging is complex and time-consuming.
  • a single level shifter consumes a lot of power and has a high temperature. In a display device with a resolution of 8k or 4k and a refresh rate of 120Hz, the size of the panel is large and the number of scanning lines is large, and the total impedance will increase significantly.
  • the timing control signal does not have chamfering control, and the transient of the timing control signal switching between high level and low level is uncontrollable, which makes the current of the clock signal larger, which is not conducive to the improvement of temperature and power consumption.
  • the embodiment of the present application improves the utilization rate of the I/O ports of the timing controller 101, the first level shifter 102, and the second level shifter 103, reduces the number of signal lines, and saves wiring and wiring space; and effectively This controls the size and cost of a single level shifter.
  • the power consumption of the level converter is distributed, which is beneficial to improve the temperature rise of the level converter.
  • the corner cutting function of the clock signal can be realized, and the control method is simple.
  • FIG. 6 is a schematic diagram of a third structure of the driving circuit provided by the embodiment of the present application.
  • the difference between the driving circuit 300 shown in FIG. 6 and the driving circuit 100 shown in FIG. 1 is that in the driving circuit 300 shown in FIG. 6 , the timing controller 101 is also used to output the third timing control signal CPV3 and the fourth timing The control signal CPV4; the first level shifter 102 is used to output the second clock signal group according to the third timing control signal CPV3 and the fourth timing control signal CPV4.
  • the second clock signal group CKB includes a plurality of second clock signals CKb. It should be noted that the number of the second clock signal CKb can be set according to actual needs.
  • the difference between the driving circuit 300 shown in FIG. 6 and the driving circuit 200 shown in FIG. 3 is only that: the driving circuit 200 shown in FIG. output the second clock signal group CKB; and the driving circuit 300 shown in FIG. 6 outputs the second clock signal group CKB through the first level shifter 102 .
  • the driving circuit 300 shown in FIG. 6 For each signal in the driving circuit 300 shown in FIG. 6 , reference may be made to the description of each signal in the driving circuit 200 shown in FIG. 3 , which will not be repeated here.
  • FIG. 7 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device 1000 provided in the embodiment of the present application includes a display panel 1002 and a control board 1001 connected to the display panel 1002 .
  • the control board 1001 includes the drive circuit 100/200/300 described above.

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Abstract

一种驱动电路(100)及显示装置(1000)。驱动电路(100)包括时序控制器(101)以及第一电平转换器(102)，第一电平转换器(102)通过时序控制器(101)输出的第一时序控制信号(CPV1)以及第二时序控制信号(CPV2)，并结合时序逻辑关系生成多个第一时钟信号(CKa)。

Description

驱动电路及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种驱动电路及显示装置。
 背景技术
在显示装置的驱动电路中，GOA(Gate Driver on Array，阵列基板行驱动技术)正得到广泛应用。GOA是直接将栅极驱动电路制作在阵列基板上的技术，其具有窄边框、低成本、高良率等优势。
GOA的驱动需要电平转换器，电平转换器将前端时序控制器发出的时序控制信号放大到可使GOA电路中的晶体管通断的正负电压，以控制GOA电路逐级打开。然而，在现有的显示装置中，时序控制器发出的时序控制信号较多，其占用了较大的走线空间；同时使得时序控制器以及电平转换器的I/O口被占用较多。
 技术问题
本申请提供一种驱动电路及显示装置，可以降低时序控制器发出的时序控制信号的数量，从而节约走线空间，减少时序控制器以及电平转换器的I/O口被占用的数量。
 技术解决方案
第一方面，本申请提供一种驱动电路，其包括：
时序控制器，用于输出第一时序控制信号以及第二时序控制信号；
第一电平转换器，与所述时序控制器连接，所述第一电平转换器用于根据所述第一时序控制信号以及所述第二时序控制信号输出第一时钟信号组；
其中，所述第一时钟信号组包括多个第一时钟信号，所述第一电平转换器根据所述第一时序控制信号确定每一所述第一时钟信号的上升沿的起始时刻，所述第一电平转换器根据所述第二时序控制信号确定每一所述第一时钟信号的下降沿的起始时刻。
在本申请的一些实施例中，第n个所述第一时钟信号的第m个上升沿的起始时刻与所述第一时序控制信号的第n+（m-1）*k个上升沿的起始时刻对应，第n个所述第一时钟信号的第m个下降沿的起始时刻与所述第二时序控制信号的第n+（m-1）*k个上升沿的起始时刻对应，n、m均为大于0的整数，k为所述第一时钟信号的个数。
在本申请的一些实施例中，所述第一电平转换器根据所述第一时序控制信号的上升沿的起始时刻以及所述第二时序控制信号的下降沿的起始时刻确定每一所述第一时钟信号的脉冲宽度。
在本申请的一些实施例中，每一所述第一时钟信号的脉冲宽度等于所述第一时序控制信号对应的上升沿的起始时刻与所述第二时序控制信号对应的下降沿的起始时刻之间的差值。
在本申请的一些实施例中，所述第一电平转换器根据所述第一时序控制信号的脉冲宽度确定所述第一时钟信号的上升沿对应的削角宽度。
在本申请的一些实施例中，所述第一时序控制信号的脉冲宽度等于所述第一时钟信号的上升沿对应的削角宽度。
在本申请的一些实施例中，所述第一电平转换器根据所述第二时序控制信号的脉冲宽度确定所述第一时钟信号的下降沿对应的削角宽度。
在本申请的一些实施例中，所述第二时序控制信号的脉冲宽度等于所述第一时钟信号的下降沿对应的削角宽度。
在本申请的一些实施例中，所述时序控制器还用于输出第三时序控制信号以及第四时序控制信号；
所述驱动电路还包括第二电平转换器，所述第二电平转换器与所述时序控制器连接，所述第二电平转换器用于根据所述第三时序控制信号以及所述第四时序控制信号输出第二时钟信号组；
所述第二时钟信号组包括多个第二时钟信号，所述第二电平转换器根据所述第三时序控制信号确定每一所述第二时钟信号的上升沿的起始时刻，所述第二电平转换器根据所述第四时序控制信号确定每一所述第二时钟信号的下降沿的起始时刻。
在本申请的一些实施例中，所述第一时序控制信号、所述第二时序控制信号、所述第三时序控制信号以及所述第四时序控制信号为周期相同、且具有预设相位差的信号。
在本申请的一些实施例中，所述第一时序控制信号与所述第三时序控制信号为同一信号，所述第二时序控制信号与所述第四时序控制信号为同一信号。
在本申请的一些实施例中，所述时序控制器还用于输出第三时序控制信号以及第四时序控制信号；
所述第一电平转换器还用于根据所述第三时序控制信号以及所述第四时序控制信号输出第二时钟信号组；
所述第二时钟信号组包括多个第二时钟信号，所述第一电平转换器根据所述第三时序控制信号确定每一所述第二时钟信号的上升沿的起始时刻，所述第二电平转换器根据所述第四时序控制信号确定每一所述第二时钟信号的下降沿的起始时刻。
在本申请的一些实施例中，所述时序控制器还用于输出起始控制信号以及复位控制信号；
所述第一电平转换器还用于根据所述起始控制信号输出起始信号；所述第一电平转换器还用于根据所述复位控制信号输出复位信号。
在本申请的一些实施例中，所述第一时钟信号的上升沿的起始时刻等于所述第一时序控制信号对应的上升沿的起始时刻，所述第一时钟信号的下降沿的起始时刻等于所述第二时序控制信号对应的上升沿的起始时刻。
第二方面，本申请还提供一种显示装置，其包括显示面板以及与所述显示面板连接的控制板，所述控制板包括驱动电路，所述驱动电路包括：
时序控制器，用于输出第一时序控制信号以及第二时序控制信号；
第一电平转换器，与所述时序控制器连接，所述第一电平转换器用于根据所述第一时序控制信号以及所述第二时序控制信号输出第一时钟信号组；
其中，所述第一时钟信号组包括多个第一时钟信号，所述第一电平转换器根据所述第一时序控制信号确定每一所述第一时钟信号的上升沿的起始时刻，所述第一电平转换器根据所述第二时序控制信号确定每一所述第一时钟信号的下降沿的起始时刻。
在本申请的一些实施例中，第n个所述第一时钟信号的第m个上升沿的起始时刻与所述第一时序控制信号的第n+（m-1）*k个上升沿的起始时刻对应，第n个所述第一时钟信号的第m个下降沿的起始时刻与所述第二时序控制信号的第n+（m-1）*k个上升沿的起始时刻对应，n、m均为大于0的整数，k为所述第一时钟信号的个数。
在本申请的一些实施例中，所述第一电平转换器根据所述第一时序控制信号的上升沿的起始时刻以及所述第二时序控制信号的下降沿的起始时刻确定每一所述第一时钟信号的脉冲宽度。
在本申请的一些实施例中，所述第一电平转换器根据所述第一时序控制信号的脉冲宽度确定所述第一时钟信号的上升沿对应的削角宽度。
在本申请的一些实施例中，所述第一电平转换器根据所述第二时序控制信号的脉冲宽度确定所述第一时钟信号的下降沿对应的削角宽度。
在本申请的一些实施例中，所述时序控制器还用于输出第三时序控制信号以及第四时序控制信号；
所述驱动电路还包括第二电平转换器，所述第二电平转换器与所述时序控制器连接，所述第二电平转换器用于根据所述第三时序控制信号以及所述第四时序控制信号输出第二时钟信号组；
所述第二时钟信号组包括多个第二时钟信号，所述第二电平转换器根据所述第三时序控制信号确定每一所述第二时钟信号的上升沿的起始时刻，所述第二电平转换器根据所述第四时序控制信号确定每一所述第二时钟信号的下降沿的起始时刻。
 有益效果
本申请提供的驱动电路以及显示装置，第一电平转换器通过时序控制器输出的第一时序控制信号以及第二时序控制信号，并结合时序逻辑关系生成多个第一时钟信号。相较于现有技术，本申请实施例可以通过更少的时序控制信号生成多个第一时钟信号，从而降低时序控制器发出的时序控制信号的数量，节省走线布线空间，减少时序控制器以及电平转换器的I/O口被占用的数量。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的驱动电路的第一种结构示意图；
图2为图1所示的驱动电路的时序示意图；
图3为本申请实施例提供的驱动电路的第二种结构示意图；
图4为图3所示的驱动电路的时序示意图；
图5为图3所示的驱动电路的另一时序示意图；
图6为本申请实施例提供的驱动电路的第三种结构示意图；
图7为本申请实施例提供的显示装置的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。本申请的权利要求书以及说明书中的术语“第一”、“第二”、“第三”、“第四”等是用于区别不同对象，而不是用于描述特定顺序。本申请的权利要求书以及说明书中的术语“包括”、“具有”以及它们任何变形，意图在于覆盖不排他的包含。
本申请实施例提供一种驱动电路以及显示装置，下文进行详细说明。需要说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参阅图1，图1为本申请实施例提供的驱动电路的第一种结构示意图。本申请实施例提供的驱动电路100，其包括时序控制器101以及第一电平转换器102。时序控制器101与第一电平转换器102连接。时序控制器101用于输出第一时序控制信号CPV1以及第二时序控制信号CPV2。第一电平转换器102用于根据第一时序控制信号CPV1以及第二时序控制信号CPV2输出第一时钟信号组CKA。其中，第一时钟信号组CKA包括多个第一时钟信号CKa。需要说明的是，第一时钟信号CKa的数量可以根据实际需要设置。
在本申请实施例中，第一电平转换器102通过时序控制器101输出的第一时序控制信号CPV1以及第二时序控制信号CPV2，并结合时序逻辑关系生成多个第一时钟信号CKa。本申请实施例可以通过更少的时序控制信号生成多个第一时钟信号CKa，从而减少时序控制器101发出的时序控制信号的数量，节省走线布线空间，减少时序控制器101以及第一电平转换器102的I/O口被占用的数量。
具体的，请参阅图2，图2为图1所示的驱动电路的时序示意图。结合图1、图2所示，第一电平转换器102根据第一时序控制信号CPV1确定每一第一时钟信号CKa的上升沿的起始时刻t1。第一电平转换器102根据第二时序控制信号CPV2确定每一第一时钟信号CKa的下降沿的起始时刻t2。
可以理解的，由于第一时序控制信号CPV1确定第一时钟信号CKa的上升沿的起始时刻t1，第二时序控制信号CPV2确定第一时钟信号CKa的下降沿的起始时刻t2，本申请实施例可以通过该时序逻辑关系生成多个第一时钟信号CKa。
在本申请实施例中，第一时钟信号CKa的上升沿的起始时刻t1可以等于第一时序控制信号CPV1对应的上升沿的起始时刻t11。第一时钟信号CKa的下降沿的起始时刻t2可以等于第二时序控制信号CPV1对应的上升沿的起始时刻t22。当然，在一些实施例中，第一时钟信号CKa的上升沿的起始时刻t1也可以不等于第一时序控制信号CPV1对应的上升沿的起始时刻t11。第一时钟信号CKa的下降沿的起始时刻t2也可以不等于第二时序控制信号CPV2对应的上升沿的起始时刻t22。也即，第一时钟信号CKa的上升沿的起始时刻t1接近等于第一时序控制信号CPV1对应的上升沿的起始时刻t11。第一时钟信号CKa的下降沿的起始时刻t2接近等于第二时序控制信号CPV2对应的上升沿的起始时刻t22。
其中，第n个第一时钟信号CKa的第m个上升沿的起始时刻t1与第一时序控制信号CPV1的第n+（m-1）*k个上升沿的起始时刻t11对应。第n个第一时钟信号CKa的第m个下降沿的起始时刻t2与第二时序控制信号CPV2的第n+（m-1）*k个上升沿的起始时刻t22对应，n、m均为大于0的整数，k为第一时钟信号CKa的个数。需要说明的是，此处的对应指的是，第n个第一时钟信号CKa的第m个上升沿的起始时刻t1等于或者接近等于第一时序控制信号CPV1的第n+（m-1）*k个上升沿的起始时刻t11；第n个第一时钟信号CKa的第m个下降沿的起始时刻t2等于或者接近等于第二时序控制信号CPV2的第n+（m-1）*k个上升沿的起始时刻t22。
比如，当n为1，m为1，k为6时，第1个第一时钟信号CKa的第1个上升沿的起始时刻t1与第一时序控制信号CPV1的第1个上升沿的起始时刻t11对应；第1个第一时钟信号CKa的第1个下降沿的起始时刻t2与第二时序控制信号CPV2的第1个上升沿的起始时刻t22对应。再比如，当n为1，m为2，k为6时，第1个第一时钟信号CKa的第2个上升沿的起始时刻t1与第一时序控制信号CPV1的第7个上升沿的起始时刻t11对应；第1个第一时钟信号CKa的第2个下降沿的起始时刻t2与第二时序控制信号CPV2的第7个上升沿的起始时刻t22对应。
其中，第一电平转换器102根据第一时序控制信号CPV1的上升沿的起始时刻t11以及第二时序控制信号CPV2的下降沿的起始时刻t22确定每一第一时钟信号CKa的脉冲宽度d。
在本申请实施例中，每一第一时钟信号CKa的脉冲宽度d可以等于第一时序控制信号CPV1对应的上升沿时刻t11与第二时序控制信号CPV2对应的下降沿的起始时刻之间的差值。当然，在一些实施例中，每一第一时钟信号CKa的脉冲宽度d也可以不等于第一时序控制信号CPV1对应的上升沿时刻t11与第二时序控制信号CPV2对应的下降沿的起始时刻之间的差值。也即，每一第一时钟信号CKa的脉冲宽度d接近等于第一时序控制信号CPV1对应的上升沿时刻t11与第二时序控制信号CPV2对应的下降沿的起始时刻之间的差值。
其中，第一电平转换器102根据第一时序控制信号CPV1的脉冲宽度d1确定第一时钟信号CKa的上升沿对应的削角宽度d11。第一电平转换器102根据第二时序控制信号CPV2的脉冲宽度d2确定第一时钟信号CKa的下降沿对应的削角宽度d22。
在本申请实施例中，第一时序控制信号CPV1的脉冲宽度d1可以等于第一时钟信号CKa的上升沿对应的削角宽度d11。当然，在一些实施例中，第一时序控制信号CPV1的脉冲宽度d1也可以不等于第一时钟信号CKa的上升沿对应的削角宽度d11。也即，第一时序控制信号CPV1的脉冲宽度d1接近等于第一时钟信号CKa的上升沿对应的削角宽度d11。
在本申请实施例中，第二时序控制信号CPV2的脉冲宽度d2可以等于第一时钟信号CKa的下降沿对应的削角宽度d22。当然，在一些实施例中，第二时序控制信号CPV2的脉冲宽度d2也可以不等于第一时钟信号CKa的下降沿对应的削角宽度d22。也即，第二时序控制信号CPV2的脉冲宽度d2接近等于第一时钟信号CKa的下降沿对应的削角宽度d22。
在一些实施例中，时序控制器101还用于输出起始控制信号STV1以及复位控制信号RES1；第一电平转换器102还用于根据起始控制信号STV1输出起始信号STV2；第一电平转换器102还用于根据复位控制信号RES1输出复位信号RES2。其中，起始控制信号STV1与起始信号STV2对应。复位控制信号RES1与复位信号RES2对应。
请参阅图3，图3为本申请实施例提供的驱动电路的第二种结构示意图。图3所示的驱动电路200与图1所示的驱动电路100的区别在于：在图3所示的驱动电路200中，时序控制器101还用于输出第三时序控制信号CPV3以及第四时序控制信号CPV4；驱动电路200还包括第二电平转换器103，第二电平转换器103与时序控制器101连接，第二电平转换器103用于根据第三时序控制信号CPV3以及第四时序控制信号CPV4输出第二时钟信号组CKB。其中，第二时钟信号组CKB包括多个第二时钟信号CKb。需要说明的是，第二时钟信号CKb的数量可以根据实际需要设置。
在本申请实施例中，第一电平转换器102通过时序控制器101输出的第一时序控制信号CPV1以及第二时序控制信号CPV2，第二电平转换器103通过时序控制器101输出的第三时序控制信号CPV3以及第四时序控制信号CPV4，并结合时序逻辑关系生成多个第一时钟信号CKa以及多个第二时钟信号CKb。本申请实施例可以通过更少的时序控制信号生成多个第一时钟信号CKa以及多个第二时钟信号CKb，从而减少时序控制器101发出的时序控制信号的数量，节省走线布线空间，减少时序控制器101、第一电平转换器102以及第二电平转换器103的I/O口被占用的数量。
具体的，请参阅图4，图4为图3所示的驱动电路的时序示意图。结合图3、图4所示，第二电平转换器103根据第三时序控制信号CPV3确定每一第二时钟信号CKb的上升沿的起始时刻T1。第二电平转换器根据第四时序控制信号CPV4确定每一第二时钟信号CKb的下降沿的起始时刻T2。
可以理解的，由于第三时序控制信号CPV3确定第二时钟信号CKb的上升沿的起始时刻T1，第四时序控制信号CPV4确定第二时钟信号CKb的下降沿的起始时刻T2，本申请实施例可以通过该时序逻辑关系生成多个第二时钟信号CKb。
在本申请实施例中，第二时钟信号CKb的上升沿的起始时刻T1可以等于第三时序控制信号CPV3对应的上升沿的起始时刻T11。第二时钟信号CKb的下降沿的起始时刻T2可以等于第四时序控制信号CPV4对应的上升沿的起始时刻T22。当然，在一些实施例中，第二时钟信号CKb的上升沿的起始时刻T1也可以不等于第三时序控制信号CPV3对应的上升沿的起始时刻T11。第二时钟信号CKb的下降沿的起始时刻T2也可以不等于第四时序控制信号CPV4对应的上升沿的起始时刻T22。也即，第二时钟信号CKb的上升沿的起始时刻T1接近等于第三时序控制信号CPV3对应的上升沿的起始时刻T11。第二时钟信号CKb的下降沿的起始时刻T2接近等于第四时序控制信号CPV4对应的上升沿的起始时刻T22。
其中，第n个第二时钟信号CKb的第m个上升沿的起始时刻T1与第三时序控制信号CPV3的第n+（m-1）*k个上升沿的起始时刻T11对应。第n个第二时钟信号CKb的第m个下降沿的起始时刻T2与第四时序控制信号CPV4的第n+（m-1）*k个上升沿的起始时刻T22对应，n、m均为大于0的整数，k为第二时钟信号的个数。需要说明的是，此处的对应指的是，第n个第二时钟信号CKb的第m个上升沿的起始时刻T1等于或者接近等于第三时序控制信号CPV3的第n+（m-1）*k个上升沿的起始时刻T11；第n个第二时钟信号CKb的第m个下降沿的起始时刻T2等于或者接近等于第四时序控制信号CPV4的第n+（m-1）*k个上升沿的起始时刻T22。
其中，第二电平转换器103根据第三时序控制信号CPV3的上升沿的起始时刻T11以及第四时序控制信号CPV4的上升沿的起始时刻T22确定每一第二时钟信号的脉冲宽度D。
在本申请实施例中，每一第二时钟信号CKb的脉冲宽度D可以等于第三时序控制信号CPV3对应的上升沿时刻T11与第四时序控制信号CPV4对应的下降沿的起始时刻之间的差值。当然，在一些实施例中，每一第二时钟信号CKb的脉冲宽度D也可以不等于第三时序控制信号CPV3对应的上升沿时刻T11与第四时序控制信号CPV4对应的下降沿的起始时刻之间的差值。也即，每一第二时钟信号CKb的脉冲宽度D接近等于第三时序控制信号CPV3对应的上升沿时刻T11与第四时序控制信号CPV4对应的下降沿的起始时刻之间的差值。
其中，第二电平转换器103根据第三时序控制信号CPV3的脉冲宽度D1确定第二时钟信号CKb的上升沿对应的削角宽度D11。第二电平转换器根据第四时序控制信号CPV4的脉冲宽度D2确定第二时钟信号CKb的下降沿对应的削角宽度D22。
在本申请实施例中，第三时序控制信号CPV3的脉冲宽度D1可以等于第二时钟信号CKb的上升沿对应的削角宽度D11。当然，在一些实施例中，第三时序控制信号CPV3的脉冲宽度D1也可以不等于第二时钟信号CKb的上升沿对应的削角宽度D11。也即，第三时序控制信号CPV3的脉冲宽度D1接近等于第二时钟信号CKb的上升沿对应的削角宽度D11。
在本申请实施例中，第四时序控制信号CPV4的脉冲宽度D2可以等于第二时钟信号CKb的下降沿对应的削角宽度D22。当然，在一些实施例中，第四时序控制信号CPV4的脉冲宽度D2也可以不等于第二时钟信号CKb的下降沿对应的削角宽度D22。也即，第四时序控制信号CPV4的脉冲宽度D2接近等于第二时钟信号CKb的下降沿对应的削角宽度D22。
在本申请实施例中，第一时序控制信号CPV1、第二时序控制信号CPV2、第三时序控制信号CPV3以及第四时序控制信号CPV4为周期相同、且具有预设相位差的信号。在实际应用中，以分辨率为8k或者4k，刷新率为120Hz的显示装置为例，GOA电路需要12个时钟信号CK1~CK12。其中,多个第一时钟信号CKa依次为CK1、CK3、CK5、CK7、CK9、CK11。多个第二时钟信号CKb依次为CK2、CK3、CK6、CK8、CK10、CK12。
请参阅图5，图5为图3所示的驱动电路的另一时序示意图。在一些实施例中，第一时序控制信号CPV1与第三时序控制信号CPV3为同一信号，第二时序控制信号CPV2与第四时序控制信号CPV4为同一信号。在实际应用中，以分辨率为8k或者2k，刷新率为240Hz的显示装置为例，GOA电路需要12个时钟信号CK1~CK12。其中,多个第一时钟信号CKa为CK1、CK3、CK5、CK7、CK9、CK11。多个第二时钟信号为CK2、CK3、CK6、CK8、CK10、CK12。
具体的，时序控制器101设置4个时序控制信号输出端，第一电平转换器102以及第二电平转换器103均设置2个时序控制信号输出端以及6个时钟信号输出端，其提升了时序控制器101、第一电平转换器102以及第二电平转换器103的I/O口利用率，精简信号线数量，节省了走线布线空间；且有效的控制了单颗电平转换器的尺寸和成本。
另外，本申请实施例提供的驱动电路200将第一时钟信号CK1、CK3、CK5、CK7、CK9、CK11的驱动置于第一电平转换器102，将第二时钟信号CK2、CK3、CK6、CK8、CK10、CK12的驱动置于第二电平转换器103，分散了电平转换器的功耗，有利于改善电平转换器的温升。且通过控制第一时序控制信号CPV1、第二时序控制信号CPV2、第三时序控制信号CPV3以及第四时序控制信号CPV4的脉冲宽度可实现时钟信号的削角功能，控制方式简单。
需要说明的是，现有技术需通过一个时序控制器101输出12个时序控制信号到一个电平转换器中，电平转换器根据这12个时序控制信号一一对应生成12个时钟信号。第一方面，多个时序控制信号占用了较大的走线布线空间，对时序控制器101以及电平转换器的I/O口占用较多；此外，各个时序控制信号的时序需分别调整，调试复杂，耗时量大。第二方面，单颗电平转换器的功耗大，温度高。在分辨率为8k或者4k，刷新率为120Hz的显示装置中，面板尺寸大，扫描线行数多，总的阻抗会显著上升，以单颗电平转换器驱动单边的方式，其高电平/低电平负载电流较大。此外，由于行时间很短（1H约为1.85us），GOA驱动的电平转换频率更高，电平转换器内置开关器件的开关损耗上升。电平转换器稳态功耗和瞬态损耗的提升，易导致温升问题。第三方面，时序控制信号没有削角控制，时序控制信号在高电平/低电平切换的瞬态不可控，进而使时钟信号电流较大，不利于温度和功耗的改善。
而本申请实施例则提升了时序控制器101、第一电平转换器102以及第二电平转换器103的I/O口利用率，精简信号线数量，节省了走线布线空间；且有效的控制了单颗电平转换器的尺寸和成本。分散了电平转换器的功耗，有利于改善电平转换器的温升。且通过控制第一时序控制信号CPV1、第二时序控制信号CPV2、第三时序控制信号CPV3以及第四时序控制信号CPV4的脉冲宽度可实现时钟信号的削角功能，控制方式简单。
请参阅图6，图6为本申请实施例提供的驱动电路的第三种结构示意图。图6所示的驱动电路300与图1所示的驱动电路100的区别在于：在图6所示的驱动电路300中，时序控制器101还用于输出第三时序控制信号CPV3以及第四时序控制信号CPV4；第一电平转换器102用于根据第三时序控制信号CPV3以及第四时序控制信号CPV4输出第二时钟信号组。其中，第二时钟信号组CKB包括多个第二时钟信号CKb。需要说明的是，第二时钟信号CKb的数量可以根据实际需要设置。
其中，图6所示的驱动电路300与图3所示的驱动电路200的区别仅仅在于：图3所示的驱动电路200设置有第二电平转换器103，通过第二电平转换器103输出第二时钟信号组CKB；而图6所示的驱动电路300则通过第一电平转换器102输出第二时钟信号组CKB。图6所示的驱动电路300中各个信号可参照图3所示的驱动电路200中各个信号的描述，在此不做赘述。
请参阅图7，图7为本申请实施例提供的显示装置的结构示意图。本申请实施例提供的显示装置1000包括显示面板1002以及与显示面板1002连接的控制板1001。控制板1001包括以上所述的驱动电路100/200/300。
以上对本申请实施例所提供的驱动电路及显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种驱动电路，其包括：
    时序控制器，用于输出第一时序控制信号以及第二时序控制信号；
    第一电平转换器，与所述时序控制器连接，所述第一电平转换器用于根据所述第一时序控制信号以及所述第二时序控制信号输出第一时钟信号组；
    其中，所述第一时钟信号组包括多个第一时钟信号，所述第一电平转换器根据所述第一时序控制信号确定每一所述第一时钟信号的上升沿的起始时刻，所述第一电平转换器根据所述第二时序控制信号确定每一所述第一时钟信号的下降沿的起始时刻。
  2. 根据权利要求1所述的驱动电路，其中，第n个所述第一时钟信号的第m个上升沿的起始时刻与所述第一时序控制信号的第n+（m-1）*k个上升沿的起始时刻对应，第n个所述第一时钟信号的第m个下降沿的起始时刻与所述第二时序控制信号的第n+（m-1）*k个上升沿的起始时刻对应，n、m均为大于0的整数，k为所述第一时钟信号的个数。
  3. 根据权利要求1所述的驱动电路，其中，所述第一电平转换器根据所述第一时序控制信号的上升沿的起始时刻以及所述第二时序控制信号的下降沿的起始时刻确定每一所述第一时钟信号的脉冲宽度。
  4. 根据权利要求3所述的驱动电路，其中，每一所述第一时钟信号的脉冲宽度等于所述第一时序控制信号对应的上升沿的起始时刻与所述第二时序控制信号对应的下降沿的起始时刻之间的差值。
  5. 根据权利要求1所述的驱动电路，其中，所述第一电平转换器根据所述第一时序控制信号的脉冲宽度确定所述第一时钟信号的上升沿对应的削角宽度。
  6. 根据权利要求5所述的驱动电路，其中，所述第一时序控制信号的脉冲宽度等于所述第一时钟信号的上升沿对应的削角宽度。
  7. 根据权利要求1所述的驱动电路，其中，所述第一电平转换器根据所述第二时序控制信号的脉冲宽度确定所述第一时钟信号的下降沿对应的削角宽度。
  8. 根据权利要求7所述的驱动电路，其中，所述第二时序控制信号的脉冲宽度等于所述第一时钟信号的下降沿对应的削角宽度。
  9. 根据权利要求1所述的驱动电路，其中，所述时序控制器还用于输出第三时序控制信号以及第四时序控制信号；
    所述驱动电路还包括第二电平转换器，所述第二电平转换器与所述时序控制器连接，所述第二电平转换器用于根据所述第三时序控制信号以及所述第四时序控制信号输出第二时钟信号组；
    所述第二时钟信号组包括多个第二时钟信号，所述第二电平转换器根据所述第三时序控制信号确定每一所述第二时钟信号的上升沿的起始时刻，所述第二电平转换器根据所述第四时序控制信号确定每一所述第二时钟信号的下降沿的起始时刻。
  10. 根据权利要求9所述的驱动电路，其中，所述第一时序控制信号、所述第二时序控制信号、所述第三时序控制信号以及所述第四时序控制信号为周期相同、且具有预设相位差的信号。
  11. 根据权利要求9所述的驱动电路，其中，所述第一时序控制信号与所述第三时序控制信号为同一信号，所述第二时序控制信号与所述第四时序控制信号为同一信号。
  12. 根据权利要求1所述的驱动电路，其中，所述时序控制器还用于输出第三时序控制信号以及第四时序控制信号；
    所述第一电平转换器还用于根据所述第三时序控制信号以及所述第四时序控制信号输出第二时钟信号组；
    所述第二时钟信号组包括多个第二时钟信号，所述第一电平转换器根据所述第三时序控制信号确定每一所述第二时钟信号的上升沿的起始时刻，所述第二电平转换器根据所述第四时序控制信号确定每一所述第二时钟信号的下降沿的起始时刻。
  13. 根据权利要求1所述的驱动电路，其中，所述时序控制器还用于输出起始控制信号以及复位控制信号；
    所述第一电平转换器还用于根据所述起始控制信号输出起始信号；所述第一电平转换器还用于根据所述复位控制信号输出复位信号。
  14. 根据权利要求1所述的驱动电路，其中，所述第一时钟信号的上升沿的起始时刻等于所述第一时序控制信号对应的上升沿的起始时刻，所述第一时钟信号的下降沿的起始时刻等于所述第二时序控制信号对应的上升沿的起始时刻。
  15. 一种显示装置，其包括显示面板以及与所述显示面板连接的控制板，所述控制板包括驱动电路，所述驱动电路包括：
    时序控制器，用于输出第一时序控制信号以及第二时序控制信号；
    第一电平转换器，与所述时序控制器连接，所述第一电平转换器用于根据所述第一时序控制信号以及所述第二时序控制信号输出第一时钟信号组；
    其中，所述第一时钟信号组包括多个第一时钟信号，所述第一电平转换器根据所述第一时序控制信号确定每一所述第一时钟信号的上升沿的起始时刻，所述第一电平转换器根据所述第二时序控制信号确定每一所述第一时钟信号的下降沿的起始时刻。
  16. 根据权利要求15所述的显示装置，其中，第n个所述第一时钟信号的第m个上升沿的起始时刻与所述第一时序控制信号的第n+（m-1）*k个上升沿的起始时刻对应，第n个所述第一时钟信号的第m个下降沿的起始时刻与所述第二时序控制信号的第n+（m-1）*k个上升沿的起始时刻对应，n、m均为大于0的整数，k为所述第一时钟信号的个数。
  17. 根据权利要求15所述的显示装置，其中，所述第一电平转换器根据所述第一时序控制信号的上升沿的起始时刻以及所述第二时序控制信号的下降沿的起始时刻确定每一所述第一时钟信号的脉冲宽度。
  18. 根据权利要求15所述的显示装置，其中，所述第一电平转换器根据所述第一时序控制信号的脉冲宽度确定所述第一时钟信号的上升沿对应的削角宽度。
  19. 根据权利要求15所述的显示装置，其中，所述第一电平转换器根据所述第二时序控制信号的脉冲宽度确定所述第一时钟信号的下降沿对应的削角宽度。
  20. 根据权利要求15所述的显示装置，其中，所述时序控制器还用于输出第三时序控制信号以及第四时序控制信号；
    所述驱动电路还包括第二电平转换器，所述第二电平转换器与所述时序控制器连接，所述第二电平转换器用于根据所述第三时序控制信号以及所述第四时序控制信号输出第二时钟信号组；
    所述第二时钟信号组包括多个第二时钟信号，所述第二电平转换器根据所述第三时序控制信号确定每一所述第二时钟信号的上升沿的起始时刻，所述第二电平转换器根据所述第四时序控制信号确定每一所述第二时钟信号的下降沿的起始时刻。
PCT/CN2021/100788 2021-04-06 2021-06-18 驱动电路及显示装置 WO2022252297A1 (zh)

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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
CN114360457B (zh) * 2022-01-26 2023-05-02 深圳市华星光电半导体显示技术有限公司 发射驱动电路以及显示装置
CN115394264B (zh) * 2022-08-29 2023-09-12 深圳创维－Rgb电子有限公司 Dlg模式切换电路以及切换方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008146079A (ja) * 2006-12-11 2008-06-26 Samsung Electronics Co Ltd ゲート駆動回路及びそれを使用する液晶表示装置
CN102074184A (zh) * 2011-01-26 2011-05-25 青岛海信电器股份有限公司 电路控制方法、栅极驱动器、液晶显示面板及多媒体终端
CN105390106A (zh) * 2015-12-07 2016-03-09 深圳市华星光电技术有限公司 薄膜晶体管液晶显示面板的电平转换电路及电平转换方法
CN108154859A (zh) * 2018-01-16 2018-06-12 深圳市华星光电技术有限公司 一种阵列基板及显示装置
CN109064982A (zh) * 2018-08-06 2018-12-21 深圳市华星光电技术有限公司 Goa电路驱动系统及goa电路驱动方法与显示装置
CN112201194A (zh) * 2020-10-21 2021-01-08 Tcl华星光电技术有限公司 显示面板及显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101931335B1 (ko) * 2012-03-23 2018-12-20 엘지디스플레이 주식회사 액정표시장치의 레벨 시프터
KR102338945B1 (ko) * 2017-09-14 2021-12-13 엘지디스플레이 주식회사 레벨 쉬프터를 갖는 디스플레이 장치
KR102396469B1 (ko) * 2017-12-22 2022-05-10 엘지디스플레이 주식회사 디스플레이 장치
KR102712575B1 (ko) * 2019-11-07 2024-10-07 삼성디스플레이 주식회사 표시 장치
KR102651800B1 (ko) * 2019-12-13 2024-03-28 엘지디스플레이 주식회사 표시 장치
CN111161664B (zh) * 2020-02-13 2023-04-07 Tcl华星光电技术有限公司 显示装置和终端

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008146079A (ja) * 2006-12-11 2008-06-26 Samsung Electronics Co Ltd ゲート駆動回路及びそれを使用する液晶表示装置
CN102074184A (zh) * 2011-01-26 2011-05-25 青岛海信电器股份有限公司 电路控制方法、栅极驱动器、液晶显示面板及多媒体终端
CN105390106A (zh) * 2015-12-07 2016-03-09 深圳市华星光电技术有限公司 薄膜晶体管液晶显示面板的电平转换电路及电平转换方法
CN108154859A (zh) * 2018-01-16 2018-06-12 深圳市华星光电技术有限公司 一种阵列基板及显示装置
CN109064982A (zh) * 2018-08-06 2018-12-21 深圳市华星光电技术有限公司 Goa电路驱动系统及goa电路驱动方法与显示装置
CN112201194A (zh) * 2020-10-21 2021-01-08 Tcl华星光电技术有限公司 显示面板及显示装置

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