WO2022199167A9 - 栅极驱动电路、驱动装置和显示装置 - Google Patents

栅极驱动电路、驱动装置和显示装置 Download PDF

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Publication number
WO2022199167A9
WO2022199167A9 PCT/CN2021/140936 CN2021140936W WO2022199167A9 WO 2022199167 A9 WO2022199167 A9 WO 2022199167A9 CN 2021140936 W CN2021140936 W CN 2021140936W WO 2022199167 A9 WO2022199167 A9 WO 2022199167A9
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Prior art keywords
signal
output
gate
switch
shift registers
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PCT/CN2021/140936
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English (en)
French (fr)
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WO2022199167A1 (zh
Inventor
李建雷
郑浩旋
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惠科股份有限公司
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Publication of WO2022199167A1 publication Critical patent/WO2022199167A1/zh
Publication of WO2022199167A9 publication Critical patent/WO2022199167A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present application belongs to the technical field of gate driving, and in particular relates to a gate driving circuit, a driving device and a display device.
  • a conventional gate driving circuit is provided with N shift registers arranged in sequence, and the N shift registers are correspondingly connected to N scan lines of the display panel, and output row scan signals to sequentially turn on each row of pixel units.
  • the gate driving circuit needs a shift register to drive each row of pixel units, resulting in high cost and complicated manufacturing process.
  • the purpose of the present application is to provide a gate driving circuit, aiming to solve the problems of high cost and complicated manufacturing process in the traditional gate driving circuit.
  • the first aspect of the embodiments of the present application proposes a gate drive circuit applied to a display panel, including:
  • each switch group includes n first switch units, the output end of each first switch unit is used for corresponding connection with a gate line of the display panel, and each switch
  • the controlled terminals of the n first switch units in the group are commonly connected to form a first controlled node
  • n first shift registers the n first shift registers are sequentially connected and respectively connected to the n input nodes one by one, and the n first shift registers are used for according to the first start signal and the first start signal
  • a clock pulse signal sequentially outputs the first row scanning signal to each of the input nodes and circulates
  • the m second shift registers are sequentially connected and respectively connected to the m controlled nodes one by one, and the m second shift registers are connected according to the second start signal and the first
  • the second clock pulse signal sequentially outputs the second row scanning signal to each of the first controlled nodes, so as to sequentially trigger the opening of the n first switch units connected to each of the first controlled nodes, so that the first The row scanning signal is sequentially fed back to each of the gate lines.
  • the first switch unit is an electronic switch tube.
  • a duty ratio of the first clock signal to the second clock signal is n:1, and n is greater than 1.
  • the gate drive circuit further includes n/2 second switch units, the first shift registers are divided into two groups, and each of the second switch units is connected in parallel to two switches in each group. Between the output terminals of the two first shift registers, the controlled terminals of the second switch units are connected in parallel to form a second controlled node, and each of the second switch units is used to receive a control signal and turn on or off at the same time.
  • the gate drive circuit further includes a pre-charging circuit, and the pre-charging circuit includes m-1 first unidirectional conduction units and m-1 second unidirectional conduction units;
  • the m-1 first unidirectional conduction units are respectively connected in parallel between the adjacent signal output ends of the m second shift registers, and each of the second unidirectional single-pass units is respectively a A unidirectional connection is made between the second shift register and the output of the mth shift register, the positive input of each of the first unidirectional conduction units is connected to the output of the previous second shift register or a The positive output terminal of the second unidirectional conduction unit is connected, and the negative output terminal of each first unidirectional conduction unit is connected with the negative output terminal of another second unidirectional conduction unit;
  • Each of the first unidirectional conduction units is used to synchronously output the second line scanning signal output by the previous second shift register to the next second line scanning signal when the previous second shift register outputs the second line scanning signal.
  • the controlled node connected to the shift register enables two thin film transistors in adjacent n rows in the display panel to be turned on to charge and precharge data signals.
  • the second unidirectional conduction unit is used to isolate the second row scanning signal from being fed back to the second shift register.
  • both the first unidirectional conduction unit and the second unidirectional conduction unit are diodes.
  • the pre-charging circuit further includes m-1 third switch units, each of the third switch units is connected to the preceding stage of each of the first unidirectional conduction units, and each of the third switches The controlled ends of the units are jointly connected to form the third controlled node;
  • Each of the third switch units is configured to receive a control signal and be turned on or off at the same time.
  • both the first shift register and the second shift register are bidirectional shift registers.
  • the gate drive circuit further includes a first signal input terminal for inputting a first row scanning direction control signal, and the first signal input terminal is respectively connected to signal terminals of n first shift registers;
  • first shift registers are further configured to sequentially output the first row scanning signals in a first direction or sequentially output the first row scanning signals in a second direction according to the first row scanning direction control signal , the first direction and the second direction are opposite.
  • the gate drive circuit further includes a second signal input terminal for inputting a second row scanning direction control signal, and the second signal input terminal is respectively connected to signal terminals of m second shift registers;
  • the m second shift registers are further configured to sequentially output the second row scanning signals in a third direction or sequentially output the second row scanning signals in a fourth direction according to the second row scanning direction control signal , the third direction is opposite to the fourth direction.
  • Each of the AND gates is configured to output the first row scan signal when the enable signal is high level, and output the first row scan signal when the enable signal is low level and cut off.
  • the gate drive circuit further includes N level shifters, each of the level shifters is connected to one of the AND gates;
  • the level converter is used to convert the first row scanning signal output by the AND gate into a row output high level signal and a row output low level signal.
  • the gate drive circuit further includes N output buffers, and the N output buffers are respectively connected to the N level shifters in a one-to-one correspondence;
  • the output buffer is used to amplify the power of the level signal output by the level shifter.
  • the second aspect of the embodiments of the present application provides a driving device, which includes a timing controller, a source driving circuit, and the above-mentioned gate driving circuit;
  • the timing controller is respectively connected to the source driving circuit and the gate driving circuit, the source driving circuit is connected to a plurality of data lines of the display panel, and the gate driving circuit is connected to the display panel.
  • the multiple gate lines of the panel are connected.
  • a third aspect of the embodiments of the present application provides a display device, which includes a display panel and the above-mentioned driving device.
  • the above-mentioned gate drive circuit outputs the first row scanning signal in a cyclic manner through the n first shift registers, and at the same time, each second shift register controls the n first switch units connected to each first controlled node to be turned on, so that The scan signal of the first row is fed back to each gate line in turn to realize progressive scan drive.
  • the gate drive circuit only needs n+m shift registers to complete the gate drive. Compared with the original gate drive circuit, which requires n *m shift registers reduce the number of shift registers, reduce the cost and simplify the manufacturing process.
  • FIG. 1 is a first structural schematic diagram of a gate drive circuit provided in an embodiment of the present application
  • FIG. 2 is a schematic waveform diagram of a clock pulse signal in the gate drive circuit shown in FIG. 1;
  • FIG. 3 is a second structural schematic diagram of the gate drive circuit provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of a polarity change of a first pixel unit of a display panel
  • FIG. 5 is a schematic diagram of a polarity change of a second pixel unit of a display panel
  • FIG. 6 is a schematic diagram of a third structure of a gate drive circuit provided in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a fourth structure of a gate drive circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a driving device provided by an embodiment of the present application.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means two or more, unless otherwise specifically defined.
  • the first aspect of the embodiments of the present application proposes a gate driving circuit 100 applied to the display panel 1 .
  • FIG. 1 is a schematic diagram of a first structure of a gate drive circuit 100 provided in an embodiment of the present application.
  • the gate drive circuit 100 includes:
  • n first shift registers the n first shift registers are sequentially connected and respectively connected to n input nodes one by one, and the n first shift registers are used according to the first start signal STV1 and the first clock pulse signal CLK1 Sequentially output the first row of scan signals to each input node and loop;
  • the m second shift registers are sequentially connected and respectively connected to the m controlled nodes one by one, and the m second shift registers are connected according to the second start signal STV2 and the second clock pulse signal CLK2 Sequentially output the second row scanning signal to each first controlled node to sequentially trigger the n first switch units connected to each first controlled node to turn on, so that the first row scanning signal is sequentially fed back to each gate Wire.
  • the n first shift registers include the first first shift register 110 to the nth first shift register
  • the m second shift registers include the first second shift register 210 to the nth first shift register.
  • the m-th second shift register, the input terminals of the i-th first switch unit in each m switch group are commonly connected to form the i-th input node, that is, the first first switch unit of the first switch group 11
  • the input terminals of K1 1_1 , the first first switch unit K1 2_1 of the second switch group 12 to the first first switch unit K1 m_1 of the mth switch group are connected together to form the first input node, and the first switch group 11
  • the second first switch unit K1 1_2 of the second switch group 12, the input end of the second first switch unit K1 2_2 of the second switch group 12 to the second first switch unit K1 m_2 of the m switch group are connected together to form the second Input nodes, and so on, each switch group includes n first switch units,
  • the controlled ends of the first switch units in each switch group are commonly connected, m switch groups form m first controlled nodes, and the m first controlled nodes are respectively connected to the m second shift registers.
  • the output ends are connected in sequence, that is, the first first controlled node formed by the controlled ends of the first switch units K1 1_1 ⁇ K1 1_n of the first switch group 11 is connected to the output end of the first second shift register 210 , the second first controlled node formed by the controlled ends of the first switch units K1 2_1 ⁇ K1 2_n of the second switch group is connected to the output end of the second shift register 220 until the mth switch The m th first controlled node formed by the controlled ends of the first switch units in the group is connected to the output end of the m th second shift register.
  • the switch group can be understood as a switch array equivalent to m rows and n columns, and the second shift register is used to output the second row scanning signal row by row to control the n first switch units in each row to be turned on and off simultaneously, and at the same time , the first shift register outputs the first row scanning signal column by column to each input node, and outputs it circularly, so that the first row scanning signal is sequentially output to each gate line of the display panel 1 to realize row-by-row scanning.
  • the first second shift register 210 outputs the second line scanning signal to the first first switch unit K1 1_1 to the nth first switch unit K1 1_n of the first switch group 11, and the n first switch units simultaneously trigger the conduction
  • the second line scan signal is used as the start signal of the second shift register 220, so as to realize the progressive opening and output of the second line scan signal, and the second line scan signal is output by the second shift register 220 at the second position.
  • the first first shift register 110 to the nth first shift register sequentially output the first line scanning signal according to the received first start signal STV1 and the first clock pulse signal CLK1, thereby sequentially outputting n
  • the scan signal of the first row is sent to the first gate line to the nth gate line of the display panel 1
  • the m second shift registers sequentially output the second row scan signal to control the sequential conduction of the m switch groups, and the n first
  • the shift register as a whole is output cyclically between two second row scanning signal output intervals, thereby outputting N first row scanning signals to N gate lines of the display panel 1, so as to control the display panel 1 to be turned on row by row .
  • the number of n can be selected according to the demand, and there is no specific limit.
  • Each first switch unit can be selected to have a switch circuit with controlled on-off.
  • the first switch unit is an electronic switch tube, and a triode or a MOS tube can be selected.
  • the first switch unit A switch unit is a MOS tube.
  • the first clock pulse signal CLK1 and the second clock pulse signal The duty ratio of CLK2 is n:1, and n is greater than 1.
  • the first second shift register 210 outputs the second row scan signal to each first switch unit of the first switch group, and at the same time, the first row scan signal
  • the first row scan signal There are n rising edges between the two second line scanning signals, that is, the first bit of the first shift register 110 to the nth bit of the first shift register sequentially output n between the two second line scanning signals
  • the first row scanning signal is sent to the first first switch unit K1 1_1 of the first switch group to the nth first switch unit K1 1_n of the first group, and is output to the first switch unit of the display panel 1 in turn through each first switch unit.
  • n the size of n can be selected according to different types of display panels 1 , design cost and wiring requirements, and there is no specific limit.
  • the display panel 1 includes M columns*N rows of pixel units, where M is the number of columns of pixel units in the display panel 1, N is the number of rows of pixel units in the display panel 1 and the number of gate lines , in order to achieve different resolutions and working modes, as shown in FIG. 3, in one embodiment, the gate drive circuit further includes n/2 second switch units (such as second switch units K21 and K22, etc.), the first A shift register is divided into two groups, and each second switch unit is connected in parallel between the output terminals of the two first shift registers in each group, and the controlled terminals of each second switch unit are connected in parallel to form a second controlled terminal. Control node Q, each second switch unit is used to receive a control signal and turn on or turn off at the same time.
  • n/2 second switch units such as second switch units K21 and K22, etc.
  • the refresh rate of the screen on the display panel 1 is 60HZ.
  • a UD screen that is, a 4K*2K LCD screen has 3840*2160 pixels, and the refresh rate is generally 60Hz.
  • Small-sized UD screens (such as 32 inches), in order to realize The small-sized UD display supports 4K*1K, 120Hz working mode at the same time, that is, the number of lines in one frame changes from 2160 to 1080, and the time of one frame changes from 1/60 second to 1/120 second.
  • the unit synthesizes a row of pixel units, that is, 3840*1080 pixel units.
  • the output terminals of the two first shift registers are connected through the second switch unit, and the scanning signal is output to the gate of the display panel 1 in the first row.
  • the polar line is connected, two rows of thin film transistors can be turned on at the same time, thereby realizing the charging of the pixel units of the two rows.
  • the refresh frequency of the first clock pulse signal and the second clock pulse signal is doubled, so that the display panel 1 can work at 4K *1K, 120Hz working mode, the working mode of the display panel 1 is added, and the display diversity of the display panel 1 is realized.
  • Figure 4 is a schematic diagram of the polarity change of the first type of pixel unit of the display panel 1.
  • the voltage polarity of the data signal on the data line of the display panel 1 remains unchanged, and in the adjacent The polarity is switched between positive and negative in the frame picture, therefore, when the data signal of the display panel 1 changes as shown in FIG. 4 , the gate driving circuit does not need to change.
  • FIG. 5 is a schematic diagram of the polarity change of the second pixel unit of the display panel 1.
  • the polarity of the voltage on the data line of the display panel 1 is reversed when the adjacent row is turned on.
  • a corresponding pre-charging circuit can be added, as shown in Figure 6.
  • the gate drive circuit also includes a pre-charging circuit, and the pre-charging circuit includes m-1 One unidirectional conduction unit (D11, D12, D13, etc.) and m-1 second unidirectional conduction units (D21, D22, D23, etc.);
  • the m-1 first unidirectional conduction units are respectively connected in parallel between the adjacent signal output terminals of the m second shift registers, and each second unidirectional conduction unit is respectively unidirectionally connected to the second On the output end of the shift register to the mth shift register, the positive input end of each first unidirectional conduction unit is connected with the output end of the previous second shift register or the positive output of a second unidirectional conduction unit The terminals are connected, and the negative output terminal of each first unidirectional conduction unit is connected to the negative output terminal of another second unidirectional conduction unit;
  • Each first unidirectional conduction unit is used to synchronously output the second row scanning signal output by the previous second shift register to the next second shift register when the previous second shift register outputs the second row scanning signal
  • the controlled nodes connected to the registers enable two thin film transistors in adjacent n rows in the display panel 1 to be turned on for charging and precharging of data signals.
  • the second row scan signal when the first second shift register 210 outputs the second row scan signal from the output port e to the first first switch unit K1-11, the second row scan signal also passes through a first unidirectional conduction unit D11 is input to the first first switch unit K1-21 in the adjacent switch group.
  • the two switch units are turned on at the same time, and the first line scan signal output by the first shift register 110 through the output port a is simultaneously Input to the gate line of the first row and the scanning line of the fifth row of the display panel 1 through two switch units, so that the scanning signal of the fifth row is turned on in advance, and the pixel voltage controlled by this row is reversed toward the target voltage of the current frame in advance, offsetting
  • the gate signal delay caused by the scan line load further improves the pixel charging rate.
  • the first unidirectional conduction unit advances the output of the second line scanning signal output by the previous second shift register to the next controlled node, so that the input of the controlled node and the first line scanning signal
  • the first switching unit connected to the node is turned on in advance, and the scanning signal of the second row is output to the gate lines separated by n rows in advance, and the two thin film transistors in adjacent n rows in the display panel 1 are turned on to charge and precharge the data signal .
  • the second unidirectional conduction unit is used for signal isolation, preventing the second row scanning signal from being fed back to the second shift register and non-adjacent controlled nodes.
  • Both the first unidirectional conduction unit and the second unidirectional conduction unit may be unidirectional output structures such as optocouplers and diodes. In one embodiment, both the first unidirectional conduction unit and the second unidirectional conduction unit are diodes.
  • the precharging circuit further includes m-1 third switch units (K31, K32, K33, etc.), each third The switch unit is connected to the front stage of each first unidirectional conduction unit, and the controlled terminals of each third switch unit are commonly connected to form a third controlled node;
  • Each third switch unit is used to receive the control signal and turn on or turn off at the same time.
  • the third switch units can be controlled to be turned on or off at the same time by outputting different control signals, so that the display panel 1 can satisfy the polarity change of the pixel units as shown in FIG. 4 and FIG. 5 , when each When the third switch unit is turned off, the gate drive circuit can be applied to the display panel 1 shown in FIG. 4 , and when each switch unit is turned on, the gate drive circuit can be applied to the display panel that needs to be precharged as shown in FIG. 5 1. According to the display requirement, the switch state of the third switch unit can be switched correspondingly, so as to improve the display diversity and compatibility of the gate drive circuit and the corresponding display panel 1 .
  • the first shift register and the second shift register are both bidirectional shift registers, that is, the m second shift registers can correspond to the slaves according to the received row scanning direction control signal
  • the first second shift register 210 to the mth second shift register are turned on sequentially, or sequentially turned on from the m second shift register to the first second shift register 210, to correspondingly trigger each switch group
  • the first shift register can be turned on sequentially from the first first shift register 110 to the nth first shift register according to the received row scanning direction control signal, or from the nth A shift register to the first first shift register 110 is turned on and circulated sequentially, therefore, as shown in FIG.
  • the first signal input terminal of U/D1 the first signal input terminal is respectively connected to the signal terminals of n first shift registers;
  • the n first shift registers are also used to sequentially output the first row scanning signal in the first direction or sequentially output the first row scanning signal in the second direction according to the first row scanning direction control signal U/D1, the first direction and The second direction is reversed, and the first direction and the second direction correspond to the first shift register 110 to the nth first shift register and the nth first shift register to the first first shift register Register 110.
  • the gate drive circuit 100 also includes a second signal input terminal for inputting the second row scanning direction control signal U/D2, and the second signal input terminal is respectively connected to the signal terminals of m second shift registers;
  • the m second shift registers are also used to sequentially output the second row scanning signal in the third direction or sequentially output the second row scanning signal in the fourth direction according to the second row scanning direction control signal U/D2, the third direction and The fourth direction is reversed, and the third direction and the fourth direction correspond to the first second shift register 210 to the mth second shift register being turned on sequentially and from the m second shift register to the first second shift register.
  • Two shift registers 210 Two shift registers 210 .
  • Each AND gate is used to output the first line scan signal when the enable signal OE is high level, and output the first line scan signal when the enable signal OE is low level, that is, when the enable signal OE is high level, it is allowed The output of the first line scan signal.
  • the gate drive circuit 100 further includes N level shifters (including L/S1 to L/S N), N output buffers (including BUF1 to BUF N), the fourth signal input terminal for inputting the row output high-level signal Vgh and the fifth signal input terminal for inputting the row output low-level signal Vgl, each level shifter is respectively connected to the fourth signal input terminal and the fifth signal input terminal, each level shifter is also connected to an AND gate, and the N output buffers are respectively connected to the N level shifters in one-to-one correspondence;
  • N level shifters including L/S1 to L/S N
  • N output buffers including BUF1 to BUF N
  • a level shifter which is used to convert the first line scan signal output by the AND gate into a line output high level signal and a line output low level signal;
  • the output buffer is used for amplifying the power of the level signal output by the level shifter.
  • the level converters are connected sequentially, and the 0V low level and 3.3V in the scanning signal of the first row are respectively converted into a low level signal Vgl of about -8V and a high level signal Vgh of about 30V, realizing The function of level shifting, at the same time, the output buffer is used to increase the driving capability of the first line of scanning signal through the analog buffer amplifier.
  • the present application also proposes a driving device 2, which includes a timing controller 300, a source driving circuit 200, and a gate driving circuit 100.
  • a driving device 2 which includes a timing controller 300, a source driving circuit 200, and a gate driving circuit 100.
  • the gate driving circuit 100 For the specific structure of the gate driving circuit 100, refer to the above implementation
  • the drive device 2 since the drive device 2 adopts all the technical solutions of all the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, and will not be repeated here.
  • the timing controller 300 is respectively connected to the source driving circuit 200 and the gate driving circuit 100
  • the source driving circuit 200 is connected to a plurality of data lines of the display panel 1
  • the gate driving circuit 100 is connected to a plurality of gates of the display panel 1. pole connection.
  • the timing controller 300 converts the data signals, control signals and clock signals received from the outside into data signals, control signals and clock signals suitable for the gate drive circuit 100 and the source drive circuit 200 to realize the display panel 1 image is displayed.
  • the present application also proposes a display device, which includes a display panel 1 and a driving device 2.
  • a display device which includes a display panel 1 and a driving device 2.
  • the driving device 2 For the specific structure of the driving device 2, refer to the above-mentioned embodiments. Since this display device adopts all the technical solutions of all the above-mentioned embodiments, at least All the beneficial effects brought by the technical solutions of the above embodiments will not be repeated here.

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Abstract

本申请提出一种栅极驱动电路（100）、驱动装置（2）和显示装置，其中，栅极驱动电路（100）包括m个开关组、n个第一移位寄存器和m个第二移位寄存器，每一开关组包括n个第一开关单元，n个第一移位寄存器循环输出第一行扫描信号，同时每个第二移位寄存器控制对应每个第一受控节点连接的n个第一开关单元开启，使第一行扫描信号依次反馈至每条栅极线，实现逐行扫描驱动，栅极驱动电路（100）仅需n+m个移位寄存器即可完成栅极驱动，相比于原栅极驱动电路（100）需要n*m个移位寄存器，减少了移位寄存器的个数，降低了成本同时简化了制造工艺。

Description

栅极驱动电路、驱动装置和显示装置
本申请要求于2021年03月25日在中国专利局提交的、申请号为202110317868.4、申请名称为“栅极驱动电路、驱动装置和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于栅极驱动技术领域，尤其涉及一种栅极驱动电路、驱动装置和显示装置。
 背景技术
目前，常规栅极驱动电路通过设置依次排列的N个移位寄存器，N个移位寄存器对应连接显示面板的N条扫描线，并输出行扫描信号以逐次开启各行像素单元。
但是，栅极驱动电路驱动每一行像素单元需要一个移位寄存器，导致成本高并且制造工艺复杂。
 技术问题
本申请的目的在于提供一种栅极驱动电路，旨在解决传统的栅极驱动电路存在的成本高以及制造工艺复杂的问题。
 技术解决方案
为了解决上述技术问题，本申请实施例采用的技术方案是：
本申请实施例的第一方面提出了一种栅极驱动电路，应用于显示面板，包括：
m个开关组，每一所述开关组包括n个第一开关单元，每个所述第一开关单元的输出端用于与所述显示面板的一条栅极线对应连接，每一所述开关组的n个第一开关单元的受控端共接构成一个第一受控节点，每一所述m个开关组中的第i个第一开关单元的输入端共接构成第i个输入节点，其中，m和n为正整数，i=1,2,…,n；
n个第一移位寄存器，所述n个第一移位寄存器依次连接并分别与n个所述输入节点一一连接，所述n个第一移位寄存器用于根据第一起始信号和第一时钟脉冲信号依次输出第一行扫描信号至每个所述输入节点并循环；
m个第二移位寄存器，所述m个第二移位寄存器依次连接并分别与m个所述受控节点一一连接，所述m个第二移位寄存器根据第二起始信号和第二时钟脉冲信号依次输出第二行扫描信号至每个所述第一受控节点，以依次触发与每个所述第一受控节点连接的n个第一开关单元开启，使所述第一行扫描信号依次反馈至每条所述栅极线。
可选地，所述第一开关单元为电子开关管。
可选地，所述第一时钟脉冲信号与所述第二时钟脉冲信号的占空比比值为n：1，n大于1。
可选地，所述栅极驱动电路还包括n/2个第二开关单元，所述第一移位寄存器两两分为一组，每一所述第二开关单元并联在每组内的两个第一移位寄存器的输出端之间，各所述第二开关单元的受控端并联构成第二受控节点，各所述第二开关单元用于接收控制信号同时导通或者关断。
可选地，所述栅极驱动电路还包括预充电电路，所述预充电电路包括m-1个第一单向导通单元和m-1个第二单向导通单元；
所述m-1个第一单向导通单元分别一一并接在所述m个第二移位寄存器的相邻的信号输出端之间，每一所述第二单向单通单元分别一一单向连接在第二个移位寄存器至第m个移位寄存器的输出端上，每一所述第一单向导通单元的正输入端与前一个第二移位寄存器的输出端或者一个第二单向导通单元的正输出端连接，每一所述第一单向导通单元的负输出端与另一个第二单向导通单元的负输出端连接；
每一所述第一单向导通单元，用于在前一个第二移位寄存器输出第二行扫描信号时将前一个第二移位寄存器输出的第二行扫描信号同步输出至下一个第二移位寄存器所连接的受控节点，以使所述显示面板中相邻n行中的两个薄膜晶体管开启进行数据信号的充电和预充电。
可选地，所述第二单向导通单元用于隔离所述第二行扫描信号回馈至所述第二移位寄存器。
可选地，所述第一单向导通单元和第二单向导通单元均为二极管。
可选地，所述预充电电路还包括m-1个第三开关单元，每一所述第三开关单元连接在每一所述第一单向导通单元的前级，各所述第三开关单元的受控端共接构成第三受控节点；
各所述第三开关单元用于接收控制信号同时导通或者关断。
可选地，所述第一移位寄存器和所述第二移位寄存器均为双向移位寄存器。
可选地，所述栅极驱动电路还包括用于输入第一行扫描方向控制信号的第一信号输入端，所述第一信号输入端分别与n个第一移位寄存器的信号端连接；
所述n个第一移位寄存器，还用于根据所述第一行扫描方向控制信号以第一方向依次输出所述第一行扫描信号或者以第二方向依次输出所述第一行扫描信号，所述第一方向和所述第二方向反向。
可选地，所述栅极驱动电路还包括用于输入第二行扫描方向控制信号的第二信号输入端，所述第二信号输入端分别与m个第二移位寄存器的信号端连接；
所述m个第二移位寄存器，还用于根据所述第二行扫描方向控制信号以第三方向依次输出所述第二行扫描信号或者以第四方向依次输出所述第二行扫描信号，所述第三方向和所述第四方向反向。
可选地，所述栅极驱动电路还包括N个与门和用于输入使能信号的第三信号输入端，所述第三信号输入端分别与每一所述与门的第一信号输入端连接，每一所述与门的第二信号输入端与一个所述第一开关单元的输出端连接，其中，N=m×n；
每一所述与门，用于在所述使能信号为高电平时输出所述第一行扫描信号，以及在所述使能信号为低电平时截止时输出所述第一行扫描信号。
可选地，所述栅极驱动电路还包括N个电平转换器，每一所述电平转换器与一个所述与门连接；
所述电平转换器，用于将所述与门输出的第一行扫描信号转换为行输出高电平信号和行输出低电平信号。
可选地，所述栅极驱动电路还包括N个输出缓冲器，N个所述输出缓冲器分别与N个所述电平转换器一一对应连接；
所述输出缓冲器，用于对所述电平转换器输出的电平信号进行功率放大。
本申请实施例的第二方面提出了一种驱动装置，驱动装置包括时序控制器、源极驱动电路和如上所述的栅极驱动电路；
所述时序控制器分别与所述源极驱动电路和所述栅极驱动电路连接，所述源极驱动电路与所述显示面板的多条数据线连接，所述栅极驱动电路与所述显示面板的多条栅极线连接。
本申请实施例的第三方面提出了一种显示装置，显示装置包括显示面板和如上所述的驱动装置。
 有益效果
上述的栅极驱动电路通过n个第一移位寄存器循环输出第一行扫描信号，同时每个第二移位寄存器控制对应每个第一受控节点连接的n个第一开关单元开启，使第一行扫描信号依次反馈至每条栅极线，实现逐行扫描驱动，栅极驱动电路仅需n+m个移位寄存器即可完成栅极驱动，相比于原栅极驱动电路需要n*m个移位寄存器，减少了移位寄存器的个数，降低了成本同时简化了制造工艺。
可以理解的是，上述第二方面和第三方面的有益效果可以参见上述第一方面中的相关描述，在此不再赘述。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的栅极驱动电路的第一种结构示意图；
图2为图1所示的栅极驱动电路中时钟脉冲信号的波形示意图；
图3为本申请实施例提供的栅极驱动电路的第二种结构示意图；
图4为显示面板的第一种像素单元极性变化的示意图；
图5为显示面板的第二种像素单元极性变化的示意图；
图6为本申请实施例提供的栅极驱动电路的第三种结构示意图；
图7为本申请实施例提供的栅极驱动电路的第四种结构示意图；
图8为本申请实施例提供的驱动装置的结构示意图。
 本发明的实施方式
为了使本申请所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
本申请实施例的第一方面提出了一种栅极驱动电路100，应用于显示面板1。
如图1所示，图1为本申请实施例提供的栅极驱动电路100的第一种结构示意图，本实施例中，栅极驱动电路100包括：
m个开关组，包括开关组11至开关组，每一开关组包括n个第一开关单元，每个第一开关单元的输出端用于与显示面板1的一条栅极线对应连接，每一开关组的n个第一开关单元的受控端共接构成一个第一受控节点，每一m个开关组中的第i个第一开关单元的输入端共接构成第i个输入节点，其中，m和n为正整数，i=1,2,…,n；
n个第一移位寄存器，n个第一移位寄存器依次连接并分别与n个输入节点一一连接，n个第一移位寄存器用于根据第一起始信号STV1和第一时钟脉冲信号CLK1依次输出第一行扫描信号至每个输入节点并循环；
m个第二移位寄存器，m个第二移位寄存器依次连接并分别与m个受控节点一一连接，m个第二移位寄存器根据第二起始信号STV2和第二时钟脉冲信号CLK2依次输出第二行扫描信号至每个第一受控节点，以依次触发与每个第一受控节点连接的n个第一开关单元开启，使第一行扫描信号依次反馈至每条栅极线。
本实施例中，n个第一移位寄存器包括第一位第一移位寄存器110至第n位第一移位寄存器，m个第二移位寄存器包括第一位第二移位寄存器210至第m位第二移位寄存器，每一m个开关组中的第i个第一开关单元的输入端共接构成第i个输入节点，即第一开关组11的第一位第一开关单元K1 1_1、第二开关组12的第一位第一开关单元K1 2_1至第m开关组的第一位第一开关单元K1 m_1的输入端共接形成第一个输入节点，第一开关组11的第二位第一开关单元K1 1_2、第二开关组12的第二位第一开关单元K1 2_2至第m开关组的第二位第一开关单元K1 m_2的输入端共接形成第二个输入节点，以此类推，每一开关组包括n个第一开关单元，从而构成n个输入节点，n个输入节点依次排列，并分别与n个第一移位寄存器的输出端依次连接，即第一个输入节点与第一位第一移位寄存器110的输出端连接，第二个输入节点与第二位第一移位寄存器120的输出端连接，直至第n个输入节点与第n位第一移位寄存器连接。
同时，每一开关组内的各第一开关单元的受控端共接，m个开关组形成m个第一受控节点，m个第一受控节点分别与m个第二移位寄存器的输出端依次连接，即第一开关组11的各第一开关单元K1 1_1~K1 1_n的受控端形成的第一个第一受控节点与第一位第二移位寄存器210的输出端连接，第二开关组的各第一开关单元K1 2_1~K1 2_n的受控端形成的第二个第一受控节点与第二位第二移位寄存器220的输出端连接，直至第m位开关组的各第一开关单元的受控端形成的第m个第一受控节点与第m位第二移位寄存器的输出端连接。
开关组可以理解为构成等同于m行n列的开关阵列，第二移位寄存器用于逐行输出第二行扫描信号以控制每一行的n个第一开关单元同时导通和关断，同时，第一移位寄存器逐列输出第一行扫描信号至各个输入节点，并循环输出，从而实现第一行扫描信号依次输出至显示面板1的各栅极线中，实现逐行扫描。
例如，以第一位第二移位寄存器210至第m位第二移位寄存器为扫描方向，第一位第二移位寄存器210接收到第二时钟脉冲信号CLK2以及第二起始信号STV2时，第一位第二移位寄存器210输出第二行扫描信号至第一开关组11的第一第一开关单元K1 1_1至第n第一开关单元K1 1_n，n个第一开关单元同时触发导通，同时第二行扫描信号作为第二位第二移位寄存器220的起始信号，从而实现逐行开启输出第二行扫描信号，在第二位第二移位寄存器220输出第二行扫描信号前，第一位第一移位寄存器110至第n位第一移位寄存器根据接收到的第一起始信号STV1和第一时钟脉冲信号CLK1依次输出第一行扫描信号，从而依次输出n个第一行扫描信号至显示面板1的第一栅极线至第n栅极线，m个第二移位寄存器依次输出第二行扫描信号控制m个开关组的依次导通，n个第一移位寄存器作为整体在两个第二行扫描信号输出间隔之间循环输出，从而输出N个第一行扫描信号至显示面板1的N个栅极线，以对显示面板1进行逐行开启控制。
通过设置n个第一移位寄存器和m个第二移位寄存器以及m个开关组，栅极驱动电路100只需m+n个移位寄存器即可实现行扫描信号的逐行输出，无需设置N个移位寄存器以逐行输出行扫描信号，其中N=m*n，n大于1，减少了移位寄存器的个数，从而达到降低设计成本和简化制造工艺的目的。
n的个数可根据设计成本、走线需求以及显示面板1的类型对应设计，例如当显示面板1包括依次排列的1080个栅极线，n可选择4、6、8、10等，但是选择10时，走线复杂，根据成本和走线需求最佳选择4，即栅极驱动电路100需要4+1080/4=274个移位寄存器，根据不同类别的显示面板1、设计成本和走线需求可对应选择n的个数，具体不做限制。
各第一开关单元可选择具备受控通断的开关电路，在一个实施例中，第一开关单元为电子开关管，可选择三极管、MOS管，为了实现高效驱动，在一个实施例中，第一开关单元为MOS管。
在一个实施例中，为了实现n个第一移位寄存器作为整体在两个第二行扫描信号输出间隔之间循环输出，如图2所示，第一时钟脉冲信号CLK1与第二时钟脉冲信号CLK2的占空比比值为n：1，n大于1。
具体地，在第一个时钟脉冲信号的上升沿到来时，第一位第二移位寄存器210输出第二行扫描信号至第一开关组的各第一开关单元，同时，第一行扫描信号的上升沿在两个第二行扫描信号之间设置有n个，即第一位第一移位寄存器110至第n位第一移位寄存器在两个第二行扫描信号之间依次输出n个第一行扫描信号至第一开关组的第一个第一开关单元K1 1_1至第一组第n个第一开关单元K1 1_n，并经各第一开关单元依次输出至显示面板1的第一栅极线至第n栅极线，以此类推，每一第二行扫描信号输出后，n个第一行扫描信号循环依次，最终输出N个第一行扫描信号至显示面板1的N个栅极线上，实现逐行开启，其中，N=m*n。
其中，n的大小根据不同类别的显示面板1、设计成本和走线需求可对应选择n的个数，具体不做限制。
本实施例中，显示面板1中包括M列*N行像素单元，其中，M为显示面板1中像素单元的列数，N为显示面板1中像素单元的行数同时为栅极线的数量，为了实现不同的分辨率和工作模式，如图3所示，在一个实施例中，栅极驱动电路还包括n/2个第二开关单元（例如第二开关单元K21和K22等），第一移位寄存器两两分为一组，每一第二开关单元并联在每组内的两个第一移位寄存器的输出端之间，各第二开关单元的受控端并联构成第二受控节点Q，各第二开关单元用于接收控制信号同时导通或者关断。
正常情况下，显示面板1的画面的刷新频率为60HZ，例如，UD屏即4K*2K的LCD屏有3840*2160像素，刷新频率一般为60Hz，小尺寸UD屏(如32寸)，为了实现小尺寸UD显示屏同时支持4K*1K，120Hz工作模式，即一帧的行数由2160变1080，且一帧时间由1/60秒变成了1/120秒，需将相邻两行像素单元合成一行像素单元，即3840*1080个像素单元，本实施例中，通过第二开关单元将两个第一移位寄存器的输出端连接，在第一行扫描信号输出至显示面板1的栅极线时可同时开启连接的两行薄膜晶体管，进而实现两行像素单元的充电，同时，将第一时钟脉冲信号和第二时钟脉冲信号的刷新频率翻倍，从而实现显示面板1工作在4K*1K，120Hz工作模式，增多了显示面板1的工作模式，实现了显示面板1的显示多样性。
如图4所示，图4为显示面板1的第一种像素单元极性变化的示意图，在同一帧画面中显示面板1的数据线上的数据信号的电压极性不变，且在相邻帧画面中进行极性正负切换，因此，当显示面板1的数据信号如图4变化时，栅极驱动电路可不做变化。
如图5所示，图5为显示面板1的第二种像素单元极性变化的示意图，在同一帧画面中显示面板1的数据线上的电压极性在相邻行开启时极性翻转，此时，为了减少正式充电所需时间，可增加对应的预充电电路，如图6所示，在一个实施例中，栅极驱动电路还包括预充电电路，预充电电路包括m-1个第一单向导通单元(D11、D12、D13等)和m-1个第二单向导通单元(D21、D22、D23等)；
m-1个第一单向导通单元分别一一并接在m个第二移位寄存器的相邻的信号输出端之间，每一第二单向导通单元分别一一单向连接在第二个移位寄存器至第m个移位寄存器的输出端上，每一第一单向导通单元的正输入端与前一个第二移位寄存器的输出端或者一个第二单向导通单元的正输出端连接，每一第一单向导通单元的负输出端与另一个第二单向导通单元的负输出端连接；
每一第一单向导通单元，用于在前一个第二移位寄存器输出第二行扫描信号时将前一个第二移位寄存器输出的第二行扫描信号同步输出至下一个第二移位寄存器所连接的受控节点，以使显示面板1中相邻n行中的两个薄膜晶体管开启进行数据信号的充电和预充电。
举例说明，当第一位第二移位寄存器210从输出端口e输出第二行扫描信号至第一个第一开关单元K1-11时，第二行扫描信号同样经过一个第一单向导通单元D11输入至相邻开关组中的第一个第一开关单元K1-21，此时两个开关单元同时开启，第一位第一移位寄存器110通过输出端口a输出的第一行扫描信号同时经过两个开关单元输入至显示面板1的第一行栅极线和第五行扫描线，从而使得第五行的扫描信号提前开启，提前使该行控制的像素电压朝当前帧的目标电压翻转，抵消扫描线负载导致的栅信号延迟，进一步提高像素充电率。
以此类推，第一单向导通单元将前一个第二移位寄存器输出的第二行扫描信号提前输出至下一个受控节点，使得与该受控节点以及接收到第一行扫描信号的输入节点连接的第一开关单元提前开启，以及第二行扫描信号提前输出至相隔n行的栅极线，显示面板1中相邻n行中的两个薄膜晶体管开启进行数据信号的充电和预充电。
第二单向导通单元用于进行信号隔离，避免第二行扫描信号回馈至第二移位寄存器以及非相邻的受控节点。
第一单向导通单元和第二单向导通单元均可为光耦、二极管等单向输出结构，在一个实施例中，第一单向导通单元和第二单向导通单元均为二极管。
请继续参阅图6，在一个实施例中，为了提高显示面板1的多样性和兼容性，预充电电路还包括m-1个第三开关单元(K31、K32、K33等)，每一第三开关单元连接在每一第一单向导通单元的前级，各第三开关单元的受控端共接构成第三受控节点；
各第三开关单元用于接收控制信号同时导通或者关断。
本实施例中，可通过输出不同的控制信号控制各第三开关单元同时导通或者关断，进而使得显示面板1满足如图4和图5所示的像素单元极性变化的情况，当各第三开关单元关断时，栅极驱动电路可应用于如图4所示的显示面板1，当各开关单元导通时，栅极驱动电路应用于如图5所示需预充电的显示面板1，根据显示需求，可对应切换第三开关单元的开关状态，提高栅极驱动电路以及对应显示面板1的显示多样性和兼容性。
为了实现双向扫描驱动，在一个实施例中，第一移位寄存器和第二移位寄存器均为双向移位寄存器，即m个第二移位寄存器可根据接收到的行扫描方向控制信号对应从第一位第二移位寄存器210至第m位第二移位寄存器依次开启，或者从第m位第二移位寄存器至第一位第二移位寄存器210依次开启，以对应触发各个开关组的顺序开启，同时，第一移位寄存器可根据接收到的行扫描方向控制信号对应从第一位第一移位寄存器110至第n位第一移位寄存器依次开启，或者从第n位第一移位寄存器至第一位第一移位寄存器110依次开启并循环，因此，如图1所示，在一个实施例中，栅极驱动电路100还包括用于输入第一行扫描方向控制信号U/D1的第一信号输入端，第一信号输入端分别与n个第一移位寄存器的信号端连接；
n个第一移位寄存器，还用于根据第一行扫描方向控制信号U/D1以第一方向依次输出第一行扫描信号或者以第二方向依次输出第一行扫描信号，第一方向和第二方向反向，第一方向和第二方向对应于第一位第一移位寄存器110至第n位第一移位寄存器和第n位第一移位寄存器至第一位第一移位寄存器110。
栅极驱动电路100还包括用于输入第二行扫描方向控制信号U/D2的第二信号输入端，第二信号输入端分别与m个第二移位寄存器的信号端连接；
m个第二移位寄存器，还用于根据第二行扫描方向控制信号U/D2以第三方向依次输出第二行扫描信号或者以第四方向依次输出第二行扫描信号，第三方向和第四方向反向，第三方向和第四方向对应于第一位第二移位寄存器210至第m位第二移位寄存器依次开启和从第m位第二移位寄存器至第一位第二移位寄存器210。
如图7所示，为了实现使能输出，在一个实施例中，栅极驱动电路100还包括N个与门(U1至UN)和用于输入使能信号OE的第三信号输入端，第三信号输入端分别与每一与门的第一信号输入端连接，每一与门的第二信号输入端与一个第一开关单元的输出端连接，其中，N=m×n；
每一与门，用于在使能信号OE为高电平时输出第一行扫描信号，在使能信号OE为低电平时截止时输出第一行扫描信号，即使能信号OE为高电平时允许第一行扫描信号的输出。
请继续参阅图7，在一个实施例中，栅极驱动电路100还包括N个电平转换器（包括L/S1至L/S N）、N个输出缓冲器（包括BUF1至BUF N）、用于输入行输出高电平信号Vgh的第四信号输入端和用于输入行输出低电平信号Vgl的第五信号输入端，每一电平转换器分别连接第四信号输入端和第五信号输入端，每一电平转换器还与一个与门连接，N个输出缓冲器分别与N个电平转换器一一对应连接；
电平转换器，用于将与门输出的第一行扫描信号转换为行输出高电平信号和行输出低电平信号；
输出缓冲器，用于对电平转换器输出的电平信号进行功率放大。
本实施例中，电平转换器依次连接，并将第一行扫描信号中的0V低电平和3.3V分别转换为约-8V的低电平信号Vgl以及约30V的高电平信号Vgh，实现电平转换的功能，同时，输出缓冲器用于通过模拟缓冲放大器增加第一行扫描信号的驱动能力。
如图8所示，本申请还提出一种驱动装置2，该驱动装置2包括时序控制器300、源极驱动电路200和栅极驱动电路100，该栅极驱动电路100的具体结构参照上述实施例，由于本驱动装置2采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有有益效果，在此不再一一赘述。其中，时序控制器300分别与源极驱动电路200和栅极驱动电路100连接，源极驱动电路200与显示面板1的多条数据线连接，栅极驱动电路100与显示面板1的多条栅极线连接。
本实施例中，时序控制器300把从外部接收的数据信号、控制信号以及时钟信号转换成适合于栅极驱动电路100和源极驱动电路200的数据信号、控制信号、时钟信号，实现显示面板1的图像显示。
本申请还提出一种显示装置，该显示装置包括显示面板1和驱动装置2，该驱动装置2的具体结构参照上述实施例，由于本显示装置采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有有益效果，在此不再一一赘述。
以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (16)

  1. 一种栅极驱动电路，其中，应用于显示面板，包括：
    m个开关组，每一所述开关组包括n个第一开关单元，每个所述第一开关单元的输出端用于与所述显示面板的一条栅极线对应连接，每一所述开关组的n个第一开关单元的受控端共接构成一个第一受控节点，每一所述m个开关组中的第i个第一开关单元的输入端共接构成第i个输入节点，其中，m和n为正整数，i=1,2,…,n；
    n个第一移位寄存器，所述n个第一移位寄存器依次连接并分别与n个所述输入节点一一连接，所述n个第一移位寄存器用于根据第一起始信号和第一时钟脉冲信号依次输出第一行扫描信号至每个所述输入节点并循环；
    m个第二移位寄存器，所述m个第二移位寄存器依次连接并分别与m个所述受控节点一一连接，所述m个第二移位寄存器根据第二起始信号和第二时钟脉冲信号依次输出第二行扫描信号至每个所述第一受控节点，以依次触发与每个所述第一受控节点连接的n个第一开关单元开启，使所述第一行扫描信号依次反馈至每条所述栅极线。
  2. 如权利要求1所述的栅极驱动电路，其中，所述第一开关单元为电子开关管。
  3. 如权利要求1所述的栅极驱动电路，其中，所述第一时钟脉冲信号与所述第二时钟脉冲信号的占空比比值为n：1，n大于1。
  4. 如权利要求1所述的栅极驱动电路，其中，所述栅极驱动电路还包括n/2个第二开关单元，所述第一移位寄存器两两分为一组，每一所述第二开关单元并联在每组内的两个第一移位寄存器的输出端之间，各所述第二开关单元的受控端并联构成第二受控节点，各所述第二开关单元用于接收控制信号同时导通或者关断。
  5. 如权利要求1所述的栅极驱动电路，其中，所述栅极驱动电路还包括预充电电路，所述预充电电路包括m-1个第一单向导通单元和m-1个第二单向导通单元；
    所述m-1个第一单向导通单元分别一一并接在所述m个第二移位寄存器的相邻的信号输出端之间，每一所述第二单向单通单元分别一一单向连接在第二个移位寄存器至第m个移位寄存器的输出端上，每一所述第一单向导通单元的正输入端与前一个第二移位寄存器的输出端或者一个第二单向导通单元的正输出端连接，每一所述第一单向导通单元的负输出端与另一个第二单向导通单元的负输出端连接；
    每一所述第一单向导通单元，用于在前一个第二移位寄存器输出第二行扫描信号时将前一个第二移位寄存器输出的第二行扫描信号同步输出至下一个第二移位寄存器所连接的受控节点，以使所述显示面板中相邻n行中的两个薄膜晶体管开启进行数据信号的充电和预充电。
  6. 如权利要求5所述的栅极驱动电路，其中，所述第二单向导通单元用于隔离所述第二行扫描信号回馈至所述第二移位寄存器。
  7. 如权利要求5所述的栅极驱动电路，其中，所述第一单向导通单元和第二单向导通单元均为二极管。
  8. 如权利要求5所述的栅极驱动电路，其中，所述预充电电路还包括m-1个第三开关单元，每一所述第三开关单元连接在每一所述第一单向导通单元的前级，各所述第三开关单元的受控端共接构成第三受控节点；
    各所述第三开关单元用于接收控制信号同时导通或者关断。
  9. 如权利要求1所述的栅极驱动电路，其中，所述第一移位寄存器和所述第二移位寄存器均为双向移位寄存器。
  10. 如权利要求9所述的栅极驱动电路，其中，所述栅极驱动电路还包括用于输入第一行扫描方向控制信号的第一信号输入端，所述第一信号输入端分别与n个第一移位寄存器的信号端连接；
    所述n个第一移位寄存器，还用于根据所述第一行扫描方向控制信号以第一方向依次输出所述第一行扫描信号或者以第二方向依次输出所述第一行扫描信号，所述第一方向和所述第二方向反向。
  11. 如权利要求9所述的栅极驱动电路，其中，所述栅极驱动电路还包括用于输入第二行扫描方向控制信号的第二信号输入端，所述第二信号输入端分别与m个第二移位寄存器的信号端连接；
    所述m个第二移位寄存器，还用于根据所述第二行扫描方向控制信号以第三方向依次输出所述第二行扫描信号或者以第四方向依次输出所述第二行扫描信号，所述第三方向和所述第四方向反向。
  12. 如权利要求1所述的栅极驱动电路，其中，所述栅极驱动电路还包括N个与门和用于输入使能信号的第三信号输入端，所述第三信号输入端分别与每一所述与门的第一信号输入端连接，每一所述与门的第二信号输入端与一个所述第一开关单元的输出端连接，其中，N=m×n；
    每一所述与门，用于在所述使能信号为高电平时输出所述第一行扫描信号，以及在所述使能信号为低电平时截止时输出所述第一行扫描信号。
  13. 如权利要求12所述的栅极驱动电路，其中，所述栅极驱动电路还包括N个电平转换器，每一所述电平转换器与一个所述与门连接；
    所述电平转换器，用于将所述与门输出的第一行扫描信号转换为行输出高电平信号和行输出低电平信号。
  14. 如权利要求13所述的栅极驱动电路，其中，所述栅极驱动电路还包括N个输出缓冲器，N个所述输出缓冲器分别与N个所述电平转换器一一对应连接；
    所述输出缓冲器，用于对所述电平转换器输出的电平信号进行功率放大。
  15. 一种驱动装置，其中，包括时序控制器、源极驱动电路和如权利要求1所述的栅极驱动电路；
    所述时序控制器分别与所述源极驱动电路和所述栅极驱动电路连接，所述源极驱动电路与所述显示面板的多条数据线连接，所述栅极驱动电路与所述显示面板的多条栅极线连接。
  16. 一种显示装置，其中，包括显示面板和如权利要求15所述的驱动装置。
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KR102464249B1 (ko) * 2018-06-27 2022-11-04 엘지디스플레이 주식회사 게이트 구동회로, 이를 포함한 영상 표시장치 및 그 구동방법
CN113035111B (zh) * 2021-03-25 2022-01-14 惠科股份有限公司 栅极驱动电路、驱动装置和显示装置

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