WO2017193627A1 - 移位寄存器、栅极驱动电路和显示装置 - Google Patents

移位寄存器、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2017193627A1
WO2017193627A1 PCT/CN2017/071257 CN2017071257W WO2017193627A1 WO 2017193627 A1 WO2017193627 A1 WO 2017193627A1 CN 2017071257 W CN2017071257 W CN 2017071257W WO 2017193627 A1 WO2017193627 A1 WO 2017193627A1
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Prior art keywords
pull
shift register
module
input
output
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PCT/CN2017/071257
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English (en)
French (fr)
Inventor
王飞
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/541,426 priority Critical patent/US10262566B2/en
Publication of WO2017193627A1 publication Critical patent/WO2017193627A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register, a gate driving circuit, and a display device.
  • An existing gate drive circuit includes a shift register composed of cascaded shift register units.
  • the reset of the shift register unit of the previous stage is normally provided by the output signal enable of the shift register unit of the next stage. Therefore, the signal output terminal of each stage shift register unit bears the load of the reset signal terminal of the shift register unit of the previous stage, resulting in a high output load and a deteriorated output signal waveform (for example, a less steep falling edge).
  • Embodiments of the present disclosure provide a shift register, a gate drive circuit, and a display device to alleviate, alleviate or eliminate at least one of the above problems.
  • a shift register comprising: at least one shift register unit group, each of the shift register unit groups including a plurality of shift register units cascaded with each other, the plurality Each of the stage shift register units includes a pull-up node and a pull-up node reset terminal.
  • a pull-up node of the n+kth shift register unit of each of the shift register unit groups is connected to a pull-up node reset terminal of the n-th shift register unit of the shift register unit group to provide an allowable a pull-up node reset signal of a potential reset at a pull-up node of the n-th stage shift register unit, the reset of the potential at the pull-up node causing an output at a signal output end of the n-th stage shift register unit Signal reset, where n is an integer greater than or equal to 1, and k is an integer greater than one.
  • each of the multi-stage shift register units further includes a signal input end, a signal output end, a first clock signal end, a second clock signal end, an input module, a pull-up module, a pull-down module, Pull-down control module, pull-up node reset module and reference level input.
  • the input module has an input coupled to the signal input and an output coupled to the pull-up node, the input module configured to cause the input to be received in response to an input of the input module The input and output of the module are turned on.
  • the pull-up module has an input connected to the first clock signal end, an output connected to the signal output end, and a control end connected to the pull-up node, the pull-up module being configured to be responsive to The control terminal of the pull-up module receives a valid signal to turn on the input end and the output end of the pull-up module.
  • the pull-down module has an input connected to the reference level input, an output connected to the signal output, and a control connected to the pull-down node, the pull-down module being configured to be responsive to the pull-down The control terminal of the module receives a valid signal to turn on the input terminal and the output terminal of the pull-down module.
  • the pull-down control module has an input connected to the second clock signal end, an output connected to the pull-down node, and a control end connected to the pull-up node, the pull-down control module being configured to respond
  • the control terminal of the pull-down control module receives a valid signal to turn on the input terminal and the output terminal of the pull-down control module.
  • the pull-up node reset module has an input connected to the reference voltage input terminal, an output terminal connected to the pull-up node, and a control terminal connected to the reset terminal of the pull-up node.
  • the input module includes a first input transistor and a second input transistor.
  • the first input transistor has a first pole, a gate connected to the first pole and formed as an input of the input module, and a second pole formed as an output of the input module.
  • the second input transistor has a first pole connected to the first pole of the first input transistor, a gate connected to the second clock signal terminal, and a second pole connected to the first input transistor The second pole.
  • the pull-up module includes: a pull-up transistor having a gate formed as a control end of the pull-up module, a first pole formed as an input end of the pull-up module, and formed as described a second pole of the output of the pull-up module; and a storage capacitor having a first end coupled to the pull-up node and a second end coupled to the signal output.
  • the pull-down module includes a pull-down transistor having a gate formed as a control terminal of the pull-down module, a first pole formed as an output of the pull-down module, and an input formed as the pull-down module The second pole of the end.
  • the pull-down control module includes a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, a fourth pull-down control transistor, and a fifth pull-down control transistor.
  • the first pull-down control transistor has a gate and a first pole and a second pole connected in common with the second clock signal terminal.
  • the second pull-down control transistor has a gate connected to the second pole of the first pull-down control transistor, a first pole connected to the second clock signal end, and a second connected to the pull-down node pole.
  • Place The third pull-down control transistor has a gate connected to the pull-up node, a first pole connected to the second pole of the first pull-down control transistor, and a second connected to the reference level input terminal pole.
  • the fourth pull-down control transistor has a gate connected to the pull-up node, a first pole connected to the pull-down node, and a second pole connected to the reference level input.
  • the fifth pull-down control transistor has a gate connected to the second clock signal terminal, a first pole connected to the signal output terminal, and a second pole connected to the reference level input terminal.
  • the pull-up node reset module includes: a first reset transistor having a gate connected to the reset terminal of the pull-up node, a first pole connected to the pull-up node, and a second pole connected to the level input terminal; and a second reset transistor having a gate connected to the pull-down node, a first pole connected to the pull-up node, and a reference level input terminal The second pole.
  • each of the multi-stage shift register units further includes an output reset module having an input coupled to the reference level input, an output coupled to the signal output, And the console.
  • a control terminal of the output reset module is coupled to the pull-up node reset terminal of the shift register unit.
  • the signal output of the n+1th stage shift register unit of each of the shift register unit groups is connected to the output reset of the nth stage shift register unit of the shift register unit group.
  • the control side of the module is connected to the output reset of the nth stage shift register unit of the shift register unit group.
  • the output reset module includes an output reset transistor having a gate formed as a control terminal of the output reset module, a first pole formed as an output of the output reset module, and formed as described The second pole of the input of the reset module is output.
  • the shift register includes two of the shift register unit groups.
  • each of the shift register unit groups further includes a k-stage dummy shift register unit for providing a corresponding pull-up for the last k-level shift register unit in the shift register unit group. Node reset signal.
  • a gate driving circuit including the above shift register is provided.
  • a display device including the above-described gate driving circuit is provided.
  • the shift register includes two of the shift register unit groups, wherein one shift register unit group is used to provide scan signals for odd-numbered rows of gate lines of the display device, and another shift The bit register unit group is for providing a scan signal for the gate lines of the even rows of the display device.
  • the reset of the nth stage shift register unit may be enabled by a signal from the pull-up node of the n+kth stage shift register unit, without necessarily requiring the shift register unit from the next stage output signal. Therefore, in the application of the gate driver, the output signals of the shift register units of each stage can be used to drive the corresponding gate lines to a greater extent, thereby improving the driving capability of the gate driver. This, in turn, can increase the charging efficiency of the pixel unit, and thus improve the display quality of the display device.
  • FIG. 1 is a schematic diagram of a shift register in accordance with an embodiment of the present disclosure
  • FIG. 2 is a timing chart of the shift register shown in FIG. 1, in which the first clock signal, the output signal of the nth stage shift register unit, the output signal of the n+1th stage shift register unit, and a potential at a pull-up node of the n+2th shift register unit;
  • FIG. 3 is a block diagram of a shift register unit in a shift register in accordance with an embodiment of the present disclosure
  • FIG. 4 is an exemplary circuit diagram of a shift register unit as shown in FIG. 3;
  • FIG. 5 is a schematic diagram of a shift register including the shift register unit illustrated in FIG. 4, according to an embodiment of the present disclosure
  • Figure 6 is another exemplary circuit diagram of the shift register unit shown in Figure 3;
  • FIG. 7 is a schematic diagram of a shift register including the shift register unit illustrated in FIG. 6 according to an embodiment of the present disclosure.
  • FIG. 8 is a block diagram of a display device in accordance with an embodiment of the present disclosure.
  • a valid signal refers to a signal that enables a component that receives the valid signal to be turned on
  • an invalid signal refers to a signal that enables a component that receives the signal to be turned off.
  • FIG. 1 is a schematic diagram of a shift register in accordance with an embodiment of the present disclosure.
  • the shift register includes a shift register unit group including a multi-stage shift register unit.
  • the three-stage shift register unit is shown: an nth stage shift register unit 1011, an n+1th stage shift register unit 1012, and an n+2th stage shift register unit 1013.
  • Each shift register unit is cascaded with each other.
  • the signal output terminal OUTPUT of the nth stage shift register unit is connected to the signal input terminal INPUT of the n+1th stage shift register unit for registering the n+1th shift register
  • the unit provides an input signal.
  • the pull-up node PU of the n+kth-stage shift register unit is connected to the pull-up node reset terminal RESET_PU of the nth-stage shift register unit to provide a pull-up node that allows the n-th stage shift register unit
  • n is an integer greater than or equal to 1
  • the reset of the potential at the pull-up node of each shift register unit may cause the output signal at the signal output terminal OUTPUT of the shift register unit to be reset, and thus the output reset terminal RESET_OUTPUT is not necessary.
  • an output signal of each shift register unit serves as a scan signal applied to a gate line of the display device.
  • the reset of the nth stage shift register unit may be enabled by a signal from the pull-up node of the n+kth stage shift register unit, without necessarily requiring the shift register unit from the next stage output signal. Therefore, in the application of the gate driver, the output signals of the shift register units of each stage can be used to drive the corresponding gate lines to a greater extent, thereby improving the driving capability of the gate driver. This, in turn, can increase the charging efficiency of the pixel unit, thereby improving the display quality of the display device.
  • FIG. 2 is a timing chart of the shift register shown in FIG. 1, in which the first clock signal CLK, the output signal OUTPUT(n) of the nth stage shift register unit, and the n+1th shift register are shown.
  • the output signal of the unit OUTPUT(n+1) and the n+2th shift register unit Pull the potential PU(n+2) at the node. As shown in FIG.
  • the signal output terminal OUTPUT(n) of the nth stage shift register unit outputs an invalid signal
  • the signal output terminal OUTPUT(n+1) of the n+1th shift register unit outputs a valid signal
  • the nth The potential PU(n+2) at the pull-up node of the +2 stage shift register unit is a valid signal.
  • the effective PU(n+2) is supplied to the pull-up node reset terminal RESET_PU of the n-th stage shift register unit to allow the potential at the pull-up node PU of the n-th stage shift register unit to be reset, and further The output signal at the signal output terminal OUTPUT(n) of the nth stage shift register unit is reset.
  • the shift register is illustrated as including one shift register unit group in FIG. 1, the present disclosure is not limited thereto.
  • the shift register may include two or more shift register unit groups.
  • the shift register units 1011, 1012, and 1013 belong to the same shift register unit group, and the shift register units 1021, 1022, and 1023 belong to the same shift register unit group.
  • FIG. 3 is a block diagram of a shift register unit in a shift register according to an embodiment of the present disclosure.
  • the shift register unit includes a signal input terminal INPUT, a signal output terminal OUTPUT, a first clock signal terminal CLK, a second clock signal terminal CLKB, an input module 100, a pull-up module 200, and a pull-down module 300.
  • the signal provided by the reference level input terminal Vss is an invalid signal.
  • the phase of the first clock signal input through the first clock signal terminal CLK is opposite to the phase of the second clock signal input through the second clock signal terminal CLKB.
  • the signal output through the first clock signal terminal CLK is a valid signal.
  • the output reset terminal RESET_OUTPUT (and potentially the output reset module 600) is not required.
  • the input of the input module 100 is connected to the signal input INPUT, and the output of the input module 100 is connected to the pull-up node PU.
  • the input module 100 is capable of inducing its input and output when it receives a valid signal at its input. In the input phase of the output shift register unit, a valid signal is supplied to the input terminal of the input module 100 through the signal input terminal INPUT, and the input terminal and the output terminal of the input module 100 are turned on. Therefore, the pull-up node is charged by a valid signal input by the signal input terminal INPUT.
  • the input end of the pull-up module 200 is connected to the first clock signal terminal CLK, the output end of the pull-up module 200 is connected to the signal output terminal OUTPUT, and the control end of the pull-up module 200 is connected to the pull-up node.
  • the control terminal of the pull-up module 200 receives the valid signal
  • the input terminal of the pull-up module 200 is turned on.
  • the signal output by the pull-up module 200 is the first clock signal input through the first clock signal terminal CLK. That is, when the first clock signal is a valid signal, the valid signal can be output through the signal output terminal OUTPUT.
  • the input end of the pull-down module 300 is connected to the reference level input terminal Vss, the output end of the pull-down module 300 is connected to the signal output terminal OUTPUT, and the control end of the pull-down module 300 is connected to the pull-down node PD.
  • the control terminal of the pull-down module 300 receives the valid signal, the input terminal of the pull-down module 300 is turned on.
  • a valid signal can be provided to the pull-down node PD to turn the input and output terminals of the pull-down module 300 into conduction.
  • the invalid signal input to the reference level input terminal Vss is output to the signal output terminal OUTPUT, thereby resetting the output signal.
  • the input end of the pull-down control module 400 is connected to the second clock signal terminal CLKB, the output end of the pull-down control module 400 is connected to the pull-down node, and the control end of the pull-down control module 400 is connected to the pull-up node.
  • the pull-down control module 400 can turn on the input terminal and the output terminal when the control terminal of the pull-down control module 400 receives the high-level signal, thereby providing the second clock signal input through the second clock signal terminal CLKB to the pull-down node. .
  • the input end of the pull-up node reset module 500 is connected to the reference voltage input terminal Vss, the output end of the pull-up node reset module 500 is connected to the pull-up node, and the control end of the pull-up node reset module 500 and the pull-up node reset end RESET_PU is connected.
  • the pull-up node reset terminal RESET_PU of the nth-stage shift register unit is connected to the pull-up node PU of the n+k-th shift register unit. Therefore, when the pull-up node PU of the n+kth shift register unit outputs a valid signal, the input terminal of the pull-up node reset module 500 of the n-th shift register unit is turned on. At this time, the invalid signal input from the reference voltage input terminal Vss is supplied to the pull-up node, and the pull-up node is reset.
  • FIG. 4 and 6 are exemplary circuit diagrams of the shift register unit shown in FIG.
  • the input module 100 includes a first input transistor M1 and a second input transistor M7.
  • the gate of the first input transistor M1 is connected to the first pole and formed as the input module 100 The input is connected to the signal input INPUT.
  • the second pole of the first input transistor M1 is coupled to the second pole of the second input transistor M2 and formed as an input of the input module 100 for connection with the pull-up node.
  • the gate of the second input transistor M7 is connected to the second clock signal terminal CLKB, and the first electrode of the second input transistor CLKB is connected to the first electrode of the first input transistor M1.
  • the signal input terminal INPTUT inputs a valid signal
  • the signal input by the second clock signal terminal CLKB is also a valid signal.
  • the first input transistor M1 and the second input transistor M7 are both turned on, thereby charging the node PU through the input module 100.
  • the pull-up module 200 includes a pull-up transistor M3 and a storage capacitor C1.
  • the gate of the pull-up transistor M3 is formed as a control terminal of the pull-up module 200 to be connected to the pull-up node.
  • the first pole of the pull-up transistor M3 is formed as an input terminal of the pull-up module 200 to be connected to the first clock signal terminal CLK.
  • the second pole of the pull-up transistor M3 is formed as an output terminal of the pull-up module 200 to be connected to the signal output terminal OUTPUT.
  • a first end of the storage capacitor C1 is connected to the pull-up node, and a second end of the storage capacitor C1 is connected to the signal output terminal OUTPUT.
  • the storage capacitor C1 can maintain the pull-up node PU at an effective potential.
  • the pull-up node reset terminal RESET_PU is supplied with a valid signal, the potential at the pull-up node PU is reset.
  • the output signal at the signal output terminal OUTPUT will also be reset. That is, the reset of the potential at the pull-up node PU can cause the output signal at the signal output terminal OUTPUT to be reset.
  • the pull-down module 300 includes a pull-down transistor M11.
  • the gate of the pull-down transistor M11 is formed as a control terminal of the pull-down module 300 to be connected to the pull-down node PD.
  • the first pole of the pull-down transistor M11 is formed as an output terminal of the pull-down module 300 to be connected to the signal output terminal OUTPUT.
  • the second pole of the pull-down transistor 300 is formed as an input of the pull-down module 300 to be coupled to the reference level input terminal Vss.
  • the pull-down transistor M11 When the gate of the pull-down transistor M11 receives the valid signal, the pull-down transistor M11 is turned on, thereby transmitting the invalid signal input from the reference level input terminal Vss to the signal output terminal OUTPUT to perform the signal output terminal OUTPUT in the output reset phase. Reset.
  • the pull-down control module 400 includes a first pull-down control transistor M9, a second pull-down control transistor M5, a third pull-down control transistor M8, a fourth pull-down control transistor M6, and a fifth pull-down control transistor M12.
  • the gate and the first pole of the first pull-down control transistor M9 are connected to the second clock signal terminal CLKB, and the second pole of the first pull-down control transistor M9 is connected to the gate of the second pull-down control transistor M5.
  • Second pull-down control transistor M5 The pole is connected to the pull-down node PD.
  • the gate of the third pull-down control transistor M8 is connected to the pull-up node, the first pole of the third pull-down control transistor M8 is connected to the second pole of the first pull-down control transistor M9, and the third pull-down control transistor M8 The two poles are connected to the reference level input terminal Vss.
  • a gate of the fourth pull-down control transistor M6 is connected to the pull-up node, a first pole of the fourth pull-down control transistor M6 is connected to the pull-down node, and a second pole of the fourth pull-down control transistor M6 is input with a reference level The ends Vss are connected.
  • the gate of the fifth pull-down control transistor M12 is connected to the second clock signal terminal CLKB, the first pole of the fifth pull-down control transistor M12 is connected to the signal output terminal OUTPUT, and the second pole of the fifth pull-down control transistor M12 is connected to the reference level.
  • the input terminals Vss are connected.
  • the pull-up node reset module 500 includes a first reset transistor M2 and a second reset transistor M10.
  • the gate of the first reset transistor M2 is connected to the pull-up node reset terminal RESET_PU, the second pole of the first reset transistor M2 is connected to the reference level input terminal Vss, and the first pole of the first reset transistor M2 is connected to the pull-up Nodes are connected.
  • the gate of the second reset transistor M10 is connected to the pull-down node PD, the first pole of the second reset transistor M10 is connected to the pull-up node, and the second pole of the second reset transistor M10 is connected to the reference level input terminal Vss Connected.
  • the shift register unit may be provided with an output reset module 600 to ensure that the output signal of the signal output terminal OUTPUT is pulled low during the output reset phase.
  • the input terminal of the output reset module 600 is connected to the reference level input terminal Vss, and the output terminal of the output reset module 600 is connected to the signal output terminal OUTPUT.
  • the output reset module 600 further includes a control terminal, that is, an output reset terminal RESET_OUTPUT.
  • the output reset module 600 can turn on the input terminal and the output terminal of the output reset module 600 when the output reset terminal RESET_OUTPUT receives the valid signal.
  • the output reset module 600 includes an output reset transistor M4.
  • the gate of the output reset transistor M4 is formed as a control terminal of the output reset module 600, the first pole of the output reset transistor M4 is formed as an output terminal of the output reset module 600, and the second pole of the output reset transistor M4 is formed as an output reset module.
  • the input of the 600 is formed as a control terminal of the output reset module 600.
  • the output reset terminal RESET_OUTPUT is a terminal independent of the pull-up node reset terminal RESET_PU.
  • the shift register as shown in FIGS. 1 and 5 includes a shift register unit in which the shift register shown in FIG. 1 includes a shift register unit group, and the shift register shown in FIG. 5 includes Two shift register unit groups. As shown, each shift register unit group The signal output terminal OUTPUT of the n+1th stage shift register unit is connected to the output reset terminal RESET_OUTPUT of the nth stage shift register unit of the shift register unit group.
  • the output reset terminal RESET_OUTPUT is connected to the pull-up node reset terminal RESET_PU.
  • the shift register as shown in FIG. 7 includes shift register units in which the pull-up node reset terminal RESET_PU and the output reset terminal RESET_OUT of each shift register unit are combined into one terminal.
  • the shift register includes two shift register unit groups. As shown, the pull-up node PU of the n+2th stage shift register unit of each shift register unit group is connected to the pull-up node reset terminal RESET_PU of the n-th stage shift register unit of the shift register unit group.
  • the pull-up node PU of the n+2th stage shift register unit of each shift register unit group provides a control signal for the control terminal RESET_OUTPUT of the output reset module 600 of the shift register unit group n-th stage shift register unit.
  • each shift register unit group may further include a k-level additional dummy shift register unit.
  • the k-stage dummy shift register units respectively provide pull-up node reset signals for the last k-stage shift register unit in the shift register unit group. It will be understood that the "dumb shift register unit" herein is only used to provide a reset signal and is not used to provide a scan signal for the gate line.
  • FIG. 8 is a block diagram of a display device 800 in accordance with an embodiment of the present disclosure.
  • the display device 800 includes a display panel 10, a timing controller 20, a gate driver 30, and a data driver 40.
  • the display panel 10 is connected to a plurality of gate lines GL and a plurality of data lines DL.
  • the display panel 10 displays an image having a plurality of gradations based on the output image data RGBD'.
  • the gate line GL may extend in the first direction D1
  • the data line DL may extend in the second direction D2 crossing (eg, substantially perpendicular) to the first direction D1.
  • the display panel 10 may include a plurality of pixels (not shown) arranged in a matrix form. Each of the pixels may be electrically connected to a corresponding one of the gate lines GL and one corresponding one of the data lines DL.
  • the timing controller 20 controls the operations of the display panel 10, the gate driver 30, and the data driver 40.
  • the timing controller 20 receives input image data RGBD and an input control signal CONT from an external device (for example, a host).
  • the input image data RGBD may include a plurality of input pixel data for a plurality of pixels. Each input pixel data can be included in a plurality of pixels Corresponding to one red gradation data R, green gradation data G, and blue gradation data B.
  • the input control signal CONT may include a main clock signal, a data enable signal, a vertical sync signal, a horizontal sync signal, and the like.
  • the timing controller 20 generates output image data RGBD', a first control signal CONT1, and a second control signal CONT2 based on the input image data RGBD and the input control signal CONT.
  • the timing controller 20 can generate output image data RGBD' based on the input image data RGBD.
  • the output image data RGBD' can be supplied to the data driver 40.
  • the output image data RGBD' may be substantially the same image data as the input image data RGBD.
  • the output image data RGBD' may be compensated image data generated by compensating the input image data RGBD.
  • the output image data RGBD' may include a plurality of output pixel data for a plurality of pixels.
  • the timing controller 20 may generate the first control signal CONT1 based on the input control signal CONT.
  • the first control signal CONT1 may be supplied to the gate driver 30, and the driving timing of the gate driver 30 may be controlled based on the first control signal CONT1.
  • the first control signal CONT1 may include a vertical enable signal, a gate clock signal, and the like.
  • the timing controller 20 may generate the second control signal CONT2 based on the input control signal CONT.
  • the second control signal CONT2 may be supplied to the data driver 40, and the driving timing of the data driver 40 may be controlled based on the second control signal CONT2.
  • the second control signal CONT2 may include a horizontal enable signal, a data clock signal, a data load signal, a polarity control signal, and the like.
  • the gate driver 30 receives the first control signal CONT1 from the timing controller 20.
  • the gate driver 30 generates a plurality of gate signals for driving the gate lines GL based on the first control signal CONT1.
  • the gate driver 30 may sequentially apply a plurality of gate signals to the gate lines GL.
  • the gate driver 30 can include a shift register as described in the above embodiments.
  • the shift register includes two shift register cell groups, one shift register cell group can be used to provide scan signals for odd rows of gate lines, and another shift register cell group can be used for even numbers.
  • the gate lines of the rows provide a scan signal.
  • the data driver 40 receives the second control signal CONT2 and the output image data RGBD' from the timing controller 20.
  • the data driver 40 generates a plurality of data voltages (e.g., analog data voltages) based on the second control signal CONT2 and the output image data RGBD' (e.g., digital image data).
  • the data driver 40 can apply a plurality of data voltages to the data lines DL.
  • gate driver 30 and/or data driver 40 may be The arrangement (eg, direct mounting) is on the display panel 10, or may be connected to the display panel 10, for example, in a Tape Carrier Package (TCP) type. In some embodiments, gate driver 30 and/or data driver 40 can be integrated into display panel 10.
  • TCP Tape Carrier Package
  • the display device 800 can be an electronic device such as a television, a cell phone, a tablet, a notebook computer, a desktop computer, a navigator, and the like.

Abstract

一种移位寄存器，包括至少一个移位寄存单元组，每个移位寄存单元组包括多级彼此级联的移位寄存单元（1011、1012、1013、1021、1022、1023），多级移位寄存单元（1011、1012、1013、1021、1022、1023）中的每个包括上拉节点（PU）和上拉节点复位端（RESET_PU）。每个移位寄存单元组的第n+k级移位寄存单元（1012、1013、1022、1023）的上拉节点（PU）连接至该移位寄存单元组的第n级移位寄存单元（1011、1021）的上拉节点复位端（RESET_PU）。

Description

移位寄存器、栅极驱动电路和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器、栅极驱动电路和显示装置。
背景技术
现有的栅极驱动电路包括由级联的移位寄存单元组成的移位寄存器。在这样的移位寄存器中，上一级移位寄存单元的复位通常是由下一级移位寄存单元的输出信号使能的提供。因此，每一级移位寄存单元的信号输出端都要承担上一级移位寄存单元的复位信号端的负载，从而导致高输出负载和恶化的输出信号波形(例如，不太陡峭的下降沿)。
发明内容
本公开的实施例提供一种移位寄存器、栅极驱动电路、显示装置，以缓解、减轻或消除上述问题中的至少一个。
根据本公开的第一个方面，提供一种移位寄存器，包括：至少一个移位寄存单元组，每个所述移位寄存单元组包括多级彼此级联的移位寄存单元，所述多级移位寄存单元中的每个包括上拉节点和上拉节点复位端。每个所述移位寄存单元组的第n+k级移位寄存单元的上拉节点连接至该移位寄存单元组的第n级移位寄存单元的上拉节点复位端，以提供允许所述第n级移位寄存单元的上拉节点处的电位复位的上拉节点复位信号，所述上拉节点处的电位的复位使得所述第n级移位寄存单元的信号输出端处的输出信号复位，其中n为大于或等于1的整数，并且k为大于1的整数。
在一些实施例中，所述多级移位寄存单元中的每个还包括信号输入端、信号输出端、第一时钟信号端、第二时钟信号端、输入模块、上拉模块、下拉模块、下拉控制模块、上拉节点复位模块和参考电平输入端。所述输入模块具有与所述信号输入端相连的输入端和与所述上拉节点相连的输出端，所述输入模块被配置成响应于该输入模块的输入端接收到有效信号而使该输入模块的输入端和输出端导通。所述 上拉模块具有与所述第一时钟信号端相连的输入端、与所述信号输出端相连的输出端、以及与所述上拉节点相连的控制端，所述上拉模块被配置成响应于所述上拉模块的控制端接收到有效信号而使所述上拉模块的输入端与输出端导通。所述下拉模块具有与所述参考电平输入端相连的输入端、与所述信号输出端相连的输出端、以及与下拉节点相连的控制端，所述下拉模块被配置成响应于所述下拉模块的控制端接收到有效信号而使所述下拉模块的输入端与输出端导通。所述下拉控制模块具有与所述第二时钟信号端相连的输入端、与所述下拉节点相连的输出端、以及与所述上拉节点相连的控制端，所述下拉控制模块被配置成响应于该下拉控制模块的控制端接收到有效信号而使该下拉控制模块的输入端和输出端导通。所述上拉节点复位模块具有与所述参考电压输入端相连的输入端、与所述上拉节点相连的输出端、以及与所述上拉节点复位端相连的控制端。
在一些实施例中，所述输入模块包括第一输入晶体管和第二输入晶体管。所述第一输入晶体管具有第一极、与所述第一极相连并形成为所述输入模块的输入端的栅极、以及形成为所述输入模块的输出端的第二极。所述第二输入晶体管具有与所述第一输入晶体管的第一极相连的第一极、与所述第二时钟信号端相连的栅极、以及与所述第一输入晶体管的第二极相连的第二极。
在一些实施例中，所述上拉模块包括：上拉晶体管，具有形成为所述上拉模块的控制端的栅极、形成为所述上拉模块的输入端的第一极、以及形成为所述上拉模块的输出端的第二极；以及存储电容，具有与所述上拉节点相连的第一端以及与所述信号输出端相连的第二端。
在一些实施例中，所述下拉模块包括下拉晶体管，其具有形成为所述下拉模块的控制端的栅极、形成为所述下拉模块的输出端的第一极、以及形成为所述下拉模块的输入端的第二极。
在一些实施例中，所述下拉控制模块包括第一下拉控制晶体管、第二下拉控制晶体管、第三下拉控制晶体管、第四下拉控制晶体管和第五下拉控制晶体管。所述第一下拉控制晶体管具有与所述第二时钟信号端共同相连的栅极和第一极、以及第二极。所述第二下拉控制晶体管具有与所述第一下拉控制晶体管的第二极相连的栅极、与所述第二时钟信号端相连的第一极、以及与所述下拉节点相连的第二极。所 述第三下拉控制晶体管具有与所述上拉节点相连的栅极、与所述第一下拉控制晶体管的第二极相连的第一极、以及与所述参考电平输入端相连的第二极。所述第四下拉控制晶体管具有与所述上拉节点相连的栅极、与所述下拉节点相连的第一极、以及与所述参考电平输入端相连的第二极。所述第五下拉控制晶体管具有与所述第二时钟信号端相连的栅极、与所述信号输出端相连的第一极、以及与所述参考电平输入端相连的第二极。
在一些实施例中，所述上拉节点复位模块包括：第一复位晶体管，具有与所述上拉节点复位端相连的栅极、与所述上拉节点相连的第一极、以及与所述参考电平输入端相连的第二极；以及第二复位晶体管，具有与所述下拉节点相连的栅极、与所述上拉节点相连的第一极、以及与所述参考电平输入端相连的第二极。
在一些实施例中，所述多级移位寄存单元中的每个还包括输出复位模块，其具有与所述参考电平输入端相连的输入端、与所述信号输出端相连的输出端、以及控制端。
在一些实施例中，对于所述多级移位寄存单元中的每个，所述输出复位模块的控制端与该移位寄存单元的所述上拉节点复位端相连。
在一些实施例中，每个所述移位寄存单元组的第n+1级移位寄存单元的信号输出端连接至该移位寄存单元组的第n级移位寄存单元的所述输出复位模块的控制端。
在一些实施例中，所述输出复位模块包括输出复位晶体管，其具有形成为所述输出复位模块的控制端的栅极、形成为所述输出复位模块的输出端的第一极、以及形成为所述输出复位模块的输入端的第二极。
在一些实施例中，所述移位寄存器包括两个所述移位寄存单元组。
在一些实施例中，每个所述移位寄存单元组还包括k级哑移位寄存单元，以用于为该移位寄存单元组中最后k级所述移位寄存单元提供相应的上拉节点复位信号。
根据本公开的另一个方面，提供一种栅极驱动电路，包括上述移位寄存器。
根据本公开的还一个方面，提供一种显示装置，包括上述栅极驱动电路。
在一些实施例中，所述移位寄存器包括两个所述移位寄存单元组，其中一个移位寄存单元组用于为所述显示装置的奇数行的栅线提供扫描信号，并且另一个移位寄存单元组用于为所述显示装置的偶数行的栅线提供扫描信号。
根据本公开的实施例，第n级移位寄存单元的复位可以由来自第n+k级移位寄存单元的上拉节点的信号使能，而不一定要求来自下一级移位寄存单元的输出信号。因此，在栅极驱动器的应用中，各级移位寄存单元的输出信号可以在更大程度上用于驱动相应的栅线，从而提高栅极驱动器的驱动能力。这进而可以提高对像素单元的充电效率，并且因此提高显示装置的显示质量。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为根据本公开的实施例的移位寄存器的示意图；
图2为如图1中所示的移位寄存器的时序图，其中示出了第一时钟信号、第n级移位寄存单元的输出信号、第n+1级移位寄存单元的输出信号和第n+2级移位寄存单元的上拉节点处的电位；
图3为根据本公开的实施例的移位寄存器中的移位寄存单元的框图；
图4为如图3所示的移位寄存单元的示例性电路图；
图5为根据本公开的实施例的包括图4中所示的移位寄存单元的移位寄存器的示意图；
图6为如图3所示的移位寄存单元的另一示例性电路图；
图7为根据本公开的实施例的包括图6中所示的移位寄存单元的移位寄存器的示意图；并且
图8为根据本公开的实施例的显示装置的框图。
具体实施方式
以下结合附图对本公开的实施例进行详细说明。应当理解的是，此处所描述的实施例仅用于说明和解释本公开，并不用于限制本公开。
附图标记说明
1011、1012、1013、1021、1022、1023：移位寄存单元
100：输入模块            200：上拉模块
300：下拉模块            400：下拉控制模块
500：上拉节点复位模块    600：输出复位模块
在本文中，有效信号是指能够使接收到该有效信号的部件导通的信号，并且无效信号是指能够使接收到该信号的部件关闭的信号。
图1为根据本公开的实施例的移位寄存器的示意图。如图1所示，所述移位寄存器包括一个移位寄存单元组，其包括多级移位寄存单元。为了简单起见，仅示出了三级移位寄存单元：第n级移位寄存单元1011、第n+1级移位寄存单元1012和第n+2级移位寄存单元1013。
各移位寄存单元相互级联。在图1的示例中，第n级移位寄存单元的信号输出端OUTPUT连接至第n+1级移位寄存单元的信号输入端INPUT，以用于为所述第n+1级移位寄存单元提供输入信号。
特别地，第n+k级移位寄存单元的上拉节点PU连接至第n级移位寄存单元的上拉节点复位端RESET_PU，以提供允许所述第n级移位寄存单元的上拉节点PU处的电位复位的上拉节点复位信号。n为大于或等于1的整数，并且k为大于1的整数(在图1的示例中，k＝2)。如稍后将描述的，每个移位寄存单元的上拉节点处的电位的复位可以使得该移位寄存单元的信号输出端OUTPUT处的输出信号复位，并且因此输出复位端RESET_OUTPUT不是必须的。
当所述移位寄存器用作显示装置中的栅极驱动器时，各移位寄存单元的输出信号充当被施加到显示装置的栅线的扫描信号。根据本公开的实施例，第n级移位寄存单元的复位可以由来自第n+k级移位寄存单元的上拉节点的信号使能，而不一定要求来自下一级移位寄存单元的输出信号。因此，在栅极驱动器的应用的，各级移位寄存单元的输出信号可以在更大程度上用于驱动相应的栅线，从而提高栅极驱动器的驱动能力。这进而可以提高对像素单元的充电效率，从而提高显示装置的显示质量。
图2为如图1中所示的移位寄存器的时序图，其中示出了第一时钟信号CLK、第n级移位寄存单元的输出信号OUTPUT(n)、第n+1级移位寄存单元的输出信号OUTPUT(n+1)和第n+2级移位寄存单元的上 拉节点处的电位PU(n+2)。如图2所示，当第n级移位寄存单元的信号输出端OUTPUT(n)输出有效信号(例如，高电平)时，第n+1级移位寄存单元的信号输出端OUTPUT(n+1)输出无效信号(例如，低电平)，并且第n+2级移位寄存单元的上拉节点处的电位PU(n+2)为无效信号。在下一个阶段，第n级移位寄存单元的信号输出端OUTPUT(n)输出无效信号时，第n+1级移位寄存单元的信号输出端OUTPUT(n+1)输出有效信号，并且第n+2级移位寄存单元的上拉节点处的电位PU(n+2)为有效信号。此时，有效的PU(n+2)被提供给第n级移位寄存单元的上拉节点复位端RESET_PU，以允许第n级移位寄存单元的上拉节点PU处的电位复位，并进一步使得第n级移位寄存单元的信号输出端OUTPUT(n)处的输出信号复位。
虽然在图1中移位寄存器被示出为包括一个移位寄存单元组，但是本公开并不限于此。例如，所述移位寄存器可以包括两个或更多移位寄存单元组。在图5和图7的示例中，移位寄存单元1011、1012和1013属于同一个移位寄存单元组，并且移位寄存单元1021、1022和1023属于同一个移位寄存单元组。
图3为根据本公开的实施例的移位寄存器中的移位寄存单元的框图。如图3中所示，所述移位寄存单元包括信号输入端INPUT、信号输出端OUTPUT、第一时钟信号端CLK、第二时钟信号端CLKB、输入模块100、上拉模块200、下拉模块300、下拉控制模块400、上拉节点复位模块500和参考电平输入端Vss。参考电平输入端Vss提供的信号为无效信号。通过第一时钟信号端CLK输入的第一时钟信号的相位与通过第二时钟信号端CLKB输入的第二时钟信号的相位是相反的。并且，在其中信号输出端OUTPUT的输出信号为有效信号(在图2的示例中，高电平)的输出阶段中，通过第一时钟信号端CLK输出的信号为有效信号。如前所述，输出复位端RESET_OUTPUT(和潜在地输出复位模块600)不是必须的。
输入模块100的输入端与信号输入端INPUT相连，并且输入模块100的输出端与所述上拉节点PU相连。输入模块100能够在其输入端接收到有效信号时，将其输入端和输出端导通(in conduction)。在输出移位寄存单元的输入阶段，通过信号输入端INPUT向输入模块100的输入端提供有效信号，并且输入模块100的输入端和输出端导通。 因此，通过信号输入端INPUT输入的有效信号对所述上拉节点进行充电。
上拉模块200的输入端与第一时钟信号端CLK相连，上拉模块200的输出端与信号输出端OUTPUT相连，并且上拉模块200的控制端与所述上拉节点相连。当上拉模块200的控制端接收到有效信号时，上拉模块200的输入端与输出端导通。当上拉模块200的输入端和输出端导通时，上拉模块200输出的信号是通过第一时钟信号端CLK输入的第一时钟信号。也即，当第一时钟信号为有效信号时，可以通过信号输出端OUTPUT输出有效信号。
下拉模块300的输入端与参考电平输入端Vss相连，下拉模块300的输出端与信号输出端OUTPUT相连，并且下拉模块300的控制端与下拉节点PD相连。当下拉模块300的控制端接收到有效信号时，下拉模块300的输入端与输出端导通。在移位寄存单元的输出复位阶段，可以向下拉节点PD提供有效信号，以将下拉模块300的输入端与输出端导通。此时，参考电平输入端Vss输入的无效信号被输出至信号输出端OUTPUT，从而使输出信号复位。
下拉控制模块400的输入端与第二时钟信号端CLKB相连，下拉控制模块400的输出端与所述下拉节点相连，并且下拉控制模块400的控制端与所述上拉节点相连。下拉控制模块400能够在该下拉控制模块400的控制端接收到高电平信号时将其输入端和输出端导通，从而将通过第二时钟信号端CLKB输入的第二时钟信号提供给下拉节点。
上拉节点复位模块500的输入端与参考电压输入端Vss相连，上拉节点复位模块500的输出端与所述上拉节点相连，并且上拉节点复位模块500的控制端与上拉节点复位端RESET_PU相连。如上文所述，第n级移位寄存单元的上拉节点复位端RESET_PU和第n+k级移位寄存单元的上拉节点PU相连。因此，当第n+k级移位寄存单元的上拉节点PU输出有效信号时，第n级移位寄存单元的上拉节点复位模块500的输入端与输出端导通。此时，参考电压输入端Vss输入的无效信号被提供给上拉节点，对所述上拉节点进行复位。
图4和图6为如图3所示的移位寄存单元的示例性电路图。
如图所示，输入模块100包括第一输入晶体管M1和第二输入晶体管M7。第一输入晶体管M1的栅极和第一极相连，形成为输入模块100 的输入端，以与信号输入端INPUT相连。第一输入晶体管M1的第二极与第二输入晶体管M2的第二极相连，形成为输入模块100的输入端，以与所述上拉节点相连。第二输入晶体管M7的栅极与第二时钟信号端CLKB相连，并且第二输入晶体管CLKB的第一极与第一输入晶体管M1的第一极相连。
当信号输入端INPTUT输入有效信号时，第二时钟信号端CLKB输入的信号也是有效信号。此时，第一输入晶体管M1和第二输入晶体管M7均导通，从而通过输入模块100向上拉节点PU充电。
上拉模块200包括上拉晶体管M3和存储电容C1。上拉晶体管M3的栅极形成为上拉模块200的控制端，以与上拉节点相连。上拉晶体管M3的第一极形成为上拉模块200的输入端，以与第一时钟信号端CLK相连。上拉晶体管M3的第二极形成为上拉模块200的输出端，以与信号输出端OUTPUT相连。存储电容C1的第一端与所述上拉节点相连，并且存储电容C1的第二端与信号输出端OUTPUT相连。当信号输入端INPUT不再有信号输入时，存储电容C1能够将上拉节点PU保持在有效电位。当上拉节点复位端RESET_PU被提供有效信号时，上拉节点PU处的电位被复位。此时，由于存储电容C1的自举效应，信号输出端OUTPUT处的输出信号也将被复位。也即，上拉节点PU处的电位的复位可以使得信号输出端OUTPUT处的输出信号复位。
下拉模块300包括下拉晶体管M11。下拉晶体管M11的栅极形成为下拉模块300的控制端，以与下拉节点PD相连。下拉晶体管M11的第一极形成为下拉模块300的输出端，以与信号输出端OUTPUT相连。下拉晶体管300的第二极形成为下拉模块300的输入端，以与参考电平输入端Vss相连。
当下拉晶体管M11的栅极接收到有效信号时，该下拉晶体管M11导通，从而将参考电平输入端Vss输入的无效信号输送至信号输出端OUTPUT，以在输出复位阶段对信号输出端OUTPUT进行复位。
下拉控制模块400包括第一下拉控制晶体管M9、第二下拉控制晶体管M5、第三下拉控制晶体管M8、第四下拉控制晶体管M6和第五下拉控制晶体管M12。第一下拉控制晶体管M9的栅极和第一极与第二时钟信号端CLKB相连，并且第一下拉控制晶体管M9的第二极与第二下拉控制晶体管M5的栅极相连。第二下拉控制晶体管M5的第二 极与下拉节点PD相连。第三下拉控制晶体管M8的栅极与所述上拉节点相连，第三下拉控制晶体管M8的第一极与第一下拉控制晶体管M9的第二极相连，并且第三下拉控制晶体管M8的第二极与参考电平输入端Vss相连。第四下拉控制晶体管M6的栅极与所述上拉节点相连，第四下拉控制晶体管M6的第一极与所述下拉节点相连，并且第四下拉控制晶体管M6的第二极与参考电平输入端Vss相连。第五下拉控制晶体管M12的栅极与第二时钟信号端CLKB相连，第五下拉控制晶体管M12的第一极与信号输出端OUTPUT相连，并且第五下拉控制晶体管M12的第二极与参考电平输入端Vss相连。
上拉节点复位模块500包括第一复位晶体管M2和第二复位晶体管M10。第一复位晶体管M2的栅极与上拉节点复位端RESET_PU相连，第一复位晶体管M2的第二极与参考电平输入端Vss相连，并且第一复位晶体管M2的第一极与所述上拉节点相连。第二复位晶体管M10的栅极与所述下拉节点PD相连，第二复位晶体管M10的第一极与所述上拉节点相连，并且第二复位晶体管M10的第二极与参考电平输入端Vss相连。
在一些实施例中，移位寄存单元可以被提供有输出复位模块600以便确保信号输出端OUTPUT的输出信号在输出复位阶段被拉低。如图4和图6中所示，输出复位模块600的输入端与参考电平输入端Vss相连，并且输出复位模块600的输出端与信号输出端OUTPUT相连。输出复位模块600还包括控制端，即输出复位端RESET_OUTPUT。该输出复位模块600能够在输出复位端RESET_OUTPUT接收到有效信号时将该输出复位模块600的输入端和输出端导通。具体地，输出复位模块600包括输出复位晶体管M4。该输出复位晶体管M4的栅极形成为输出复位模块600的控制端，输出复位晶体管M4的第一极形成为输出复位模块600的输出端，并且输出复位晶体管M4的第二极形成为输出复位模块600的输入端。
在图4中所示的移位寄存单元的示例电路中，输出复位端RESET_OUTPUT是一个独立于上拉节点复位端RESET_PU的端子。如图1和图5中所示的移位寄存器包括这样的移位寄存单元，其中图1中所示的移位寄存器包括一个移位寄存单元组，而图5中所示的移位寄存器包括两个移位寄存单元组。如所示的，每个移位寄存单元组的 第n+1级移位寄存单元的信号输出端OUTPUT连接至该移位寄存单元组的第n级移位寄存单元的输出复位端RESET_OUTPUT。
在图6中所示的移位寄存单元的示例电路中，输出复位端RESET_OUTPUT与上拉节点复位端RESET_PU相连。如图7中所示的移位寄存器包括这样的移位寄存单元，其中每个移位寄存单元的上拉节点复位端RESET_PU与输出复位端RESET_OUT被合并为一个端子。该移位寄存器包括两个移位寄存单元组。如所示的，每个移位寄存单元组的第n+2级移位寄存单元的上拉节点PU连接到该移位寄存单元组第n级移位寄存单元的上拉节点复位端RESET_PU。因此，每个移位寄存单元组的第n+2级移位寄存单元的上拉节点PU为该移位寄存单元组第n级移位寄存单元的输出复位模块600的控制端RESET_OUTPUT提供控制信号。
在各实施例中，可以利用下一帧的开始信号STV对每个所述移位寄存单元组的最后k级移位寄存单元进行复位。在一些实施例中，每个移位寄存单元组还可以包括k级附加的哑(dummy)移位寄存单元。这k级哑移位寄存单元分别为该移位寄存单元组中的最后k级移位寄存单元提供上拉节点复位信号。将理解的是，此处的“哑移位寄存单元”仅用于提供复位信号，而并不用于为栅线提供扫描信号。
图8为根据本公开的实施例的显示装置800的框图。
如图8所示，显示装置800包括显示面板10、时序控制器20、栅极驱动器30和数据驱动器40。
显示面板10连接至多个栅极线GL和多个数据线DL。显示面板10基于输出图像数据RGBD’显示具有多个灰度的图像。栅极线GL可在第一方向D1延伸，并且数据线DL可在与第一方向D1交叉(例如，基本垂直)的第二方向D2延伸。
显示面板10可包括以矩阵形式排列的多个像素(未示出)。每个像素可电连接至栅极线GL的对应一个栅极线和数据线DL的对应一个数据线。
时序控制器20控制显示面板10、栅极驱动器30和数据驱动器40的操作。时序控制器20从外部设备(例如，主机)接收输入图像数据RGBD和输入控制信号CONT。输入图像数据RGBD可包括用于多个像素的多个输入像素数据。每个输入像素数据可包括用于多个像素中 的对应一个的红色灰度数据R、绿色灰度数据G和蓝色灰度数据B。输入控制信号CONT可包括主时钟信号、数据使能信号、垂直同步信号、水平同步信号等。
时序控制器20基于输入图像数据RGBD和输入控制信号CONT生成输出图像数据RGBD’、第一控制信号CONT1和第二控制信号CONT2。
例如，时序控制器20可基于输入图像数据RGBD生成输出图像数据RGBD’。输出图像数据RGBD’可被提供给数据驱动器40。在一些实施例中，输出图像数据RGBD’可以是与输入图像数据RGBD基本相同的图像数据。在一些实施例中，输出图像数据RGBD’可以是通过补偿输入图像数据RGBD生成的补偿图像数据。输出图像数据RGBD’可包括用于多个像素的多个输出像素数据。
时序控制器20可基于输入控制信号CONT生成第一控制信号CONT1。第一控制信号CONT1可被提供给栅极驱动器30，并且栅极驱动器30的驱动时序可基于第一控制信号CONT1被控制。第一控制信号CONT1可包括垂直启动信号、栅极时钟信号等。时序控制器20可基于输入控制信号CONT生成第二控制信号CONT2。第二控制信号CONT2可被提供给数据驱动器40，并且数据驱动器40的驱动时序可基于第二控制信号CONT2被控制。第二控制信号CONT2可包括水平启动信号、数据时钟信号、数据负载信号、极性控制信号等。
栅极驱动器30从时序控制器20接收第一控制信号CONT1。栅极驱动器30基于第一控制信号CONT1生成用于驱动栅极线GL的多个栅极信号。栅极驱动器30可顺序地将多个栅极信号施加至栅极线GL。
栅极驱动器30可以包括如上面实施例中描述的移位寄存器。在其中移位寄存器包括两个移位寄存单元组的实施例中，一个移位寄存单元组可以用于为奇数行的栅线提供扫描信号，并且另一个移位寄存单元组可以用于为偶数行的栅线提供扫描信号。
数据驱动器40从时序控制器20接收第二控制信号CONT2和输出图像数据RGBD’。数据驱动器40基于第二控制信号CONT2和输出图像数据RGBD’(例如，数字图像数据)生成多个数据电压(例如，模拟数据电压)。数据驱动器40可将多个数据电压施加至数据线DL。
在一些示例性实施例中，栅极驱动器30和/或数据驱动器40可被 设置(例如，直接安装)在显示面板10上，或者可以例如带式载体封装(Tape Carrier Package，TCP)类型连接至显示面板10。在一些实施例中，栅极驱动器30和/或数据驱动器40可被集成在显示面板10中。
作为示例而非限制，所述显示装置800可以是电视、手机、平板电脑、笔记本电脑、台式电脑、导航仪等电子设备。
可以理解的是，以上实施例仅仅是为了说明本公开的原理的目的而被描述；然而本公开并不局限于此。本领域内的普通技术人员可以在不脱离本公开的精神和实质的情况下做出各种变型和改进，这些变型和改进也落入本公开的保护范围。

Claims (16)

  1. 一种移位寄存器，包括：
    至少一个移位寄存单元组，每个所述移位寄存单元组包括多级彼此级联的移位寄存单元，所述多级移位寄存单元中的每个包括上拉节点和上拉节点复位端，
    其中每个所述移位寄存单元组的第n+k级移位寄存单元的上拉节点连接至该移位寄存单元组的第n级移位寄存单元的上拉节点复位端，以提供允许所述第n级移位寄存单元的上拉节点处的电位复位的上拉节点复位信号，所述上拉节点处的电位的复位使得所述第n级移位寄存单元的信号输出端处的输出信号复位，其中n为大于或等于1的整数，并且k为大于1的整数。
  2. 根据权利要求1所述的移位寄存器，其中所述多级移位寄存单元中的每个还包括信号输入端、信号输出端、第一时钟信号端、第二时钟信号端、输入模块、上拉模块、下拉模块、下拉控制模块、上拉节点复位模块和参考电平输入端，其中：
    所述输入模块具有与所述信号输入端相连的输入端和与所述上拉节点相连的输出端，所述输入模块被配置成响应于该输入模块的输入端接收到有效信号而使该输入模块的输入端和输出端导通；
    所述上拉模块具有与所述第一时钟信号端相连的输入端、与所述信号输出端相连的输出端、以及与所述上拉节点相连的控制端，所述上拉模块被配置成响应于所述上拉模块的控制端接收到有效信号而使所述上拉模块的输入端与输出端导通；
    所述下拉模块具有与所述参考电平输入端相连的输入端、与所述信号输出端相连的输出端、以及与下拉节点相连的控制端，所述下拉模块被配置成响应于所述下拉模块的控制端接收到有效信号而使所述下拉模块的输入端与输出端导通；
    所述下拉控制模块具有与所述第二时钟信号端相连的输入端、与所述下拉节点相连的输出端、以及与所述上拉节点相连的控制端，所述下拉控制模块被配置成响应于该下拉控制模块的控制端接收到有效信号而使该下拉控制模块的输入端和输出端导通；并且
    所述上拉节点复位模块具有与所述参考电压输入端相连的输入端、 与所述上拉节点相连的输出端、以及与所述上拉节点复位端相连的控制端。
  3. 根据权利要求2所述的移位寄存器，其中所述输入模块包括第一输入晶体管和第二输入晶体管，其中：
    所述第一输入晶体管具有第一极、与所述第一极相连并形成为所述输入模块的输入端的栅极、以及形成为所述输入模块的输出端的第二极；并且
    所述第二输入晶体管具有与所述第一输入晶体管的第一极相连的第一极、与所述第二时钟信号端相连的栅极、以及与所述第一输入晶体管的第二极相连的第二极。
  4. 根据权利里要求2所述的移位寄存器，其中所述上拉模块包括：
    上拉晶体管，具有形成为所述上拉模块的控制端的栅极、形成为所述上拉模块的输入端的第一极、以及形成为所述上拉模块的输出端的第二极；以及
    存储电容，具有与所述上拉节点相连的第一端以及与所述信号输出端相连的第二端。
  5. 根据权利要求2所述的移位寄存器，其中所述下拉模块包括下拉晶体管，其具有形成为所述下拉模块的控制端的栅极、形成为所述下拉模块的输出端的第一极、以及形成为所述下拉模块的输入端的第二极。
  6. 根据权利要求2所述的移位寄存器，其中所述下拉控制模块包括第一下拉控制晶体管、第二下拉控制晶体管、第三下拉控制晶体管、第四下拉控制晶体管和第五下拉控制晶体管，其中：
    所述第一下拉控制晶体管具有与所述第二时钟信号端共同相连的栅极和第一极、以及第二极；
    所述第二下拉控制晶体管具有与所述第一下拉控制晶体管的第二极相连的栅极、与所述第二时钟信号端相连的第一极、以及与所述下拉节点相连的第二极；
    所述第三下拉控制晶体管具有与所述上拉节点相连的栅极、与所述第一下拉控制晶体管的第二极相连的第一极、以及与所述参考电平输入端相连的第二极；
    所述第四下拉控制晶体管具有与所述上拉节点相连的栅极、与所 述下拉节点相连的第一极、以及与所述参考电平输入端相连的第二极；并且
    所述第五下拉控制晶体管具有与所述第二时钟信号端相连的栅极、与所述信号输出端相连的第一极、以及与所述参考电平输入端相连的第二极。
  7. 根据权利要求2所述的移位寄存器，其中所述上拉节点复位模块包括：
    第一复位晶体管，具有与所述上拉节点复位端相连的栅极、与所述上拉节点相连的第一极、以及与所述参考电平输入端相连的第二极；以及
    第二复位晶体管，具有与所述下拉节点相连的栅极、与所述上拉节点相连的第一极、以及与所述参考电平输入端相连的第二极。
  8. 根据权利要求2至7中任意一项所述的移位寄存器，其中所述多级移位寄存单元中的每个还包括输出复位模块，其具有与所述参考电平输入端相连的输入端、与所述信号输出端相连的输出端、以及控制端。
  9. 根据权利要求8所述的移位寄存器，其中对于所述多级移位寄存单元中的每个，所述输出复位模块的控制端与该移位寄存单元的所述上拉节点复位端相连。
  10. 根据权利要求8所述的移位寄存器，其中每个所述移位寄存单元组的第n+1级移位寄存单元的信号输出端连接至该移位寄存单元组的第n级移位寄存单元的所述输出复位模块的控制端。
  11. 根据权利要求8所述的移位寄存器，其中所述输出复位模块包括输出复位晶体管，其具有形成为所述输出复位模块的控制端的栅极、形成为所述输出复位模块的输出端的第一极、以及形成为所述输出复位模块的输入端的第二极。
  12. 根据权利要求1至7中任意一项所述的移位寄存器，其中所述移位寄存器包括两个所述移位寄存单元组。
  13. 根据权利要求1至7中任意一项所述的移位寄存器，其中每个所述移位寄存单元组还包括k级哑移位寄存单元，以用于为该移位寄存单元组中最后k级所述移位寄存单元提供相应的上拉节点复位信号。
  14. 一种栅极驱动电路，包括根据权利要求1至13中任意一项所述的移位寄存器。
  15. 一种显示装置，包括根据权利要求14所述的栅极驱动电路。
  16. 根据权利要求15所述的显示装置，其中所述移位寄存器包括两个所述移位寄存单元组，其中一个移位寄存单元组用于为所述显示装置的奇数行的栅线提供扫描信号，并且另一个移位寄存单元组用于为所述显示装置的偶数行的栅线提供扫描信号。
PCT/CN2017/071257 2016-05-13 2017-01-16 移位寄存器、栅极驱动电路和显示装置 WO2017193627A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10923060B2 (en) 2017-04-19 2021-02-16 Boe Technology Group Co., Ltd. Shift register unit with power signal terminals having same frequencies and reverse phases, shift register circuit and display panel

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN205595037U (zh) 2016-05-13 2016-09-21 合肥鑫晟光电科技有限公司 移位寄存器、栅极驱动电路和显示装置
CN106448533A (zh) * 2016-09-30 2017-02-22 京东方科技集团股份有限公司 移位寄存器单元、栅极扫描电路、驱动方法、显示装置
CN106448596B (zh) * 2016-10-31 2019-03-15 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN108022560B (zh) * 2016-11-01 2023-10-10 合肥鑫晟光电科技有限公司 栅极驱动电路及其驱动方法、显示基板和显示装置
US11942041B2 (en) 2018-07-18 2024-03-26 Hefei Xinsheng Optoelectronics Technology Co., Ltd. Shift register unit, gate driving circuit, display device, and driving method
US11403990B2 (en) 2018-07-18 2022-08-02 Hefei Xinsheng Optoelectronics Technology Co., Ltd. Shift register unit, gate driving circuit, display device, and driving method
CN109935199B (zh) * 2018-07-18 2021-01-26 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN108717846B (zh) * 2018-08-13 2021-04-16 惠科股份有限公司 移位暂存电路和显示装置
CN108962121B (zh) * 2018-08-13 2021-04-16 惠科股份有限公司 移位暂存电路和显示装置
TWI680463B (zh) * 2019-02-12 2019-12-21 友達光電股份有限公司 移位暫存裝置與顯示裝置
CN111243489B (zh) * 2020-03-24 2022-11-01 合肥鑫晟光电科技有限公司 一种移位寄存器及其驱动方法、栅极驱动电路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN204406959U (zh) * 2014-12-26 2015-06-17 合肥鑫晟光电科技有限公司 移位寄存器单元、移位寄存器电路以及显示装置
CN105118473A (zh) * 2015-10-10 2015-12-02 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器及驱动方法、阵列基板
CN204966019U (zh) * 2015-10-08 2016-01-13 京东方科技集团股份有限公司 移位寄存器单元和栅线驱动装置
KR20160019301A (ko) * 2014-08-11 2016-02-19 엘지디스플레이 주식회사 쉬프트 레지스터 및 그를 이용한 표시 장치
CN205595037U (zh) * 2016-05-13 2016-09-21 合肥鑫晟光电科技有限公司 移位寄存器、栅极驱动电路和显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101415562B1 (ko) * 2007-08-06 2014-07-07 삼성디스플레이 주식회사 게이트 구동회로 및 이를 가지는 표시장치
EP2549483A4 (en) * 2010-03-19 2016-03-02 Sharp Kk SHIFT REGISTER
CN103928001B (zh) * 2013-12-31 2016-12-07 上海天马微电子有限公司 一种栅极驱动电路和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160019301A (ko) * 2014-08-11 2016-02-19 엘지디스플레이 주식회사 쉬프트 레지스터 및 그를 이용한 표시 장치
CN204406959U (zh) * 2014-12-26 2015-06-17 合肥鑫晟光电科技有限公司 移位寄存器单元、移位寄存器电路以及显示装置
CN204966019U (zh) * 2015-10-08 2016-01-13 京东方科技集团股份有限公司 移位寄存器单元和栅线驱动装置
CN105118473A (zh) * 2015-10-10 2015-12-02 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器及驱动方法、阵列基板
CN205595037U (zh) * 2016-05-13 2016-09-21 合肥鑫晟光电科技有限公司 移位寄存器、栅极驱动电路和显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10923060B2 (en) 2017-04-19 2021-02-16 Boe Technology Group Co., Ltd. Shift register unit with power signal terminals having same frequencies and reverse phases, shift register circuit and display panel

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