WO2022252000A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2022252000A1
WO2022252000A1 PCT/CN2021/097156 CN2021097156W WO2022252000A1 WO 2022252000 A1 WO2022252000 A1 WO 2022252000A1 CN 2021097156 W CN2021097156 W CN 2021097156W WO 2022252000 A1 WO2022252000 A1 WO 2022252000A1
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Prior art keywords
layer
forming
opening
conductive
dielectric layer
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Ceased
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PCT/CN2021/097156
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English (en)
French (fr)
Inventor
许增升
荆学珍
张�浩
张田田
于海龙
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202180094242.XA priority Critical patent/CN116897427A/zh
Priority to US18/565,406 priority patent/US20240258238A1/en
Priority to PCT/CN2021/097156 priority patent/WO2022252000A1/zh
Publication of WO2022252000A1 publication Critical patent/WO2022252000A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/418—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H10P14/432—Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4437—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal
    • H10W20/4441—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal the principal metal being a refractory metal

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.
  • the technical problem solved by the present invention is to provide a semiconductor structure and its forming method, so as to improve the performance of the semiconductor structure.
  • the technical solution of the present invention provides a semiconductor structure, comprising: a substrate; a cover layer located on part of the substrate; an auxiliary layer located on the surface of the cover layer; located on the substrate and the The first dielectric layer on the surface of the auxiliary layer; the conductive structure located in the first dielectric layer, the top surface of the first dielectric layer is flush with the top surface of the conductive structure; located between the first dielectric layer and the A second dielectric layer on the surface of the conductive structure; a first opening located in the second dielectric layer and the first dielectric layer, and the first opening exposes the auxiliary layer and is located in the second dielectric layer and the second opening exposes the top surface of the conductive structure; the first conductive layer located in the first opening, and the second conductive layer located in the second opening.
  • the substrate includes a base, a gate structure on the base, and an interlayer dielectric layer on the base, and the interlayer dielectric layer is also located on the sidewall of the gate structure and exposes out of the top surface of the gate structure, the capping layer is located on the top surface of the gate structure.
  • the substrate further includes source and drain layers located in the substrate on both sides of the gate structure, and the bottom of the conductive structure is deep into the substrate and located on the surface of the source and drain layers.
  • the material of the covering layer includes metal.
  • the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a covering layer on part of the substrate; forming an auxiliary layer on the surface of the covering layer by using a first selective deposition process ; forming a first dielectric layer on the surface of the substrate and the auxiliary layer; forming a conductive structure in the first dielectric layer, the top surface of the first dielectric layer is flush with the top surface of the conductive structure; A second dielectric layer is formed on the surface of the first dielectric layer and the conductive structure; a first opening and a second opening are formed, the first opening is located in the second dielectric layer and the first dielectric layer and the first opening The auxiliary layer is exposed, the second opening is located in the second dielectric layer and the second opening exposes the top surface of the conductive structure; a first conductive layer is formed in the first opening, and the A second conductive layer is formed in the second opening, and the growth rate of the material of the first conductive layer on the surface of
  • the material of the auxiliary layer includes tungsten.
  • the formation process of the auxiliary layer includes a chemical vapor deposition process; the process parameters of the chemical vapor deposition process include: the reaction gas includes tungsten hexafluoride and hydrogen, and the reaction temperature ranges from 300 degrees Celsius to 400 degrees Celsius.
  • the substrate includes a base, a gate structure on the base, and an interlayer dielectric layer on the base, and the interlayer dielectric layer is also located on the sidewall of the gate structure and exposes the top surface of the gate structure; the capping layer is located on the top surface of the gate structure.
  • the substrate further includes source-drain layers located in the substrate on both sides of the gate structure; the bottom of the conductive structure is deep into the substrate and located on the surface of the source-drain layer.
  • first ions in the covering layer the material of the covering layer includes metal ions, and a first chemical bond is formed between the first ions and the metal ions; the metal ions are in the auxiliary layer.
  • An ion and a second ion, the second ion and the metal ion form a second chemical bond, and the bond energy of the second chemical bond is lower than the bond energy of the first chemical bond.
  • the first ion includes chloride ion; the second ion includes fluoride ion.
  • the metal includes tungsten.
  • the forming process of the covering layer includes a selective atomic layer deposition process.
  • the process parameters of the atomic layer deposition process include: the reaction gas includes tungsten chloride and hydrogen, and the reaction temperature ranges from 400°C to 500°C.
  • the forming process of the first conductive layer and the second conductive layer includes a second selective deposition process.
  • the process parameters of the second selective deposition process include: the reaction gas includes tungsten hexafluoride and hydrogen, and the reaction temperature ranges from 300 degrees Celsius to 400 degrees Celsius.
  • the method for forming the first conductive layer and the second conductive layer includes: depositing a conductive material layer in the first opening and the second opening until the first opening and the second The second opening is filled; planarizing the conductive material layer until the second dielectric layer is exposed.
  • the growth rate of the conductive material layer on the surface of the auxiliary layer is higher than the growth rate on the surface of the conductive structure.
  • materials of the first conductive layer and the second conductive layer include tungsten.
  • the thickness of the auxiliary layer ranges from 1 nm to 10 nm.
  • the material of the conductive structure includes cobalt.
  • an auxiliary layer is formed on the surface of the cover layer by using a first selective deposition process, a first conductive layer is formed in the first opening, and a first conductive layer is formed in the second opening.
  • the growth rate of the material of the first conductive layer on the surface of the auxiliary layer is higher than the growth rate of the material of the first conductive layer on the surface of the covering layer, so as to reduce the growth rate of the material of the first conductive layer on the surface of the auxiliary layer
  • the difference between the growth rate in the first opening on the surface of the auxiliary layer and the growth rate of the material of the second conductive layer in the second opening on the surface of the conductive structure, thereby reducing the time when the first opening on the auxiliary layer is filled The case of early closure, thereby improving the performance of the formed semiconductor structure.
  • first ions in the covering layer there are first ions in the covering layer, and the material of the covering layer includes metal ions, and a first chemical bond is formed between the first ions and the metal ions; there are the metal ions and the metal ions in the auxiliary layer.
  • the second ion, the second ion and the metal ion form a second chemical bond, the bond energy of the second chemical bond is lower than the bond energy of the first chemical bond, and the second chemical bond is easier to be bonded than the first chemical bond Breaking down increases the reaction rate of the material forming the first conductive layer on the surface of the auxiliary layer.
  • the first ions include chlorine ions
  • the second ions include fluorine ions
  • the existence of tungsten-fluorine bonds provides preparations for the formation of tungsten materials in the auxiliary layer, shortening
  • the time for absorbing tungsten hexafluoride gas during the formation process of the first conductive layer is shortened, the growth rate of the tungsten material formed on the surface of the auxiliary layer is improved, and the growth rate of the tungsten material in the first opening is higher than that in the second opening.
  • the growth rate in the opening is reduced, thereby reducing the situation that the first opening is closed before being filled, thereby improving the performance of the formed semiconductor structure.
  • 1 to 5 are schematic cross-sectional views of a semiconductor structure forming process
  • Fig. 6 to Fig. 12 are structural schematic diagrams of each step of a method for forming a semiconductor structure in an embodiment of the present invention.
  • 1 to 5 are schematic cross-sectional views of a process of forming a semiconductor structure.
  • a substrate 101 is provided, and a gate structure is provided on the substrate 101, the gate structure includes a metal gate 101 and a gate dielectric layer 102, and sidewalls 103 are provided on the side walls of the gate structure, There are source and drain regions 104 in the substrate 101 located on both sides of the sidewall 103, and an interlayer dielectric layer 105 is located on the substrate 100, and the interlayer dielectric layer 105 is located on the sidewall 103 sidewalls, and expose the top surface of the gate structure.
  • a cover layer 106 is formed on the surface of the metal gate 101; a first etching stop layer 108 is formed on the interlayer dielectric layer 105, the surface of the gate structure and the top of the spacer 102; The first dielectric layer 107 is formed on the surface of the first etching stop layer 108 .
  • a first opening (not shown in the figure) is formed in the first dielectric layer 107, the first etch stop layer 108 and the interlayer dielectric layer 105, and the first opening exposes the source and drain regions 104; and form a conductive structure 109 in the first opening.
  • a second etch stop layer 110 is formed on the surface of the conductive structure 109 and the first dielectric layer 107; a second dielectric layer 112 is formed on the surface of the second etch stop layer 110; A second opening 112 is formed in the second dielectric layer 112, the second etch stop layer 110, the first dielectric layer 107 and the first etch stop layer 108, and the second opening 112 exposes the top surface of the cover layer 106; A third opening 113 is formed in the second dielectric layer 112 and the second etch stop layer 110 , and the third opening 113 exposes the top surface of the conductive structure 109 .
  • a metal layer 114 is formed in the second opening 112 and the third opening 113 .
  • the method described above is used in the metal interconnection process.
  • the covering layer 106 is made of tungsten, which is formed by atomic layer deposition (ALD).
  • the formed metal tungsten has good selectivity on the surface of the metal gate 101 and is conducive to forming a uniform and dense covering layer 106 .
  • the formation process of the atomic layer deposition process does not contain fluorine ions, so as to avoid the adverse effect of fluorine ions on the work function layer of the gate structure, but the deposition rate is slow.
  • the material of the conductive structure 109 is cobalt.
  • the material of the metal layer 114 is also tungsten, and the metal layer 114 is formed by the chemical vapor deposition (CVD) process because the chemical vapor deposition (CVD) process has better step coverage and takes less time than the atomic layer deposition process.
  • CVD chemical vapor deposition
  • the atomic layer deposition process is formed by reacting tungsten chloride (such as WCl 3 ) with hydrogen, there are a large number of tungsten-chlorine bonds in the capping layer 106 .
  • the reaction temperature of the reaction between tungsten chloride and hydrogen is 460 degrees Celsius.
  • metal tungsten is selectively grown on the surface of the metal material, the reaction gas includes tungsten hexafluoride and hydrogen, and the reaction temperature is lower than 400 degrees Celsius.
  • the depth of the second opening 112 is higher than the depth of the third opening 113, and it is easier to cause the third opening 113 to be filled with tungsten material, but the second opening 112 is not yet filled with tungsten material.
  • the tungsten material continues to grow after filling the third opening 113 so that it may cover the surface of the second opening 112, so that the second opening 112 is closed in advance, resulting in the inside of the second opening 112
  • the formed metal layer 114 produces defects such as holes, which affect the conductivity of the metal layer 114 and reduce the performance of the formed semiconductor structure.
  • an auxiliary layer is formed on the surface of the cover layer by using a first selective deposition process, a first conductive layer is formed in the first opening, and a first conductive layer is formed in the first opening.
  • a second conductive layer is formed in the second opening, and the growth rate of the material of the first conductive layer on the surface of the auxiliary layer is higher than the growth rate of the material of the first conductive layer on the surface of the covering layer, so as to reduce the first
  • the opening is closed before it is filled, thereby improving the performance of the formed semiconductor structure.
  • FIG. 6 to FIG. 12 are structural schematic diagrams of each step of a method for forming a semiconductor structure in an embodiment of the present invention.
  • a substrate is provided.
  • the substrate includes a substrate 201, a gate structure located on the substrate 201, and an interlayer dielectric layer 202 located on the substrate 201, and the interlayer dielectric layer 202 is also located on the gate structure. structure sidewalls, and expose the top surface of the gate structure.
  • the gate structure includes a gate layer 203 and sidewalls 204 located on sidewalls of the gate layer 203 .
  • the material of the gate layer 203 includes metal. In this embodiment, the material of the gate layer 203 is aluminum.
  • the method for forming the gate structure includes: forming a dummy gate (not shown in the figure) on the substrate 201; forming the sidewall 204 on the sidewall of the dummy gate; forming a dummy gate on the surface of the substrate 201
  • the interlayer dielectric layer 202, the interlayer dielectric layer 202 exposes the top surface of the dummy gate; the dummy gate is removed by etching, and a groove is formed in the interlayer dielectric layer 202 (not shown in the figure ); the gate layer 203 in the groove.
  • a gate dielectric layer 205 is formed on the sidewall and bottom of the groove.
  • the material of the gate dielectric layer 205 includes a high-K dielectric material.
  • the gate structure further includes a work function layer (not shown in the figure) located between the gate dielectric layer 205 and the gate layer 203.
  • the substrate 200 further includes source and drain layers 206 located in the substrate 201 on both sides of the gate structure.
  • a covering layer 207 is formed on part of the substrate; an auxiliary layer 208 is formed on the surface of the covering layer 207 by using a first selective deposition process.
  • the auxiliary layer 208 is used to subsequently increase the growth rate of the material of the first conductive layer on the covering layer 207 .
  • the covering layer 207 is located on the top surface of the gate structure 202 , specifically, the covering layer 207 is located on the top surface of the gate layer 203 .
  • the covering layer 207 is used to prevent ions from diffusing into the gate layer 203 , which is beneficial to maintain the performance such as the threshold voltage of the formed device.
  • the material of the covering layer 207 includes metal, and the metal includes tungsten.
  • the metal is tungsten.
  • the forming process of the covering layer 207 includes a selective atomic layer deposition process.
  • the process parameters of the atomic layer deposition process include: the reaction gas includes tungsten chloride and hydrogen, and the reaction temperature ranges from 400 degrees Celsius to 500 degrees Celsius. Tungsten chloride reacts with hydrogen to form tungsten.
  • the selective atomic layer deposition process makes the tungsten material have good selectivity on the surface of the gate layer 203 and is conducive to forming a uniform and dense material film.
  • the formation process of the covering layer 207 does not contain fluorine ions, so as to avoid the adverse effect of fluorine ions on the work function layer of the gate structure, but the deposition rate is relatively slow due to the limitation of the atomic layer deposition process.
  • first ions in the covering layer 207 there are first ions in the covering layer 207, the material of the covering layer 207 includes metal ions, and a first chemical bond is formed between the first ions and the metal ions.
  • the first ion includes chloride ion.
  • the covering layer 207 is formed by reacting tungsten chloride and hydrogen, and chloride ions are inevitably introduced into the covering layer 207, and the first ion is chloride ion.
  • the material of the covering layer 207 is tungsten ions, and the first chemical bond formed between the chloride ions and the tungsten ions is a tungsten-chlorine bond. The tungsten-chlorine bond is not easily broken compared to the tungsten-fluorine bond.
  • the first conductive layer of tungsten material is formed by reacting tungsten hexafluoride and hydrogen on the surface of the covering layer 207, due to the existence of the tungsten-chlorine bond, the tungsten Material growth becomes difficult.
  • the auxiliary layer 208 contains the metal ion and the second ion, the second ion and the metal ion form a second chemical bond, and the bond energy of the second chemical bond is lower than the bond energy of the first chemical bond.
  • the second chemical bond is easier to break than the first chemical bond, which increases the reaction rate of the material that subsequently forms the first conductive layer on the surface of the auxiliary layer 208 .
  • the material of the auxiliary layer 208 includes tungsten; the second ions include fluorine ions.
  • the material of the auxiliary layer 208 is tungsten; the second ion is fluorine ion.
  • the formation process of the auxiliary layer 208 includes a chemical vapor deposition process; the process parameters of the chemical vapor deposition process include: the reaction gas includes tungsten hexafluoride and hydrogen, and the reaction temperature ranges from 300°C to 400°C.
  • tungsten-fluorine bonds in the auxiliary layer 208 there are tungsten-fluorine bonds in the auxiliary layer 208, and chlorine-tungsten bonds in the covering layer 207. Since the bond energy of the tungsten-fluorine bond is lower than that of the chlorine-tungsten bond, Compared with forming the first conductive layer on the surface of the covering layer 207 , it is relatively easy to grow the tungsten material on the surface of the auxiliary layer 208 .
  • the auxiliary layer 208 has a thickness ranging from 1 nm to 10 nm.
  • the auxiliary layer 208 may be damaged in the subsequent etching process of forming the first opening to expose the auxiliary layer 208. If the thickness of the auxiliary layer 208 is too small (ie, less than 1 nanometer), the The auxiliary layer 208 may not function due to being consumed; if the thickness of the auxiliary layer 208 is too large, that is, greater than 10 nanometers.
  • the surface of the material film of the first dielectric layer 210 formed subsequently on the surface of the substrate may be uneven, affecting device performance. On the other hand, unnecessary process waste will also be caused.
  • a first dielectric layer 210 is formed on the surface of the substrate and the auxiliary layer 208 .
  • the material of the first dielectric layer 210 is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
  • a first etching stop layer 209 is formed on the surface of the substrate and the auxiliary layer 208 .
  • the first etching stop layer 209 is used to reduce etching damage to the auxiliary layer 208 .
  • a conductive structure 211 is formed in the first dielectric layer 210 , and the top surface of the first dielectric layer 210 is flush with the top surface of the conductive structure 211 .
  • the bottom of the conductive structure 211 is deep into the substrate and located on the surface of the source-drain layer 206 .
  • the method for forming the conductive structure 211 includes: forming a first patterned layer (not shown in the figure) on the surface of the first dielectric layer 210, and the first patterned layer exposes part of the first dielectric layer 210 ; using the first patterned layer as a mask, etching the first dielectric layer 210, the first etch stop layer 209, and the interlayer dielectric layer 202 until the surface of the source and drain layer 206 is exposed; Form a third opening (not shown in the figure) in the first dielectric layer, the first etch stop layer 209 and the interlayer dielectric layer 206; deposit a metal material in the third opening to form The conductive structure 211 .
  • the material of the conductive structure 211 includes cobalt.
  • cobalt material As a wire material, cobalt material has good filling ability and electrical conductivity, so that the formed device has strong electrical conductivity and lower power consumption.
  • a second dielectric layer 213 is formed on the surface of the first dielectric layer 210 and the conductive structure 211 .
  • the material of the second dielectric layer 213 is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
  • a second etching stop layer 212 is formed on the surface of the first dielectric layer 210 and the conductive structure 211.
  • the second etching stop layer 212 is used to reduce etching damage to the conductive structure 211 .
  • a first opening 214 and a second opening 215 are formed, the first opening 214 is located in the second dielectric layer 213 and the first dielectric layer 210, and the first opening 214 exposes the The auxiliary layer 208, the second opening 215 is located in the second dielectric layer 213, and the second opening 215 exposes the top surface of the conductive structure 211.
  • the forming process of the first opening 214 includes a dry etching process; the forming process of the second opening 215 includes a dry etching process.
  • the dry etching process is conducive to forming openings with better morphology.
  • the method for forming the second opening 215 includes: forming a second patterned layer on the surface of the second dielectric layer 213, and the second patterned layer exposes part of the first layer on the conductive structure 211.
  • the second dielectric layer 213 using the second patterned layer as a mask, etching the second dielectric layer 213 until the conductive structure 211 is exposed.
  • the method for forming the first opening 214 includes: forming a third patterned layer on the surface of the second dielectric layer 213 and in the second opening 215, and the third patterned layer exposes a portion the second dielectric layer 213 on the auxiliary layer 208; using the third patterned layer as a mask, etch the second dielectric layer 213 and the first dielectric layer 210 until the auxiliary layer is exposed 208: After forming the auxiliary layer 208, remove the third patterned layer.
  • the first opening 214 is formed behind the second opening 215 . In other embodiments, the sequence of forming the first opening 214 and the second opening 215 is not required.
  • a first conductive layer 216 is formed in the first opening 214
  • a second conductive layer 217 is formed in the second opening 215
  • the material of the first conductive layer 216 is in the auxiliary layer 208
  • the growth rate of the surface is higher than the growth rate of the material of the first conductive layer 216 on the surface of the covering layer 207 .
  • the growth rate of the material of the first conductive layer 216 on the surface of the auxiliary layer 208 is higher than the growth rate of the material of the first conductive layer 216 on the surface of the covering layer 207, so as to shrink the material of the first conductive layer 216
  • Materials of the first conductive layer 216 and the second conductive layer 217 include tungsten.
  • the forming method of the first conductive layer 216 and the second conductive layer 217 includes: depositing a conductive material layer (not shown in the figure) in the first opening 214 and the second opening 215 until the The first opening 214 and the second opening 215 are filled; the conductive material layer is planarized until the second dielectric layer 213 is exposed.
  • the first conductive layer 216 and the second conductive layer 217 are deposited and formed simultaneously using the same metal material in the same process, which is beneficial to reduce the production cost.
  • the forming process of the first conductive layer 216 and the second conductive layer 217 includes a second selective deposition process.
  • the formation process of the first conductive layer 216 and the second conductive layer 217 is a chemical vapor deposition process.
  • the chemical vapor deposition process has better step coverage, and has the characteristics of shorter time consumption and lower cost compared with the atomic layer deposition process.
  • the process parameters of the second selective deposition process include: the reaction gas includes tungsten hexafluoride and hydrogen, and the reaction temperature ranges from 300 degrees Celsius to 400 degrees Celsius.
  • the growth rate of the conductive material layer on the surface of the auxiliary layer 208 is higher than that on the surface of the conductive structure 211 . Since the depth of the first opening 214 is higher than the depth of the second opening 215, it is easy to cause further deposition after the first opening 214 has not been filled and the second opening 215 is filled. The material of the second conductive layer in the second opening 215 continues to grow, so as to cover the first opening 214 , causing the first opening 214 to be closed in advance.
  • the auxiliary layer 208 has a tungsten-fluorine bond.
  • the existence of the tungsten-fluorine bond provides preparation for the formation of tungsten material, shortens the time for adsorbing tungsten hexafluoride gas during the formation of the first conductive layer, and improves the auxiliary layer 208.
  • the growth rate of the tungsten material formed on the surface of the layer 208 further makes the growth rate of the tungsten material in the first opening 214 higher than the growth rate in the second opening 215, thereby reducing the speed at which the first opening 214 is Filling the previously closed situation improves the performance of the formed semiconductor structure.
  • an embodiment of the present invention also provides a semiconductor structure formed by the above method, please continue to refer to FIG. 12 , including: a substrate; a covering layer 207 located on part of the substrate; The auxiliary layer 208; the first dielectric layer 210 located on the substrate and the surface of the auxiliary layer 208; the conductive structure 211 located in the first dielectric layer 210, the top surface of the first dielectric layer 210 and the The top surface of the conductive structure 211 is flush; the second dielectric layer 213 located on the surface of the first dielectric layer 210 and the conductive structure 211; the second dielectric layer 213 located in the second dielectric layer 213 and the first dielectric layer 210 An opening 214 (as shown in FIG.
  • the first opening 214 exposes the auxiliary layer 208, and a second opening 215 (as shown in FIG. 11 ) located in the second dielectric layer 213 , and the The second opening 215 exposes the top surface of the conductive structure 211 ; the first conductive layer 216 inside the first opening 214 , and the second conductive layer 217 inside the second opening 215 .
  • the substrate includes a base 201, a gate structure on the base 201, and an interlayer dielectric layer 211 (as shown in FIG. 11 ) on the base 201, and the interlayer dielectric layer 211 is also located on the
  • the sidewall of the gate structure exposes the top surface of the gate structure; the covering layer 207 is located on the top surface of the gate structure.
  • the substrate also includes source and drain layers 206 located in the substrate on both sides of the gate structure; the bottom of the conductive structure 211 is deep into the substrate and located on the surface of the source and drain layers 206 .
  • the material of the covering layer 207 includes metal, and the metal includes tungsten. In this embodiment, the material of the covering layer 207 is tungsten.

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  • Crystallography & Structural Chemistry (AREA)

Abstract

一种半导体结构及其形成方法，其中方法包括：采用第一选择性沉积工艺在所述覆盖层表面形成辅助层；在所述衬底和所述辅助层表面形成第一介质层；在所述第一介质层内形成导电结构；在所述第一介质层和所述导电结构表面形成第二介质层；形成第一开口和第二开口，所述第一开口位于所述第二介质层和所述第一介质层内且第一开口暴露出所述辅助层，所述第二开口位于所述第二介质层内且所述第二开口暴露出所述导电结构顶部表面；在所述第一开口内形成第一导电层，在所述第二开口内形成第二导电层，所述第一导电层的材料在所述辅助层表面的生长速率高于所述第一导电层的材料在所述覆盖层表面的生长速率，提高所形成的半导体结构的性能。

Description

半导体结构及其形成方法 技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体结构及其形成方法。
背景技术
随着半导体集成电路的集成度不断提高，半导体器件的特征尺寸不断缩小，各种实际的和基本的限制和技术挑战开始出现，器件尺寸的进一步缩小正变得越来越困难。
集成电路技术的快速发展对金属互连技术提出了更高的要求。传统的铝金属互连技术已经不能满足现代互连技术发展的需要，大马士革结构的铜金属互连技术已成为互连技术的重点发展方向之一。然而，在集成电路特征线宽缩小进入几纳米阶段后，铜互连技术也面临着巨大挑战。金属布线的层数越来越多，金属导线的自身电阻及其间的寄生电容越来越成为影响器件速度的制约因素。
因此，现有的金属互连线工艺有待进一步改进。
发明内容
本发明解决的技术问题是提供一种半导体结构及其形成方法，以提升半导体结构的性能。
为解决上述技术问题，本发明技术方案提供一种半导体结构，包括：衬底；位于部分所述衬底上的覆盖层；位于所述覆盖层表面的辅助层；位于所述衬底和所述辅助层表面的第一介质层；位于所述第一介质层内的导电结构，所述第一介质层顶表面与所述导电结构顶部表面齐平；位于在所述第一介质层和所述导电结构表面的第二介质层；位于所述第二介质层和所述第一介质层内的第一开口，且所述第一开 口暴露出所述辅助层，位于所述第二介质层内的第二开口且所述第二开口暴露出所述导电结构顶部表面；位于所述第一开口内的第一导电层，位于所述第二开口内的第二导电层。
可选的，所述衬底包括基底、位于所述基底上的栅极结构和位于所述基底上的层间介质层，所述层间介质层还位于所述栅极结构侧壁，且暴露出所述栅极结构顶部表面，所述覆盖层位于所述栅极结构顶部表面。
可选的，所述衬底还包括位于所述栅极结构两侧衬底内的源漏层，所述导电结构的底部深入所述衬底内，且位于所述源漏层表面。
可选的，所述覆盖层的材料包括金属。
相应的，本发明技术方案还提供一种半导体结构的形成方法，包括：提供衬底；在部分所述衬底上形成覆盖层；采用第一选择性沉积工艺在所述覆盖层表面形成辅助层；在所述衬底和所述辅助层表面形成第一介质层；在所述第一介质层内形成导电结构，所述第一介质层顶部表面与所述导电结构顶表面齐平；在所述第一介质层和所述导电结构表面形成第二介质层；形成第一开口和第二开口，所述第一开口位于所述第二介质层和所述第一介质层内且第一开口暴露出所述辅助层，所述第二开口位于所述第二介质层内且所述第二开口暴露出所述导电结构顶部表面；在所述第一开口内形成第一导电层，在所述第二开口内形成第二导电层，所述第一导电层的材料在所述辅助层表面的生长速率高于所述第一导电层的材料在所述覆盖层表面的生长速率。
可选的，所述辅助层的材料包括钨。
可选的，所述辅助层的形成工艺包括化学气相沉积工艺；所述化学气相沉积工艺的工艺参数包括：反应气体包括六氟化钨和氢气，反应温度范围为300摄氏度至400摄氏度。
可选的，所述衬底包括基底、位于所述基底上的栅极结构和位于 所述基底上的层间介质层，所述层间介质层还位于所述栅极结构侧壁，且暴露出所述栅极结构顶部表面；所述覆盖层位于所述栅极结构顶部表面。
可选的，所述衬底还包括位于所述栅极结构两侧衬底内的源漏层；所述导电结构的底部深入所述衬底内，且位于所述源漏层表面。
可选的，所述覆盖层内具有第一离子，所述覆盖层的材料包括金属离子，所述第一离子和所述金属离子之间构成第一化学键；所述辅助层内具有所述金属离子和第二离子，所述第二离子和所述金属离子构成第二化学键，所述第二化学键键能低于所述第一化学键键能。
可选的，所述第一离子包括氯离子；所述第二离子包括氟离子。
可选的，所述金属包括钨。
可选的，所述覆盖层的形成工艺包括选择性原子层沉积工艺。
可选的，所述原子层沉积工艺的工艺参数包括：反应气体包括氯化钨和氢气，反应温度范围为400摄氏度至500摄氏度。
可选的，所述第一导电层和所述第二导电层的形成工艺包括第二选择性沉积工艺。
可选的，所述第二选择性沉积工艺的工艺参数包括：反应气体包括六氟化钨和氢气，反应温度范围为300摄氏度至400摄氏度。
可选的，所述第一导电层和所述第二导电层的形成方法包括：在所述第一开口和所述第二开口内沉积导电材料层，直到所述第一开口和所述第二开口被填满；平坦化所述导电材料层直到暴露出所述第二介质层。
可选的，其特征在于，所述导电材料层在所述辅助层表面的生长速率高于在所述导电结构表面的生长速速率。
可选的，所述第一导电层和所述第二导电层的材料包括钨。
可选的，所述辅助层的厚度范围为1纳米至10纳米。
可选的，所述导电结构的材料包括钴。
与现有技术相比，本发明的技术方案具有以下有益效果：
本发明技术方案提供的半导体结构的形成方法中，采用第一选择性沉积工艺在所述覆盖层表面形成辅助层，在所述第一开口内形成第一导电层，在所述第二开口内形成第二导电层，所述第一导电层材料在所述辅助层表面的生长速率高于所述第一导电层材料在所述覆盖层表面的生长速率，以缩小第一导电层的材料在所述辅助层表面的第一开口内的生长速率与第二导电层的材料在导电结构表面的第二开口内的生长速率之间的差异，从而减少辅助层上的第一开口在被填满之前提前封闭的情况，进而提高所形成的半导体结构的性能。
进一步，所述覆盖层内具有第一离子，所述覆盖层的材料包括金属离子，所述第一离子和所述金属离子之间构成第一化学键；所述辅助层内具有所述金属离子和第二离子，所述第二离子和所述金属离子构成第二化学键，所述第二化学键键能低于所述第一化学键键能，所述第二化学键相对所述第一化学键更容易被打破，提高了在所述辅助层表面形成所述第一导电层的材料的反应速率。
进一步，所述第一离子包括氯离子，所述第二离子包括氟离子，所述辅助层内具有钨-氟键，钨-氟键的存在为在所述辅助层形成钨材料提供准备，缩短了第一导电层形成过程吸附六氟化钨气体的时间，提升了在辅助层表面形成钨材料的生长速率，进一步使钨材料在所述第一开口内的生长速率高于在所述第二开口内的生长速率，从而减少了所述第一开口在被填满之前提前封闭的情况，从而提高所形成的半导体结构的性能。
附图说明
图1至图5是一种半导体结构形成过程的剖面示意图；
图6至图12是本发明一实施例中的半导体结构的形成方法各步 骤的结构示意图。
具体实施方式
需要注意的是，本说明书中的“表面”、“上”，用于描述空间的相对位置关系，并不限定于是否直接接触。
如背景技术所述，采用现有的金属互连线工艺形成的半导体结构，性能亟需提升。现结合一种半导体结构的形成方法进行说明分析。
图1至图5是一种半导体结构形成过程的剖面示意图。
请参考图1，提供衬底101，位于所述衬底101上具有栅极结构，所述栅极结构包括金属栅101和栅介质层102，位于所述栅极结构侧壁具有侧墙103，位于所述侧墙103两侧的所述衬底101内具有源漏区104，且位于所述衬底100上的还具有层间介质层105，所述层间介质层105位于所述侧墙103侧壁，且暴露出所述栅极结构顶部表面。
请参考图2，在所述金属栅101表面形成覆盖层106；在所述层间介质层105、所述栅极结构表面和所述侧墙102顶部形成第一刻蚀停止层108；在所述第一刻蚀停止层108表面形成第一介质层107。
请参考图3，在所述第一介质层107、所述第一刻蚀停止层108和所述层间介质层105内形成第一开口(图中未标出)，所述第一开口暴露出所述源漏区104；在所述第一开口内形成导电结构109。
请参考图4，在所述导电结构109和所述第一介质层107表面形成第二刻蚀停止层110；在所述第二刻蚀停止层110表面形成第二介质层112；在所述第二介质层112、第二刻蚀停止层110、第一介质层107和第一刻蚀停止层108内形成第二开口112，所述第二开口112暴露出所述覆盖层106顶部表面；在所述第二介质层112和所述第二刻蚀停止层110内形成第三开口113，所述第三开口113暴露出所述导电结构109顶部表面。
请参考图5，在所述第二开口112和所述第三开口113内形成金 属层114。
上述方法用于金属互连线工艺中。所述覆盖层106的材料为钨，采用原子层沉积(ALD)工艺形成，形成的金属钨在所述金属栅101表面具有很好的选择性，且有利于形成均匀且致密的覆盖层106。所述原子层沉积工艺形成过程不含氟离子，避免氟离子对所述栅极结构的功函数层的不利影响，但沉积速率慢。所述导电结构109的材料为钴。所述金属层114的材料也为钨，由于化学气相沉积(CVD)工艺具有较好的台阶覆盖率，且相对原子层沉积工艺耗费时间短，因此所述金属层114采用化学气相沉积工艺形成。
然而，由于原子层沉积工艺采用氯化钨(如WCl 3)和氢反应形成，使得覆盖层106中具有大量的钨-氯键。原子层沉积工艺中，氯化钨和氢反应的反应温度为460摄氏度。而采用化学气相沉积工艺形成金属层114的过程中，金属钨在金属材料表面选择性的生长，反应气体包括六氟化钨和氢气，反应温度低于400摄氏度。在低于400摄氏度的条件下，覆盖层106中存在的大量的钨-氯键比反应气体六氟化钨中的钨-氟键更稳定，钨-氯键的存在使化学气相沉积工艺中钨材料膜的形成变的困难，从而导致在覆盖层106表面钨材料的生长速度远低于在导电结构109表面的钨材料的生长速度。另外，所述第二开口112的深度高于所述第三开口113的深度，进而，更容易导致所述三开口113被钨材料填满后，所述第二开口112尚未被钨材料填满，钨材料在填满所述第三开口113后继续生长以至于可能覆盖到所述第二开口112表面，使所述第二开口112提前封闭的情况发生，从而导致所述第二开口112内形成的金属层114产生孔洞等缺陷，影响所述金属层114的导电性能，降低所形成的半导体结构的性能。
为了解决上述问题，本发明提供的一种半导体结构的形成方法中，采用第一选择性沉积工艺在所述覆盖层表面形成辅助层，在所述第一开口内形成第一导电层，在所述第二开口内形成第二导电层，所述第一导电层材料在所述辅助层表面的生长速率高于所述第一导电 层材料在所述覆盖层表面的生长速率，以缩小第一导电层的材料在所述辅助层表面的第一开口内的生长速率与第二导电层的材料在导电结构表面的第二开口内的生长速率之间的差异，从而减少辅助层上的第一开口在被填满之前提前封闭的情况，进而提高所形成的半导体结构的性能。
为使本发明的上述目的、特征和有益效果能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图6至图12是本发明一实施例中的半导体结构的形成方法各步骤的结构示意图。
请参考图6，提供衬底。
本实施例中，所述衬底包括基底201、位于所述基底201上的栅极结构和位于所述基底201上的层间介质层202，所述层间介质层202还位于所述栅极结构侧壁，且暴露出所述栅极结构顶部表面。
所述栅极结构包括栅极层203和位于所述栅极层203侧壁的侧墙204。
所述栅极层203的材料包括金属。本实施例中，所述栅极层203的材料为铝。
所述栅极结构的形成方法包括：在所述基底201上形成伪栅极(图中未标出)；在所述伪栅极侧壁形成所述侧墙204；在所述基底201表面形成层间介质层202，所述层间介质层202暴露出所述伪栅极顶部表面；刻蚀去除所述伪栅极，在所述层间介质层202内形成凹槽(图中未标出)；在所述凹槽内所述栅极层203。
本实施例中，形成所述凹槽后，形成所述栅极层203前，还在所述凹槽侧壁和底部形成栅介质层205。所述栅介质层205的材料包括高K介质材料。
本实施例中，所述栅极结构还包括位于所述栅介质层205和所述 栅极层203之间的功函数层(图中未标出)。
本实施例中，所述衬底200还包括位于所述栅极结构两侧基底201内的源漏层206。
请参考图7，在部分所述衬底上形成覆盖层207；采用第一选择性沉积工艺在所述覆盖层207表面形成辅助层208。
所述辅助层208用于后续提高第一导电层的材料在所述覆盖层207的生长速率。
本实施例中，所述覆盖层207位于所述栅极结构202顶部表面，具体地，所述覆盖层207位于所述栅极层203顶部表面。所述覆盖层207用于阻挡离子向所述栅极层203内扩散，利于维持所形成的器件的阈值电压等性能。
所述覆盖层207的材料包括金属，所述金属包括钨。本实施例中，所述金属为钨。
所述覆盖层207的形成工艺包括选择性原子层沉积工艺。
本实施例中，所述原子层沉积工艺的工艺参数包括：反应气体包括氯化钨和氢气，反应温度范围为400摄氏度至500摄氏度。氯化钨和氢气反应形成钨，所述选择性原子层沉积工艺，使钨材料在所述栅极层203表面具有很好的选择性，且有利于形成均匀且致密的材料膜。所述覆盖层207的形成过程不含氟离子，避免氟离子对所述栅极结构的功函数层的不利影响，但受限于原子层沉积工艺，沉积速率较慢。
所述覆盖层207内具有第一离子，所述覆盖层207的材料包括金属离子，所述第一离子和金属离子之间构成第一化学键。
具体地，所述第一离子包括氯离子。本实施例中，所述覆盖层207采用氯化钨和氢气反应形成，不可避免地会在所述覆盖层207内引入氯离子，所述第一离子为氯离子。另外，所述覆盖层207的材料 为钨离子，氯离子和钨离子之间构成的第一化学键为钨-氯键。钨-氯键相对于钨-氟键不容易被打破，在所述覆盖层207表面采用六氟化钨和氢气反应形成钨材料的第一导电层时，由于钨-氯键的存在，使钨材料生长变得困难。
所述辅助层208内具有所述金属离子和第二离子，所述第二离子和所述金属离子构成第二化学键，所述第二化学键键能低于所述第一化学键键能。所述第二化学键相对所述第一化学键更容易被打破，提高了后续在所述辅助层208表面形成所述第一导电层的材料的反应速率。
具体地，所述辅助层208的材料包括钨；所述第二离子包括氟离子。本实施例中，所述辅助层208的材料为钨；所述第二离子为氟离子。
所述辅助层208的形成工艺包括化学气相沉积工艺；所述化学气相沉积工艺的工艺参数包括：反应气体包括六氟化钨和氢气，反应温度范围为300度至400摄氏度。
具体地，本实施例中，所述辅助层208内具有钨-氟键，所述覆盖层207内具有氯-钨键，由于钨-氟键的键能低于氯-钨键的键能，相对于在所述覆盖层207表面形成第一导电层，在所述辅助层208表面生长钨材料相对容易。
所述辅助层208的厚度范围为1纳米至10纳米。在后续形成第一开口暴露出所述辅助层208的刻蚀工艺中可能会对所述辅助层208的造成损伤，所述辅助层208若厚度过小(即低于1纳米)，则所述辅助层208可能会因被消耗而起不到作用；若所述辅助层208的厚度过大，即大于10纳米。一方面，可能使后续在所述衬底表面形成的第一介质层210材料膜的表面不平整，影响器件性能。另一方面，也会造成不必要的工艺浪费。
请参考图8，在所述衬底和所述辅助层208表面形成第一介质层 210。
所述第一介质层210的材料为介质材料，所述介质材料包括氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅和碳氮氧化硅中的一种或多种。
本实施例中，形成所述第一介质层210前，还在所述衬底和所述辅助层208表面形成第一刻蚀停止层209。在后续形成第一开口时，所述第一刻蚀停止层209用于减少对所述辅助层208的刻蚀损伤。
请参考图9，在所述第一介质层210内形成导电结构211，所述第一介质层210顶部表面与所述导电结构211顶表面齐平。
本实施例中，所述导电结构211的底部深入所述衬底内，且位于所述源漏层206表面。
所述导电结构211的形成方法包括：在所述第一介质层210表面形成第一图形化层(图中未标出)，所述第一图形化层暴露出部分所述第一介质层210；以所述第一图形化层为掩膜，刻蚀所述第一介质层210、所述第一刻蚀停止层209、层间介质层202，直到暴露出所述源漏层206表面；在所述第一介质层、所述第一刻蚀停止层209和所述层间介质层206内形成第三开口(图中未标出)；在所述第三开口内沉积金属材料，形成所述导电结构211。
所述导电结构211的材料包括钴。钴材料作为导线材料，具有较好的填充能力和导电性，使形成的器件导电性能强、功耗更低。
请参考图10，在所述第一介质层210和所述导电结构211表面形成第二介质层213。
所述第二介质层213的材料为介质材料，所述介质材料包括氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅和碳氮氧化硅中的一种或多种。
本实施例中，形成所述第二介质层213前，还在所述第一介质层 210和所述导电结构211表面形成第二刻蚀停止层212。在后续形成第二开口时，所述第二刻蚀停止层212用于减少对所述导电结构211的刻蚀损伤。
请参考图11，形成第一开口214和第二开口215，所述第一开口214位于所述第二介质层213和所述第一介质层210内，且所述第一开口214暴露出所述辅助层208，所述第二开口215位于所述第二介质层213内，且所述第二开口215暴露出所述导电结构211顶部表面。
所述第一开口214的形成工艺包括干法刻蚀工艺；所述第二开口215的形成工艺包括干法刻蚀工艺。所述干法刻蚀工艺有利于形成较好形貌的开口。
本实施例中，所述第二开口215的形成方法包括：在所述第二介质层213表面形成第二图形化层，所述第二图形化层暴露出部分所述导电结构211上的第二介质层213；以所述第二图形化层为掩膜，刻蚀所述第二介质层213，直到暴露出所述导电结构211。
本实施例中，所述第一开口214的形成方法包括:在所述第二介质层213表面和所述第二开口215内形成第三图形化层，所述第三图形化层暴露出部分所述辅助层208上的第二介质层213；以所述第三图形化层为掩膜，刻蚀所述第二介质层213和所述第一介质层210，直到暴露出所述辅助层208；形成所述辅助层208后，去除所述第三图形化层。本实施例中，所述第一开口214在所述第二开口215后形成。其他实施例中，对形成所述第一开口214和所述第二开口215的先后顺序不做要求。
请参考图12，在所述第一开口214内形成第一导电层216，在所述第二开口215内形成第二导电层217，所述第一导电层216的材料在所述辅助层208表面的生长速率高于所述第一导电层216的材料在所述覆盖层207表面的生长速率。
所述第一导电层216的材料在所述辅助层208表面的生长速率高 于所述第一导电层216的材料在所述覆盖层207表面的生长速率，以缩小第一导电层216的材料在第一开口214内的生长速率与第二导电层217的材料在第二开口215内的生长速率之间的差异，从而减少所述辅助层208上的第一开口214在被填满之前提前封闭的情况，进而提高所形成的半导体结构的性能。
所述第一导电层216和所述第二导电层217的材料包括钨。
所述第一导电层216和所述第二导电层217的形成方法包括：在所述第一开口214和所述第二开口215内沉积导电材料层(图中未标出)，直到所述第一开口214和所述第二开口215被填满；平坦化所述导电材料层直到暴露出所述第二介质层213。所述第一导电层216和所述第二导电层217在同一工艺中，采用同一金属材料同时沉积形成，有利于降低生产成本。
所述第一导电层216和所述第二导电层217的形成工艺包括第二选择性沉积工艺。具体地，所述第一导电层216和所述第二导电层217的形成工艺为化学气相沉积工艺。所述化学气相沉积工艺具有较好的台阶覆盖率，且相对于原子层沉积工艺具有耗时短、低成本的特点。
所述第二选择性沉积工艺的工艺参数包括：反应气体包括六氟化钨和氢气，反应温度范围为300摄氏度至400摄氏度。
所述导电材料层在所述辅助层208表面的生长速率高于在所述导电结构211表面的生长速率。由于所述第一开口214的深度高于所述第二开口215的深度，容易导致在所述第一开口214尚未被填满，所述第二开口215被填满后，进一步地沉积使所述第二开口215内的第二导电层的材料继续生长，以至于覆盖到所述第一开口214上方，导致第一开口214提前封闭的情况。本实施例中，所述辅助层208具有钨-氟键，钨-氟键的存在为形成钨材料提供准备，缩短了第一导电层形成过程吸附六氟化钨气体的时间，提升了在辅助层208表面形成钨材料的生长速率，进一步使钨材料在所述第一开口214内的生长速 率高于在所述第二开口215内的生长速率，从而减少了所述第一开口214在被填满之前提前封闭的情况，从而提高所形成的半导体结构的性能。
相应的，本发明一实施例还提供一种上述方法所形成的半导体结构，请继续参考图12，包括：衬底；位于部分所述衬底上的覆盖层207；位于所述覆盖层207表面的辅助层208；位于所述衬底和所述辅助层208表面的第一介质层210；位于所述第一介质层210内的导电结构211，所述第一介质层210顶部表面与所述导电结构211顶表面齐平；位于在所述第一介质层210和所述导电结构211表面的第二介质层213；位于所述第二介质层213和所述第一介质层210内的第一开口214(如图11所示)，且所述第一开口214暴露出所述辅助层208，位于所述第二介质层213内的第二开口215(如图11所示)，且所述第二开口215暴露出所述导电结构211顶部表面；位于所述第一开口214内的第一导电层216，位于所述第二开口215内的第二导电层217。
所述衬底包括基底201、位于所述基底201上的栅极结构和位于所述基底201上的层间介质层211(如图11所示)，所述层间介质层211还位于所述栅极结构侧壁，且暴露出所述栅极结构顶部表面；所述覆盖层207位于所述栅极结构顶部表面。
所述衬底还包括位于所述栅极结构两侧衬底内的源漏层206；所述导电结构211的底部深入所述衬底内，且位于所述源漏层206表面。
所述覆盖层207的材料包括金属，所述金属包括钨。本实施例中，所述覆盖层207的材料为钨。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (21)

  1. 一种半导体结构，其特征在于，包括：
    衬底；
    位于部分所述衬底上的覆盖层；
    位于所述覆盖层表面的辅助层；
    位于所述衬底和所述辅助层表面的第一介质层；
    位于所述第一介质层内的导电结构，所述第一介质层顶表面与导电结构顶表面齐平；
    位于在所述第一介质层和所述导电结构表面的第二介质层；
    位于所述第二介质层和所述第一介质层内的第一开口，且所述第一开口暴露出所述辅助层，位于所述第二介质层内的第二开口且所述第二开口暴露出所述导电结构顶部表面；
    位于所述第一开口内的第一导电层，位于所述第二开口内的第二导电层。
  2. 如权利要求1所述的半导体结构，其特征在于，所述衬底包括基底、位于所述基底上的栅极结构和位于所述基底上的层间介质层，所述层间介质层还位于所述栅极结构侧壁，且暴露出所述栅极结构顶部表面，所述覆盖层位于所述栅极结构顶部表面。
  3. 如权利要求2所述的半导体结构，其特征在于，所述衬底还包括位于所述栅极结构两侧衬底内的源漏层，所述导电结构的底部深入所述衬底内，且位于所述源漏层表面。
  4. 如权利要求1所述的半导体结构，其特征在于，所述覆盖层的材料包括金属。
  5. 一种半导体结构的形成方法，其特征在于，包括：
    提供衬底；
    在部分所述衬底上形成覆盖层；
    采用第一选择性沉积工艺在所述覆盖层表面形成辅助层；
    在所述衬底和所述辅助层表面形成第一介质层；
    在所述第一介质层内形成导电结构，所述第一介质层顶部表面与所述导电结构顶表面齐平；
    在所述第一介质层和所述导电结构表面形成第二介质层；
    形成第一开口和第二开口，所述第一开口位于所述第二介质层和所述第一介质层内且第一开口暴露出所述辅助层，所述第二开口位于所述第二介质层内且所述第二开口暴露出所述导电结构顶部表面；
    在所述第一开口内形成第一导电层，在所述第二开口内形成第二导电层，所述第一导电层的材料在所述辅助层表面的生长速率高于所述第一导电层的材料在所述覆盖层表面的生长速率。
  6. 如权利要求5所述的半导体结构的形成方法，其特征在于，所述辅助层的材料包括钨。
  7. 如权利要求6所述的半导体结构的形成方法，其特征在于，所述辅助层的形成工艺包括化学气相沉积工艺；所述化学气相沉积工艺的工艺参数包括：反应气体包括六氟化钨和氢气，反应温度范围为300摄氏度至400摄氏度。
  8. 如权利要求5所述的半导体结构的形成方法，其特征在于，所述衬底包括基底、位于所述基底上的栅极结构和位于所述基底上的层间介质层，所述层间介质层还位于所述栅极结构侧壁，且暴露出所述栅极结构顶部表面；所述覆盖层位于所述栅极结构顶部表面。
  9. 如权利要求8所述的半导体结构的形成方法，其特征在于，所述衬底还包括位于所述栅极结构两侧衬底内的源漏层；所述导电结构的底部深入所述衬底内，且位于所述源漏层表面。
  10. 如权利要求5所述的半导体结构的形成方法，其特征在于，所述覆盖层内具有第一离子，所述覆盖层的材料包括金属离子，所述第一离子和所述金属离子之间构成第一化学键；所述辅助层内具有所述金属离子和第二离子，所述第二离子和所述金属离子构成第二化学键，所述第二化学键键能低于所述第一化学键键能。
  11. 如权利要求10所述的半导体结构的形成方法，其特征在于，所述第一离子包括氯离子；所述第二离子包括氟离子。
  12. 如权利要求5所述的半导体结构的形成方法，其特征在于，所述金属包括钨。
  13. 如权利要求12所述的半导体结构的形成方法，其特征在于，所述覆盖层的形成工艺包括选择性原子层沉积工艺。
  14. 如权利要求13所述的半导体结构的形成方法，其特征在于，所述原子层沉积工艺的工艺参数包括：反应气体包括氯化钨和氢气，反应温度范围为400摄氏度至500摄氏度。
  15. 如权利要求5所述的半导体结构的形成方法，其特征在于，所述第一导电层和所述第二导电层的形成工艺包括第二选择性沉积工艺。
  16. 如权利要求15所述的半导体结构的形成方法，其特征在于，所述第二选择性沉积工艺的工艺参数包括：反应气体包括六氟化钨和氢气，反应温度范围为300摄氏度至400摄氏度。
  17. 如权利要求15所述的半导体结构的形成方法，其特征在于，所述第一导电层和所述第二导电层的形成方法包括：在所述第一开口和所述第二开口内沉积导电材料层，直到所述第一开口和所述第二开口被填满；平坦化所述导电材料层直到暴露出所述第二介质 层。
  18. 如权利要求15所述的半导体结构的形成方法，其特征在于，所述导电材料层在所述辅助层表面的生长速率高于在所述导电结构表面的生长速率。
  19. 如权利要求5所述的半导体结构的形成方法，其特征在于，所述第一导电层和所述第二导电层的材料包括钨。
  20. 如权利要求5所述的半导体结构的形成方法，所述辅助层的厚度范围为1纳米至10纳米。
  21. 如权利要求5所述的半导体结构的形成方法，其特征在于，所述导电结构的材料包括钴。
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