WO2022247271A1 - 薄膜晶体管及其制备方法和阵列基板、显示器件 - Google Patents

薄膜晶体管及其制备方法和阵列基板、显示器件 Download PDF

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Publication number
WO2022247271A1
WO2022247271A1 PCT/CN2021/142744 CN2021142744W WO2022247271A1 WO 2022247271 A1 WO2022247271 A1 WO 2022247271A1 CN 2021142744 W CN2021142744 W CN 2021142744W WO 2022247271 A1 WO2022247271 A1 WO 2022247271A1
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Prior art keywords
thin film
film transistor
gate insulating
layer
substrate
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English (en)
French (fr)
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夏玉明
卓恩宗
郑浩旋
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HKC Co Ltd
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HKC Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the application belongs to the field of display technology, and in particular relates to a thin film transistor, a preparation method thereof, an array substrate, and a display device.
  • High energy light test is to check the reliability parameters of liquid crystal display panels under high-intensity long-term light. It is an important indicator of panel display quality. It can reflect panel materials and thin film transistors (Thin Film Transistor, TFT) Controls the stability of the device.
  • TFT Thi Film Transistor
  • the electric field generated by the upper and lower substrates is controlled by the thin film transistor switch tube to change the deflection direction of the liquid crystal molecules, thereby realizing the light intensity of the transparent pixels. control.
  • TFT switch tubes usually consist of three electrodes (gate, source and drain), a gate insulating film and a semiconductor active layer.
  • the gate insulating film is one of the important materials that affect the performance of the thin film transistor.
  • the surface of the gate insulating film contained in the existing thin-film transistors contains a large number of Si-H and Si-Si bonds. These bonds are very weak bonds, which are prone to breakage under high-energy light irradiation, resulting in poor film quality.
  • Thin-film transistors The threshold voltage of the device drifts, which leads to the deterioration of the thin film transistor device, resulting in a decrease in the performance of the display device such as high brightness.
  • the purpose of the embodiments of the present application is to overcome the above-mentioned deficiencies in the prior art, provide a thin film transistor with a modified gate insulating film and a preparation method thereof, endow the thin film transistor with stable and excellent electrochemical properties including threshold voltage, and solve the current problems.
  • the surface of the gate insulating layer contained in the thin film transistor contains a large number of unstable chemical bonds, which leads to the drift of the threshold voltage of the thin film transistor device and the deterioration of the thin film transistor device.
  • Another purpose of the embodiments of the present application is to provide an array substrate and a display device of a thin film transistor, so as to solve the performance degradation of the existing array substrate and display device due to the drift and deterioration of the threshold voltage of the thin film transistor device, such as high brightness of the display device. technical problems.
  • one aspect of the present application provides a method for manufacturing a thin film transistor.
  • the preparation method of the thin film transistor comprises the following steps:
  • the gate (2), gate insulating layer (3), active layer (4), n + amorphous silicon layer (5), source electrode (6) and leakage are sequentially formed on the surface of the substrate.
  • electrode (7) to form a thin film transistor; the method for forming a gate insulating layer (3) includes the following steps:
  • the temperature of the gate insulating film is 200-300° C., and the time of the heat modification treatment is 10-60 s.
  • the temperature of the gate insulating film is 230-270° C.
  • the time for thermal modification treatment is 20-40 s.
  • the method for thermally modifying the gate insulating film includes the following steps:
  • heat treatment is performed on the gate insulating film, so that a chemical reaction occurs between the surface of the gate insulating film and the gas of nitrogen element and/or oxygen, and the gate insulating film Si-N or/and Si-O chemical bonds are formed on the surface of the film.
  • the method for thermally modifying the gate insulating film includes the following steps:
  • the substrate (1) is subjected to heating treatment until the temperature of the preset thermal modification treatment is adjusted, and heat preservation treatment is performed; so that a chemical reaction occurs between the surface of the gate insulating film and nitrogen gas and/or oxygen.
  • the nitrogen-containing gas environment and/or the oxygen-containing gas pass through the surface of the gate insulating film at a flow rate of 1000-5000 sccm.
  • the nitrogen-containing gas includes at least one of N 2 and NH 3 .
  • the material of the formed gate insulating film includes an insulating compound of nitrogen and silicon.
  • the insulating compound includes at least one of silicon nitride, silicon oxynitride, and silicon fluoride nitride.
  • a flat layer (8) is formed on the outer surface of the gate insulating layer (3) provided with the source electrode (6), the drain electrode (7), the n + amorphous silicon layer (5), and the active layer (4), so as to Covering the source electrode (6), the drain electrode (7), the n + amorphous silicon layer (5), and the active layer (4).
  • the thin film transistor of the present application includes a gate insulating layer (3) and a gate (2) formed on the substrate (1), and the gate insulating layer (3) is laminated with the surface of the substrate (1) provided with the gate (2) , and cover the gate (2), the material of the gate insulating layer (3) contains silicon element, and the surface of the gate insulating layer (3) contains Si-N or/and Si-O chemical bonds.
  • the material of the insulating compound includes an insulating compound containing nitrogen and silicon.
  • the insulating compound includes at least one of silicon nitride, silicon oxynitride, and silicon fluoride nitride.
  • an active layer (4) is provided on the surface of the gate insulating layer (3) away from the substrate (1), an n + amorphous silicon layer (5) is provided on the outside of the active layer (4), and an n + + The outer surface of the amorphous silicon layer (5) is provided with a source electrode (6) and a drain electrode (7).
  • the flat layer (8) is formed on the surface of the active layer (4) provided with the source electrode (6) and the drain electrode (7), and covers the source electrode (6) , a drain electrode (7), an n + amorphous silicon layer (5) and an active layer (4).
  • a thin film transistor array substrate includes a base substrate and a thin film transistor disposed on the base substrate, and the thin film transistor is a thin film transistor of the present application.
  • a display device in yet another aspect of the present application, includes a thin film transistor array substrate, and the thin film transistor array substrate is the thin film transistor array substrate of the present application.
  • the preparation method of the thin-film transistor of the present application is through thermal modification treatment on the surface of the gate insulating film containing silicon elements, and Si-N or/and Si-O chemical bonds with high bond energy are formed on the surface, and the chemical bond energy of these bonds is high.
  • the chemical properties are stable, and these chemical bonds can form a protective layer on the modified surface of the gate insulating film, and will not damage the film quality of the modified gate insulating film when exposed to high light, thus endowing the prepared thin film transistor device such as
  • the performance such as threshold voltage is stable, which effectively overcomes the deficiency that the gate insulating layer contained in the existing thin film transistor has poor reliability under high-intensity light, which leads to unstable performance of the thin film transistor device.
  • the preparation method of the thin film transistor of the present application is easy to control the process, can make the performance of the prepared thin film transistor stable, and the efficiency is high, and the cost is reduced.
  • the thin film transistor of the present application contains Si-N or/and Si-O chemical bonds on the surface of the gate insulating layer (3), thereby forming a protective layer on the surface of the gate insulating layer (3), so that The film quality of the modified gate insulating layer (3) will not be damaged when irradiated by high light, so that the performance of the thin film transistor device such as the threshold voltage is stable.
  • the performance of the thin film transistor array substrate is stable, and the performance such as high brightness of the display device using the thin film transistor array substrate is improved, and the display performance is stable. high quality.
  • FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of the Si-N chemical bond contained on the surface of the gate insulating layer contained in the thin film transistor of the embodiment of the present application;
  • FIG. 3 is a schematic process flow diagram of a method for preparing a thin film transistor according to an embodiment of the present application
  • FIG. 4 is a schematic flowchart of a step of forming a planar layer based on the manufacturing method of the thin film transistor of the embodiment of the present application shown in FIG. 3 .
  • the term "and/or” describes the association relationship of associated objects, indicating that there may be three relationships, for example, A and/or B may mean: A exists alone, A and B exist simultaneously, and B exists alone Happening. Among them, A and B can be singular or plural.
  • the character "/" generally indicates that the contextual objects are an "or" relationship.
  • At least one means one or more, and “multiple” means two or more.
  • At least one of the following” or similar expressions refer to any combination of these items, including any combination of single or plural items.
  • “at least one (one) of a, b, or c”, or “at least one (one) of a, b, and c” can mean: a, b, c, a-b ( That is, a and b), a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.
  • sequence numbers of the above-mentioned processes do not mean the order of execution, and some or all steps may be executed in parallel or sequentially, and the execution order of each process shall be based on its functions and The internal logic is determined and should not constitute any limitation to the implementation process of the embodiment of the present application.
  • the weight of the relevant components mentioned in the description of the embodiments of the present application can not only refer to the specific content of each component, but also represent the proportional relationship between the weights of the various components.
  • the scaling up or down of the content of the fraction is within the scope disclosed in the description of the embodiments of the present application.
  • the mass described in the description of the embodiments of the present application may be ⁇ g, mg, g, kg and other well-known mass units in the chemical industry.
  • first and second are only used for descriptive purposes to distinguish objects such as substances from each other, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • first XX can also be called the second XX
  • second XX can also be called the first XX.
  • a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • the embodiment of the present application provides a thin film transistor.
  • the thin film transistor in the embodiment of the present application may be a conventional structure in the field or an improved structure based on an existing conventional structure.
  • the structure of the thin film transistor may be as shown in FIG. 1, which includes a gate 2 disposed on the substrate 1, and a gate formed, that is, stacked on the surface of the substrate 1 on which the gate 2 is disposed.
  • pole insulating layer 3 an active layer 4 formed on the surface of the gate insulating layer 3 that is away from the substrate 1, an n + amorphous silicon layer 5 formed on the outer surface of the oxide active layer 4, and the arrangement source electrode 6 and drain electrode 7 on the outer surface of the n + amorphous silicon layer.
  • the gate insulating layer 3 covers the gate 2 .
  • the structure shown in FIG. 1 is only an example of one structure of the thin film transistor in the embodiment of the present application, and the structure of the thin film transistor is not limited to the structure shown in FIG. 1 .
  • it contains a gate insulating layer, as shown in Figure 1.
  • the material of the gate insulating layer 3 contains silicon elements, and the surface of the gate insulating layer 3 contains Si-N or/and Si-O chemical bond.
  • the thin film transistor of the embodiment of the present application contains Si-N or/and Si-O chemical bonds on the surface of the gate insulating layer to form a protective layer on the surface of the gate insulating layer, so that it is exposed to high light It will not damage the film quality of the modified gate insulating layer, thus endowing the prepared thin film transistor device with stable performance such as threshold voltage.
  • the substrate 1 contained in the thin film transistor as shown in FIG. 1 may be a conventional substrate, which may be selected according to the requirements of actual display production.
  • it can be a hard material or a flexible material.
  • the material of the substrate 1 can be glass; when it is a flexible material, it can be a flexible polymer material or the like.
  • the gate 2 contained in the thin film transistor shown in FIG. 1 has no special requirements on the structure and material, and may be a conventional structure and material.
  • the gate insulating layer 3 contained in the thin film transistor shown in FIG. 1 contains silicon element as mentioned above, and contains Si—N or/and Si—O chemical bonds on the surface of the gate insulating layer 3 .
  • the chemical bond energy of the Si—N or/and Si—O chemical bond is significantly higher than the chemical bond energy of Si—H and Si—Si contained on the surface of the existing gate insulating layer.
  • the specific chemical bond energies of Si-H, Si-Si, Si-N and Si-O are shown in Table 1 below:
  • the surface of the gate insulating layer 3 contained in the thin film transistor contains chemical bonds Si-N or/and Si-O has high chemical bond energy, wherein, when the surface of the gate insulating layer 3 contains chemical bonds Si-N
  • the schematic diagram of the chemical bond structure is shown in Figure 2.
  • the chemical bond Si-N or/and Si-O has stable chemical properties and can form a stable protective layer on the surface of the gate insulating layer 3, thereby ensuring the stability of the chemical properties and working performance of the gate insulating layer 3 under high-energy light irradiation , so as to endow the prepared thin film transistor device of the embodiment of the present application with good stability in properties such as threshold voltage and the like.
  • the material of the gate insulating layer 3 contains silicon
  • the material of the gate insulating layer 3 includes an insulating compound of silicon, and further includes an insulating compound of nitrogen and silicon.
  • the The insulating compound includes at least one of silicon nitride, silicon oxynitride, and silicon fluoride nitride. The gate insulating layer 3 formed by the insulating compound can effectively ensure the formation of Si—N and/or Si—O chemical bonds on its surface.
  • the thickness and other dimensions of the gate insulating layer 3 may be conventional thicknesses.
  • the material of the active layer 4 contained in the thin film transistor as shown in FIG. 1 can be the material of the active layer of the existing thin film transistor, such as a-Si:H.
  • the material of the active layer 4 may also be other materials such as oxides and the like.
  • the thickness and other dimensions of the active layer 4 may also be conventional thicknesses.
  • n + amorphous silicon layer 5, the source electrode 6 and the drain electrode 7 contained in the thin film transistor shown in FIG. 1 can all be of conventional size and material of the thin film transistor.
  • the thin film transistor further includes a flat layer 8 formed on the surface of the active layer 4 provided with the source electrode 6 and the drain electrode 7 superior. As shown in FIG. 1 , the flat layer 8 covers the source electrode 6 , the drain electrode 7 , the n + amorphous silicon layer 5 , and the active layer 4 .
  • the planar layer 8 is used to make each layer of the photoelectric display device prepared subsequently exhibit good local and overall uniformity, and also play a role of insulation between devices.
  • the embodiment of the present application also provides a method for manufacturing the above-mentioned thin film transistor.
  • the preparation method of the thin film transistor of the embodiment of the present application includes the following steps:
  • the gate, gate insulating layer, active layer, n + amorphous silicon layer, source electrode and drain electrode are sequentially formed on the surface of the substrate to form thin film transistors and other components.
  • the method for forming the gate insulating layer comprises the following steps:
  • the process flow of the preparation method of the thin film transistor is shown in FIG. 3, including the following steps:
  • Step S01 forming a grid 2 on the outer surface of the substrate 1;
  • Step S02 forming a gate insulating film containing silicon on the surface of the substrate 1 on which the gate 2 is formed;
  • Step S03 Perform thermal modification treatment on the gate insulating film to generate Si-N or/and Si-O chemical bonds on the surface of the gate insulating film to form the gate insulating layer 3 as shown in FIG. 1 ;
  • Step S04 forming an active layer 4 on the surface of the modified gate insulating layer 3;
  • Step S05 forming an n + amorphous silicon layer 5 , a source electrode 6 and a drain electrode 7 sequentially on the surface of the active layer 4 .
  • the above-mentioned steps S01 and S02 are relative to the above-mentioned step (1).
  • the materials of the substrate 1 and the gate 2 in the step S01 can be selected from the materials of conventional substrates of thin film transistors.
  • the method of forming the gate 2 may be to form the gate on the surface of the substrate according to the conventional preparation method of thin film transistors.
  • the gate insulating film formed in step S02 should be understood as the precursor of the gate insulating layer 3 contained in the thin film transistor above, and also the gate insulating layer 3 before modification. Therefore, the method of forming the gate insulating film can be It is formed according to a conventional preparation method of a thin film transistor.
  • the material for forming the gate insulating film is the material of the gate insulating layer 3 contained in the thin film transistor above, such as an insulating compound containing silicon elements, and an insulating compound further including nitrogen and silicon elements.
  • the insulating compound Including at least one of silicon nitride, silicon oxynitride, and silicon fluoride nitrogen.
  • Step S03 is equivalent to the above-mentioned step (2), by thermally modifying the gate insulating film, Si-N or/and Si-O chemical bonds are formed on the surface of the gate insulating film, that is, the formation of the above thin film transistor
  • the gate insulating layer 3 contained in the above thin film transistor has the function of the gate insulating layer 3 contained in it.
  • the temperature of the gate insulating film (that is, the gate insulating layer 3 before modification) is 200-300°C, further 230-270°C, specifically At 250°C, the time for thermal modification treatment is 10-60s, further 20-40s, specifically 30s.
  • the temperature and time of the thermal modification treatment have different modification effects on the gate insulating film, that is, the performance of the gate insulating layer 3 is different.
  • the time and temperature of the thermal modification treatment are controlled at Within the above range, the surface of the gate insulating layer 3 generated after thermal modification can generate abundant Si-N or/and Si-O chemical bonds with high chemical bond energy, and a protective layer can be formed on the surface of the gate insulating layer 3 , thereby significantly improving the stability of the gate insulating layer 3 under high-energy light irradiation conditions.
  • the thermal modification time and temperature are insufficient, the Si-N or/and Si-O chemical bonds with high chemical bond energy generated on the surface of the gate insulating film will have insufficient content, so that the gate insulating layer 3 will remain stable under high-energy light irradiation conditions. The stability performance is reduced. If the thermal modification time and temperature are prolonged, other negative products may be generated, resulting in impurities on the surface of the gate insulating layer 3 and affecting the stability of the gate insulating layer 3 under high-energy light irradiation conditions.
  • the method for thermally modifying the gate insulating film includes the following steps:
  • heat treatment is performed on the gate insulating film, so that a chemical reaction occurs between the surface of the gate insulating film and the gas of nitrogen element and/or oxygen, and the gate insulating film Si-N or/and Si-O chemical bonds are formed on the surface of the film.
  • the method for thermal modification treatment includes the following steps:
  • the nitrogen-containing gas or the oxygen-containing gas passes through the surface of the gate insulating film at a flow rate of 1000-5000 sccm, further 2500-3500 sccm, specifically 3000 sccm.
  • the nitrogen-containing gas includes at least one of N 2 and NH 3
  • the oxygen-containing gas may be oxygen.
  • the substrate of the gate insulating film containing silicon can be heat-treated first in the chamber, and then a nitrogen-containing gas environment or an oxygen-containing gas is introduced into the chamber to exhaust the air in the chamber, and the entire During the heat treatment process, the nitrogen-containing gas environment and/or the feeding of oxygen-containing gas are maintained, for example, according to a flow rate of 1000-5000 sccm.
  • a flow rate of nitrogen-containing gas and oxygen-containing gas in thermal modification, abundant Si-N or/and Si-O chemical bonds with high chemical bond energy are generated on the surface of the gate insulating film, thereby improving the generated
  • the gate insulating layer 3 has good stability under the condition of high-energy light irradiation.
  • the method for forming the active layer 4 in step S04 and the formation of the n + amorphous silicon layer 5, the source electrode 6 and the drain electrode 7 in the step S05 can be prepared according to existing methods such as preparing the active layer, n + amorphous silicon layer layer, source electrode and drain electrode to prepare active layer 4, n + amorphous silicon layer 5, source electrode 6 and drain electrode 7 respectively.
  • the above thin film transistor manufacturing method further includes step S06 as shown in FIG .
  • a flat layer 8 is formed on the outer surface of the gate insulating layer 3 of the amorphous silicon layer 5 and the active layer 4 to cover the source electrode 6 , the drain electrode 7 , the n + amorphous silicon layer 5 and the active layer 4 .
  • the planar layer 8 can be formed by but not only by spin coating. Its material can but not only choose vinyl chloride resin (PV).
  • the preparation method of the thin film transistor in the above-mentioned embodiments is to thermally modify the surface of the gate insulating film containing silicon elements to form Si-N or/and Si-O on the surface with high bond energy.
  • Chemical bonds, these bonds have high chemical bond energy and stable chemical properties, and these chemical bonds can form a protective layer on the modified surface of the formed gate insulating layer 3, and will not damage the modified gate insulating film ( That is to say, the film quality of the gate insulating layer 3) is damaged, thereby endowing the prepared thin film transistor device with stable performance such as threshold voltage, effectively overcoming the deterioration of the gate insulating layer contained in the existing thin film transistor under high-intensity light. Poor results in unstable performance of thin film transistor devices.
  • the preparation method of the thin film transistor is easy to control the process, can make the performance of the prepared thin film transistor stable, and the efficiency is high, and the cost is reduced.
  • the embodiment of the present application also provides a thin film transistor array substrate.
  • the thin film transistor array substrate includes a base substrate and thin film transistors arranged on the base substrate.
  • the thin film transistors in the thin film transistor array substrate are the thin film transistors mentioned above.
  • the thin film transistor array substrate may also include other components contained in the existing thin film transistor array substrate, such as gate lines, data lines, and pixel electrodes.
  • the thin film transistor array substrate is provided with pixel electrodes, as shown in FIG. 1
  • the drain electrode 7 included in the thin film transistor is connected to the pixel electrode.
  • the connection relationship and positional relationship between other components contained in the thin film transistor array substrate can be set according to the existing thin film transistor array substrate, and there is no special requirement for the embodiment of the present application.
  • the thin film transistor array substrate contains the above-mentioned thin film transistors, and because the surface of the gate insulating layer 3 contained in the above-mentioned thin film transistors contains Si-N or/and Si-O chemical bonds, it suffers from high light Good stability is maintained when irradiated, therefore, the working performance of the thin film transistor array substrate is stable, especially in the environment of high light irradiation.
  • an embodiment of the present application also provides a display device.
  • the display device includes a thin film transistor array substrate, and the thin film transistor array substrate is the above thin film transistor array substrate. Since the display device includes the thin film transistor array-based thin film transistor of the embodiment of the present application, the display device of the embodiment of the present application has stable display performance and high display quality.
  • Embodiment 1 thin film transistor embodiment
  • This embodiment provides a thin film transistor and a manufacturing method thereof.
  • the structure of the thin film transistor is shown in Figure 1, wherein the material of the substrate 1 is glass; the material of the gate insulating layer 3 is SiNx , and the surface of the SiNx layer contains Si-O and Si-N chemical bonds, and the active layer 4
  • the material of the flat layer 8 is a-Si:H, and the material of the flat layer 8 is PV.
  • the preparation method of the thin film transistor of the embodiment is prepared according to the process in Figure 3, wherein the thermal modification treatment method in step S03 includes the following steps:
  • the gate insulating film is heat-treated at 250°C for 10s, so that a chemical reaction occurs between the surface of the gate insulating film and oxygen, and the Si-O chemical bond is formed on the surface of the gate insulating film, and the gate insulating film is formed at the same time.
  • the surface of layer 3 contains Si-N chemical bonds.
  • oxygen is passed through the reaction system at a flow rate of 1000 sccm.
  • This embodiment provides a thin film transistor and a manufacturing method thereof.
  • the structure of the thin film transistor and its preparation method are the same as in Example A1.
  • the difference from the embodiment A1 is that the gate insulating film is heat-treated at 250° C. for 60 s, and oxygen is passed through the reaction system at a flow rate of 5000 sccm.
  • This embodiment provides a thin film transistor and a manufacturing method thereof.
  • the structure of the thin film transistor and its preparation method are the same as in Example A1.
  • the difference from the embodiment A1 is that the gate insulating film is heat-treated at 250° C. for 30 s in a nitrogen environment, and oxygen is passed through the reaction system at a flow rate of 3000 sccm.
  • This embodiment provides a thin film transistor and a manufacturing method thereof.
  • the structure of the thin film transistor and its preparation method are the same as in Example A1.
  • the difference from the embodiment A1 is that the gate insulating film is heat-treated at 200° C. for 30 seconds in an ammonia atmosphere, and oxygen is passed through the reaction system at a flow rate of 3000 sccm, and the material of the gate insulating film is silicon oxynitride.
  • This comparative example provides a thin film transistor, the structure of which is the same as in Example A1, the difference is that the gate insulating layer 3 contained in the thin film transistor of this comparative example is a SiN x layer, that is, compared with Example 1, the thin film of this comparative example The gate insulating layer 3 contained in the transistor does not undergo the thermal modification treatment in step S03 in Example 1, that is, the surface of the gate insulating layer 3 contained in the thin film transistor of this comparative example is the surface of a conventional SiNx layer.
  • Embodiment 2 Embodiment of Thin Film Transistor Array Substrate
  • Embodiment B1 to Embodiment B4 respectively provide a thin film transistor array substrate.
  • the thin film transistor array substrate in each embodiment includes a base substrate and thin film transistors disposed on the base substrate.
  • the thin film transistors contained in the thin film transistor array substrate provided in embodiment B1 are the thin film transistors provided in embodiment A1
  • the thin film transistors contained in the thin film transistor array substrate provided in embodiment B2 are the thin film transistors provided in embodiment A2.
  • the thin film transistors contained in the thin film transistor array substrate provided in B3 are the thin film transistors provided in embodiment A3, and the thin film transistors contained in the thin film transistor array substrate provided in embodiment B4 are the thin film transistors provided in embodiment A4.
  • Embodiment 3 embodiment of a thin film transistor display device
  • Embodiment C1 to Embodiment C4 respectively provide a display device.
  • Display devices in various embodiments include a thin film transistor array substrate.
  • the thin film transistors contained in the thin film transistor array substrate provided in embodiment C1 are the thin film transistors provided in embodiment B1
  • the thin film transistors contained in the thin film transistor array substrate provided in embodiment C2 are the thin film transistors provided in embodiment B2.
  • the thin film transistors contained in the thin film transistor array substrate provided by C3 are the thin film transistors provided by embodiment B3, and the thin film transistors contained in the thin film transistor array substrate provided by embodiment C4 are the thin film transistors provided by embodiment B4.
  • Example A1 to Example A4 and Comparative Example A1 were characterized by electrical characteristic values.
  • the measured results are shown in Table 2 below:

Landscapes

  • Thin Film Transistor (AREA)

Abstract

本申请公开了一种薄膜晶体管及其制备方法和阵列基板、显示器件。薄膜晶体管包括栅极绝缘层（3），且栅极绝缘层（3）的材料含有硅元素，且栅极绝缘层（3）的表面上含有Si-N或/和Si-O化学键。薄膜晶体管的制备方法包括步骤有：在形成有栅极的基板（1）表面上形成含硅元素的栅极绝缘膜；对栅极绝缘膜进行热改性处理在栅极绝缘膜表面生成Si-N或/和Si-O化学键。薄膜晶体管阵列基板、显示器件均含有薄膜晶体管。薄膜晶体管在栅极绝缘层（3）表面上含有Si-N或/和Si-O化学键，薄膜晶体管器件如阈值电压等性能稳定。薄膜晶体管的制备方法工艺易控，制备的薄膜晶体管性能稳定，薄膜晶体管阵列基板性能和显示器件的显示质量均得以提高。

Description

薄膜晶体管及其制备方法和阵列基板、显示器件
本申请要求于2021年05月27日提交中国专利局，申请号为202110584006.8，申请名称为“薄膜晶体管及其制备方法和阵列基板、显示器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于显示技术领域，具体涉及一种薄膜晶体管及其制备方法和阵列基板、显示器件。
 背景技术
高光亮测试（High energy light test）是检查液晶显示面板在高强度长时间光照下的信耐性参数，是面板显示品质的重要检测指标，其可以反应面板材料和薄膜晶体管（Thin Film Transistor，TFT）控制器件的稳定性。
在薄膜晶体管-LCD(Thin Film Transistor Liquid Crystal Display薄膜晶体管液晶显示器) 显示技术中，通过薄膜晶体管开关管控制上、下基板产生的电场来改变液晶分子的偏转方向，从而实现对透明像素的光强的控制。
常用的薄膜晶体管开关管通常由三电极(栅极、源极以及漏极)、栅极绝缘膜以及半导体活性层组成。其中，栅极绝缘膜是影响薄膜晶体管性能的重要材料之一。但是现有薄膜晶体管所含的栅极绝缘膜表面含有大量的Si-H和Si-Si键，这些键都是非常弱的键，在高能量光照射容易发生断裂，导致膜质变差，薄膜晶体管器件阈值电压漂移，从而导致薄膜晶体管器件恶化，导致显示器件的如高光亮等性能降低。
 技术问题
本申请实施例的目的在于克服现有技术的上述不足，提供一种含改性栅极绝缘膜的薄膜晶体管及其制备方法，赋予薄膜晶体管具有包括阈值电压等电化学性能稳定优异，以解决现有薄膜晶体管所含栅极绝缘层表面含有大量的不稳定化学键而导致薄膜晶体管器件阈值电压漂移和薄膜晶体管器件恶化的技术问题。
本申请实施例的另一目的是提供一种薄膜晶体管的阵列基板、显示器件，以解决现有阵列基板、显示器件由于薄膜晶体管器件阈值电压易发生漂移和恶化导致的显示器件高光亮等性能降低的技术问题。
 技术解决方案
为了实现上述申请目的，本申请的一方面，提供了一种薄膜晶体管的制备方法。所述薄膜晶体管的制备方法包括如下步骤：
按照薄膜晶体管的结构在基板表面上依次形成包括栅极（2）、栅极绝缘层（3）、有源层（4）、n +非晶硅层（5）、源电极（6）和漏电极（7），形成薄膜晶体管；形成栅极绝缘层（3）的方法包括如下步骤：
在形成有栅极（2）的基板（1）表面上形成含硅元素的栅极绝缘膜；
对栅极绝缘膜进行热改性处理，在栅极绝缘膜表面生成Si-N或/和Si-O化学键，形成表面改性的栅极绝缘层（3）。
进一步地，在热改性处理过程中，栅极绝缘膜的温度为200-300℃，热改性处理的时间为10-60s。
更进一步地，栅极绝缘膜的温度为230-270℃，热改性处理的时间为20-40 s。
进一步地，对栅极绝缘膜进行热改性处理的方法包括如下步骤：
在含氮元素的气体环境和/或含有氧的气体环境中，对栅极绝缘膜进行热处理，使得栅极绝缘膜表面与氮元素的气体和/或氧之间发生化学反应，在栅极绝缘膜表面生成Si-N或/和Si-O化学键。
更进一步地，对栅极绝缘膜进行热改性处理的方法包括如下步骤：
将形成含硅元素的栅极绝缘膜的基板（1）置于在含氮元素的气体环境和/或含有氧的气体环境中；
对基板（1）进行升温处理直至调节预设热改性处理的温度，并进行保温处理；使得栅极绝缘膜表面与氮元素的气体和/或氧之间发生化学反应。
更进一步地，含氮元素的气体环境和/或含有氧的气体是按照流量为1000-5000sccm的流量通过栅极绝缘膜的表面。
更进一步地，含氮元素的气体包括N 2、NH 3中的至少一种。
进一步地，形成的栅极绝缘膜的材料包括氮元素和硅元素的绝缘化合物。
更进一步地，绝缘化合物包括氮化硅、氮氧化硅、氮氟化硅中的至少一种。
进一步地，还包括如下步骤：
在设置有源电极（6）、漏电极（7）、n +非晶硅层（5）、有源层（4）的栅极绝缘层（3）的外表面形成平坦层（8），以覆盖源电极（6）、漏电极（7）、n +非晶硅层（5）、有源层（4）。
本申请的另一方面，提供了一种薄膜晶体管。本申请薄膜晶体管包括栅极绝缘层（3）和形成于基板（1）上的栅极（2），栅极绝缘层（3）与设置有栅极（2）的基板（1）表面层叠设置，且覆盖栅极（2），栅极绝缘层（3）的材料含有硅元素，且栅极绝缘层（3）的表面上含有Si-N或/和Si-O化学键。
进一步地，绝缘化合物的材料包括含氮元素和硅元素的绝缘化合物。
更进一步地，绝缘化合物包括氮化硅、氮氧化硅、氮氟化硅中的至少一种。
进一步地，在栅极绝缘层（3）背离基板（1）的表面上设有源层（4）和在有源层（4）外面上设有n +非晶硅层（5）以及在n +非晶硅层（5）外表面设有源电极（6）和漏电极（7）。
更进一步地，还包括平坦层（8），平坦层（8）形成于设置有源电极（6）和漏电极（7）的有源层（4）的表面上，并覆盖源电极（6）、漏电极（7）、n +非晶硅层（5）和有源层（4）。
本申请的再一方面，提供了一种薄膜晶体管阵列基板。薄膜晶体管阵列基板包括衬底基板、设置于衬底基板上的薄膜晶体管，薄膜晶体管为本申请薄膜晶体管。
本申请的又一方面，提供了一种显示器件。显示器件包括薄膜晶体管阵列基板，薄膜晶体管阵列基板为本申请薄膜晶体管阵列基板。
与现有技术相比，本申请具有以下的技术效果：
本申请薄膜晶体管的制备方法通过对含硅元素的栅极绝缘膜表面通过热改性处理，在其表面生成键能高是Si-N或/和Si-O化学键，这些键的化学键能高，化学性能稳定，该些化学键能够在栅极绝缘膜的改性表面形成保护层，在遭受高光照射时不会对改性后的栅极绝缘膜膜质产生破坏，从而赋予制备的薄膜晶体管器件如阈值电压等性能稳定，有效克服了现有薄膜晶体管所含栅极绝缘层在较高强度光照时信耐性变差而导致薄膜晶体管器件性能不稳定的不足。另外，本申请薄膜晶体管的制备方法工艺易控，能够使得制备的薄膜晶体管性能稳定，而且效率高，降低了成本。
本申请薄膜晶体管由于在其所含的栅极绝缘层（3）的表面上含有Si-N或/和Si-O化学键，从而在栅极绝缘层（3）的表面形成保护层，从而在遭受高光照射时不会对改性后的栅极绝缘层（3）膜质产生破坏，从而薄膜晶体管器件如阈值电压等性能稳定。
本申请薄膜晶体管阵列基板和显示器件由于均含有上述本申请薄膜晶体管，因此，该薄膜晶体管阵列基板性能稳定，提高了采用该薄膜晶体管阵列基板的显示器件高光亮等性能，且显示性能稳定，显示质量高。
 附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例薄膜晶体管的结构示意图；
图2为本申请实施例薄膜晶体管所含栅极绝缘层表面所含Si-N化学键的结构示意图；
图3为本申请实施例薄膜晶体管的一种制备方法的工艺流程示意图；
图4为在图3所示的本申请实施例薄膜晶体管制备方法工艺的基础上设有形成平坦层步骤的流程示意图。
 本发明的实施方式
为了使本申请要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请中，术语“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况。其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项（个）或复数项（个）的任意组合。例如，“ a,b,或c中的至少一项（个）”，或，“a,b,和c中的至少一项（个）”，均可以表示：a, b, c, a-b（即a和b）, a-c, b-c, 或a-b-c，其中a,b,c分别可以是单个，也可以是多个。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，部分或全部步骤可以并行执行或先后执行，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
在本申请实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
本申请实施例说明书中所提到的相关成分的重量不仅仅可以指代各组分的具体含量，也可以表示各组分间重量的比例关系，因此，只要是按照本申请实施例说明书相关组分的含量按比例放大或缩小均在本申请实施例说明书公开的范围之内。具体地，本申请实施例说明书中所述的质量可以是µg、mg、g、kg等化工领域公知的质量单位。
术语“第一”、“第二”仅用于描述目的，用来将目的如物质彼此区分开，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。例如，在不脱离本申请实施例范围的情况下，第一XX也可以被称为第二XX，类似地，第二XX也可以被称为第一XX 。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。
一方面，本申请实施例提供了一种薄膜晶体管。本申请实施例薄膜晶体管可以是本领域的常规结构也可以是根据现有常规结构进行改进后的结构。如实施例中，该薄膜晶体管的结构可以是如图1所示，其包括设置在基板1上的栅极2、形成也即是层叠设置于设置有该栅极2的基板1表面上的栅极绝缘层3、在该栅极绝缘层3外面也即是背离基板1的表面上形成的有源层4和在该氧化物有源层4外面上形成的n +非晶硅层5以及设置在n +非晶硅层外表面的源电极6和漏电极7。其中，栅极绝缘层3覆盖栅极2。当然，图1所示结构仅仅为本申请实施例薄膜晶体管的其中一种结构举例，薄膜晶体管的结构不仅仅限于图1所示的结构。不管薄膜晶体管是何种结构，其是含有栅极绝缘层，如图1中栅极绝缘层3的材料含有硅元素，且栅极绝缘层3的表面上含有Si-N或/和Si-O化学键。这样，本申请实施例薄膜晶体管由于在其所含的栅极绝缘层的表面上含有Si-N或/和Si-O化学键，以在栅极绝缘层的表面形成保护层，从而在遭受高光照射时不会对改性后的栅极绝缘层膜质产生破坏，从而赋予制备的薄膜晶体管器件如阈值电压等性能稳定。
实施例中，如图1所示的薄膜晶体管所含的基板1可以是常规的基板，可以根据实际显示器生产的需要进行选用。如可以是硬质材料也可以是柔性材料，当为硬质材料时，基板1的材料可以是玻璃；当为柔性材料时，可以是柔性聚合物材料等。
如图1所示的薄膜晶体管所含的栅极2在结构和材料上没有特别要求，可以是常规结构和材料。
如图1所示的薄膜晶体管所含的栅极绝缘层3如上文所述的，其含有硅元素，且在栅极绝缘层3的表面上含有Si-N或/和Si-O化学键。该Si-N或/和Si-O化学键的化学键能显著高与现有栅极绝缘层表面含有的Si-H和Si-Si的化学键能。具体的Si-H、Si-Si、Si-N和Si-O的化学键能分别如下表1中所示：
表1
Si-Si 176 KJ/mol
Si-H 277 KJ/mol
Si-O 460 KJ/mol
Si-N 342 KJ/mol
因此，由表1中各化学键能数据可知，Si-H和Si-Si显著低于Si-N和Si-O，因此，Si-H和Si-Si化学键能均低，均属于非常弱的化学键，在高能量光照射容易发生断裂，具体Si-H和Si-Si之间发生的反应为SiHHSi+Si-Si〈=〉SiHDSi。正因为Si-H和Si-Si不稳定，导致现有薄膜晶体管所含的栅极绝缘层膜质变差，薄膜晶体管器件阈值电压漂移，从而导致薄膜晶体管器件恶化。而在本申请实施例中，薄膜晶体管所含的栅极绝缘层3表面含有化学键Si-N或/和Si-O具有高的化学键能，其中，当栅极绝缘层3表面含有化学键Si-N化学键的结构示意图如图2所示。化学键Si-N或/和Si-O化学性能稳定，能够在栅极绝缘层3表面形成稳定的保护层，从而保证栅极绝缘层3在高能量光照射下的化学性能和工作性能的稳定性，从而赋予制备的本申请实施例薄膜晶体管器件如阈值电压等性能良好的稳定性。
由于栅极绝缘层3的材料含有硅元素，因此，实施例中，栅极绝缘层3的材料包括硅元素的绝缘化合物，进一步包括氮元素和硅元素的绝缘化合物，在具体实施例中，该绝缘化合物包括氮化硅、氮氧化硅、氮氟化硅中的至少一种。该绝缘化合物形成的栅极绝缘层3能够有效保证在其表面形成Si-N和/或Si-O的化学键。
另外，该栅极绝缘层3的厚度等尺寸可以是常规的厚度。
如图1所示的薄膜晶体管所含的有源层4的材料可以是现有薄膜晶体管有源层的材料，如可以是a-Si : H。当然有源层4的材料还可以是其他材料如，氧化物等。该有源层4的厚度等尺寸也可以是常规的厚度。
如图1所示的薄膜晶体管所含的n +非晶硅层5、源电极6和漏电极7均可以是薄膜晶体管常规的尺寸和材料。
在进一步实施例中，在上述各实施例中薄膜晶体管结构的基础上，薄膜晶体管还包括平坦层8，该平坦层8形成于设置有该源电极6和漏电极7的有源层4的表面上。如图1中，该平坦层8覆盖源电极6、漏电极7、n +非晶硅层5、有源层4。
该平坦层8是为了使后续制备的光电显示器件各层呈现出良好的局部和总体均匀性，同时也起到器件间绝缘的作用。
相应地，本申请实施例还提供了上述薄膜晶体管的制备方法。本申请实施例薄膜晶体管的制备方法包括如下步骤：
按照薄膜晶体管的结构在基板表面上依次形成包括栅极、栅极绝缘层、有源层、n +非晶硅层、源电极和漏电极，形成薄膜晶体管等部件。
其中，形成栅极绝缘层的方法包括如下步骤：
(1) 在有栅极的基板表面上形成含硅元素的栅极绝缘膜；
(2) 对栅极绝缘膜进行热改性处理，在栅极绝缘膜表面生成Si-N或/和Si-O化学键，形成薄膜晶体管。
结合上文薄膜晶体管和图1所示薄膜晶体管和上述薄膜晶体管的制备方法的制备方法，实施例中，薄膜晶体管的制备方法工艺流程如图3所示，包括如下步骤：
步骤S01：在基板1的外表面上形成栅极2；
步骤S02：在形成有栅极2的基板1表面上形成含硅元素的栅极绝缘膜；
步骤S03：对栅极绝缘膜进行热改性处理，在栅极绝缘膜表面生成Si-N或/和Si-O化学键，形成如图1中栅极绝缘层3；
步骤S04：在改性后的栅极绝缘层3表面上形成有源层4；
步骤S05：在有源层4的表面上依次形成n +非晶硅层5、源电极6和漏电极7。
其中，上述的步骤S01和S02相对于上述步骤(1)。该步骤S01中基板1和栅极2的材料可以选用薄膜晶体管常规基板的材料。如上文薄膜晶体管中基板1和栅极2所选用的材料。形成栅极2的方法可以是按照薄膜晶体管的常规制备方法形成基板表面上栅极。
步骤S02形成的栅极绝缘膜应该理解为上文薄膜晶体管所含栅极绝缘层3的前体，也既是为改性前的栅极绝缘层3，因此，形成栅极绝缘膜的方法可以是按照薄膜晶体管的常规制备方法形成。形成栅极绝缘膜的材料是如上文薄膜晶体管所含栅极绝缘层3的材料，如包硅元素的绝缘化合物，进一步包括氮元素和硅元素的绝缘化合物，在具体实施例中，该绝缘化合物包括氮化硅、氮氧化硅、氮氟化硅中的至少一种。
步骤S03相当于上述步骤(2)，通过对栅极绝缘膜进行热改性处理，使得在栅极绝缘膜表面生成Si-N或/和Si-O化学键，也即是生成上文薄膜晶体管所含的栅极绝缘层3，赋予上文薄膜晶体管所含栅极绝缘层3的作用。
实施例中，在步骤S03的热改性处理过程中，栅极绝缘膜（也即是改性前的栅极绝缘层3）的温度为200-300℃，进一步为230-270℃，具体为250℃，热改性处理的时间为10-60s，进一步为20-40s，具体为30s。申请人在研究中发现，热改性处理的温度和时间对栅极绝缘膜的改性效果不同，也即是栅极绝缘层3的性能不同，具体的是，将热处理的时间和温度控制在上述范围内，能使得经热改性处理后生成的栅极绝缘层3表面生成丰富的高化学键能的Si-N或/和Si-O化学键，并在栅极绝缘层3的表面形成保护层，从而显著提高栅极绝缘层3在高能量光照射条件下的稳定性能。研究发现，如果热改性时间和温度不足，栅极绝缘膜表面生成的高化学键能的Si-N或/和Si-O化学键含量不足，使得栅极绝缘层3在高能量光照射条件下的稳定性能降低，如果热改性时间和温度延长，可能会生成其他负产物，从而导致栅极绝缘层3表面产生杂质也影响栅极绝缘层3在高能量光照射条件下的稳定性能。
实施例中，对栅极绝缘膜进行热改性处理的方法包括如下步骤：
在含氮元素的气体环境和/或含有氧的气体环境中，对栅极绝缘膜进行热处理，使得栅极绝缘膜表面与氮元素的气体和/或氧之间发生化学反应，在栅极绝缘膜表面生成Si-N或/和Si-O化学键。
进一步实施例中，热改性处理的方法包括如下步骤：
将形成含硅元素的栅极绝缘膜的基板置于在含氮元素的气体环境和/或含有氧的气体环境中；
对基板进行升温处理直至调节预设热改性处理的温度，并进行保温处理。
具体实施例中，含氮元素的气体或含氧的气体是按照流量为1000-5000sccm进一步为2500-3500sccm具体为3000sccm的流量通过栅极绝缘膜的表面。其中，含氮元素的气体包括N 2、NH 3中的至少一种，含氧的气体可以是氧气。具体地，可以先将形成含硅元素的栅极绝缘膜的基板热处理的腔室内，然后向腔室内通入含氮元素的气体环境或含氧的气体，以排出腔室的空气，且在整个热处理过程保持含氮元素的气体环境和/或含有氧的气体的通入，如按照流量为1000-5000sccm的流量通入。通过控制含氮元素的气体和含氧的气体在热改性中的流速，使得在栅极绝缘膜表面生成丰富的高化学键能的Si-N或/和Si-O化学键，提高从而提高生成的栅极绝缘层3在高能量光照射条件下良好的稳定性能。
步骤S04中形成有源层4的方法和步骤S05中形成n +非晶硅层5、源电极6和漏电极7均可以按照现有的制备各层如制备有源层、n +非晶硅层、源电极和漏电极的方法分别制备有源层4、n +非晶硅层5、源电极6和漏电极7。制备形成的有源层4、n +非晶硅层5、源电极6和漏电极7的材料分别如上文薄膜晶体管所含有源层4、n +非晶硅层5、源电极6和漏电极7的材料。
在进一步实施例中，如图1所示的薄膜晶体管还包括平坦层8时，上述薄膜晶体管制备方法还包括如图4所示的步骤S06：在设置有源电极6、漏电极7、n +非晶硅层5、有源层4的栅极绝缘层3的外表面形成平坦层8，以覆盖源电极6、漏电极7、n +非晶硅层5、有源层4。在优选实施例中，该平坦层8可以采用但不仅仅为旋涂法形成。其材料可以但不仅仅选用氯乙烯树脂（PV）。
因此，由上述可知，上述各实施例中薄膜晶体管的制备方法通过对含硅元素的栅极绝缘膜表面通过热改性处理，在其表面生成键能高是Si-N或/和Si-O化学键，这些键的化学键能高，化学性能稳定，该些化学键能够在形成的栅极绝缘层3的改性表面形成保护层，在遭受高光照射时不会对改性后的栅极绝缘膜（也即是栅极绝缘层3）膜质产生破坏，从而赋予制备的薄膜晶体管器件如阈值电压等性能稳定，有效克服了现有薄膜晶体管所含栅极绝缘层在较高强度光照时信耐性变差而导致薄膜晶体管器件性能不稳定的不足。另外，该薄膜晶体管的制备方法工艺易控，能够使得制备的薄膜晶体管性能稳定，而且效率高，降低了成本。
另一方面，在上述薄膜晶体管的基础上，本申请实施例还提供了一种薄膜晶体管阵列基板。该薄膜晶体管阵列基板包括衬底基板和设置于衬底基板上的薄膜晶体管。其中，该薄膜晶体管阵列基板中的薄膜晶体管为上文所述的薄膜晶体管。
当然，薄膜晶体管阵列基板还可以包括现有薄膜晶体管阵列基板所含的其他部件，如栅线、数据线和像素电极等，如当薄膜晶体管阵列基板设置有像素电极时，如图1所示的薄膜晶体管所含的漏电极7与像素电极连接。该薄膜晶体管阵列基板所含的其他部件之间连接关系以及位置关系均可以按照现有薄膜晶体管阵列基板进行设置，对于本申请实施例没有特别要求。由于该薄膜晶体管阵列基板是含有上文所述的薄膜晶体管，又由于如上文所述薄膜晶体管所含的栅极绝缘层3的表面上含有Si-N或/和Si-O化学键，在遭受高光照射时保持良好的稳定性，因此，该薄膜晶体管阵列基板工作性能特别是在高光照射环境中工作性能稳定。
同样，基于上述薄膜晶体管阵列基板的基础上，本申请实施例还提供了一种显示器件。该显示器件包括薄膜晶体管阵列基板，且该薄膜晶体管阵列基板为上述的薄膜晶体管阵列基板。由于显示器件含有本申请实施例薄膜晶体管阵列基薄膜晶体管，因此，本申请实施例显示器件且显示性能稳定，显示质量高。
以下通过多个实施例来举例进一步说明上述薄膜晶体管及其制备方法、显示器件的相关性能等方面。
实施例一：薄膜晶体管实施例
实施例A1
本实施例提供一种薄膜晶体管及其制备方法。该薄膜晶体管的结构如图1所示，其中，基板1的材料为玻璃；栅极绝缘层3的材料为SiN x，且SiN x层表面含有Si-O和Si-N化学键，有源层4的材料为a-Si : H，平坦层8的材料为PV。
实施例薄膜晶体管的制备方法按照图3中工艺制备获得，其中，步骤S03中的热改性处理方法包括如下步骤：
在氧气环境中，对栅极绝缘膜于250℃进行热处理10s，使得栅极绝缘膜表面与氧之间发生化学反应，在栅极绝缘膜表面生成所述Si-O化学键，同时生成栅极绝缘层3表面含有Si-N化学键。其中，氧气是以1000sccm的流速通过反应体系。
实施例A2
本实施例提供一种薄膜晶体管及其制备方法。该薄膜晶体管的结构和其制备方法如同实施例A1。其中，与实施例A1不同的是栅极绝缘膜于250℃进行热处理60s，且氧气是以5000sccm的流速通过反应体系。
实施例A3
本实施例提供一种薄膜晶体管及其制备方法。该薄膜晶体管的结构和其制备方法如同实施例A1。其中，与实施例A1不同的是在氮气环境中对进行栅极绝缘膜于250℃进行热处理30s，且氧气是以3000sccm的流速通过反应体系。
实施例A4
本实施例提供一种薄膜晶体管及其制备方法。该薄膜晶体管的结构和其制备方法如同实施例A1。其中，与实施例A1不同的是在氨气环境中对进行栅极绝缘膜于200℃进行热处理30s，且氧气是以3000sccm的流速通过反应体系，栅极绝缘膜的材料为氮氧化硅。
对比例1：
本对比例提供薄膜晶体管，其结构与实施例A1中相同，不同在于本对比例薄膜晶体管所含的栅极绝缘层3为SiN x层，也即是与实施例1相比，本对比例薄膜晶体管所含的栅极绝缘层3不经过实施例1中步骤S03中的热改性处理，也即是本对比例薄膜晶体管所含的栅极绝缘层3表面为常规SiN x层表面。
实施例二：薄膜晶体管阵列基板实施例
实施例B1至实施例B4
实施例B1至实施例B4分别提供一种薄膜晶体管阵列基板。各实施例薄膜晶体管阵列基板包括衬底基板和设置于衬底基板上的薄膜晶体管。其中，实施例B1提供的薄膜晶体管阵列基板所含的薄膜晶体管为实施例A1提供的薄膜晶体管，实施例B2提供的薄膜晶体管阵列基板所含的薄膜晶体管为实施例A2提供的薄膜晶体管，实施例B3提供的薄膜晶体管阵列基板所含的薄膜晶体管为实施例A3提供的薄膜晶体管，实施例B4提供的薄膜晶体管阵列基板所含的薄膜晶体管为实施例A4提供的薄膜晶体管。
实施例三：薄膜晶体管显示器件实施例
实施例C1至实施例C4
实施例C1至实施例C4分别提供一种显示器件。各实施例显示器件包括薄膜晶体管阵列基板。其中，实施例C1提供的薄膜晶体管阵列基板所含的薄膜晶体管为实施例B1提供的薄膜晶体管，实施例C2提供的薄膜晶体管阵列基板所含的薄膜晶体管为实施例B2提供的薄膜晶体管，实施例C3提供的薄膜晶体管阵列基板所含的薄膜晶体管为实施例B3提供的薄膜晶体管，实施例C4提供的薄膜晶体管阵列基板所含的薄膜晶体管为实施例B4提供的薄膜晶体管。
性能测试：
将上述实施例A1至实施例A4和对比例A1中薄膜晶体管进行电性特征值来表征，具体测试条件是Vd=10V 光罩=1000lux，测得的结果如下表2中所示：
表2
Figure dest_path_image001
从上表2可看出，相比对比例1中提供的未改性处理的常规栅极绝缘层，本申请实施例A1至实施例A4薄膜晶体管的漏电流得到了显著的降低，并且可以显著提升薄膜晶体管器件的开关比，提升薄膜晶体管的开关特性，其中实施例A3的效果最为显著。因此，本申请实施例薄膜晶体管在较高强度光照时信耐性得到了明显的提高，提高了薄膜晶体管器件性能稳定性。
进一步对上述实施例B1至实施例B4提供的薄膜晶体管阵列基板和实施例C1至实施例C4提供的显示器件分别进行相关性能测试得知，基于实施例A1至实施例A4的薄膜晶体管薄膜，实施例B1至实施例B4提供的各薄膜晶体管阵列基板均在高光照射环境中工作性能稳定，对应的实施例C1至实施例C4提供的显示器显示性能稳定。与含有对比例1提供的传统薄膜晶体管的薄膜晶体管阵列基板和显示器相比，本申请实施例提供的各薄膜晶体管阵列基板和对应的显示器的工作稳定性能得到了明显的提高。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包括在本申请的保护范围之内。

Claims (17)

  1. 一种薄膜晶体管的制备方法，包括如下步骤：
    按照薄膜晶体管的结构在基板（1）表面上依次形成包括栅极（2）、栅极绝缘层（3）、有源层（4）、n +非晶硅层（5）、源电极（6）和漏电极（7），形成薄膜晶体管；
    其中，形成所述栅极绝缘层（3）的方法包括如下步骤：
    在形成有栅极（2）的基板（1）表面上形成含硅元素的栅极绝缘膜；
    对所述栅极绝缘膜进行热改性处理，在所述栅极绝缘膜表面生成Si-N或/和Si-O化学键，形成表面改性的所述栅极绝缘层（3）。
  2. 如权利要求1所述的制备方法，其中，在所述热改性处理过程中，所述栅极绝缘膜的温度为200-300℃，所述热改性处理的时间为10-60s。
  3. 如权利要求2所述的制备方法，其中，所述栅极绝缘膜的温度为230-270℃，所述热改性处理的时间为20-40 s。
  4. 如权利要求1-3任一项所述的制备方法，其中，对所述栅极绝缘膜进行热改性处理的方法包括如下步骤：
    在含氮元素的气体环境和/或含有氧的气体环境中，对所述栅极绝缘膜进行热处理，使得栅极绝缘膜表面与氮元素的气体和/或氧之间发生化学反应，在栅极绝缘膜表面生成所述Si-N或/和Si-O化学键。
  5. 如权利要求4所述的制备方法，其中，对所述栅极绝缘膜进行热改性处理的方法包括如下步骤：
    将形成含硅元素的所述栅极绝缘膜的所述基板（1）置于在含氮元素的气体环境和/或含有氧的气体环境中；
    对所述基板（1）进行升温处理直至调节预设所述热改性处理的温度，并进行保温处理；使得所述栅极绝缘膜表面与氮元素的气体和/或氧之间发生所述化学反应。
  6. 如权利要求4所述的制备方法，其中，所述含氮元素的气体环境和/或含有氧的气体是按照流量为1000-5000sccm的流量通过所述栅极绝缘膜的表面。
  7. 如权利要求4所述的制备方法，其中，所述含氮元素的气体包括N 2、NH 3中的至少一种。
  8. 如权利要求1-3、5-7所述的制备方法，其中，形成的所述栅极绝缘膜的材料包括氮元素和硅元素的绝缘化合物。
  9. 如权利要求8所述的制备方法，其中，所述绝缘化合物包括氮化硅、氮氧化硅、氮氟化硅中的至少一种。
  10. 如权利要求1-3、5-7、9所述的制备方法，其中，还包括如下步骤：
    在设置有所述源电极（6）、漏电极（7）、n +非晶硅层（5）、有源层（4）的栅极绝缘层（3）的外表面形成平坦层（8），以覆盖所述源电极（6）、漏电极（7）、n +非晶硅层（5）、有源层（4）。
  11. 一种薄膜晶体管，包括栅极绝缘层（3）和形成于基板（1）上的栅极（2），所述栅极绝缘层（3）与设置有所述栅极（2）的所述基板（1）表面层叠设置，且覆盖所述栅极（2），其中，所述栅极绝缘层（3）的材料含有硅元素，且所述栅极绝缘层（3）的表面上含有Si-N或/和Si-O化学键。
  12. 如权利要求11所述的薄膜晶体管，其中，所述绝缘化合物的材料包括含氮元素和硅元素的绝缘化合物。
  13. 如权利要求12所述的薄膜晶体管，其中，所述绝缘化合物包括氮化硅、氮氧化硅、氮氟化硅中的至少一种。
  14. 如权利要求11-13任一项所述的薄膜晶体管，其中，在所述栅极绝缘层（3）背离所述基板（1）的表面上设有源层（4）和在所述有源层（4）外面上设有n +非晶硅层（5）以及在所述n +非晶硅层（5）外表面设有源电极（6）和漏电极（7）。
  15. 如权利要求14所述的薄膜晶体管，其中，还包括平坦层（8），所述平坦层（8）形成于设置有所述源电极（6）和漏电极（7）的有源层（4）的表面上，并覆盖所述源电极（6）、漏电极（7）、n +非晶硅层（5）和有源层（4）。
  16. 一种薄膜晶体管阵列基板，包括衬底基板、设置于所述衬底基板上的薄膜晶体管，其中，所述薄膜晶体管为权利要求11-15任一项所述的薄膜晶体管。
  17. 一种显示器件，包括薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板为权利要求16所述的薄膜晶体管阵列基板。
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