WO2022247271A1

WO2022247271A1 - Thin film transistor, preparation method therefor, array substrate, and display device

Info

Publication number: WO2022247271A1
Application number: PCT/CN2021/142744
Authority: WO
Inventors: 夏玉明; 卓恩宗; 郑浩旋
Original assignee: 惠科股份有限公司
Priority date: 2021-05-27
Filing date: 2021-12-29
Publication date: 2022-12-01
Also published as: CN113314424A; CN113314424B

Abstract

The present application discloses a thin film transistor, a preparation method therefor, an array substrate, and a display device. The thin film transistor comprises a gate insulating layer (3), the material of the gate insulating layer (3) containing silicon, and the surface of the gate insulating layer (3) containing Si-N and/or Si-O chemical bonds. The preparation method for the thin film transistor comprises the steps of: forming a silicon-containing gate insulating film on the surface of a substrate (1) on which a gate is formed; and performing thermal modification on the gate insulating film to generate Si-N and/or Si-O chemical bonds on the surface of the gate insulating film. The thin film transistor array substrate and the display device both contain the thin film transistor. The thin film transistor contains Si-N and/or Si-O chemical bonds on the surface of the gate insulating layer (3), and a thin film transistor device has stable properties, such as threshold voltage. The process of the preparation method for the thin film transistor is easy to control, and the properties of the prepared thin film transistor are stable, improving both the properties of the thin film transistor array substrate and the display quality of the display device.

Description

Thin film transistor and its preparation method, array substrate, and display device

This application claims the priority of the Chinese patent application with the application number 202110584006.8 submitted to the China Patent Office on May 27, 2021, and the application name is "thin film transistor and its preparation method, array substrate, and display device", the entire content of which is incorporated by reference incorporated in this application.

technical field

The application belongs to the field of display technology, and in particular relates to a thin film transistor, a preparation method thereof, an array substrate, and a display device.

Background technique

High energy light test is to check the reliability parameters of liquid crystal display panels under high-intensity long-term light. It is an important indicator of panel display quality. It can reflect panel materials and thin film transistors (Thin Film Transistor, TFT) Controls the stability of the device.

In the thin film transistor-LCD (Thin Film Transistor Liquid Crystal Display) display technology, the electric field generated by the upper and lower substrates is controlled by the thin film transistor switch tube to change the deflection direction of the liquid crystal molecules, thereby realizing the light intensity of the transparent pixels. control.

Commonly used TFT switch tubes usually consist of three electrodes (gate, source and drain), a gate insulating film and a semiconductor active layer. Among them, the gate insulating film is one of the important materials that affect the performance of the thin film transistor. However, the surface of the gate insulating film contained in the existing thin-film transistors contains a large number of Si-H and Si-Si bonds. These bonds are very weak bonds, which are prone to breakage under high-energy light irradiation, resulting in poor film quality. Thin-film transistors The threshold voltage of the device drifts, which leads to the deterioration of the thin film transistor device, resulting in a decrease in the performance of the display device such as high brightness.

technical problem

The purpose of the embodiments of the present application is to overcome the above-mentioned deficiencies in the prior art, provide a thin film transistor with a modified gate insulating film and a preparation method thereof, endow the thin film transistor with stable and excellent electrochemical properties including threshold voltage, and solve the current problems. There is a technical problem that the surface of the gate insulating layer contained in the thin film transistor contains a large number of unstable chemical bonds, which leads to the drift of the threshold voltage of the thin film transistor device and the deterioration of the thin film transistor device.

Another purpose of the embodiments of the present application is to provide an array substrate and a display device of a thin film transistor, so as to solve the performance degradation of the existing array substrate and display device due to the drift and deterioration of the threshold voltage of the thin film transistor device, such as high brightness of the display device. technical problems.

technical solution

In order to achieve the purpose of the above application, one aspect of the present application provides a method for manufacturing a thin film transistor. The preparation method of the thin film transistor comprises the following steps:

According to the structure of the thin film transistor, the gate (2), gate insulating layer (3), active layer (4), n ⁺ amorphous silicon layer (5), source electrode (6) and leakage are sequentially formed on the surface of the substrate. electrode (7) to form a thin film transistor; the method for forming a gate insulating layer (3) includes the following steps:

forming a gate insulating film containing silicon on the surface of the substrate (1) on which the gate (2) is formed;

Performing thermal modification treatment on the gate insulating film to generate Si-N or/and Si-O chemical bonds on the surface of the gate insulating film to form a surface-modified gate insulating layer (3).

Further, during the heat modification process, the temperature of the gate insulating film is 200-300° C., and the time of the heat modification treatment is 10-60 s.

Furthermore, the temperature of the gate insulating film is 230-270° C., and the time for thermal modification treatment is 20-40 s.

Further, the method for thermally modifying the gate insulating film includes the following steps:

In a nitrogen-containing gas environment and/or an oxygen-containing gas environment, heat treatment is performed on the gate insulating film, so that a chemical reaction occurs between the surface of the gate insulating film and the gas of nitrogen element and/or oxygen, and the gate insulating film Si-N or/and Si-O chemical bonds are formed on the surface of the film.

Furthermore, the method for thermally modifying the gate insulating film includes the following steps:

placing the substrate (1) on which the gate insulating film containing silicon is formed in a nitrogen-containing gas environment and/or an oxygen-containing gas environment;

The substrate (1) is subjected to heating treatment until the temperature of the preset thermal modification treatment is adjusted, and heat preservation treatment is performed; so that a chemical reaction occurs between the surface of the gate insulating film and nitrogen gas and/or oxygen.

Furthermore, the nitrogen-containing gas environment and/or the oxygen-containing gas pass through the surface of the gate insulating film at a flow rate of 1000-5000 sccm.

Furthermore, the nitrogen-containing gas includes at least one of N ₂ and NH ₃ .

Further, the material of the formed gate insulating film includes an insulating compound of nitrogen and silicon.

Furthermore, the insulating compound includes at least one of silicon nitride, silicon oxynitride, and silicon fluoride nitride.

Further, the following steps are also included:

A flat layer (8) is formed on the outer surface of the gate insulating layer (3) provided with the source electrode (6), the drain electrode (7), the n ⁺ amorphous silicon layer (5), and the active layer (4), so as to Covering the source electrode (6), the drain electrode (7), the n ⁺ amorphous silicon layer (5), and the active layer (4).

Another aspect of the present application provides a thin film transistor. The thin film transistor of the present application includes a gate insulating layer (3) and a gate (2) formed on the substrate (1), and the gate insulating layer (3) is laminated with the surface of the substrate (1) provided with the gate (2) , and cover the gate (2), the material of the gate insulating layer (3) contains silicon element, and the surface of the gate insulating layer (3) contains Si-N or/and Si-O chemical bonds.

Further, the material of the insulating compound includes an insulating compound containing nitrogen and silicon.

Further, an active layer (4) is provided on the surface of the gate insulating layer (3) away from the substrate (1), an n ⁺ amorphous silicon layer (5) is provided on the outside of the active layer (4), and an n + ⁺ The outer surface of the amorphous silicon layer (5) is provided with a source electrode (6) and a drain electrode (7).

Further, it also includes a flat layer (8), the flat layer (8) is formed on the surface of the active layer (4) provided with the source electrode (6) and the drain electrode (7), and covers the source electrode (6) , a drain electrode (7), an n ⁺ amorphous silicon layer (5) and an active layer (4).

In yet another aspect of the present application, a thin film transistor array substrate is provided. The thin film transistor array substrate includes a base substrate and a thin film transistor disposed on the base substrate, and the thin film transistor is a thin film transistor of the present application.

In yet another aspect of the present application, a display device is provided. The display device includes a thin film transistor array substrate, and the thin film transistor array substrate is the thin film transistor array substrate of the present application.

Compared with the prior art, the present application has the following technical effects:

The preparation method of the thin-film transistor of the present application is through thermal modification treatment on the surface of the gate insulating film containing silicon elements, and Si-N or/and Si-O chemical bonds with high bond energy are formed on the surface, and the chemical bond energy of these bonds is high. The chemical properties are stable, and these chemical bonds can form a protective layer on the modified surface of the gate insulating film, and will not damage the film quality of the modified gate insulating film when exposed to high light, thus endowing the prepared thin film transistor device such as The performance such as threshold voltage is stable, which effectively overcomes the deficiency that the gate insulating layer contained in the existing thin film transistor has poor reliability under high-intensity light, which leads to unstable performance of the thin film transistor device. In addition, the preparation method of the thin film transistor of the present application is easy to control the process, can make the performance of the prepared thin film transistor stable, and the efficiency is high, and the cost is reduced.

The thin film transistor of the present application contains Si-N or/and Si-O chemical bonds on the surface of the gate insulating layer (3), thereby forming a protective layer on the surface of the gate insulating layer (3), so that The film quality of the modified gate insulating layer (3) will not be damaged when irradiated by high light, so that the performance of the thin film transistor device such as the threshold voltage is stable.

Since the thin film transistor array substrate and the display device of the present application both contain the above-mentioned thin film transistors of the present application, the performance of the thin film transistor array substrate is stable, and the performance such as high brightness of the display device using the thin film transistor array substrate is improved, and the display performance is stable. high quality.

Description of drawings

In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the specific embodiments or prior art. Obviously, the accompanying drawings in the following description The drawings are some implementations of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present application;

2 is a schematic structural diagram of the Si-N chemical bond contained on the surface of the gate insulating layer contained in the thin film transistor of the embodiment of the present application;

FIG. 3 is a schematic process flow diagram of a method for preparing a thin film transistor according to an embodiment of the present application;

FIG. 4 is a schematic flowchart of a step of forming a planar layer based on the manufacturing method of the thin film transistor of the embodiment of the present application shown in FIG. 3 .

Embodiments of the present invention

In order to make the technical problems, technical solutions and beneficial effects to be solved in the present application clearer, the present application will be further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

In this application, the term "and/or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, A and/or B may mean: A exists alone, A and B exist simultaneously, and B exists alone Happening. Among them, A and B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship.

In this application, "at least one" means one or more, and "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, "at least one (one) of a, b, or c", or "at least one (one) of a, b, and c" can mean: a, b, c, a-b ( That is, a and b), a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

It should be understood that in various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the order of execution, and some or all steps may be executed in parallel or sequentially, and the execution order of each process shall be based on its functions and The internal logic is determined and should not constitute any limitation to the implementation process of the embodiment of the present application.

Terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of this application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

The weight of the relevant components mentioned in the description of the embodiments of the present application can not only refer to the specific content of each component, but also represent the proportional relationship between the weights of the various components. The scaling up or down of the content of the fraction is within the scope disclosed in the description of the embodiments of the present application. Specifically, the mass described in the description of the embodiments of the present application may be µg, mg, g, kg and other well-known mass units in the chemical industry.

The terms "first" and "second" are only used for descriptive purposes to distinguish objects such as substances from each other, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. For example, without departing from the scope of the embodiments of the present application, the first XX can also be called the second XX, and similarly, the second XX can also be called the first XX. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features.

On the one hand, the embodiment of the present application provides a thin film transistor. The thin film transistor in the embodiment of the present application may be a conventional structure in the field or an improved structure based on an existing conventional structure. As in the embodiment, the structure of the thin film transistor may be as shown in FIG. 1, which includes a gate 2 disposed on the substrate 1, and a gate formed, that is, stacked on the surface of the substrate 1 on which the gate 2 is disposed. pole insulating layer 3, an active layer 4 formed on the surface of the gate insulating layer 3 that is away from the substrate 1, an n ⁺ amorphous silicon layer 5 formed on the outer surface of the oxide active layer 4, and the arrangement source electrode 6 and drain electrode 7 on the outer surface of the n ⁺ amorphous silicon layer. Wherein, the gate insulating layer 3 covers the gate 2 . Of course, the structure shown in FIG. 1 is only an example of one structure of the thin film transistor in the embodiment of the present application, and the structure of the thin film transistor is not limited to the structure shown in FIG. 1 . Regardless of the structure of the thin film transistor, it contains a gate insulating layer, as shown in Figure 1. The material of the gate insulating layer 3 contains silicon elements, and the surface of the gate insulating layer 3 contains Si-N or/and Si-O chemical bond. In this way, the thin film transistor of the embodiment of the present application contains Si-N or/and Si-O chemical bonds on the surface of the gate insulating layer to form a protective layer on the surface of the gate insulating layer, so that it is exposed to high light It will not damage the film quality of the modified gate insulating layer, thus endowing the prepared thin film transistor device with stable performance such as threshold voltage.

In an embodiment, the substrate 1 contained in the thin film transistor as shown in FIG. 1 may be a conventional substrate, which may be selected according to the requirements of actual display production. For example, it can be a hard material or a flexible material. When it is a hard material, the material of the substrate 1 can be glass; when it is a flexible material, it can be a flexible polymer material or the like.

The gate 2 contained in the thin film transistor shown in FIG. 1 has no special requirements on the structure and material, and may be a conventional structure and material.

The gate insulating layer 3 contained in the thin film transistor shown in FIG. 1 contains silicon element as mentioned above, and contains Si—N or/and Si—O chemical bonds on the surface of the gate insulating layer 3 . The chemical bond energy of the Si—N or/and Si—O chemical bond is significantly higher than the chemical bond energy of Si—H and Si—Si contained on the surface of the existing gate insulating layer. The specific chemical bond energies of Si-H, Si-Si, Si-N and Si-O are shown in Table 1 below:

Table 1

Si-Si Si-Si	176 KJ/mol 176 KJ/mol
Si-H Si-H	277 KJ/mol 277 KJ/mol
Si-O Si-O	460 KJ/mol 460 KJ/mol
Si-N Si-N	342 KJ/mol 342 KJ/mol

Therefore, from the chemical bond energy data in Table 1, it can be seen that Si-H and Si-Si are significantly lower than Si-N and Si-O, therefore, Si-H and Si-Si chemical bond energy are both low, and both belong to very weak chemical bonds , it is easy to break when exposed to high-energy light, and the specific reaction between Si-H and Si-Si is SiHHSi+Si-Si<=>SiHDSi. Because of the instability of Si-H and Si-Si, the film quality of the gate insulating layer contained in the existing thin film transistor is deteriorated, and the threshold voltage of the thin film transistor device drifts, which leads to the deterioration of the thin film transistor device. In the embodiment of the present application, the surface of the gate insulating layer 3 contained in the thin film transistor contains chemical bonds Si-N or/and Si-O has high chemical bond energy, wherein, when the surface of the gate insulating layer 3 contains chemical bonds Si-N The schematic diagram of the chemical bond structure is shown in Figure 2. The chemical bond Si-N or/and Si-O has stable chemical properties and can form a stable protective layer on the surface of the gate insulating layer 3, thereby ensuring the stability of the chemical properties and working performance of the gate insulating layer 3 under high-energy light irradiation , so as to endow the prepared thin film transistor device of the embodiment of the present application with good stability in properties such as threshold voltage and the like.

Since the material of the gate insulating layer 3 contains silicon, in an embodiment, the material of the gate insulating layer 3 includes an insulating compound of silicon, and further includes an insulating compound of nitrogen and silicon. In a specific embodiment, the The insulating compound includes at least one of silicon nitride, silicon oxynitride, and silicon fluoride nitride. The gate insulating layer 3 formed by the insulating compound can effectively ensure the formation of Si—N and/or Si—O chemical bonds on its surface.

In addition, the thickness and other dimensions of the gate insulating layer 3 may be conventional thicknesses.

The material of the active layer 4 contained in the thin film transistor as shown in FIG. 1 can be the material of the active layer of the existing thin film transistor, such as a-Si:H. Of course, the material of the active layer 4 may also be other materials such as oxides and the like. The thickness and other dimensions of the active layer 4 may also be conventional thicknesses.

The n ⁺ amorphous silicon layer 5, the source electrode 6 and the drain electrode 7 contained in the thin film transistor shown in FIG. 1 can all be of conventional size and material of the thin film transistor.

In a further embodiment, on the basis of the structure of the thin film transistor in the above embodiments, the thin film transistor further includes a flat layer 8 formed on the surface of the active layer 4 provided with the source electrode 6 and the drain electrode 7 superior. As shown in FIG. 1 , the flat layer 8 covers the source electrode 6 , the drain electrode 7 , the n ⁺ amorphous silicon layer 5 , and the active layer 4 .

The planar layer 8 is used to make each layer of the photoelectric display device prepared subsequently exhibit good local and overall uniformity, and also play a role of insulation between devices.

Correspondingly, the embodiment of the present application also provides a method for manufacturing the above-mentioned thin film transistor. The preparation method of the thin film transistor of the embodiment of the present application includes the following steps:

According to the structure of the thin film transistor, the gate, gate insulating layer, active layer, n ⁺ amorphous silicon layer, source electrode and drain electrode are sequentially formed on the surface of the substrate to form thin film transistors and other components.

Wherein, the method for forming the gate insulating layer comprises the following steps:

(1) Forming a gate insulating film containing silicon elements on the surface of the substrate with the gate;

(2) Perform thermal modification treatment on the gate insulating film to generate Si-N or/and Si-O chemical bonds on the surface of the gate insulating film to form a thin film transistor.

Combining the preparation method of the above thin film transistor and the thin film transistor shown in FIG. 1 and the preparation method of the above thin film transistor, in the embodiment, the process flow of the preparation method of the thin film transistor is shown in FIG. 3, including the following steps:

Step S01: forming a grid 2 on the outer surface of the substrate 1;

Step S02: forming a gate insulating film containing silicon on the surface of the substrate 1 on which the gate 2 is formed;

Step S03: Perform thermal modification treatment on the gate insulating film to generate Si-N or/and Si-O chemical bonds on the surface of the gate insulating film to form the gate insulating layer 3 as shown in FIG. 1 ;

Step S04: forming an active layer 4 on the surface of the modified gate insulating layer 3;

Step S05 : forming an n ⁺ amorphous silicon layer 5 , a source electrode 6 and a drain electrode 7 sequentially on the surface of the active layer 4 .

Wherein, the above-mentioned steps S01 and S02 are relative to the above-mentioned step (1). The materials of the substrate 1 and the gate 2 in the step S01 can be selected from the materials of conventional substrates of thin film transistors. The materials selected for the substrate 1 and the gate 2 in the above thin film transistor. The method of forming the gate 2 may be to form the gate on the surface of the substrate according to the conventional preparation method of thin film transistors.

The gate insulating film formed in step S02 should be understood as the precursor of the gate insulating layer 3 contained in the thin film transistor above, and also the gate insulating layer 3 before modification. Therefore, the method of forming the gate insulating film can be It is formed according to a conventional preparation method of a thin film transistor. The material for forming the gate insulating film is the material of the gate insulating layer 3 contained in the thin film transistor above, such as an insulating compound containing silicon elements, and an insulating compound further including nitrogen and silicon elements. In a specific embodiment, the insulating compound Including at least one of silicon nitride, silicon oxynitride, and silicon fluoride nitrogen.

Step S03 is equivalent to the above-mentioned step (2), by thermally modifying the gate insulating film, Si-N or/and Si-O chemical bonds are formed on the surface of the gate insulating film, that is, the formation of the above thin film transistor The gate insulating layer 3 contained in the above thin film transistor has the function of the gate insulating layer 3 contained in it.

In an embodiment, during the thermal modification process in step S03, the temperature of the gate insulating film (that is, the gate insulating layer 3 before modification) is 200-300°C, further 230-270°C, specifically At 250°C, the time for thermal modification treatment is 10-60s, further 20-40s, specifically 30s. The applicant found in the research that the temperature and time of the thermal modification treatment have different modification effects on the gate insulating film, that is, the performance of the gate insulating layer 3 is different. Specifically, the time and temperature of the thermal modification treatment are controlled at Within the above range, the surface of the gate insulating layer 3 generated after thermal modification can generate abundant Si-N or/and Si-O chemical bonds with high chemical bond energy, and a protective layer can be formed on the surface of the gate insulating layer 3 , thereby significantly improving the stability of the gate insulating layer 3 under high-energy light irradiation conditions. Studies have found that if the thermal modification time and temperature are insufficient, the Si-N or/and Si-O chemical bonds with high chemical bond energy generated on the surface of the gate insulating film will have insufficient content, so that the gate insulating layer 3 will remain stable under high-energy light irradiation conditions. The stability performance is reduced. If the thermal modification time and temperature are prolonged, other negative products may be generated, resulting in impurities on the surface of the gate insulating layer 3 and affecting the stability of the gate insulating layer 3 under high-energy light irradiation conditions.

In an embodiment, the method for thermally modifying the gate insulating film includes the following steps:

In a further embodiment, the method for thermal modification treatment includes the following steps:

placing the substrate on which the gate insulating film containing silicon is formed in a nitrogen-containing gas environment and/or an oxygen-containing gas environment;

Carrying out temperature rise treatment on the substrate until the temperature of the preset thermal modification treatment is adjusted, and performing heat preservation treatment.

In a specific embodiment, the nitrogen-containing gas or the oxygen-containing gas passes through the surface of the gate insulating film at a flow rate of 1000-5000 sccm, further 2500-3500 sccm, specifically 3000 sccm. Wherein, the nitrogen-containing gas includes at least one of N ₂ and NH ₃ , and the oxygen-containing gas may be oxygen. Specifically, the substrate of the gate insulating film containing silicon can be heat-treated first in the chamber, and then a nitrogen-containing gas environment or an oxygen-containing gas is introduced into the chamber to exhaust the air in the chamber, and the entire During the heat treatment process, the nitrogen-containing gas environment and/or the feeding of oxygen-containing gas are maintained, for example, according to a flow rate of 1000-5000 sccm. By controlling the flow rate of nitrogen-containing gas and oxygen-containing gas in thermal modification, abundant Si-N or/and Si-O chemical bonds with high chemical bond energy are generated on the surface of the gate insulating film, thereby improving the generated The gate insulating layer 3 has good stability under the condition of high-energy light irradiation.

The method for forming the active layer 4 in step S04 and the formation of the n ⁺ amorphous silicon layer 5, the source electrode 6 and the drain electrode 7 in the step S05 can be prepared according to existing methods such as preparing the active layer, n ⁺ amorphous silicon layer layer, source electrode and drain electrode to prepare active layer 4, n ⁺ amorphous silicon layer 5, source electrode 6 and drain electrode 7 respectively. Prepare and form the active layer 4, n ⁺ amorphous silicon layer 5, source electrode 6 and drain electrode 7 materials respectively as the active layer 4, n ⁺ amorphous silicon layer 5, source electrode 6 and drain electrode contained in the above thin film transistor 7 materials.

In a further embodiment, when the thin film transistor as shown in FIG. 1 further includes a planar layer 8, the above thin film transistor manufacturing method further includes step S06 as shown in FIG ^. A flat layer 8 is formed on the outer surface of the gate insulating layer 3 of the amorphous silicon layer 5 and the active layer 4 to cover the source electrode 6 , the drain electrode 7 , the n ⁺ amorphous silicon layer 5 and the active layer 4 . In a preferred embodiment, the planar layer 8 can be formed by but not only by spin coating. Its material can but not only choose vinyl chloride resin (PV).

Therefore, it can be seen from the above that the preparation method of the thin film transistor in the above-mentioned embodiments is to thermally modify the surface of the gate insulating film containing silicon elements to form Si-N or/and Si-O on the surface with high bond energy. Chemical bonds, these bonds have high chemical bond energy and stable chemical properties, and these chemical bonds can form a protective layer on the modified surface of the formed gate insulating layer 3, and will not damage the modified gate insulating film ( That is to say, the film quality of the gate insulating layer 3) is damaged, thereby endowing the prepared thin film transistor device with stable performance such as threshold voltage, effectively overcoming the deterioration of the gate insulating layer contained in the existing thin film transistor under high-intensity light. Poor results in unstable performance of thin film transistor devices. In addition, the preparation method of the thin film transistor is easy to control the process, can make the performance of the prepared thin film transistor stable, and the efficiency is high, and the cost is reduced.

On the other hand, on the basis of the above thin film transistor, the embodiment of the present application also provides a thin film transistor array substrate. The thin film transistor array substrate includes a base substrate and thin film transistors arranged on the base substrate. Wherein, the thin film transistors in the thin film transistor array substrate are the thin film transistors mentioned above.

Of course, the thin film transistor array substrate may also include other components contained in the existing thin film transistor array substrate, such as gate lines, data lines, and pixel electrodes. For example, when the thin film transistor array substrate is provided with pixel electrodes, as shown in FIG. 1 The drain electrode 7 included in the thin film transistor is connected to the pixel electrode. The connection relationship and positional relationship between other components contained in the thin film transistor array substrate can be set according to the existing thin film transistor array substrate, and there is no special requirement for the embodiment of the present application. Since the thin film transistor array substrate contains the above-mentioned thin film transistors, and because the surface of the gate insulating layer 3 contained in the above-mentioned thin film transistors contains Si-N or/and Si-O chemical bonds, it suffers from high light Good stability is maintained when irradiated, therefore, the working performance of the thin film transistor array substrate is stable, especially in the environment of high light irradiation.

Likewise, based on the above-mentioned thin film transistor array substrate, an embodiment of the present application also provides a display device. The display device includes a thin film transistor array substrate, and the thin film transistor array substrate is the above thin film transistor array substrate. Since the display device includes the thin film transistor array-based thin film transistor of the embodiment of the present application, the display device of the embodiment of the present application has stable display performance and high display quality.

In the following, a plurality of examples are used to further illustrate the above-mentioned thin film transistor, its preparation method, the related performance of the display device, and the like.

Embodiment 1: thin film transistor embodiment

Example A1

This embodiment provides a thin film transistor and a manufacturing method thereof. The structure of the thin film transistor is shown in Figure 1, wherein the material of the substrate 1 is glass; the material of the gate insulating layer 3 is _SiNx , and the surface of the _SiNx layer contains Si-O and Si-N chemical bonds, and the active layer 4 The material of the flat layer 8 is a-Si:H, and the material of the flat layer 8 is PV.

The preparation method of the thin film transistor of the embodiment is prepared according to the process in Figure 3, wherein the thermal modification treatment method in step S03 includes the following steps:

In an oxygen environment, the gate insulating film is heat-treated at 250°C for 10s, so that a chemical reaction occurs between the surface of the gate insulating film and oxygen, and the Si-O chemical bond is formed on the surface of the gate insulating film, and the gate insulating film is formed at the same time. The surface of layer 3 contains Si-N chemical bonds. Wherein, oxygen is passed through the reaction system at a flow rate of 1000 sccm.

Example A2

This embodiment provides a thin film transistor and a manufacturing method thereof. The structure of the thin film transistor and its preparation method are the same as in Example A1. Wherein, the difference from the embodiment A1 is that the gate insulating film is heat-treated at 250° C. for 60 s, and oxygen is passed through the reaction system at a flow rate of 5000 sccm.

Example A3

This embodiment provides a thin film transistor and a manufacturing method thereof. The structure of the thin film transistor and its preparation method are the same as in Example A1. Wherein, the difference from the embodiment A1 is that the gate insulating film is heat-treated at 250° C. for 30 s in a nitrogen environment, and oxygen is passed through the reaction system at a flow rate of 3000 sccm.

Example A4

This embodiment provides a thin film transistor and a manufacturing method thereof. The structure of the thin film transistor and its preparation method are the same as in Example A1. Wherein, the difference from the embodiment A1 is that the gate insulating film is heat-treated at 200° C. for 30 seconds in an ammonia atmosphere, and oxygen is passed through the reaction system at a flow rate of 3000 sccm, and the material of the gate insulating film is silicon oxynitride.

Comparative example 1:

This comparative example provides a thin film transistor, the structure of which is the same as in Example A1, the difference is that the gate insulating layer 3 contained in the thin film transistor of this comparative example is a SiN _x layer, that is, compared with Example 1, the thin film of this comparative example The gate insulating layer 3 contained in the transistor does not undergo the thermal modification treatment in step S03 in Example 1, that is, the surface of the gate insulating layer 3 contained in the thin film transistor of this comparative example is the surface of a conventional _SiNx layer.

Embodiment 2: Embodiment of Thin Film Transistor Array Substrate

Example B1 to Example B4

Embodiment B1 to Embodiment B4 respectively provide a thin film transistor array substrate. The thin film transistor array substrate in each embodiment includes a base substrate and thin film transistors disposed on the base substrate. Wherein, the thin film transistors contained in the thin film transistor array substrate provided in embodiment B1 are the thin film transistors provided in embodiment A1, and the thin film transistors contained in the thin film transistor array substrate provided in embodiment B2 are the thin film transistors provided in embodiment A2. The thin film transistors contained in the thin film transistor array substrate provided in B3 are the thin film transistors provided in embodiment A3, and the thin film transistors contained in the thin film transistor array substrate provided in embodiment B4 are the thin film transistors provided in embodiment A4.

Embodiment 3: embodiment of a thin film transistor display device

Example C1 to Example C4

Embodiment C1 to Embodiment C4 respectively provide a display device. Display devices in various embodiments include a thin film transistor array substrate. Wherein, the thin film transistors contained in the thin film transistor array substrate provided in embodiment C1 are the thin film transistors provided in embodiment B1, and the thin film transistors contained in the thin film transistor array substrate provided in embodiment C2 are the thin film transistors provided in embodiment B2. The thin film transistors contained in the thin film transistor array substrate provided by C3 are the thin film transistors provided by embodiment B3, and the thin film transistors contained in the thin film transistor array substrate provided by embodiment C4 are the thin film transistors provided by embodiment B4.

Performance Testing:

The thin film transistors in the above-mentioned Example A1 to Example A4 and Comparative Example A1 were characterized by electrical characteristic values. The specific test conditions were Vd=10V mask=1000lux. The measured results are shown in Table 2 below:

Table 2

It can be seen from the above Table 2 that, compared with the unmodified conventional gate insulating layer provided in Comparative Example 1, the leakage current of the thin film transistors of Example A1 to Example A4 of the present application has been significantly reduced, and can be significantly reduced. The switching ratio of the thin film transistor device is improved, and the switching characteristics of the thin film transistor are improved, and the effect of embodiment A3 is the most remarkable. Therefore, the reliability of the thin film transistor of the embodiment of the present application is significantly improved under relatively high-intensity light, and the performance stability of the thin film transistor device is improved.

Further relevant performance tests were carried out on the thin film transistor array substrates provided in the above-mentioned embodiments B1 to B4 and the display devices provided in the embodiments C1 to C4, and it was found that based on the thin film transistor films in the embodiments A1 to A4, the implementation The thin film transistor array substrates provided in Example B1 to Example B4 all have stable performance in high light irradiation environments, and the corresponding displays provided in Example C1 to Example C4 have stable display performance. Compared with the TFT array substrate and display provided in Comparative Example 1, the TFT array substrates and corresponding displays provided by the embodiments of the present application have significantly improved working stability.

The above descriptions are only preferred embodiments of the application, and are not intended to limit the application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the application should be included in the protection of the application. within range.

Claims

A method for preparing a thin film transistor, comprising the steps of:

According to the structure of the thin film transistor, on the surface of the substrate (1), sequentially form a gate (2), a gate insulating layer (3), an active layer (4), an n + amorphous silicon layer (5), a source electrode (6 ) and drain electrode (7), forming a thin film transistor;

Wherein, the method for forming the gate insulating layer (3) includes the following steps:

forming a gate insulating film containing silicon on the surface of the substrate (1) on which the gate (2) is formed;

Performing thermal modification treatment on the gate insulating film to generate Si-N or/and Si-O chemical bonds on the surface of the gate insulating film to form a surface-modified gate insulating layer (3).
The preparation method according to claim 1, wherein, during the heat modification treatment, the temperature of the gate insulating film is 200-300° C., and the time of the heat modification treatment is 10-60 s.
The preparation method according to claim 2, wherein the temperature of the gate insulating film is 230-270° C., and the time of the thermal modification treatment is 20-40 s.
The preparation method according to any one of claims 1-3, wherein the method of thermally modifying the gate insulating film comprises the following steps:

In a nitrogen-containing gas environment and/or an oxygen-containing gas environment, heat treatment is performed on the gate insulating film, so that a chemical reaction occurs between the surface of the gate insulating film and the gas of nitrogen element and/or oxygen, and the The Si-N or/and Si-O chemical bonds are formed on the surface of the pole insulating film.
The preparation method according to claim 4, wherein the method of thermally modifying the gate insulating film comprises the following steps:

placing the substrate (1) on which the gate insulating film containing silicon is formed in a nitrogen-containing gas environment and/or an oxygen-containing gas environment;

The substrate (1) is subjected to heating treatment until the preset temperature of the thermal modification treatment is adjusted, and heat preservation treatment is carried out; so that the above described chemical reaction.
The preparation method according to claim 4, wherein the nitrogen-containing gas environment and/or the oxygen-containing gas pass through the surface of the gate insulating film at a flow rate of 1000-5000 sccm.
The preparation method according to claim 4, wherein the nitrogen-containing gas includes at least one of N 2 and NH 3 .
The preparation method according to claims 1-3, 5-7, wherein the material of the formed gate insulating film comprises an insulating compound of nitrogen and silicon.
The preparation method according to claim 8, wherein the insulating compound comprises at least one of silicon nitride, silicon oxynitride, and silicon fluoride nitride.
The preparation method as claimed in claims 1-3, 5-7, 9, further comprising the steps of:

Forming a flat layer (8) on the outer surface of the gate insulating layer (3) provided with the source electrode (6), drain electrode (7), n + amorphous silicon layer (5), and active layer (4) , to cover the source electrode (6), the drain electrode (7), the n + amorphous silicon layer (5), and the active layer (4).
A thin film transistor, comprising a gate insulating layer (3) and a gate (2) formed on a substrate (1), the gate insulating layer (3) and the gate (2) provided with the gate The surface of the substrate (1) is laminated and covers the gate (2), wherein the material of the gate insulating layer (3) contains silicon element, and the surface of the gate insulating layer (3) contains Si -N or/and Si-O chemical bond.
The thin film transistor according to claim 11, wherein a material of the insulating compound comprises an insulating compound containing nitrogen and silicon.
The thin film transistor according to claim 12, wherein the insulating compound comprises at least one of silicon nitride, silicon oxynitride, and silicon fluoride nitride.
The thin film transistor according to any one of claims 11-13, wherein an active layer (4) is provided on the surface of the gate insulating layer (3) away from the substrate (1) and an active layer (4) is provided on the active An n + amorphous silicon layer (5) is arranged on the outer surface of the layer (4), and a source electrode (6) and a drain electrode (7) are arranged on the outer surface of the n + amorphous silicon layer (5).
The thin film transistor according to claim 14, further comprising a flat layer (8), the flat layer (8) is formed on the active layer (4) provided with the source electrode (6) and the drain electrode (7) ) and cover the source electrode (6), drain electrode (7), n + amorphous silicon layer (5) and active layer (4).
A thin film transistor array substrate, comprising a base substrate and a thin film transistor disposed on the base substrate, wherein the thin film transistor is the thin film transistor according to any one of claims 11-15.
A display device comprising a thin film transistor array substrate, wherein the thin film transistor array substrate is the thin film transistor array substrate according to claim 16 .