WO2022242065A1 - 一种应用于高密度互连电路板无芯板的制作方法 - Google Patents
一种应用于高密度互连电路板无芯板的制作方法 Download PDFInfo
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- WO2022242065A1 WO2022242065A1 PCT/CN2021/130219 CN2021130219W WO2022242065A1 WO 2022242065 A1 WO2022242065 A1 WO 2022242065A1 CN 2021130219 W CN2021130219 W CN 2021130219W WO 2022242065 A1 WO2022242065 A1 WO 2022242065A1
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- WIPO (PCT)
- Prior art keywords
- manufacturing
- coreless
- carrier
- copper
- circuit board
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 73
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 238000005520 cutting process Methods 0.000 claims abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 60
- 229910052802 copper Inorganic materials 0.000 claims description 56
- 239000010949 copper Substances 0.000 claims description 56
- 238000003475 lamination Methods 0.000 claims description 25
- 238000005516 engineering process Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 15
- 238000003825 pressing Methods 0.000 claims description 7
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 5
- 239000003504 photosensitizing agent Substances 0.000 claims description 5
- 238000005562 fading Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 28
- 239000011229 interlayer Substances 0.000 abstract description 7
- 238000009713 electroplating Methods 0.000 description 15
- 238000007747 plating Methods 0.000 description 10
- 238000005406 washing Methods 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- 239000007788 liquid Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- 238000005553 drilling Methods 0.000 description 6
- 238000010030 laminating Methods 0.000 description 6
- 239000000654 additive Substances 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004810 polytetrafluoroethylene Substances 0.000 description 2
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 2
- VOZKAJLKRJDJLL-UHFFFAOYSA-N 2,4-diaminotoluene Chemical compound CC1=CC=C(N)C=C1N VOZKAJLKRJDJLL-UHFFFAOYSA-N 0.000 description 1
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 239000004696 Poly ether ether ketone Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- JUPQTSLXMOCDHR-UHFFFAOYSA-N benzene-1,4-diol;bis(4-fluorophenyl)methanone Chemical compound OC1=CC=C(O)C=C1.C1=CC(F)=CC=C1C(=O)C1=CC=C(F)C=C1 JUPQTSLXMOCDHR-UHFFFAOYSA-N 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 238000005554 pickling Methods 0.000 description 1
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 1
- 229920002530 polyetherether ketone Polymers 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
Definitions
- the invention belongs to the technical field of circuit board processing, and in particular relates to a method for manufacturing a coreless board applied to a high-density interconnect circuit board.
- B 2 it embedded bump interconnect technology: B 2 it technology was developed by Toshiba in June 1997. B 2 it (Buried Bump Imterconnection Technology) is a high-density interconnection technology (HDI) formed by embedding bumps. The biggest difference from the traditional printed board process is that the electrical interconnection between printed board layers is not through "holes". "It is formed by a conductive adhesive bump penetrating the prepreg to connect the two copper foils, so there is no need for drilling, electroless copper plating and electroplating copper and other production processes. technical problem
- the conductive glue (containing silver or copper, etc.) is printed on the copper foil, and the conductive bump is formed after drying.
- pressure and heat are applied to make the conductive bumps penetrate the prepreg resin layer, and the laminated and interconnected board undergoes a traditional image transfer process to form a double-sided board.
- the prepreg and copper foil with bumps are stacked on the double-sided board, and after pressing, the image can be transferred to form a 4-layer board, 6-layer board, etc.
- the accuracy and process capability of bump printing are limited, and the hole density processing capability is limited.
- NMBI copper bump conduction interconnection this technology was developed by North Corporation of Japan.
- the main method is: use copper bumps on the copper foil to conduct the interlayer lines, so that the drilling (mechanical drilling or laser drilling) required for the production of traditional via holes can be omitted.
- electroplating two processes Even better, it can avoid uneven copper plating caused by electroplating, so that it is difficult to control the line width during etching, and it is difficult to control the impedance.
- the processability is not high due to poor density and uniformity of copper bump fabrication.
- the present invention provides a method for manufacturing a coreless board applied to a high-density interconnection circuit board.
- a method for manufacturing a coreless board applied to a high-density interconnect circuit board characterized in that it comprises the following steps:
- the metal carrier is a copper carrier or a copper alloy carrier.
- steps S2-S4 are repeated to realize single-side build-up.
- layer deviation can be effectively avoided by using the single-side layer build-up method.
- step S2 the specific method includes lamination-exposure and development-electroplating-film removal. Use exposure and development to make copper pillars and open windows, and use electroplating to make metal pillars.
- step S2 it is specifically as follows: lamination: film lamination speed is 0.5-1.5m/min, film lamination temperature is 90-120°C, film lamination pressure is 4-8kgf/cm2, board entry temperature is 30-60°C, board exit The temperature is 50-60°C; the time from film application to exposure is controlled at 0.25-24H; the exposure: the uniformity of exposure energy is ⁇ 90%, and the time from exposure to development is controlled at 0.25-24H; development: the development temperature is 30 ⁇ 2°C; The control range of A liquid K 2 CO 3 or Na 2 CO 3 is 10 ⁇ 2g/l, the pH value is 9-12, the control range of developing B liquid K 2 CO 3 or Na 2 CO 3 is 10 ⁇ 2g/l, pH value is 9-12; film removal: including bulking, film removal, pickling, overflow washing, pressure washing, swinging high pressure washing, dry plate combination.
- step S2 a photosensitizer or a photosensitive dry film is used for lamination.
- the specific method includes pressing with an insulating medium, and then exposing the top of the copper pillar by grinding.
- the insulating medium with good filling effect and uniformity is selected, such as various insulating resins in the prior art, for lamination.
- the insulating medium is any one of polyimide, PET, PEN, LCP, PEEK, PTFE, insulating ink and resin.
- step S4 use SAP technology to make lines.
- the circuit is formed by using a semi-additive method.
- a photosensitive dry film is covered, exposed to ultraviolet light and developed to expose the required place, and then the exposed place is thickened by electroplating. To the required thickness specifications, then remove the photosensitive dry film, remove the pre-fabricated thin copper, and keep the required circuit.
- step S4 the specific method includes: planting seed copper—laminating film—exposure and development—electroplating—film stripping—seed copper stripping.
- the SAP technology includes: making seed copper; sticking a dry film on the seed copper; exposure and development; electroplating, including via copper plating and line copper plating; film removal: using a stripping solution to dissolve the dry film; : Remove the unplated and thickened seed copper by etching potion.
- the exposure and development include: irradiating with UV light from the front of the film negative.
- the film negative has two parts, black and transparent. The black part cannot pass through the light, and the transparent part can pass through the light.
- the photosensitivity of the dry film changes, and the graphics on the film negative are transferred to the dry film; after exposure, the film negative can be removed or the required lines can be drawn directly on the photosensitive dry film on the board surface by using ultraviolet light.
- develop with developing solution the photosensitive dry film will remain, the non-photosensitive dry film will be dissolved, the part with conductor circuit will be exposed, and the part without conductor circuit will be protected by dry film.
- step S5 the carrier is removed by an etching method in the prior art.
- step S6 the specific method includes selecting and directly etching the metal carrier according to the wiring density to realize the bottom circuit.
- step S6 the specific method includes, according to the wiring density, if any one of the line width/line spacing is less than or equal to 50 ⁇ m, first perform step 5 to remove the carrier, and then use the SAP technology in step S4 to make the circuit.
- the present invention realizes conduction and interconnection by copper pillars, uses copper or other conduction metals as the carrier, adds metal pillars on the carrier and realizes conduction between metal pillar layers, eliminating the need for traditional interlayer conduction. Hole processing (mechanical drilling, laser drilling, etc.) wiring density.
- the processability of the coreless board manufacturing method can be effectively improved, and the layout density and the interlayer connection density of the product can be improved at the same time, so as to realize the interconnection of any layer.
- a method for manufacturing a coreless board applied to a high-density interconnect circuit board characterized in that it comprises the following steps:
- the metal carrier is a copper carrier or a copper alloy carrier.
- steps S2-S4 are repeated to realize single-side build-up.
- layer deviation can be effectively avoided by using the single-side layer build-up method.
- step S2 the specific method includes lamination-exposure and development-electroplating-film removal. Use exposure and development to make copper pillars and open windows, and use electroplating to make metal pillars.
- step S2 it is specifically: film lamination: film lamination speed is 0.7m/min, film lamination temperature is 110°C, film lamination pressure is 6kgf/cm2, board entry temperature is 30°C, board exit temperature is 50°C; film lamination to exposure The time is controlled at 0.25-24H; the exposure: exposure energy uniformity ⁇ 90%, the time from exposure to development is controlled at 0.25-24H; development: the development temperature is 30 ⁇ 2°C; the control range of the development A liquid K 2 CO 3 is 10 ⁇ 2g/l, pH value is 10.7, the control range of developing liquid B K 2 CO 3 is 10 ⁇ 2g/l, pH value is 11.5; Pressurized water washing, rocking high pressure water washing, dry plate combination.
- step S2 a photosensitizer or a photosensitive dry film is used for lamination.
- the specific method includes using an insulating medium to perform thermocompression bonding, and then exposing the top of the copper pillar by grinding.
- An insulating medium with a good filling effect and uniformity is selected, such as various insulating resins in the prior art, for thermocompression bonding.
- the insulating medium is insulating resin.
- step S4 use SAP technology to make lines.
- the circuit is formed by using a semi-additive method.
- a photosensitive dry film is covered, exposed to ultraviolet light and developed to expose the required place, and then the exposed place is thickened by electroplating. To the required thickness specifications, then remove the photosensitive dry film, remove the pre-fabricated thin copper, and keep the required circuit.
- step S4 the specific method includes: planting seed copper—laminating film—exposure and development—electroplating—film stripping—seed copper stripping.
- the SAP process includes: making seed copper; sticking a dry film on the seed; exposure and development; electroplating, including via copper plating and line copper plating; film fading: using a stripping potion to dissolve the dry film; fading the seed copper: Remove the unplated and thickened seed copper with etching solution.
- the exposure and development include: directly use ultraviolet light to draw the required lines on the photosensitive dry film on the board surface, and then develop with the developing potion after standing still, the photosensitive dry film will remain, and the non-photosensitive dry film will be dissolved , the part with the conductor line will be exposed, and the part without the conductor line will be protected by the dry film.
- step S5 the carrier is removed by an etching method in the prior art.
- step S6 the specific method includes selecting and directly etching the metal carrier according to the wiring density to realize the bottom circuit.
- step S6 the specific method includes, according to the wiring density, if any one of the line width/line spacing is less than or equal to 50 ⁇ m, first perform step 5 to remove the carrier, and then use the SAP technology in step S4 to make the circuit.
- the processability of the coreless board manufacturing method can be effectively improved, and the layout density and the interlayer connection density of the product can be improved at the same time, so as to realize the interconnection of any layer.
- a method for manufacturing a coreless board applied to a high-density interconnect circuit board characterized in that it comprises the following steps:
- the metal carrier is a copper carrier or a copper alloy carrier.
- steps S2-S4 are repeated to realize single-side build-up.
- layer deviation can be effectively avoided by using the single-side layer build-up method.
- step S2 the specific method includes lamination-exposure and development-electroplating-film removal. Use exposure and development to make copper pillars and open windows, and use electroplating to make metal pillars.
- step S2 it is specifically as follows: lamination: film laminating speed is 1m/min, film lamination temperature is 100°C, film laminating pressure is 5kgf/cm2, board entry temperature is 45°C, board exit temperature is 55°C; film lamination to exposure time Control at 0.25-24H; the exposure: the uniformity of exposure energy ⁇ 90%, the time from exposure to development is controlled at 0.25-24H; development: the development temperature is 30 ⁇ 2°C; the control range of the development A liquid K 2 CO 3 is 10 ⁇ 2g/l, pH value is 10.5, the control range of developing liquid B K 2 CO 3 is 10 ⁇ 2g/l, pH value is 12; Pressure washing, swinging high pressure washing, dry board combination.
- step S2 a photosensitizer or a photosensitive dry film is used for lamination.
- the specific method includes pressing with an insulating medium, and then exposing the top of the copper pillar by grinding.
- the insulating medium with good filling effect and uniformity is selected, such as various insulating resins in the prior art, for lamination.
- the insulating medium is PTFE.
- step S4 the SAP process is used to fabricate the circuit.
- the circuit is formed by using a semi-additive method.
- a photosensitive dry film is covered, exposed to ultraviolet light and developed to expose the required place, and then the exposed place is thickened by electroplating. To the required thickness specifications, then remove the photosensitive dry film, remove the pre-fabricated thin copper, and keep the required circuit.
- step S4 the specific method includes: planting seed copper—laminating film—exposure and development—electroplating—film stripping—seed copper stripping.
- the SAP process includes: making seed copper; sticking a dry film on the seed copper; exposure and development; electroplating, including via copper plating and line copper plating; film removal: using a stripping solution to dissolve the dry film; : Remove the unplated and thickened seed copper by etching potion.
- the exposure and development include: directly use ultraviolet light to draw the required lines on the photosensitive dry film on the board surface, and then develop with the developing potion after standing still, the photosensitive dry film will remain, and the non-photosensitive dry film will be dissolved , the part with the conductor line will be exposed, and the part without the conductor line will be protected by the dry film.
- step S5 the carrier is removed by an etching method in the prior art.
- step S6 the specific method includes selecting and directly etching the metal carrier according to the wiring density to realize the bottom circuit.
- step S6 the specific method includes, according to the wiring density, if any one of the line width/line spacing is less than or equal to 50 ⁇ m, first perform step 5 to remove the carrier, and then use the SAP process in step S4 to fabricate the circuit.
- the processability of the coreless board manufacturing method can be effectively improved, and the layout density and the interlayer connection density of the product can be improved at the same time, so as to realize the interconnection of any layer.
- a method for manufacturing a coreless board applied to a high-density interconnect circuit board characterized in that it comprises the following steps:
- the metal carrier is a copper carrier or a copper alloy carrier.
- steps S2-S4 are repeated to realize single-side build-up.
- layer deviation can be effectively avoided by using the single-side layer build-up method.
- step S2 the specific method includes lamination-exposure and development-electroplating-film removal. Use exposure and development to make copper pillars and open windows, and use electroplating to make metal pillars.
- step S2 it is specifically: film lamination: film lamination speed is 1.3m/min, film lamination temperature is 120°C, film lamination pressure is 7kgf/cm2, board entry temperature is 30°C, board exit temperature is 80°C; film lamination to exposure The time is controlled at 0.25-24H; the exposure: exposure energy uniformity ⁇ 90%, the time from exposure to development is controlled at 0.25-24H; development: the development temperature is 30 ⁇ 2°C; the control range of the development A liquid K 2 CO 3 is 10 ⁇ 2g/l, pH value is 12, the control range of developer B liquid K 2 CO 3 is 10 ⁇ 2g/l, pH value is 12; Pressurized water washing, rocking high pressure water washing, dry plate combination.
- step S2 a photosensitizer or a photosensitive dry film is used for lamination.
- the specific method includes pressing with an insulating medium, and then exposing the top of the copper pillar by grinding.
- the insulating medium with good filling effect and uniformity is selected, such as various insulating resins in the prior art, for lamination.
- the insulating medium is polyimide.
- step S4 use SAP technology to make lines.
- the circuit is formed by using a semi-additive method.
- a photosensitive dry film is covered, exposed to ultraviolet light and developed to expose the required place, and then the exposed place is thickened by electroplating. To the required thickness specifications, then remove the photosensitive dry film, remove the pre-fabricated thin copper, and keep the required circuit.
- step S4 the specific method includes: planting seed copper—laminating film—exposure and development—electroplating—film stripping—seed copper stripping.
- the SAP process includes: making seed copper; sticking a dry film on the seed copper; exposure and development; electroplating, including via copper plating and line copper plating; film removal: using a stripping solution to dissolve the dry film; : Remove the unplated and thickened seed copper by etching potion.
- the exposure and development include: directly use ultraviolet light to draw the required lines on the photosensitive dry film on the board surface, and then develop with the developing potion after standing still, the photosensitive dry film will remain, and the non-photosensitive dry film will be dissolved , the part with the conductor line will be exposed, and the part without the conductor line will be protected by the dry film.
- step S5 the carrier is removed by an etching method in the prior art.
- step S6 the specific method includes selecting and directly etching the metal carrier according to the wiring density to realize the bottom circuit.
- step S6 the specific method includes, according to the wiring density, if any one of the line width/line spacing is less than or equal to 50 ⁇ m, first perform step 5 to remove the carrier, and then use the SAP technology in step S4 to make the circuit.
- the processability of the coreless board manufacturing method can be effectively improved, and the layout density and the interlayer connection density of the product can be improved at the same time, so as to realize the interconnection of any layer.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
本发明属于电路板加工技术领域,具体涉及一种应用于高密度互连电路板无芯板的制作方法,其特征在于,包括以下步骤:S1. 金属载体开料;S2. 金属柱制作;S3. 绝缘层制作;S4. 顶层线路制作;S5. 载体去除;S6. 底部线路制作。通过本发明方法,可有效提升无芯板制作方法的可加工性,同时提升产品的布局密度及层间连接密度,实现任意层的互连。
Description
本发明属于电路板加工技术领域,具体涉及一种应用于高密度互连电路板无芯板的制作方法。
B
2it 嵌入凸块互连技术: B
2it技术是1997年6月由日本东芝开发的。B
2it(Buried Bump Imterconnection Technology)是一种嵌入凸块而形成的高密度互连技术(HDI),与传统的印制板工艺最大区别是,印制板层间电气互连不是通过“孔”来形成的,而是通过一种导电胶凸块穿透半固化片连接两个面铜箔来完成的,因而不需钻孔、化学镀铜和电镀铜等生产过程。
技术问题
首先将导电胶(含银或铜等)印制于铜箔上,烘干后形成导电凸块。在压制互连过程中,加压和加热使导电凸块穿透半固化片树脂层,经过层压互连后的板进行传统的图像转移工艺来形成双面板。依此类推,在此双面板上叠上半固化片和带有凸块的铜箔,经过压制,图像转移便可形成4层板、6 层板等。但是,凸块印刷的精度及工艺能力有限,孔密度加工能力有限。
另外,NMBI 铜凸块导通互连:此项技术由日本North公司开发。其主要方法为:使用长在铜箔上的铜凸块来作各层间线路的导通,如此可以省去传统导通孔制作时所需的钻孔(机械钻孔或是镭射钻孔)以及电镀两个制程。更好的是,可以避免因电镀造成的镀铜不均,以致在蚀刻时线路宽度不易控制,以及造成阻抗难以掌控。但是,由于铜凸块制作的密度和一致性较差,可加工性不高。
有鉴于此,本发明提供一种应用于高密度互连电路板无芯板的制作方法。
本发明的技术方案为:
一种应用于高密度互连电路板无芯板的制作方法,其特征在于,包括以下步骤:
S1. 金属载体开料;
S2. 金属柱制作;
S3. 绝缘层制作;
S4. 顶层线路制作;
S5. 载体去除;
S6. 底部线路制作。
进一步的,所述金属载体为铜载体或铜合金载体。
进一步的,对于多层板,重复步骤S2-S4的流程,实现单面增层。本发明中,通过使用单面增层法可以有效避免层偏。
进一步的,步骤S2中,具体方法包括压膜—曝光显影—电镀—褪膜。采用曝光显影制作铜柱开窗,使用电镀加成的方式制作金属柱。
所述步骤S2中,具体为:压膜:贴膜速度为0.5-1.5m/min,贴膜温度为90-120℃,贴膜压力为4-8kgf/cm²,入板温度为30-60℃,出板温度为50-60℃;贴膜到曝光时间控制在0.25-24H;所述曝光:曝光能量均匀性≥90%,曝光到显影时间控制在0.25-24H;显影:显影温度为30±2℃;显影A液K
2CO
3或Na
2CO
3的控制范围为10±2g/l,pH值为9-12,显影B液K
2CO
3或Na
2CO
3的控制范围为10±2g/l,pH值为9-12;退膜:包括膨松、退膜、酸洗、溢流水洗、加压水洗、摇摆高压水洗、干板组合。
进一步的,步骤S2中,使用光敏剂或感光干膜进行压膜。
进一步的,步骤S3中,具体方法包括采用绝缘介质进行压合,再通过研磨的方式露出铜柱顶部。选用填充效果及均匀性好的绝缘介质,如现有技术中的各类绝缘树脂,进行压合。
所述绝缘介质为聚酰亚胺、PET、PEN、LCP、PEEK、PTFE、绝缘油墨、树脂的任一种。
进一步的,步骤S4中,使用SAP技术制作线路。
本发明中,线路的形成是采用半加成法,在预先制作薄铜的基板上,覆盖感光干膜,经紫外光曝光-显影,把需要的地方露出,再利用电镀把露出的地方加厚至所需要的厚度规格,然后去除感光干膜,在褪除预先制作的薄铜,保留下来所需要的线路。
进一步的,步骤S4中,具体方法包括:种种子铜—压膜—曝光显影—电镀—褪膜—褪种子铜。
所述SAP技术包括:制作种子铜;在所述种子铜上贴干膜;曝光显影;电镀,包括过孔镀铜和线路镀铜;褪膜:使用脱膜药水将干膜溶解;褪种子铜:将未电镀加厚的种子铜通过蚀刻药水去除干净。
所述曝光显影包括:从所述菲林底片正面采用UV光线照射,所述菲林底片有黑色和透明两部分,黑色部分光线透不过去,透明部分光线可以透过去,透过去的光线将使下面的干膜感光发生变化,完成所述菲林底片上的图形转印到所述干膜上;曝光后即可以去掉所述菲林底片或者直接使用紫外光在板面感光干膜上绘制所需线路,静置后再通过显影药水进行显影,已感光反应的干膜将仍保留,没有感光的干膜将被溶解,有导体线路部分将裸露出来,没有导体线路部分将被干膜保护住。
进一步的,步骤S5中,通过现有技术的蚀刻方法去除载体。
进一步的,步骤S6中,具体方法包括根据布线密度,选择直接蚀刻金属载体,实现底部线路。
进一步的,步骤S6中,具体方法包括,根据布线密度,若线宽/线距任意一个小于等于50μm,先执行步骤5去除载体,再使用步骤S4中SAP技术制作线路。
本发明是由铜柱实现导通互连,使用铜或者其他导通金属作为载体,通过在载体上加成金属柱以及实现金属柱层间的导通,省去传统层间导通所需要的孔加工(机械钻孔、激光钻孔等)和孔金属化的制程,金属柱不但可以有效提升电气导通性能,而且可以提升产品导通金属柱的布局密度,线路选用SAP技术,有效提升产品的布线密度。
通过本发明方法,可有效提升无芯板制作方法的可加工性,同时提升产品的布局密度及层间连接密度,实现任意层的互连。
为使本发明的目的、技术方案及优点更加清楚明白,以下结合具体实施方式,对本发明进行进一步的详细说明。应当理解的是,此处所描述的具体实施方式仅用以解释本发明,并不限定本发明的保护范围。
实施例1
一种应用于高密度互连电路板无芯板的制作方法,其特征在于,包括以下步骤:
S1. 金属载体开料;
S2. 金属柱制作;
S3. 绝缘层制作;
S4. 顶层线路制作;
S5. 载体去除;
S6. 底部线路制作。
进一步的,所述金属载体为铜载体或铜合金载体。
进一步的,对于多层板,重复步骤S2-S4的流程,实现单面增层。本发明中,通过使用单面增层法可以有效避免层偏。
进一步的,步骤S2中,具体方法包括压膜—曝光显影—电镀—褪膜。采用曝光显影制作铜柱开窗,使用电镀加成的方式制作金属柱。
所述步骤S2中,具体为:压膜:贴膜速度为0.7m/min,贴膜温度为110℃,贴膜压力为6kgf/cm²,入板温度为30℃,出板温度为50℃;贴膜到曝光时间控制在0.25-24H;所述曝光:曝光能量均匀性≥90%,曝光到显影时间控制在0.25-24H;显影:显影温度为30±2℃;显影A液K
2CO
3的控制范围为10±2g/l,pH值为10.7,显影B液K
2CO
3的控制范围为10±2g/l,pH值为11.5;退膜:包括膨松、退膜、酸洗、溢流水洗、加压水洗、摇摆高压水洗、干板组合。
进一步的,步骤S2中,使用光敏剂或感光干膜进行压膜。
进一步的,步骤S3中,具体方法包括采用绝缘介质进行热压合,再通过研磨的方式露出铜柱顶部。选用填充效果及均匀性好的绝缘介质,如现有技术中的各类绝缘树脂,进行热压合。
所述绝缘介质为绝缘树脂。
进一步的,步骤S4中,使用SAP技术制作线路。
本发明中,线路的形成是采用半加成法,在预先制作薄铜的基板上,覆盖感光干膜,经紫外光曝光-显影,把需要的地方露出,再利用电镀把露出的地方加厚至所需要的厚度规格,然后去除感光干膜,在褪除预先制作的薄铜,保留下来所需要的线路。
进一步的,步骤S4中,具体方法包括:种种子铜—压膜—曝光显影—电镀—褪膜—褪种子铜。
所述SAP工艺包括:制作种子铜;在所述种子上贴干膜;曝光显影;电镀,包括过孔镀铜和线路镀铜;褪膜:使用脱膜药水将干膜溶解;褪种子铜:将未电镀加厚的种子铜通过蚀刻药水去除干净。
所述曝光显影包括:直接使用紫外光在板面感光干膜上绘制所需线路,静置后再通过显影药水进行显影,已感光反应的干膜将仍保留,没有感光的干膜将被溶解,有导体线路部分将裸露出来,没有导体线路部分将被干膜保护住。
进一步的,步骤S5中,通过现有技术的蚀刻方法去除载体。
进一步的,步骤S6中,具体方法包括根据布线密度,选择直接蚀刻金属载体,实现底部线路。
进一步的,步骤S6中,具体方法包括,根据布线密度,若线宽/线距任意一个小于等于50μm,先执行步骤5去除载体,再使用步骤S4中SAP技术制作线路。
通过本发明方法,可有效提升无芯板制作方法的可加工性,同时提升产品的布局密度及层间连接密度,实现任意层的互连。
实施例2
一种应用于高密度互连电路板无芯板的制作方法,其特征在于,包括以下步骤:
S1. 金属载体开料;
S2. 金属柱制作;
S3. 绝缘层制作;
S4. 顶层线路制作;
S5. 载体去除;
S6. 底部线路制作。
进一步的,所述金属载体为铜载体或铜合金载体。
进一步的,对于多层板,重复步骤S2-S4的流程,实现单面增层。本发明中,通过使用单面增层法可以有效避免层偏。
进一步的,步骤S2中,具体方法包括压膜—曝光显影—电镀—褪膜。采用曝光显影制作铜柱开窗,使用电镀加成的方式制作金属柱。
所述步骤S2中,具体为:压膜:贴膜速度为1m/min,贴膜温度为100℃,贴膜压力为5kgf/cm²,入板温度为45℃,出板温度为55℃;贴膜到曝光时间控制在0.25-24H;所述曝光:曝光能量均匀性≥90%,曝光到显影时间控制在0.25-24H;显影:显影温度为30±2℃;显影A液K
2CO
3的控制范围为10±2g/l,pH值为10.5,显影B液K
2CO
3的控制范围为10±2g/l,pH值为12;退膜:包括膨松、退膜、酸洗、溢流水洗、加压水洗、摇摆高压水洗、干板组合。
进一步的,步骤S2中,使用光敏剂或感光干膜进行压膜。
进一步的,步骤S3中,具体方法包括采用绝缘介质进行压合,再通过研磨的方式露出铜柱顶部。选用填充效果及均匀性好的绝缘介质,如现有技术中的各类绝缘树脂,进行压合。
所述绝缘介质为PTFE。
进一步的,步骤S4中,使用SAP工艺制作线路。
本发明中,线路的形成是采用半加成法,在预先制作薄铜的基板上,覆盖感光干膜,经紫外光曝光-显影,把需要的地方露出,再利用电镀把露出的地方加厚至所需要的厚度规格,然后去除感光干膜,在褪除预先制作的薄铜,保留下来所需要的线路。
进一步的,步骤S4中,具体方法包括:种种子铜—压膜—曝光显影—电镀—褪膜—褪种子铜。
所述SAP工艺包括:制作种子铜;在所述种子铜上贴干膜;曝光显影;电镀,包括过孔镀铜和线路镀铜;褪膜:使用脱膜药水将干膜溶解;褪种子铜:将未电镀加厚的种子铜通过蚀刻药水去除干净。
所述曝光显影包括:直接使用紫外光在板面感光干膜上绘制所需线路,静置后再通过显影药水进行显影,已感光反应的干膜将仍保留,没有感光的干膜将被溶解,有导体线路部分将裸露出来,没有导体线路部分将被干膜保护住。
进一步的,步骤S5中,通过现有技术的蚀刻方法去除载体。
进一步的,步骤S6中,具体方法包括根据布线密度,选择直接蚀刻金属载体,实现底部线路。
进一步的,步骤S6中,具体方法包括,根据布线密度,若线宽/线距任意一个小于等于50μm,先执行步骤5去除载体,再使用步骤S4中SAP工艺制作线路。
通过本发明方法,可有效提升无芯板制作方法的可加工性,同时提升产品的布局密度及层间连接密度,实现任意层的互连。
实施例3
一种应用于高密度互连电路板无芯板的制作方法,其特征在于,包括以下步骤:
S1. 金属载体开料;
S2. 金属柱制作;
S3. 绝缘层制作;
S4. 顶层线路制作;
S5. 载体去除;
S6. 底部线路制作。
进一步的,所述金属载体为铜载体或铜合金载体。
进一步的,对于多层板,重复步骤S2-S4的流程,实现单面增层。本发明中,通过使用单面增层法可以有效避免层偏。
进一步的,步骤S2中,具体方法包括压膜—曝光显影—电镀—褪膜。采用曝光显影制作铜柱开窗,使用电镀加成的方式制作金属柱。
所述步骤S2中,具体为:压膜:贴膜速度为1.3m/min,贴膜温度为120℃,贴膜压力为7kgf/cm²,入板温度为30℃,出板温度为80℃;贴膜到曝光时间控制在0.25-24H;所述曝光:曝光能量均匀性≥90%,曝光到显影时间控制在0.25-24H;显影:显影温度为30±2℃;显影A液K
2CO
3的控制范围为10±2g/l,pH值为12,显影B液K
2CO
3的控制范围为10±2g/l,pH值为12;退膜:包括膨松、退膜、酸洗、溢流水洗、加压水洗、摇摆高压水洗、干板组合。
进一步的,步骤S2中,使用光敏剂或感光干膜进行压膜。
进一步的,步骤S3中,具体方法包括采用绝缘介质进行压合,再通过研磨的方式露出铜柱顶部。选用填充效果及均匀性好的绝缘介质,如现有技术中的各类绝缘树脂,进行压合。
所述绝缘介质为聚酰亚胺。
进一步的,步骤S4中,使用SAP技术制作线路。
本发明中,线路的形成是采用半加成法,在预先制作薄铜的基板上,覆盖感光干膜,经紫外光曝光-显影,把需要的地方露出,再利用电镀把露出的地方加厚至所需要的厚度规格,然后去除感光干膜,在褪除预先制作的薄铜,保留下来所需要的线路。
进一步的,步骤S4中,具体方法包括:种种子铜—压膜—曝光显影—电镀—褪膜—褪种子铜。
所述SAP工艺包括:制作种子铜;在所述种子铜上贴干膜;曝光显影;电镀,包括过孔镀铜和线路镀铜;褪膜:使用脱膜药水将干膜溶解;褪种子铜:将未电镀加厚的种子铜通过蚀刻药水去除干净。
所述曝光显影包括:直接使用紫外光在板面感光干膜上绘制所需线路,静置后再通过显影药水进行显影,已感光反应的干膜将仍保留,没有感光的干膜将被溶解,有导体线路部分将裸露出来,没有导体线路部分将被干膜保护住。
进一步的,步骤S5中,通过现有技术的蚀刻方法去除载体。
进一步的,步骤S6中,具体方法包括根据布线密度,选择直接蚀刻金属载体,实现底部线路。
进一步的,步骤S6中,具体方法包括,根据布线密度,若线宽/线距任意一个小于等于50μm,先执行步骤5去除载体,再使用步骤S4中SAP技术制作线路。
通过本发明方法,可有效提升无芯板制作方法的可加工性,同时提升产品的布局密度及层间连接密度,实现任意层的互连。
对于本领域技术人员而言,显然本发明不限于上述示范性实施例的细节,而且在不背离本发明的精神或基本特征的情况下,能够以其他的具体形式实现本发明。因此,无论从哪一点来看,均应将实施例看作是示范性的,而且是非限制性的,本发明的范围由所附权利要求而不是上述说明限定,因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。
此外,应当理解,虽然本说明书按照实施方式加以描述,但并非每个实施方式仅包含一个独立的技术方案,说明书的这种叙述方式仅仅是为清楚起见,本领域技术人员应当将说明书作为一个整体,各实施例中的技术方案也可以经适当组合,形成本领域技术人员可以理解的其他实施方式。需注意的是,本发明中所未详细描述的技术特征,均可以通过本领域任一现有技术实现。
Claims (10)
- 一种应用于高密度互连电路板无芯板的制作方法,其特征在于,包括以下步骤:S1. 金属载体开料;S2. 金属柱制作;S3. 绝缘层制作;S4. 顶层线路制作;S5. 载体去除;S6. 底部线路制作。
- 根据权利要求1所述的应用于高密度互连电路板无芯板的制作方法,其特征在于,所述金属载体为铜载体或铜合金载体。
- 根据权利要求1或2所述的应用于高密度互连电路板无芯板的制作方法,其特征在于,对于多层板,重复步骤S2-S4的流程,实现单面增层。
- 根据权利要求3所述的应用于高密度互连电路板无芯板的制作方法,其特征在于,步骤S2中,具体方法包括压膜—曝光显影—电镀—褪膜。
- 根据权利要求4所述的应用于高密度互连电路板无芯板的制作方法,其特征在于,步骤S2中,使用光敏剂或感光干膜进行压膜。
- 根据权利要求3所述的应用于高密度互连电路板无芯板的制作方法,其特征在于,步骤S3中,具体方法包括采用绝缘介质进行压合,再通过研磨的方式露出铜柱顶部。
- 根据权利要求3所述的应用于高密度互连电路板无芯板的制作方法,其特征在于,步骤S4中,使用SAP技术制作线路。
- 根据权利要求7所述的应用于高密度互连电路板无芯板的制作方法,其特征在于,步骤S4中,具体方法包括:种种子铜—压膜—曝光显影—电镀—褪膜—褪种子铜。
- 根据权利要求3所述的应用于高密度互连电路板无芯板的制作方法,其特征在于,步骤S5中,通过蚀刻的方法去除载体。
- 根据权利要求3所述的应用于高密度互连电路板无芯板的制作方法,其特征在于,步骤S6中,具体方法包括根据布线密度,选择直接蚀刻金属载体,实现底部线路;若线宽/线距任意一个小于等于50μm,先执行步骤5去除载体,再使用步骤S4中SAP技术制作线路。
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US20090308644A1 (en) * | 2006-07-04 | 2009-12-17 | Kyung-Ai Son | Method for Manufacturing PCB and PCB Manufactured using the Same |
CN103596358A (zh) * | 2013-12-04 | 2014-02-19 | 江苏长电科技股份有限公司 | Smt加法高密度封装多层线路板结构及其制作方法 |
CN103874347A (zh) * | 2014-03-28 | 2014-06-18 | 江苏长电科技股份有限公司 | 新型高密度高性能多层基板表面对称结构及制作方法 |
CN113225937A (zh) * | 2021-05-19 | 2021-08-06 | 惠州市金百泽电路科技有限公司 | 一种应用于高密度互连电路板无芯板的制作方法 |
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