WO2022237231A1 - 双绝缘体上硅器件及其制造方法 - Google Patents

双绝缘体上硅器件及其制造方法 Download PDF

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WO2022237231A1
WO2022237231A1 PCT/CN2022/073107 CN2022073107W WO2022237231A1 WO 2022237231 A1 WO2022237231 A1 WO 2022237231A1 CN 2022073107 W CN2022073107 W CN 2022073107W WO 2022237231 A1 WO2022237231 A1 WO 2022237231A1
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back gate
semiconductor layer
region
layer
substrate
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PCT/CN2022/073107
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English (en)
French (fr)
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梁志彬
张松
金炎
王德进
李小红
刘群
过夏雨
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无锡华润上华科技有限公司
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Publication of WO2022237231A1 publication Critical patent/WO2022237231A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to a silicon-on-insulator device and a method for manufacturing the silicon-on-insulator device.
  • Double Silicon On Insulator (DSOI) devices are formed by adding a silicon dioxide layer (SiO 2 ) and a single crystal silicon layer (Si) on the basis of Silicon On Insulator (SOI), which inherits the excellent anti-single-crystal silicon layer (Si) of SOI. Particle effects and other capabilities are greatly improved compared with bulk silicon technology and SOI technology in terms of back gate effect, total radiation dose effect and electrode crosstalk effect.
  • the traditional DSOI device can only apply a bias voltage through the substrate, and the effect of modulating the device by applying a bias voltage is limited.
  • a double silicon-on-insulator device comprising: a substrate; a second buried insulating layer disposed on the substrate; a second semiconductor layer disposed on the second buried insulating layer; a first buried insulating layer disposed on the second semiconductor layer; a first semiconductor layer disposed on the first buried insulating layer, the first semiconductor layer including an active region; and a gate disposed on the first semiconductor layer;
  • the dual silicon-on-insulator device is formed with a first back gate recess region recessed to the second semiconductor layer, and a second back gate recess region recessed to the substrate; in the first back gate recess region, The second semiconductor layer is extracted through the top as a first back gate terminal; in the second back gate recess region, the substrate is extracted through the top as a second back gate terminal.
  • a method for manufacturing a silicon-on-insulator device comprising: obtaining a substrate, the substrate including a substrate, a second buried insulating layer, a second semiconductor layer, a first buried insulating layer, and a first semiconductor layer stacked in sequence; a pattern Forming the first semiconductor layer to form an active region; forming a gate on the active region; patterning the upper structure of the second semiconductor layer to form a first back gate recessed region, the first back gate recessed Exposing a part of the second semiconductor layer at the bottom of the region; patterning the upper structure of the substrate to form a second back gate recess region, the bottom of the second back gate recess region exposing part of the substrate; and The top of the second semiconductor layer at the position of the first back gate recessed region is drawn out as a first back gate end, and the top of the substrate at the position of the second back gate recessed area is drawn out as a second back gate end.
  • Fig. 1 is a schematic cross-sectional structure diagram of a double silicon-on-insulator device in an embodiment
  • Fig. 2 is a flowchart of a method for manufacturing a double silicon-on-insulator device in an embodiment
  • 3a-3d are schematic cross-sectional views of a double silicon-on-insulator device during fabrication by the fabrication method shown in FIG. 2 according to an embodiment.
  • Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
  • P+ type simply represents P-type with heavy doping concentration
  • P-type represents medium P-type with doping concentration
  • P-type represents P-type with light doping concentration
  • N+ type represents N-type with heavy doping concentration
  • N-type represents N-type with medium doping concentration
  • N-type represents light-doped concentration Type N.
  • Fig. 1 is a schematic cross-sectional structure diagram of a double silicon-on-insulator device in an embodiment.
  • the dual silicon-on-insulator device includes, from bottom to top, a substrate 110 , a second buried insulating layer 124 , a second semiconductor layer 134 , a first buried insulating layer 122 , a first semiconductor layer 132 and a gate.
  • the second buried insulating layer 124 is disposed on the substrate 110 .
  • the second semiconductor layer 134 is disposed on the second buried insulating layer 124 .
  • the first buried insulating layer 122 is disposed on the second semiconductor layer 134 .
  • the first semiconductor layer 132 is disposed on the first buried insulating layer 122 .
  • the active region (not shown in FIG. 1 ) is disposed in the first semiconductor layer 132 .
  • the gate is disposed on the first semiconductor layer 132 .
  • the above dual SOI device is formed with a first back gate recessed region 181 recessed to the second semiconductor layer 134 , and a second back gate recessed region 183 recessed to the substrate 110 .
  • the first back gate recessed region 181 the second semiconductor layer 134 is drawn out through the top as a first back gate terminal.
  • the substrate 110 is drawn out through the top as a second back gate terminal.
  • the above-mentioned double silicon-on-insulator device has two back gate terminals, the first back gate terminal and the second back gate terminal. Since the second back gate recessed region 183 is recessed to the substrate 110, the second semiconductor layer 134 is in the second The back gate recessed region 183 is truncated to form an independent area, so the back gate voltage of the device on the corresponding independent area can be individually adjusted by applying a voltage to the first back gate terminal, and/or can be adjusted by applying a voltage to the second back gate terminal.
  • the back gate voltage of multiple devices is adjusted (since multiple devices share the substrate 110). Therefore, the design flexibility of the device is stronger, and different back bias voltages can be applied according to design requirements, so as to achieve the purpose of optimizing the device.
  • the gate comprises a polysilicon gate 142 .
  • a gate dielectric layer 144 is further provided between the polysilicon gate 142 and the first semiconductor layer 132 .
  • the material of the gate dielectric layer 144 may be silicon dioxide.
  • a sidewall structure 146 is also provided on the side of the gate.
  • the dual silicon-on-insulator device includes a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the active region in the first semiconductor layer 132 includes a source region and a drain region, and the gate, Both the source region and the drain region are constituent structures of the MOSFET.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the substrate 110 , the first semiconductor layer 132 and the second semiconductor layer 134 are all silicon layers.
  • Both the first buried insulating layer 122 and the second buried insulating layer 124 are buried oxide layers, and their material may be silicon dioxide.
  • the dual SOI device further includes a shallow trench isolation structure 150 .
  • Shallow trench isolation structures 150 are formed around the second back gate recess region 183 .
  • the second semiconductor layer 134 is cut off to form an independent region, a part of the shallow trench isolation structure 150 is formed between one side of the independent region and the second back gate recess region 183, and the other side of the independent region is also provided with a shallow trench isolation structure 150.
  • Trench isolation structure 150 (thus truncating the other side of the isolated area).
  • the dual SOI device further includes an interlayer dielectric (ILD) 160 on the first semiconductor layer 132 and on the gate. Both the first back gate recessed region 181 and the second back gate recessed region 183 are filled with the interlayer dielectric 160 .
  • ILD interlayer dielectric
  • the top of the second semiconductor layer 134 is drawn out through the first back gate contact hole 171 as the first back gate end, and the top of the substrate 110 is drawn out through the second back gate contact hole 173 as the second back gate terminal. back gate terminal.
  • the source region, the drain region and the gate are also drawn out through the source contact hole 175 , the drain contact hole 177 and the gate contact hole 179 respectively.
  • Each contact hole is filled with conductive material, which may be metal and/or alloy. Further, a metal silicide 152 is formed at the position where the bottom of each contact hole is in contact with the underlying structure.
  • the thickness of the second buried insulating layer 124 is The thickness of the second semiconductor layer 134 is The thickness of the first buried insulating layer 122 is The thickness of the first semiconductor layer 132 is The thickness of the polysilicon gate 142 is
  • Fig. 2 is a flowchart of a method for manufacturing a silicon-on-insulator device in an embodiment, including the following steps:
  • the base includes a substrate 110 , a second buried insulating layer 124 , a second semiconductor layer 134 , a first buried insulating layer 122 and a first semiconductor layer 132 stacked in sequence.
  • Part of the first semiconductor layer 132 can be removed by photolithography and etching (the removed position can be used to form a shallow trench isolation structure in a subsequent process).
  • step S220 includes: forming a pad oxide layer 212 on the first semiconductor layer 132 .
  • a hard mask layer 214 is then formed on the pad oxide layer 212 .
  • a photoresist pattern 222 is formed by photolithography on the hard mask layer 214, and then the photoresist pattern 222 is used as an etching mask layer to etch the hard mask layer 214, the pad oxide layer 212 and the first semiconductor layer 132. , forming the active region.
  • the hard mask layer 214 is a silicon nitride layer.
  • a step of patterning the first buried insulating layer 122 and the second semiconductor layer 134 is also included before step S230 . Specifically, photolithography and etching of the first insulating buried layer 122 and the second semiconductor layer 134 can be performed, so that the second semiconductor layer 134 forms a plurality of independent regions that are isolated from each other, and each independent region is set in a subsequent process. a first back gate terminal.
  • the shallow trench isolation structure 150 may also be formed. Specifically, the shallow trench isolation structure 150 is formed in a region outside the active region, referring to FIG. 3c.
  • step S230 includes forming a gate dielectric layer 144 on the active region, and forming a polysilicon gate 142 on the gate dielectric layer 144 .
  • the gate dielectric layer 144 can be formed by thermal oxidation or deposition process.
  • the polysilicon gate 142 can be formed by depositing polysilicon on the gate dielectric layer 144 .
  • the polysilicon gate 142 and the gate dielectric layer 144 may be etched after the photoresist 224 is formed by photolithography and used as an etching mask to etch the polysilicon gate 142 and the gate dielectric layer 144 .
  • the hard mask layer 214 and the pad oxide layer 212 are removed.
  • a step of forming a spacer structure 146 on the side of the gate is further included.
  • a source region and a drain region may be formed in the active region by an ion implantation process.
  • the dual silicon-on-insulator device includes a MOSFET, and the gate, the source region and the drain region are all constituent structures of the MOSFET.
  • the upper structure of the second semiconductor layer 134 is patterned to form a first back gate recessed region 181 , and the bottom of the first back gate recessed region 181 exposes the second semiconductor layer 134 at a corresponding position.
  • the first back gate recess region 181 can be formed by photolithography and etching the shallow trench isolation structure 150 and the first buried insulating layer 122 , as shown in FIG. 3 d .
  • the upper structure of the substrate 110 is patterned to form a second back gate recessed region 183 , and the bottom of the second back gate recessed region 183 exposes the substrate 100 at a corresponding position.
  • the second back gate recessed region 183 can be formed by photolithography and etching the shallow trench isolation structure 150 and the second buried insulating layer 124 . Since part of the first buried insulating layer 122 and the second semiconductor layer 134 have been removed in the step of patterning the first buried insulating layer 122 and the second semiconductor layer 134, the etching in step S250 is to etch in the removed area. After the shallow trench isolation structure 150 is penetrated, the second insulating buried layer 124 is continuously etched downward.
  • the top of the second semiconductor layer 134 at the position of the first back gate recessed region 181 is taken out as the first back gate terminal, and the top of the substrate 110 at the position of the second back gate recessed region 183 is taken out as the second back gate terminal.
  • the second semiconductor layer 134 is led out by forming the first back gate contact hole 171 above the second semiconductor layer 134 at the position of the first back gate recess region 181; the first back gate contact The hole 171 is filled with a conductive material.
  • the substrate 110 is led out by forming a second back gate contact hole 173 above the substrate 110 at the position of the second back gate recess region 183 ; the second back gate contact hole 173 is filled with conductive material. Refer to FIG. 1 for the device structure after step S260 is completed.
  • the step of leading out the first back gate terminal and the second back gate terminal includes: aligning the top of the second semiconductor layer 134 at the position of the first back gate recessed region 181 and the position of the second back gate recessed region 183 Metallization treatment is performed on the top of the substrate 110 to form a metal silicide 152 .
  • An interlayer dielectric 160 is then deposited on the front side of the device.
  • the interlayer dielectric 160 is etched to form a first back gate contact hole 171 and a second back gate contact hole 173 .
  • conductive material is filled in the first back gate contact hole 171 and the second back gate contact hole 173 .
  • the double silicon-on-insulator device formed by the above manufacturing method has two back gate terminals, the first back gate terminal and the second back gate terminal. Since the second back gate recessed region is recessed to the substrate, the second semiconductor layer The two back gate recessed regions are truncated to form an independent area, so the back gate voltage of the device on the corresponding independent area can be individually adjusted by applying a voltage to the first back gate terminal, and/or can be adjusted by applying a voltage to the second back gate terminal Regulates the backgate voltage of multiple devices. Therefore, the design flexibility of the device is stronger, and different back bias voltages can be applied according to design requirements, so as to achieve the purpose of optimizing the device.
  • steps in the flow chart of the present application are displayed in sequence according to the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the flow chart of the present application may include multiple steps or stages. These steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution of these steps or stages The sequence is not necessarily performed sequentially, but may be performed alternately or alternately with other steps or at least a part of steps or stages in other steps.

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Abstract

一种双绝缘体上硅器件及其制造方法，所述双绝缘体上硅器件包括：衬底(110)；第二绝缘埋层(124)，设于所述衬底(110)上；第二半导体层(134)，设于所述第二绝缘埋层(124)上；第一绝缘埋层(122)，设于所述第二半导体层(134)上；第一半导体层(132)，设于所述第一绝缘埋层(122)上，所述第一半导体层(132)包括有源区；栅极，设于所述第一半导体层(134)上；所述双绝缘体上硅器件形成有凹陷至所述第二半导体层(134)的第一背栅凹陷区(181)，和凹陷至所述衬底(110)的第二背栅凹陷区(183)；在所述第一背栅凹陷区(181)，所述第二半导体层(134)通过顶部引出作为第一背栅端；在所述第二背栅凹陷区(183)，所述衬底(110)通过顶部引出作为第二背栅端。

Description

双绝缘体上硅器件及其制造方法
相关申请的交叉引用
本申请要求于2021年5月10日提交中国专利局、申请号为202110504675X、发明名称为“双绝缘体上硅器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体制造领域，特别是涉及一种双绝缘体上硅器件，还涉及一种双绝缘体上硅器件的制造方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
双绝缘体上硅(Double Silicon On Insulator，DSOI)器件是在Silicon On Insulator(SOI)基础上增加二氧化硅层(SiO 2)和单晶硅层(Si)形成，其继承了SOI优秀的抗单粒子效应等能力，在背栅效应、辐射总剂量效应以及电极串扰效应等方面要比体硅工艺和SOI工艺都有较大的改进。
传统的DSOI器件只能通过衬底加偏置电压，通过施加偏置电压来调制器件的作用有限。
发明内容
基于此，有必要提供一种偏置电压的调节更为灵活的双绝缘体上硅器件及其制造方法。
一种双绝缘体上硅器件，包括：衬底；第二绝缘埋层，设于所述衬底上；第二半导体层，设于所述第二绝缘埋层上；第一绝缘埋层，设于所述第二半导体层上；第一半导体层，设于所述第一绝缘埋层上，所述第一半导体层包 括有源区；以及栅极，设于所述第一半导体层上；所述双绝缘体上硅器件形成有凹陷至所述第二半导体层的第一背栅凹陷区，和凹陷至所述衬底的第二背栅凹陷区；在所述第一背栅凹陷区，所述第二半导体层通过顶部引出作为第一背栅端；在所述第二背栅凹陷区，所述衬底通过顶部引出作为第二背栅端。
一种双绝缘体上硅器件的制造方法，包括：获取基底，所述基底包括依次叠设的衬底、第二绝缘埋层、第二半导体层、第一绝缘埋层、第一半导体层；图案化所述第一半导体层形成有源区；在所述有源区上形成栅极；图案化所述第二半导体层的上方结构，形成第一背栅凹陷区，所述第一背栅凹陷区的底部露出部分所述第二半导体层；；图案化所述衬底的上方结构，形成第二背栅凹陷区，所述第二背栅凹陷区的底部露出部分所述衬底；以及将所述第一背栅凹陷区位置处的第二半导体层顶部引出作为第一背栅端，并将所述第二背栅凹陷区位置处的衬底顶部引出作为第二背栅端。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中双绝缘体上硅器件的剖面结构示意图；
图2是一实施例中双绝缘体上硅器件的制造方法的流程图；
图3a-3d是一实施例采用图2所示的制造方法制造的过程中双绝缘体上硅器件的剖面示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中双绝缘体上硅器件的剖面结构示意图。双绝缘体上硅器件从下到上包括衬底110、第二绝缘埋层124、第二半导体层134、第一绝缘埋层122、第一半导体层132及栅极。第二绝缘埋层124设于衬底110上。第二半导体层134设于第二绝缘埋层124上。第一绝缘埋层122设于第二半导体层134上。第一半导体层132设于第一绝缘埋层122上。有源区(图1中未标示)设于第一半导体层132中。栅极设于第一半导体层132上。
上述双绝缘体上硅器件形成有下凹至第二半导体层134的第一背栅凹陷 区181，和下凹至衬底110的第二背栅凹陷区183。在第一背栅凹陷区181，第二半导体层134通过顶部引出作为第一背栅端。在第二背栅凹陷区183，衬底110通过顶部引出作为第二背栅端。
上述双绝缘体上硅器件，设置了第一背栅端和第二背栅端两个背栅端，由于第二背栅凹陷区183下凹至衬底110，因此第二半导体层134在第二背栅凹陷区183被截断形成独立区域，因此可以通过对第一背栅端施加电压来单独调节对应的独立区域上的器件的背栅电压，和/或通过对第二背栅端施加电压来调节多个器件的背栅电压(因为多个器件共用衬底110)。因此器件的设计灵活性更强，可以根据设计需要施加不同的背偏电压，以达到优化器件的目的。
在图1所示的实施例中，栅极包括多晶硅栅142。多晶硅栅142和第一半导体层132之间还设有栅介质层144。栅介质层144的材质可以是二氧化硅。栅极的侧面还设有侧墙结构146。
在本申请的一个实施例中，双绝缘体上硅器件包括金属氧化物半导体场效应晶体管(MOSFET)，第一半导体层132中的有源区包括源极区和漏极区，所述栅极、源极区和漏极区均为该MOSFET的组成结构。
在本申请的一个实施例中，衬底110、第一半导体层132及第二半导体层134均为硅层。第一绝缘埋层122和第二绝缘埋层124均为埋氧层，其材质可以为二氧化硅。
在图1所示的实施例中，双绝缘体上硅器件还包括浅槽隔离结构150。第二背栅凹陷区183的四周形成有浅槽隔离结构150。如前述，第二半导体层134被截断形成独立区域，一部分的浅槽隔离结构150形成于该独立区域的一侧与第二背栅凹陷区183之间，该独立区域的另一侧也设置浅槽隔离结构150(从而将独立区域的另一侧截断)。
在图1所示的实施例中，双绝缘体上硅器件还包括第一半导体层132上及栅极上的层间介质(ILD)160。第一背栅凹陷区181内和第二背栅凹陷区183内均填充有层间介质160。
在图1所示的实施例中，第二半导体层134的顶部通过第一背栅接触孔171引出作为第一背栅端，衬底110的顶部通过第二背栅接触孔173引出作为第二背栅端。源极区、漏极区和栅极也分别通过源极接触孔175、漏极接触孔177及栅极接触孔179引出。各接触孔内填充有导电材料，导电材料可以是金属和/或合金。进一步地，各接触孔在底部与下方结构接触的位置形成金属硅化物152。
在本申请的一个实施例中，第二绝缘埋层124的厚度为
Figure PCTCN2022073107-appb-000001
第二半导体层134的厚度为
Figure PCTCN2022073107-appb-000002
第一绝缘埋层122的厚度为
Figure PCTCN2022073107-appb-000003
第一半导体层132的厚度为
Figure PCTCN2022073107-appb-000004
多晶硅栅142的厚度为
Figure PCTCN2022073107-appb-000005
本申请相应提供一种双绝缘体上硅器件的制造方法，可以用于制造以上相应实施例所述的双绝缘体上硅器件。图2是一实施例中双绝缘体上硅器件的制造方法的流程图，包括下列步骤：
S210，获取基底。
在图3a所示的实施例中，基底包括依次叠设的衬底110、第二绝缘埋层124、第二半导体层134、第一绝缘埋层122及第一半导体层132。
S220，图案化第一半导体层形成有源区。
可以通过光刻和刻蚀工艺去除部分第一半导体层132(去除的位置可以在后续工艺中形成浅沟槽隔离结构)。
在本申请的一个实施例中，步骤S220包括：在第一半导体层132上形成衬垫氧化层212。然后在衬垫氧化层212上形成硬掩膜层214。接着在硬掩膜层214上光刻形成光刻胶图案222，再以光刻胶图案222作为刻蚀掩膜层，刻蚀硬掩膜层214、衬垫氧化层212及第一半导体层132，形成有源区。步骤S220完成后器件的剖面参照图3b。在本申请的一个实施例中，硬掩膜层214为氮化硅层。
S230，在有源区上形成栅极。
在本申请的一个实施例中，步骤S230之前还包括图案化第一绝缘埋层122和第二半导体层134的步骤。具体可以通过光刻及刻蚀第一绝缘埋层122 和第二半导体层134，使得第二半导体层134形成多个相互之间被隔离开的独立区域，每个独立区域在后续工艺中配套设置一个第一背栅端。
在本申请的一个实施例中，在图案化第一绝缘埋层122和第二半导体层134之后，还可以形成浅槽隔离结构150。具体地，浅槽隔离结构150形成在有源区之外的区域，参照图3c。
在本申请的一个实施例中，步骤S230包括在有源区上形成栅介质层144，以及在栅介质层144上形成多晶硅栅142。栅介质层144可以通过热氧化或者沉积工艺形成。多晶硅栅142可以通过在栅介质层144上沉积多晶硅形成。如图3c所示，可以光刻形成光刻胶224后作为刻蚀掩膜刻蚀多晶硅栅142和栅介质层144，对多晶硅栅142和栅介质层144进行刻蚀。
在形成栅极之前先要将硬掩膜层214和衬垫氧化层212去除。
在本申请的一个实施例中，刻蚀多晶硅栅142和栅介质层144之后还包括在栅极的侧面形成侧墙结构146的步骤。
在本申请的一个实施例中，在形成侧墙结构146之后，可以通过离子注入工艺在有源区中形成源极区和漏极区。在本申请的一个实施例中，双绝缘体上硅器件包括MOSFET，所述栅极、源极区和漏极区均为该MOSFET的组成结构。
S240，形成第一背栅凹陷区。
图案化第二半导体层134的上方结构，形成第一背栅凹陷区181，第一背栅凹陷区181的底部将相应位置的第二半导体层134露出，。具体可以通过光刻并刻蚀浅槽隔离结构150和第一绝缘埋层122，形成第一背栅凹陷区181，参照图3d。
S250，形成第二背栅凹陷区。
图案化衬底110的上方结构，形成第二背栅凹陷区183，第二背栅凹陷区183的底部将相应位置的衬底100露出。具体可以通过光刻并刻蚀浅槽隔离结构150和第二绝缘埋层124，形成第二背栅凹陷区183。由于在前述图案化第一绝缘埋层122和第二半导体层134的步骤中已将部分区域的第一绝缘 埋层122和第二半导体层134去除，步骤S250的刻蚀是在该去除区域刻穿浅槽隔离结构150后继续向下刻蚀第二绝缘埋层124。
S260，引出第一背栅端和第二背栅端。
将第一背栅凹陷区181位置处的第二半导体层134的顶部引出作为第一背栅端，并将第二背栅凹陷区183位置处的衬底110顶部引出作为第二背栅端。
在本申请的一个实施例中，通过在第一背栅凹陷区181位置处的第二半导体层134上方形成第一背栅接触孔171，从而将第二半导体层134引出；第一背栅接触孔171中填充导电材料。通过在第二背栅凹陷区183位置处的衬底110上方形成第二背栅接触孔173，从而将衬底110引出；第二背栅接触孔173中填充导电材料。步骤S260完成后的器件结构可以参考图1。
在本申请的一个实施例中，引出第一背栅端和第二背栅端的步骤包括：对第一背栅凹陷区181位置处的第二半导体层134顶部和第二背栅凹陷区183位置处的衬底110顶部进行金属化处理，形成金属硅化物152。然后在器件正面淀积形成层间介质160。接着刻蚀层间介质160形成第一背栅接触孔171和第二背栅接触孔173。最后在第一背栅接触孔171和第二背栅接触孔173内填充导电材料。
上述制造方法形成的双绝缘体上硅器件，设置了第一背栅端和第二背栅端两个背栅端，由于第二背栅凹陷区下凹至衬底，因此第二半导体层在第二背栅凹陷区被截断形成独立区域，因此可以通过对第一背栅端施加电压来单独调节对应的独立区域上的器件的背栅电压，和/或通过对第二背栅端施加电压来调节多个器件的背栅电压。因此器件的设计灵活性更强，可以根据设计需要施加不同的背偏电压，以达到优化器件的目的。
应该理解的是，虽然本申请的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且本申请的流程图中的至少一部分步骤可以包括多个步骤 或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种双绝缘体上硅器件，包括：
    衬底；
    第二绝缘埋层，设于所述衬底上；
    第二半导体层，设于所述第二绝缘埋层上；
    第一绝缘埋层，设于所述第二半导体层上；
    第一半导体层，设于所述第一绝缘埋层上，所述第一半导体层包括有源区；以及
    栅极，设于所述第一半导体层上；
    所述双绝缘体上硅器件形成有凹陷至所述第二半导体层的第一背栅凹陷区，和凹陷至所述衬底的第二背栅凹陷区；在所述第一背栅凹陷区，所述第二半导体层通过顶部引出作为第一背栅端；在所述第二背栅凹陷区，所述衬底通过顶部引出作为第二背栅端。
  2. 根据权利要求1所述的双绝缘体上硅器件，其特征在于，还包括浅槽隔离结构，所述第二背栅凹陷区的四周形成有所述浅槽隔离结构。
  3. 根据权利要求1所述的双绝缘体上硅器件，其特征在于，还包括层间介质，所述第一背栅凹陷区内和第二背栅凹陷区内填充有所述层间介质。
  4. 根据权利要求1所述的双绝缘体上硅器件，其特征在于，所述有源区包括源极区和漏极区，所述双绝缘体上硅器件包括金属氧化物半导体场效应晶体管，所述栅极、源极区及漏极区为所述金属氧化物半导体场效应晶体管的组成结构。
  5. 根据权利要求1所述的双绝缘体上硅器件，其特征在于，所述第二半导体层和衬底通过各自的接触孔引出依次分别作为第一背栅端和第二背栅端。
  6. 根据权利要求1所述的双绝缘体上硅器件，其特征在于，所述所述第一绝缘埋层和第二绝缘埋层是埋氧层。
  7. 一种双绝缘体上硅器件的制造方法，包括：
    获取基底，所述基底包括依次叠设的衬底、第二绝缘埋层、第二半导体层、第一绝缘埋层、第一半导体层；
    图案化所述第一半导体层形成有源区；
    在所述有源区上形成栅极；
    图案化所述第二半导体层的上方结构，形成第一背栅凹陷区，所述第一背栅凹陷区的底部露出部分所述第二半导体层；
    图案化所述衬底的上方结构，形成第二背栅凹陷区，所述第二背栅凹陷区的底部露出部分所述衬底；以及
    将所述第一背栅凹陷区位置处的第二半导体层顶部引出作为第一背栅端，并将所述第二背栅凹陷区位置处的衬底顶部引出作为第二背栅端。
  8. 根据权利要求7所述的方法，其特征在于，所述在所述有源区上形成栅极的步骤包括：
    在所述有源区上形成栅介质层；以及
    在所述栅介质层上形成多晶硅栅；
    所述去除部分区域的所述第二半导体层的上方结构的步骤之前，还包括在所述栅极的侧面形成侧墙结构的步骤。
  9. 根据权利要求7所述的方法，其特征在于，所述图案化所述第一半导体层形成有源区的步骤之后、所述在所述有源区上形成栅极的步骤之前，还包括形成浅槽隔离结构的步骤。
  10. 根据权利要求9所述的方法，其特征在于，所述图案化所述第一半导体层形成有源区的步骤之后、所述形成浅槽隔离结构的步骤之前，还包括图案化所述第一绝缘埋层和第二半导体层的步骤。
  11. 根据权利要求10所述的方法，其特征在于，所述图案化所述第二半导体层的上方结构的步骤，包括光刻并刻蚀所述第一背栅凹陷区的浅槽隔离结构和第一背栅凹陷区的第一绝缘埋层；所述图案化所述衬底的上方结构的步骤，包括光刻并刻蚀所述第二背栅凹陷区的浅槽隔离结构和第二绝缘埋层； 所述图案化所述第一绝缘埋层和第二半导体层的步骤包括光刻并刻蚀所述第一绝缘埋层和第二半导体层，且刻蚀去除的区域在所述衬底上的正投影为第一区域，所述刻蚀所述第二背栅凹陷区的浅槽隔离结构和第二绝缘埋层的步骤刻蚀去除的区域在所述衬底上的正投影位于所述第一区域内。
  12. 根据权利要求7所述的方法，其特征在于，所述将所述第一背栅凹陷区位置处的第二半导体层顶部引出作为第一背栅端的步骤包括：在所述第一背栅凹陷区位置处的第二半导体层上方形成第一背栅接触孔，从而将所述第二半导体层引出；
    所述将所述第二背栅凹陷区位置处的衬底顶部引出作为第二背栅端的步骤包括：在所述第二背栅凹陷区位置处的衬底上方形成第二背栅接触孔，从而将所述衬底引出。
  13. 根据权利要求7所述的方法，其特征在于，所述将所述第一背栅凹陷区位置处的第二半导体层顶部引出作为第一背栅端的步骤包括：
    对所述第一背栅凹陷区位置处的第二半导体层顶部进行金属化处理，形成金属硅化物；以及
    通过刻蚀形成所述第一背栅接触孔，并在所述第一背栅接触孔内填充导电材料；
    所述将所述第二背栅凹陷区位置处的衬底顶部引出作为第二背栅端的步骤包括：
    对所述第二背栅凹陷区位置处的衬底顶部进行金属化处理，形成金属硅化物；以及
    通过刻蚀形成所述第二背栅接触孔，并在所述第二背栅接触孔内填充导电材料。
  14. 根据权利要求7所述的方法，其特征在于，所述图案化所述第一半导体层形成有源区的步骤包括：
    在所述第一半导体层上形成衬垫氧化层；
    在所述衬垫氧化层上形成硬掩膜层；以及
    在所述硬掩膜层上光刻，并刻蚀所述硬掩膜层、衬垫氧化层及第一半导体层，形成所述有源区。
  15. 根据权利要求14所述的方法，其特征在于，所述硬掩膜层是氮化硅层。
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