TWI685882B - 具有多閘極結構之ｌｄｍｏｓ ｆｉｎｆｅｔ結構 - Google Patents

具有多閘極結構之ｌｄｍｏｓ ｆｉｎｆｅｔ結構 Download PDF

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TWI685882B
TWI685882B TW107117235A TW107117235A TWI685882B TW I685882 B TWI685882 B TW I685882B TW 107117235 A TW107117235 A TW 107117235A TW 107117235 A TW107117235 A TW 107117235A TW I685882 B TWI685882 B TW I685882B
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gate structure
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傑羅米 希瓦提
杰高爾 辛格
輝 臧
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明提供用於橫向擴散金屬氧化物半導體(laterally-diffused metal-oxide-semiconductor；LDMOS)裝置的場效電晶體結構以及形成LDMOS裝置的方法。在基板上形成第一及第二鰭片。具有第一導電類型的第一阱(well)部分設於該基板中且部分設於該第一鰭片中。具有第二導電類型的第二阱部分設於該基板中、部分設於該第一鰭片中、且部分設於該第二鰭片中。在該第一鰭片中的該第一阱內及該第二鰭片中的該第二阱內分別形成具有該第二導電類型的第一及第二源/汲區。形成與該第一鰭片的相應部分重疊的相互隔開的閘極結構。在該第一與第二閘極結構之間的該第一鰭片中的該第二阱內設置具有該第一導電類型的摻雜區。

Description

具有多閘極結構之LDMOS FINFET結構
本發明為有關半導體裝置製造及積體電路，尤其是用於橫向擴散金屬氧化物半導體(laterally-diffused metal-oxide-semiconductor；LDMOS)裝置的場效電晶體結構以及形成LDMOS裝置的方法。
用於場效電晶體的裝置結構通常包括本體區，定義於該本體區中的源極及汲極，以及經配置以切換在該本體中在操作期間所形成的通道中的載子流(carrier flow)的閘極電極。當向該閘極電極施加超過指定閾值電壓的控制電壓時，在該源極與汲極之間的該通道中的反轉層(inversion layer)或耗盡層(depletion layer)中發生載子流，從而產生裝置輸出電流。
鰭式場效電晶體(fin-type field-effect transistor；FinFET)是非平面裝置結構，與平面場效電晶體相比，它可被更密集地封裝於積體電路中。FinFET可包括由半導體材料實心單體組成的鰭片，形成於該本體的部分中的重摻雜源/汲區，以及環繞在該源/汲區之間的該鰭 片本體中所設置的通道的閘極電極。與平面電晶體相比，在該閘極電極與鰭片本體之間的該佈置改進對通道的控制並降低該FinFET處於“關閉”(off)狀態時的漏電流。相應地，與平面電晶體相比，這能夠使用較低的閾值電壓，從而改進性能以及降低功耗。
例如，用於微波/RF功率放大器的高壓積體電路通常需要能夠忍受較高電壓的專用電路技術。與邏輯場效電晶體相比，橫向擴散金屬氧化物半導體(LDMOS)裝置係設計成處理較高的電壓。
需要用於LDMOS裝置的改進場效電晶體結構以及形成LDMOS裝置的方法。
在本發明的一個實施例中，提供一種場效電晶體的結構。該結構包括位於基板上的第一及第二鰭片，部分設於該基板中且部分設於該第二鰭片中的第一阱，以及部分設於該基板中、部分設於該第一鰭片中、且部分設於該第二鰭片中的第二阱。該第一阱具有第一導電類型，且該第二阱具有第二導電類型。該結構還包括具有該第二導電類型的第一源/汲區，位於該第一鰭片中的該第一阱內；以及具有該第二導電類型的第二源/汲區，位於該第二鰭片中的該第二阱內。第一閘極結構經設置以與該第一鰭片的第一部分重疊，且第二閘極結構經設置以與該第一鰭片的第二部分重疊。該第二閘極結構沿該第一鰭片與該第一閘極結構隔開。摻雜區設於該第一閘極結構與該第二閘極結 構之間的該第一鰭片中的該第二阱內，且具有該第一導電類型。
在本發明的一個實施例中，提供一種製造場效電晶體的方法。該方法包括在基板上形成第一及第二鰭片，形成部分設於該基板中且部分設於該第一鰭片中的第一阱，以及形成部分設於該基板中、部分設於該第一鰭片中，且部分設於該第二鰭片中的第二阱。該第一阱具有第一導電類型，且該第二阱具有第二導電類型。在該第一鰭片中的該第一阱內形成具有該第二導電類型的第一源/汲區，以及在該第二鰭片中的該第二阱內形成具有該第二導電類型的第二源/汲區。形成與該第一鰭片的第一部分重疊的第一閘極結構，以及形成與該第一鰭片的第二部分重疊的第二閘極結構。該第二閘極結構沿該第一鰭片與該第一閘極結構隔開。摻雜區形成於該第一閘極結構與該第二閘極結構之間的該第一鰭片中的該第二阱內，並具有該第一導電類型。
10、11‧‧‧鰭片
12‧‧‧基板
13‧‧‧頂部表面
14‧‧‧深溝槽隔離區
16、18‧‧‧阱
19‧‧‧界面
20‧‧‧槽區
21‧‧‧摻雜區
22‧‧‧p-n結
23‧‧‧摻雜區
24、25、26‧‧‧閘極結構
28、30‧‧‧源/汲區
32‧‧‧摻雜區
34‧‧‧場效電晶體
包含於並構成本說明書的一部分的附圖說明本發明的各種實施例，並與上面所作的有關本發明的概括說明以及下面所作的有關實施例的詳細說明一起用以解釋本發明的實施例。
第1圖至第3圖顯示依據本發明的實施例處於制程方法的連續製造階段的裝置結構的剖視圖。
第4圖顯示依據本發明的替代實施例的裝置 結構的剖視圖。
請參照第1圖並依據本發明的實施例，鰭片10及鰭片11分別相對於基板12(例如塊體單晶矽基板(bulk single crystal silicon substrate))而沿垂直方向凸出。鰭片10、11是由例如矽的半導體材料組成的三維體。從鰭片10、11向基板12的頂部表面13的過渡是由第1圖中的虛線圖示。因此，鰭片10、11在基板的頂部表面13與基板12無縫鄰接，且具有各自高度，該些高度(相對於基板12的頂部表面13沿垂直方向測量)可相等。
可利用側壁圖像轉移(sidewall imaging transfer；SIT)制程或自對準雙重圖案化(self-aglined double patterning；SADP)通過圖案化基板12或生長於基板12上的外延層而形成鰭片10、11，其中，在基板12中蝕刻淺溝槽並用介電材料(例如通過化學氣相沉積(chemical vapor deposition；CVD)所沉積的矽的氧化物(例如，SiO2))填充，以及通過化學機械拋光(chemical mechanical polishing；CMP)平坦化以形成淺溝槽隔離區(未顯示)。在形成鰭片10、11及淺溝槽隔離區以後，形成圍繞鰭片10、11並設於鰭片10、11之間的深溝槽隔離區14。為形成深溝槽隔離區14，可蝕刻穿過鰭片10、11及淺溝槽隔離至基板12中的深溝槽並用介電材料(例如通過CVD沉積並用CMP平坦化的矽的氧化物(例如，SiO2))填充該深溝槽。回蝕刻(etch back)該淺溝槽隔離區的該介電材 料及深溝槽隔離區14的該介電材料，以暴露設於該介電材料的相應凹入頂部表面之上的鰭片10、11的相應部分。鰭片10、11的其它部分嵌埋於該淺溝槽隔離區及深溝槽隔離區14中。
在鰭片10、11及基板12中形成阱16及阱18。阱16(部分位於鰭片10中且部分位於基板12中)由具有與阱18相反的導電類型的半導體材料組成。阱18部分位於鰭片10中、部分位於鰭片11中，且部分位於基板12中。具體地說，阱18包括位於基板12及鰭片11中的摻雜區21，以及位於基板12及鰭片10中的槽(moat)區20。槽區20由具有與摻雜區21相同的導電類型的半導體材料組成，與阱18的摻雜區21相比，槽區20為較輕摻雜(也就是，具有較低摻雜物濃度)。
阱18的槽區20設於阱16與阱18的摻雜區21之間。槽區20沿著定義p-n結22的界面而與阱16鄰接並且沿著界面19而與阱18的摻雜區21鄰接。界面19與p-n結22可沿垂直方向取向。在一個實施例中，界面19直接位於深溝槽隔離區14下方。在一個實施例中，阱18的槽區20可圍繞阱18的摻雜區21，以使界面19圍繞摻雜區21的周邊延伸。
阱16可通過例如在基板12及鰭片10中引入摻雜物濃度的離子注入引入摻雜物來形成。阱18的摻雜區21可通過在基板12及鰭片11中引入具有相反導電類型的不同摻雜物濃度來形成。可使用相應圖案化注入掩膜來定 義暴露的選定區域以供該注入。在相關注入以後，且在形成用以形成阱18的摻雜區21的注入掩膜之前，剝除用以選擇暴露區域以形成阱16的注入掩膜。類似地，在執行相關注入以後，剝除用以選擇暴露區域以形成阱18的摻雜區21的注入掩膜。該些注入掩膜可包括光敏材料層，例如有機光阻，其通過旋塗制程鋪設、經歷預烘烤、暴露於通過光掩膜投射的光、曝光後烘烤，以及用化學顯影劑顯影。用以形成阱16以及形成阱18的摻雜區21的該些注入掩膜具有足夠的厚度及阻止能力來阻止鰭片10、11及基板12的選定掩蔽區接受該注入離子的劑量。
注入條件(例如，離子種類、劑量、動能)可經選擇以調節阱16的電性及物理特性(例如，電阻率及深度分佈)。類似地，注入條件可經選擇以調節阱18的摻雜區21的電性及物理特性。在一個實施例中，可用有效提供n型導電性的來自週期表的第V族的n型摻雜物(例如，磷(P)及/或砷(As))摻雜阱16的半導體材料。在一個實施例中，可用有效提供p型導電性的來自週期表的第III族的p型摻雜物(例如，硼)摻雜阱18的摻雜區21的半導體材料。
阱18的槽區20具有與阱18的摻雜區21相比較輕的摻雜物濃度。在一個實施例中，槽區20可通過向鰭片10及基板12中透過離子注入引入摻雜物濃度來形成。在一個實施例中，槽區20可為輕摻雜基板12的區段。在任一個實施例中，槽區20由用以後續形成阱16及阱18的結22相對於槽區20的位置。在形成阱18的摻雜區21時的該注入掩蔽以及深溝槽隔離區14的設置可經選擇以使槽區20圍繞阱18。
在基板12中可形成與阱18具有相同的導電類型或與阱18具有相反的導電類型的摻雜區23。摻雜區23將阱18的摻雜區21及槽區20與基板12電性隔離。
請參照第2圖，其中相同的附圖標記表示第1圖中類似的特徵且在下一製造階段，形成閘極結構24、26，它們延伸橫貫鰭片10及淺溝槽隔離的不同部分並與其重疊。閘極結構26也部分地延伸於鰭片10、11之間的深溝槽隔離區14上並與其重疊。閘極結構24、26可通過沉積不同組分材料的層堆疊並通過光刻(photolithography)及蝕刻圖案化所沉積的層堆疊而形成。閘極結構24、26可包括由導體(例如金屬、摻雜多晶矽(polysilicon))，或這些及其它導電材料的層堆疊組成的閘極電極；以及包括但不限於二氧化矽(SiO2)、高k介電材料(如氧化鉿(HfO2))，或這些及其它介電材料的層堆疊的電性絕緣體。該電性絕緣體設於該導體與鰭片10的外表面之間。在一個實施例中，閘極結構24、26可為功能閘極結構，其為用以控制場效電晶體的輸出電流(也就是，通道中的載子流)的永久閘極結構。在一個實施例中，閘極結構24、26可為犧牲閘極結構，其為後續將形成於替代金屬閘極製程中的功能閘極結構的占位結構(placeholder structure)。閘極結構24、26或替代閘極結構24、26的該功能閘極結構可通過中間或替代閘極結構24、26的該功能閘極結構可通過中間工藝以及/或者後端工藝互連結構中的線路短接在一起。
具有相同導電類型的源/汲區28、30分別在鰭片10中及鰭片11中形成作為摻雜區。源/汲區28設於鰭片10中的阱16的部分中，並由具有與阱16相反的導電類型的重摻雜半導體材料組成。源/汲區30設於鰭片11中的阱18的摻雜區21的部分中，並由在較高摻雜物濃度的具有與阱18的摻雜區21相同的導電類型的重摻雜半導體材料組成。源/汲區28、30可通過蝕刻鰭片10、11並在鰭片10、11的相應蝕刻體積中外延生長摻雜半導體材料而形成。在阱16為n型半導體材料且阱18為p型半導體材料的實施例中，構成源/汲區28、30的該半導體材料可由p型摻雜物摻雜以提供p型導電性，且可由該p型摻雜物的濃度重摻雜。
請參照第3圖，其中相同的附圖標記表示第2圖中類似的特徵且在下一製造階段，形成摻雜區32，其位於閘極結構24與閘極結構26之間的位置的鰭片10中的槽區20內。摻雜區32由具有與槽區20相反的導電類型且也具有與源/汲區28、30相反的導電類型的半導體材料組成。摻雜區32可與具有相反導電類型的槽區20直接耦接，以形成結。摻雜區32可通過蝕刻鰭片10並在鰭片10的該蝕刻體積中外延生長摻雜半導體材料形成。在槽區20為p型半導體材料的實施例中，摻雜區32的該半導體材料可由n型摻雜物(例如，磷(P)及/或砷(As))摻雜以提供n 型導電性，且可由該n型摻雜物的濃度重摻雜。摻雜區32可形成於源/汲區28、30之前或之後。
本文中所使用的重摻雜半導體材料可被視為具有高於輕摻雜半導體材料的摻雜物濃度至少一個量級的摻雜物濃度。例如，重摻雜半導體材料的代表性摻雜物濃度可大於或等於1018cm-3，而輕摻雜半導體材料的代表性摻雜物濃度可小於或等於1016cm-3。
所得的場效電晶體34包括鰭片10、11，阱16、18，閘極結構24、26，以及源/汲區28、30。阱16在裝置操作期間充當通道區。閘極結構24在裝置操作期間控制場效電晶體34的通道。部分地延伸於鰭片10、11之間的深溝槽隔離區14上並與其重疊的閘極結構26可在場效電晶體34的操作期間提供電場電鍍(electric field plating)。設於p-n結22與源/汲區30之間的槽區20及阱18的摻雜區21共同構成場效電晶體34的汲極延伸區或漂移區。
槽區20及摻雜區32代表傳統LDMOS裝置結構未發現的額外特徵。槽區20的存在具有增加場效電晶體34的擊穿電壓的效果。摻雜區32提供與槽區20的浮置結(floating junction)，其可用於在源極至汲極電壓為零伏時在鰭片10中垂直耗盡槽區20。
接著執行中間工藝(middle-of-line；MOL)制程及後端工藝(back-end-of-line；BEOL)制程，其包括形成局部互連結構的接觸及線路，以及形成通過該局部互連結構與場效電晶體34耦接的BEOL互連結構的介電層、 過孔塞以及線路。
請參照第4圖，其中相同的附圖標記表示第3圖中類似的特徵且依據本發明的替代實施例，在閘極結構24與閘極結構26之間可形成額外閘極結構25。摻雜區32沿著位於閘極結構25與閘極結構26之間的鰭片10設置。這導致在裝置操作期間，摻雜區32進一步偏離在阱16中所形成的通道區。使用不止一個閘極結構24、25會有效形成在源/汲區30提供高壓汲極的堆疊邏輯場效電晶體。
如上所述的方法用於積體電路芯片的製造中。製造者可以原始晶圓形式(例如作為具有多個未封裝芯片的單個晶圓)、作為裸芯片，或者以封裝形式分配所得的積體電路芯片。在後一種情況中，該芯片設於單芯片封裝件中(例如塑料承載件，其具有附著至母板或其它更高層次承載件的引腳)或者多芯片封裝件中(例如陶瓷承載件，其具有單面或雙面互連或嵌埋互連)。在任何情況下，可將該芯片與其它芯片、分立電路元件和/或其它信號處理裝置集成，作為中間產品或最終產品的部分。
本文中引用術語例如“垂直”、“水平”等作為示例來建立參考框架，並非限制。本文中所使用的術語“水平”係定義為與半導體基板的傳統平面平行的平面，而不論其實際的三維空間取向。術語“垂直”及“正交”是指垂直於如剛剛所定義的水平面的方向。術語“橫向”是指在該水平平面內的方向。術語例如“上方”及“下方” 用以表示元件或結構相對彼此的定位，而不是相對標高。
與另一個元件“連接”或“耦接”的特徵可與該另一個元件直接連接或耦接，或者可存在一個或多個中間元件。如果不存在中間元件，則特徵可與另一個元件“直接連接”或“直接耦接”。如存在至少一個中間元件，則特徵可與另一個元件“非直接連接”或“非直接耦接”。
對本發明的各種實施例所作的說明是出於說明目的，而非意圖詳盡無遺或限於所揭露的實施例。許多修改及變更對於本領域的普通技術人員將顯而易見，而不背離所述實施例的範圍及精神。本文中所使用的術語經選擇以最佳解釋實施例的原理、實際應用或在市場已知技術上的技術改進，或者使本領域的普通技術人員能夠理解本文中所揭露的實施例。
10‧‧‧鰭片
11‧‧‧鰭片
12‧‧‧基板
13‧‧‧頂部表面
14‧‧‧深溝槽隔離區
16‧‧‧阱
18‧‧‧阱
19‧‧‧界面
20‧‧‧槽區
21‧‧‧摻雜區
22‧‧‧p-n結
23‧‧‧摻雜區

Claims (20)

  1. 一種利用基板形成的場效電晶體的結構，該結構包括：第一鰭片及第二鰭片，位於該基板上；第一阱，部分設於該基板中且部分設於該第一鰭片中，該第一阱具有第一導電類型；第二阱，部分設於該基板中、部分設於該第一鰭片中，且部分設於該第二鰭片中，該第二阱具有第二導電類型；第一源/汲區，具有該第二導電類型，位於該第一鰭片中的該第一阱內；第二源/汲區，具有該第二導電類型，位於該第二鰭片中的該第二阱內；第一閘極結構，經設置以與該第一鰭片的第一部分重疊；第二閘極結構，經設置以與該第一鰭片的第二部分重疊，該第二閘極結構沿著該第一鰭片而與該第一閘極結構隔開；以及摻雜區，設於該第一閘極結構與該第二閘極結構之間的該第一鰭片中的該第二阱內，該摻雜區具有該第一導電類型。
  2. 如申請專利範圍第1項所述的結構，其中，該第二阱包括第一區及第二區，該第二源/汲區設於該第二區中，該第二阱的該第一區在該第一阱與該第二阱的該第二區之間部分設於該第一鰭片中且部分設於該基板中，以 及該第二阱的該第二區位於該第二鰭片中。
  3. 如申請專利範圍第2項所述的結構，其中，該第一阱與該第二阱的該第一區沿結會合，且該第二阱的該第一區將該第一阱與該第二阱的該第二區隔開。
  4. 如申請專利範圍第3項所述的結構，其中，該第一閘極結構位於該第一阱與該第二阱的該第一區之間的該結上方。
  5. 如申請專利範圍第4項所述的結構，還包括：溝槽隔離區，位於該第一鰭片與該第二鰭片之間，其中，該第二阱的該第一區與該第二阱的該第二區在該溝槽隔離區下方會合。
  6. 如申請專利範圍第2項所述的結構，其中，該第二阱的該第一區由提供該第二導電類型的摻雜物的第一濃度摻雜，該第二阱的該第二區由提供該第二導電類型的該摻雜物的第二濃度摻雜，且該第二濃度大於該第一濃度。
  7. 如申請專利範圍第2項所述的結構，其中，該摻雜區與該第二阱的該第一區耦接。
  8. 如申請專利範圍第7項所述的結構，還包括：溝槽隔離區，位於該第一鰭片與該第二鰭片之間，其中，該第二閘極結構設於該摻雜區與該溝槽隔離區之間。
  9. 如申請專利範圍第2項所述的結構，其中，該第二阱的該第一區圍繞該第二阱的該第二區。
  10. 如申請專利範圍第1項所述的結構，還包括：第三閘極結構，與該第一鰭片的第三部分重疊，該第三閘極結構沿著該第一鰭片而與該第一閘極結構隔開，且該第一閘極結構及該第三閘極結構設於該第一源/汲區與該摻雜區之間。
  11. 如申請專利範圍第1項所述的結構，其中，該摻雜區未被接觸。
  12. 如申請專利範圍第1項所述的結構，還包括：溝槽隔離區，位於該第一鰭片與該第二鰭片之間，其中，該第二閘極結構的部分與該溝槽隔離區具有重疊關係。
  13. 如申請專利範圍第1項所述的結構，其中，該第一導電類型為n型導電性，且該第二導電類型為p型導電性。
  14. 一種製造場效電晶體的方法，該方法包括：在基板上形成第一鰭片及第二鰭片；形成部分設於該基板中且部分設於該第一鰭片中的第一阱，該第一阱具有第一導電類型；形成部分設於該基板中、部分設於該第一鰭片中、且部分設於該第二鰭片中的第二阱，該第二阱具有第二導電類型；在該第一鰭片中的該第一阱內形成具有該第二導 電類型的第一源/汲區；在該第二鰭片中的該第二阱內形成具有該第二導電類型的第二源/汲區；形成與該第一鰭片的第一部分重疊的第一閘極結構；形成與該第一鰭片的第二部分重疊的第二閘極結構，該第二閘極結構沿著該第一鰭片而與該第一閘極結構隔開；以及形成設於該第一閘極結構與該第二閘極結構之間的該第一鰭片中的該第二阱內的摻雜區，該摻雜區具有該第一導電類型。
  15. 如申請專利範圍第14項所述的方法，其中，該第二阱包括第一區及第二區，該第二源/汲區設於該第二區中，該第二阱的該第一區在該第一阱與該第二阱的該第二區之間部分設於該第一鰭片中且部分設於該基板中，以及該第二阱的該第二區位於該第二鰭片中。
  16. 如申請專利範圍第15項所述的方法，其中，該第一阱與該第二阱的該第一區沿著結會合，且該第二阱的該第一區將該第一阱與該第二阱的該第二區隔開。
  17. 如申請專利範圍第15項所述的方法，其中，該摻雜區與該第二阱的該第一區直接耦接，且與該第二阱的該第二區相比，該第二阱的該第一區為較輕摻雜。
  18. 如申請專利範圍第17項所述的方法，還包括：形成設於該第一鰭片與該第二鰭片之間的溝槽隔 離區，其中，該第二閘極結構的部分與該溝槽隔離區具有重疊關係，且該第二閘極結構設於該摻雜區與該溝槽隔離區之間。
  19. 如申請專利範圍第17項所述的方法，還包括：形成與該第一鰭片的第三部分重疊的第三閘極結構，其中，該第三閘極結構沿著該第一鰭片與該第一閘極結構隔開，且該第一閘極結構及該第三閘極結構設於該第一源/汲區與該摻雜區之間。
  20. 如申請專利範圍第14項所述的方法，還包括：在該第一鰭片與該第二鰭片之間形成溝槽隔離區，其中，該第二閘極結構的部分與該溝槽隔離區具有重疊關係。
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