CN109585558A - 具有多个栅极结构的ldmos finfet结构 - Google Patents

具有多个栅极结构的ldmos finfet结构 Download PDF

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CN109585558A
CN109585558A CN201811120061.6A CN201811120061A CN109585558A CN 109585558 A CN109585558 A CN 109585558A CN 201811120061 A CN201811120061 A CN 201811120061A CN 109585558 A CN109585558 A CN 109585558A
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CN109585558B (zh
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杰罗米·希瓦提
杰高尔·辛格
臧辉
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GlobalFoundries US Inc
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Abstract

本发明涉及具有多个栅极结构的LDMOS FINFET结构，揭示用于横向扩散金属氧化物半导体(LDMOS)装置的场效应晶体管结构以及形成LDMOS装置的方法。在衬底上形成第一及第二鳍片。具有第一导电类型的第一阱部分设于该衬底中且部分设于该第一鳍片中。具有第二导电类型的第二阱部分设于该衬底中、部分设于该第一鳍片中、且部分设于该第二鳍片中。在该第一鳍片中的该第一阱内及该第二鳍片中的该第二阱内分别形成具有该第二导电类型的第一及第二源/漏区。形成与该第一鳍片的相应部分重叠的相互隔开的栅极结构。在该第一与第二栅极结构之间的该第一鳍片中的该第二阱内设置具有该第一导电类型的掺杂区。

Description

具有多个栅极结构的LDMOS FINFET结构
技术领域
本发明涉及半导体装置制造及集成电路，尤其涉及用于横向扩散金属氧化物半导体(laterally-diffused metal-oxide-semiconductor；LDMOS)装置的场效应晶体管结构以及形成LDMOS装置的方法。
背景技术
用于场效应晶体管的装置结构通常包括本体区，定义于该本体区中的源极及漏极，以及经配置以切换在该本体中在操作期间所形成的沟道中的载流子流的栅极电极。当向该栅极电极施加超过指定阈值电压的控制电压时，在该源极与漏极之间的该沟道中的反转层(inversion layer)或耗尽层(depletion layer)中发生载流子流，从而产生装置输出电流。
鳍式场效应晶体管(fin-type field-effect transistor；FinFET)是非平面装置结构，与平面场效应晶体管相比，它可被更密集地封装于集成电路中。FinFET可包括由半导体材料实心单体组成的鳍片，形成于该本体的部分中的重掺杂源/漏区，以及环绕在该源/漏区之间的该鳍片本体中所设置的沟道的栅极电极。与平面晶体管相比，在该栅极电极与鳍片本体之间的该布置改进对沟道的控制并降低该FinFET处于“关闭”状态时的漏电流。相应地，与平面晶体管相比，这能够使用较低的阈值电压，从而改进性能以及降低功耗。
例如，用于微波/RF功率放大器的高压集成电路通常需要能够忍受较高电压的专用电路技术。与逻辑场效应晶体管相比，横向扩散金属氧化物半导体(LDMOS)装置被设计成处理较高的电压。
需要用于LDMOS装置的改进场效应晶体管结构以及形成LDMOS装置的方法。
发明内容
在本发明的一个实施例中，提供一种场效应晶体管的结构。该结构包括位于衬底上的第一及第二鳍片，部分设于该衬底中且部分设于该第二鳍片中的第一阱，以及部分设于该衬底中、部分设于该第一鳍片中、且部分设于该第二鳍片中的第二阱。该第一阱具有第一导电类型，且该第二阱具有第二导电类型。该结构还包括具有该第二导电类型的第一源/漏区，位于该第一鳍片中的该第一阱内；以及具有该第二导电类型的第二源/漏区，位于该第二鳍片中的该第二阱内。第一栅极结构经设置以与该第一鳍片的第一部分重叠，且第二栅极结构经设置以与该第一鳍片的第二部分重叠。该第二栅极结构沿该第一鳍片与该第一栅极结构隔开。掺杂区设于该第一栅极结构与该第二栅极结构之间的该第一鳍片中的该第二阱内，且具有该第一导电类型。
在本发明的一个实施例中，提供一种制造场效应晶体管的方法。该方法包括在衬底上形成第一及第二鳍片，形成部分设于该衬底中且部分设于该第一鳍片中的第一阱，以及形成部分设于该衬底中、部分设于该第一鳍片中，且部分设于该第二鳍片中的第二阱。该第一阱具有第一导电类型，且该第二阱具有第二导电类型。在该第一鳍片中的该第一阱内形成具有该第二导电类型的第一源/漏区，以及在该第二鳍片中的该第二阱内形成具有该第二导电类型的第二源/漏区。形成与该第一鳍片的第一部分重叠的第一栅极结构，以及形成与该第一鳍片的第二部分重叠的第二栅极结构。该第二栅极结构沿该第一鳍片与该第一栅极结构隔开。掺杂区形成于该第一栅极结构与该第二栅极结构之间的该第一鳍片中的该第二阱内，并具有该第一导电类型。
附图说明
包含于并构成本说明书的一部分的附图说明本发明的各种实施例，并与上面所作的有关本发明的概括说明以及下面所作的有关实施例的详细说明一起用以解释本发明的实施例。
图1至3显示依据本发明的实施例处于制程方法的连续制造阶段的装置结构的剖视图。
图4显示依据本发明的替代实施例的装置结构的剖视图。
具体实施方式
请参照图1并依据本发明的实施例，鳍片10及鳍片11分别相对于衬底12(例如块体单晶硅衬底)而沿垂直方向凸出。鳍片10、11是由例如硅的半导体材料组成的三维体。从鳍片10、11向衬底12的顶部表面13的过渡是由图1中的虚线图示。因此，鳍片10、11在衬底的顶部表面13与衬底12无缝邻接，且具有各自高度，该些高度(相对于衬底12的顶部表面13沿垂直方向测量)可相等。
可利用侧壁图像转移(sidewall imaging transfer；SIT)制程或自对准双重图案化(self-aglined double patterning；SADP)通过图案化衬底12或生长于衬底12上的外延层而形成鳍片10、11，其中，在衬底12中蚀刻浅沟槽并用介电材料(例如通过化学气相沉积(chemical vapor deposition；CVD)所沉积的硅的氧化物(例如，SiO2))填充，以及通过化学机械抛光(chemical mechanical polishing；CMP)平坦化以形成浅沟槽隔离区(未显示)。在形成鳍片10、11及浅沟槽隔离区以后，形成围绕鳍片10、11并设于鳍片10、11之间的深沟槽隔离区14。为形成深沟槽隔离区14，可蚀刻穿过鳍片10、11及浅沟槽隔离至衬底12中的深沟槽并用介电材料(例如通过CVD沉积并用CMP平坦化的硅的氧化物(例如，SiO2))填充该深沟槽。回蚀刻(etch back)该浅沟槽隔离区的该介电材料及深沟槽隔离区14的该介电材料，以暴露设于该介电材料的相应凹入顶部表面之上的鳍片10、11的相应部分。鳍片10、11的其它部分嵌埋于该浅沟槽隔离区及深沟槽隔离区14中。
在鳍片10、11及衬底12中形成阱16及阱18。阱16(部分位于鳍片10中且部分位于衬底12中)由具有与阱18相反的导电类型的半导体材料组成。阱18部分位于鳍片10中、部分位于鳍片11中，且部分位于衬底12中。具体地说，阱18包括位于衬底12及鳍片11中的掺杂区21，以及位于衬底12及鳍片10中的槽(moat)区20。槽区20由具有与掺杂区21相同的导电类型的半导体材料组成，与阱18的掺杂区21相比，槽区20为较轻掺杂(也就是，具有较低掺杂物浓度)。
阱18的槽区20设于阱16与阱18的掺杂区21之间。槽区20沿着定义p-n结22的界面而与阱16邻接并且沿着界面19而与阱18的掺杂区21邻接。界面19与p-n结22可沿垂直方向取向。在一个实施例中，界面19直接位于深沟槽隔离区14下方。在一个实施例中，阱18的槽区20可围绕阱18的掺杂区21，以使界面19围绕掺杂区21的周边延伸。
阱16可通过例如在衬底12及鳍片10中引入掺杂物浓度的离子注入引入掺杂物来形成。阱18的掺杂区21可通过在衬底12及鳍片11中引入具有相反导电类型的不同掺杂物浓度来形成。可使用相应图案化注入掩膜来定义暴露的选定区域以供该注入。在相关注入以后，且在形成用以形成阱18的掺杂区21的注入掩膜之前，剥除用以选择暴露区域以形成阱16的注入掩膜。类似地，在执行相关注入以后，剥除用以选择暴露区域以形成阱18的掺杂区21的注入掩膜。该些注入掩膜可包括光敏材料层，例如有机光阻，其通过旋涂制程铺设、经历预烘烤、暴露于通过光掩膜投射的光、曝光后烘烤，以及用化学显影剂显影。用以形成阱16以及形成阱18的掺杂区21的该些注入掩膜具有足够的厚度及阻止能力来阻止鳍片10、11及衬底12的选定掩蔽区接受该注入离子的剂量。
注入条件(例如，离子种类、剂量、动能)可经选择以调节阱16的电性及物理特性(例如，电阻率及深度分布)。类似地，注入条件可经选择以调节阱18的掺杂区21的电性及物理特性。在一个实施例中，可用有效提供n型导电性的来自周期表的第V族的n型掺杂物(例如，磷(P)及/或砷(As))掺杂阱16的半导体材料。在一个实施例中，可用有效提供p型导电性的来自周期表的第III族的p型掺杂物(例如，硼)掺杂阱18的掺杂区21的半导体材料。
阱18的槽区20具有与阱18的掺杂区21相比较轻的掺杂物浓度。在一个实施例中，槽区20可通过向鳍片10及衬底12中透过离子注入引入掺杂物浓度来形成。在一个实施例中，槽区20可为轻掺杂衬底12的区段。在任一个实施例中，槽区20由用以后续形成阱16及阱18的掺杂区21的该些注入掩膜掩蔽，从而确定界面19及p-n结22相对于槽区20的位置。在形成阱18的掺杂区21时的该注入掩蔽以及深沟槽隔离区14的设置可经选择以使槽区20围绕阱18。
在衬底12中可形成与阱18具有相同的导电类型或与阱18具有相反的导电类型的掺杂区23。掺杂物23将阱18的掺杂区21及槽区20与衬底12电性隔离。
请参照图2，其中相同的附图标记表示图1中类似的特征且在下一制造阶段，形成栅极结构24、26，它们延伸横贯鳍片10及浅沟槽隔离的不同部分并与其重叠。栅极结构26也部分地延伸于鳍片10、11之间的深沟槽隔离区14上并与其重叠。栅极结构24、26可通过沉积不同组分材料的层堆叠并通过光刻及蚀刻图案化所沉积的层堆叠而形成。栅极结构24、26可包括由导体(例如金属、掺杂多晶硅(polysilicon))，或这些及其它导电材料的层堆叠组成的栅极电极；以及包括但不限于二氧化硅(SiO2)、高k介电材料(如氧化铪(HfO2))，或这些及其它介电材料的层堆叠的电性绝缘体。该电性绝缘体设于该导体与鳍片10的外表面之间。在一个实施例中，栅极结构24、26可为功能栅极结构，其为用以控制场效应晶体管的输出电流(也就是，沟道中的载流子流)的永久栅极结构。在一个实施例中，栅极结构24、26可为牺牲栅极结构，其为后续将形成于替代金属栅极制程中的功能栅极结构的占位结构(placeholder structure)。栅极结构24、26或替代栅极结构24、26的该功能栅极结构可通过中间工艺以及/或者后端工艺互连结构中的线路短接在一起。
具有相同导电类型的源/漏区28、30分别在鳍片10中及鳍片11中形成作为掺杂区。源/漏区28设于鳍片10中的阱16的部分中，并由具有与阱16相反的导电类型的重掺杂半导体材料组成。源/漏区30设于鳍片11中的阱18的掺杂区21的部分中，并由在较高掺杂物浓度的具有与阱18的掺杂区21相同的导电类型的重掺杂半导体材料组成。源/漏区28、30可通过蚀刻鳍片10、11并在鳍片10、11的相应蚀刻体积中外延生长掺杂半导体材料而形成。在阱16为n型半导体材料且阱18为p型半导体材料的实施例中，构成源/漏区28、30的该半导体材料可由p型掺杂物掺杂以提供p型导电性，且可由该p型掺杂物的浓度重掺杂。
请参照图3，其中相同的附图标记表示图2中类似的特征且在下一制造阶段，形成掺杂区32，其位于栅极结构24与栅极结构26之间的位置的鳍片10中的槽区20内。掺杂区32由具有与槽区20相反的导电类型且也具有与源/漏区28、30相反的导电类型的半导体材料组成。掺杂区32可与具有相反导电类型的槽区20直接耦接，以形成结。掺杂区32可通过蚀刻鳍片10并在鳍片10的该蚀刻体积中外延生长掺杂半导体材料形成。在槽区20为p型半导体材料的实施例中，掺杂区32的该半导体材料可由n型掺杂物(例如，磷(P)及/或砷(As))掺杂以提供n型导电性，且可由该n型掺杂物的浓度重掺杂。掺杂区32可形成于源/漏区28、30之前或之后。
本文中所使用的重掺杂半导体材料可被视为具有高于轻掺杂半导体材料的掺杂物浓度至少一个量级的掺杂物浓度。例如，重掺杂半导体材料的代表性掺杂物浓度可大于或等于1018cm-3，而轻掺杂半导体材料的代表性掺杂物浓度可小于或等于1016cm-3。
所得的场效应晶体管34包括鳍片10、11，阱16、18，栅极结构24、26，以及源/漏区28、30。阱16在装置操作期间充当沟道区。栅极结构24在装置操作期间控制场效应晶体管34的沟道。部分地延伸于鳍片10、11之间的深沟槽隔离区14上并与其重叠的栅极结构26可在场效应晶体管34的操作期间提供电场电镀(electric field plating)。设于p-n结22与源/漏区30之间的槽区20及阱18的掺杂区21共同构成场效应晶体管34的漏极延伸区或漂移区。
槽区20及掺杂区32代表传统LDMOS装置结构未发现的额外特征。槽区20的存在具有增加场效应晶体管34的击穿电压的效果。掺杂区32提供与槽区20的浮置结(floatingjunction)，其可用于在源极至漏极电压为零伏时在鳍片10中垂直耗尽槽区20。
接着执行中间工艺(middle-of-line；MOL)制程及后端工艺(back-end-of-line；BEOL)制程，其包括形成局部互连结构的接触及线路，以及形成通过该局部互连结构与场效应晶体管34耦接的BEOL互连结构的介电层、过孔塞以及线路。
请参照图4，其中相同的附图标记表示图3中类似的特征且依据本发明的替代实施例，在栅极结构24与栅极结构26之间可形成额外栅极结构25。掺杂区32沿着位于栅极结构25与栅极结构26之间的鳍片10设置。这导致在装置操作期间，掺杂区32进一步偏离在阱16中所形成的沟道区。使用不止一个栅极结构24、25会有效形成在源/漏区30提供高压漏极的堆叠逻辑场效应晶体管。
如上所述的方法用于集成电路芯片的制造中。制造者可以原始晶圆形式(例如作为具有多个未封装芯片的单个晶圆)、作为裸芯片，或者以封装形式分配所得的集成电路芯片。在后一种情况中，该芯片设于单芯片封装件中(例如塑料承载件，其具有附着至母板或其它更高层次承载件的引脚)或者多芯片封装件中(例如陶瓷承载件，其具有单面或双面互连或嵌埋互连)。在任何情况下，可将该芯片与其它芯片、分立电路元件和/或其它信号处理装置集成，作为中间产品或最终产品的部分。
本文中引用术语例如“垂直”、“水平”等作为示例来建立参考框架，并非限制。本文中所使用的术语“水平”被定义为与半导体衬底的传统平面平行的平面，而不论其实际的三维空间取向。术语“垂直”及“正交”是指垂直于如刚刚所定义的水平面的方向。术语“横向”是指在该水平平面内的方向。术语例如“上方”及“下方”用以表示元件或结构相对彼此的定位，而不是相对标高。
与另一个元件“连接”或“耦接”的特征可与该另一个元件直接连接或耦接，或者可存在一个或多个中间元件。如果不存在中间元件，则特征可与另一个元件“直接连接”或“直接耦接”。如存在至少一个中间元件，则特征可与另一个元件“非直接连接”或“非直接耦接”。
对本发明的各种实施例所作的说明是出于说明目的，而非意图详尽无遗或限于所揭示的实施例。许多修改及变更对于本领域的普通技术人员将显而易见，而不背离所述实施例的范围及精神。本文中所使用的术语经选择以最佳解释实施例的原理、实际应用或在市场已知技术上的技术改进，或者使本领域的普通技术人员能够理解本文中所揭示的实施例。

Claims (20)

1.一种利用衬底形成的场效应晶体管的结构，该结构包括：
第一鳍片及第二鳍片，位于该衬底上；
第一阱，部分设于该衬底中且部分设于该第一鳍片中，该第一阱具有第一导电类型；
第二阱，部分设于该衬底中、部分设于该第一鳍片中，且部分设于该第二鳍片中，该第二阱具有第二导电类型；
第一源/漏区，具有该第二导电类型，位于该第一鳍片中的该第一阱内；
第二源/漏区，具有该第二导电类型，位于该第二鳍片中的该第二阱内；
第一栅极结构，经设置以与该第一鳍片的第一部分重叠；
第二栅极结构，经设置以与该第一鳍片的第二部分重叠，该第二栅极结构沿着该第一鳍片而与该第一栅极结构隔开；以及
掺杂区，设于该第一栅极结构与该第二栅极结构之间的该第一鳍片中的该第二阱内，该掺杂区具有该第一导电类型。
2.如权利要求1所述的结构，其中，该第二阱包括第一区及第二区，该第二源/漏区设于该第二区中，该第二阱的该第一区在该第一阱与该第二阱的该第二区之间部分设于该第一鳍片中且部分设于该衬底中，以及该第二阱的该第二区位于该第二鳍片中。
3.如权利要求2所述的结构，其中，该第一阱与该第二阱的该第一区沿结会合，且该第二阱的该第一区将该第一阱与该第二阱的该第二区隔开。
4.如权利要求3所述的结构，其中，该第一栅极结构位于该第一阱与该第二阱的该第一区之间的该结上方。
5.如权利要求4所述的结构，还包括：
沟槽隔离区，位于该第一鳍片与该第二鳍片之间，
其中，该第二阱的该第一区与该第二阱的该第二区在该沟槽隔离区下方会合。
6.如权利要求2所述的结构，其中，该第二阱的该第一区由提供该第二导电类型的掺杂物的第一浓度掺杂，该第二阱的该第二区由提供该第二导电类型的该掺杂物的第二浓度掺杂，且该第二浓度大于该第一浓度。
7.如权利要求2所述的结构，其中，该掺杂区与该第二阱的该第一区耦接。
8.如权利要求7所述的结构，还包括：
沟槽隔离区，位于该第一鳍片与该第二鳍片之间，
其中，该第二栅极结构设于该掺杂区与该沟槽隔离区之间。
9.如权利要求2所述的结构，其中，该第二阱的该第一区围绕该第二阱的该第二区。
10.如权利要求1所述的结构，还包括：
第三栅极结构，与该第一鳍片的第三部分重叠，该第三栅极结构沿着该第一鳍片而与该第一栅极结构隔开，且该第一栅极结构及该第三栅极结构设于该第一源/漏区与该掺杂区之间。
11.如权利要求1所述的结构，其中，该掺杂区未被接触。
12.如权利要求1所述的结构，还包括：
沟槽隔离区，位于该第一鳍片与该第二鳍片之间，
其中，该第二栅极结构的部分与该沟槽隔离区具有重叠关系。
13.如权利要求1所述的结构，其中，该第一导电类型为n型导电性，且该第二导电类型为p型导电性。
14.一种制造场效应晶体管的方法，该方法包括：
在衬底上形成第一鳍片及第二鳍片；
形成部分设于该衬底中且部分设于该第一鳍片中的第一阱，该第一阱具有第一导电类型；
形成部分设于该衬底中、部分设于该第一鳍片中、且部分设于该第二鳍片中的第二阱，该第二阱具有第二导电类型；
在该第一鳍片中的该第一阱内形成具有该第二导电类型的第一源/漏区；
在该第二鳍片中的该第二阱内形成具有该第二导电类型的第二源/漏区；
形成与该第一鳍片的第一部分重叠的第一栅极结构；
形成与该第一鳍片的第二部分重叠的第二栅极结构，该第二栅极结构沿着该第一鳍片而与该第一栅极结构隔开；以及
形成设于该第一栅极结构与该第二栅极结构之间的该第一鳍片中的该第二阱内的掺杂区，该掺杂区具有该第一导电类型。
15.如权利要求14所述的方法，其中，该第二阱包括第一区及第二区，该第二源/漏区设于该第二区中，该第二阱的该第一区在该第一阱与该第二阱的该第二区之间部分设于该第一鳍片中且部分设于该衬底中，以及该第二阱的该第二区位于该第二鳍片中。
16.如权利要求15所述的方法，其中，该第一阱与该第二阱的该第一区沿着结会合，且该第二阱的该第一区将该第一阱与该第二阱的该第二区隔开。
17.如权利要求15所述的方法，其中，该掺杂区与该第二阱的该第一区直接耦接，且与该第二阱的该第二区相比，该第二阱的该第一区为较轻掺杂。
18.如权利要求17所述的方法，还包括：
形成设于该第一鳍片与该第二鳍片之间的沟槽隔离区，
其中，该第二栅极结构的部分与该沟槽隔离区具有重叠关系，且该第二栅极结构设于该掺杂区与该沟槽隔离区之间。
19.如权利要求17所述的方法，还包括：
形成与该第一鳍片的第三部分重叠的第三栅极结构，
其中，该第三栅极结构沿着该第一鳍片与该第一栅极结构隔开，且该第一栅极结构及该第三栅极结构设于该第一源/漏区与该掺杂区之间。
20.如权利要求14所述的方法，还包括：
在该第一鳍片与该第二鳍片之间形成沟槽隔离区，
其中，该第二栅极结构的部分与该沟槽隔离区具有重叠关系。
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