WO2022160568A1 - 存储器的制备方法 - Google Patents

存储器的制备方法 Download PDF

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Publication number
WO2022160568A1
WO2022160568A1 PCT/CN2021/100586 CN2021100586W WO2022160568A1 WO 2022160568 A1 WO2022160568 A1 WO 2022160568A1 CN 2021100586 W CN2021100586 W CN 2021100586W WO 2022160568 A1 WO2022160568 A1 WO 2022160568A1
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Prior art keywords
layer
area
mask
pattern
test
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PCT/CN2021/100586
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English (en)
French (fr)
Inventor
张家云
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长鑫存储技术有限公司
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Priority to US17/607,768 priority Critical patent/US11956941B2/en
Publication of WO2022160568A1 publication Critical patent/WO2022160568A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

Definitions

  • the present application relates to semiconductor integrated circuit manufacturing technology, and in particular, to a method for manufacturing a memory.
  • DRAM Dynamic random access memory
  • the dynamic random access memory includes a base and a plurality of isolation walls disposed on the base, and the base and the multiple isolation walls on the base are constituent structures in the dynamic random access memory.
  • the above-mentioned isolation wall has structural defects, which may lead to poor performance of the memory.
  • the present application provides a method for preparing a memory to solve the problem of poor memory performance.
  • An embodiment of the present application provides a method for fabricating a memory, which includes the following steps: providing a substrate, the substrate including a first functional area and a second functional area; forming a first isolation layer on the substrate; forming a pattern on the first isolation layer the first mask layer of the area, the pattern area includes a first pattern area opposite to the first functional area, and a second pattern area opposite to the second functional area, the first pattern area includes a plurality of first mask walls and formed a first trench between adjacent first mask walls, the second pattern area includes a plurality of second mask walls and a second trench formed between adjacent second mask walls; A second isolation layer is formed on the film layer and on the first isolation layer exposed in the first trench and the second trench, the second isolation layer forms a third trench in the first trench, and is in the second trench A fourth trench is formed inside; a second mask layer is formed on the second isolation layer, the second mask layer fills the third trench and the fourth trench, and covers the top surface of the second isolation layer, the second mask layer
  • the mask layer has a
  • a first isolation layer is formed on a substrate, a first mask layer having a first trench and a second trench is formed on the first isolation layer, and a first mask layer and a second trench are formed on the first isolation layer.
  • the first isolation layer not covered by the first mask layer forms a second isolation layer
  • the second isolation layer forms a third trench in the corresponding first trench
  • a fourth trench is formed in the corresponding second trench
  • a second mask layer is formed on the second isolation layer in the third trench and the fourth trench, and then part of the second mask layer and part of the second isolation layer are removed first, and then the first mask layer is removed and the remaining
  • the second mask layer is formed, and a third mask layer is formed on the first isolation layer and the second isolation layer, and then part of the structure of the third mask layer is removed, so that the top surface of the third mask layer and the remaining
  • the top surface of the second isolation layer is flush, and then using the remaining third mask layer as a mask, the remaining second isolation layer and the lower first isolation layer are etched.
  • the first isolation layer can be etched
  • a first functional pattern and a second functional pattern with a complete pattern structure are formed, thereby improving the performance of the memory.
  • the step of forming a first mask layer having patterned regions on the first isolation layer includes: forming a first mask germ layer on the first spacer layer; forming a photoresist layer on the first mask germ layer performing patterning treatment on the photoresist layer; etching part of the first mask germ layer with the patterned photoresist layer to form a first mask layer with a pattern area.
  • the first isolation layer of a set depth is also etched and removed, and the set depth is defined as L.
  • the depth L is set equal to the thickness D of the second isolation layer.
  • the method further includes: forming a dielectric anti-reflection layer on the first mask layer coating.
  • the material of the dielectric anti-reflection coating is silicon oxynitride.
  • the first mask layer and the remaining second mask layer are removed by oxygen plasma etching.
  • the first functional region includes a storage region on which a semiconductor structure is formed for storage and release of charges.
  • the second functional area includes a test area
  • the semiconductor structure formed on the test area is used for electrical testing of the semiconductor structure formed on the storage area during the fabrication process.
  • the second pattern area includes a test pattern area opposite to the test area, and the test pattern area includes a plurality of test mask walls and test trenches formed between adjacent test mask walls.
  • the second functional area further includes an alignment area, and the semiconductor structure formed on the alignment area is used for aligning the semiconductor structure formed on the storage area and the test area during exposure.
  • the second pattern area further includes an alignment pattern area opposite to the alignment area, at least one sub-pattern area is formed in the alignment pattern area, and a plurality of sub-mask walls arranged at intervals are formed in each sub-pattern area and the sub-trenches formed by every two adjacent sub-mask walls, the groove width of the sub-trenches is smaller than that of the test trenches, and the pattern density of the sub-trenches on the sub-pattern area is greater than that of the test trenches in the test pattern area Pattern density of grooves.
  • the number of sub-pattern regions is four, each sub-pattern region is rectangular, the four sub-pattern regions are arranged in a matrix of two rows and two columns, and are rotationally symmetric along the center of the matrix of the four sub-pattern regions.
  • the number of the storage areas formed on the substrate is multiple; the substrate is further formed with a cutting area for separating the multiple storage areas, and the cutting area is used to cut the substrate into after the semiconductor structure is formed on the substrate.
  • a plurality of memory cells; the alignment area is formed on the dicing area.
  • masking is performed with the remaining third mask layer, and part of the remaining second isolation layer and the first isolation layer thereunder are etched, and the process is performed by using a mixture of hexafluorobutadiene and oxygen. Plasma etching.
  • 1a is a schematic structural diagram of the photoresist on the storage area in the related art after patterning
  • 1b is a schematic structural diagram of a first mask layer with a pattern area disposed on a storage area in the related art
  • 1c is a schematic structural diagram of a second isolation layer and a second mask layer disposed on the storage area in the related art
  • FIG. 1d is a schematic structural diagram of removing part of the second mask layer from the storage area in the related art
  • FIG. 1e is a schematic structural diagram of the storage area after removing part of the second isolation layer, the first mask layer and the second mask layer in the related art
  • 2a is a schematic structural diagram of the photoresist on the test area in the related art after patterning
  • 2b is a schematic structural diagram of a first mask layer with a pattern area disposed on the test area in the related art
  • 2c is a schematic structural diagram of a second isolation layer and a second mask layer disposed on the test area in the related art
  • FIG. 2d is a schematic structural diagram of removing part of the second mask layer in the test area in the related art
  • 2e is a schematic structural diagram of the test area after removing a part of the second isolation layer, the first mask layer and the second mask layer in the related art
  • FIG. 3 a is a schematic structural diagram of the photoresist on the alignment region after patterning in the related art
  • 3b is a schematic structural diagram of a first mask layer with a pattern area disposed on the alignment area in the related art
  • 3c is a schematic structural diagram of a second isolation layer and a second mask layer disposed on the alignment region in the related art
  • 3d is a schematic structural diagram of removing part of the second mask layer in the alignment region in the related art
  • 3e is a schematic structural diagram of the alignment region after removing a part of the second isolation layer, the first mask layer and the second mask layer in the related art
  • 4a is a flowchart of a method for preparing a memory in an embodiment of the present application
  • 4b is a schematic structural diagram of an alignment region in an embodiment of the present application.
  • 4c is a schematic structural diagram of a test area in an embodiment of the present application.
  • 4d is a flowchart of a method for preparing a first mask layer in an embodiment of the present application
  • FIG. 5a is a schematic structural diagram of the photoresist on the storage area after patterning processing in an embodiment of the present application
  • 5b is a schematic structural diagram of a first mask layer having a pattern area disposed on the storage area according to an embodiment of the present application
  • FIG. 5c is a schematic structural diagram of setting a second isolation layer and a second mask layer on the storage area in an embodiment of the present application
  • FIG. 5d is a schematic structural diagram of removing part of the second mask layer and the second isolation layer in the storage area according to the embodiment of the present application;
  • 5e is a schematic structural diagram of the second mask layer and the first mask layer remaining after the storage area is removed in an embodiment of the present application;
  • FIG. 5f is a schematic structural diagram of setting a third mask layer on the storage area in an embodiment of the present application.
  • FIG. 5g is a schematic structural diagram of removing a part of the third mask layer from the storage area in an embodiment of the present application.
  • 5h is a schematic structural diagram of a third mask layer, a second isolation layer and a part of the first isolation layer remaining in the storage area removed in an embodiment of the present application;
  • FIG. 6a is a schematic structural diagram of the photoresist on the test area after patterning processing in an embodiment of the present application
  • FIG. 6b is a schematic structural diagram of a first mask layer with a pattern area disposed on the test area according to an embodiment of the present application;
  • Fig. 6c is the structural representation that the second isolation layer and the second mask layer are arranged on the test area in the embodiment of the application;
  • FIG. 6d is a schematic structural diagram of removing part of the second mask layer and the second isolation layer in the test area in an embodiment of the present application;
  • 6e is a schematic structural diagram of the second mask layer and the first mask layer remaining after the test area is removed in an embodiment of the present application;
  • 6f is a schematic structural diagram of a third mask layer disposed on the test area in an embodiment of the present application.
  • FIG. 6g is a schematic structural diagram of removing a part of the third mask layer in the test area according to an embodiment of the present application.
  • FIG. 6h is a schematic structural diagram of the third mask layer, the second isolation layer and a part of the first isolation layer remaining in the test area removed in the embodiment of the present application;
  • FIG. 7a is a schematic structural diagram of the photoresist on the alignment area after patterning in an embodiment of the present application.
  • 7b is a schematic structural diagram of a first mask layer with a pattern area disposed on the alignment area according to an embodiment of the present application;
  • 7c is a schematic structural diagram of disposing a second isolation layer and a second mask layer on the alignment region according to an embodiment of the present application;
  • 7d is a schematic structural diagram of removing part of the second mask layer and the second isolation layer in the alignment region according to the embodiment of the present application;
  • 7e is a schematic structural diagram of the second mask layer and the first mask layer remaining after the alignment region is removed in an embodiment of the present application;
  • 7f is a schematic structural diagram of a third mask layer disposed on the alignment region in an embodiment of the present application.
  • FIG. 7g is a schematic structural diagram of removing a part of the third mask layer in the alignment region according to an embodiment of the present application.
  • FIG. 7h is a schematic structural diagram of the third mask layer, the second isolation layer, and a part of the first isolation layer remaining after the alignment region is removed according to an embodiment of the present application.
  • 200 first isolation layer
  • 201 metal tungsten layer
  • Dynamic random access memory is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage devices or devices.
  • the dynamic random access memory includes a base and a plurality of isolation walls arranged on the base, and the base and the multiple isolation walls on the base are constituent structures in the dynamic random access memory.
  • a method for preparing an isolation wall on a substrate is: providing a substrate, the substrate including a storage area, a test area and an alignment area; forming a first isolation layer on the substrate, the structure formed by these two steps is shown in Figure 1a 2a and 3a, the substrate 100 includes a storage area, a test area and an alignment area, and a first isolation layer 200 is provided on the substrate 100;
  • the pattern area includes a first pattern area opposite to the storage area, a second pattern area opposite to the test area, and a third pattern area opposite to the alignment area, the first pattern area, the second pattern area and the The third pattern area is provided with a first mask layer trench.
  • the structure formed in this step is shown in FIG. 1b, FIG.
  • the first mask layer trench is provided on the first mask layer 300;
  • a second isolation layer is formed on the first mask layer 300 and on the first isolation layer 200 exposed in the trenches of the first mask layer, and the second isolation layer forms a second mask layer in the trenches of the first mask layer
  • the trench, the structure formed in this step is shown in FIG. 1c, FIG. 2c and FIG. 3c.
  • the second isolation layer 400 is disposed on the first mask layer 300 and the first isolation layer 200 in the trench of the first mask layer. ;
  • a second mask layer is formed on the second isolation layer 400, the second mask layer fills the trenches of the second mask layer and covers the top surface of the second isolation layer 400, and the second mask layer has the same characteristics as the first mask layer.
  • the first concave portion corresponding to the pattern area, the second concave portion corresponding to the second pattern area, and the third concave portion opposite to the third pattern area, the structures formed by this step are shown in Figure 1c, Figure 2c and Figure 3c , the second mask layer 500 covers the second isolation layer 400 and fills the trenches of the second mask layer; part of the second mask layer 500 is removed, and the top surface of the remaining second mask layer 500 is lower than The top surface of the second isolation layer 400, the structure formed in this step is shown in FIG. 1d, FIG. 2d and FIG.
  • the remaining second mask layer 500 is lower than the top surface of the second isolation layer 400 in the storage area, and the remaining The lower second mask layer 500 is lower than the top surface of the second isolation layer 400 in the test area and the alignment area; the remaining first mask layer 300 and the remaining second mask layer 500 are used as masks, The second isolation layer 400 and the first isolation layer 200 below it are etched to form an isolation wall.
  • the structure formed in this step is shown in FIG. 1e, FIG. 2e and FIG. 3e.
  • the structure of the isolation wall formed by the storage area is Basically intact, however, the structure of the isolation wall formed by the test area and the alignment area has a problem of over-etching, which will cause the isolation wall to be patterned and transferred to the metal layer between the substrate and the first isolation layer.
  • the pattern structure of the metal layer is defective, and the performance of the memory is poor.
  • the inventor of the present application tried to solve the problem of over-etching by reducing the etching depth.
  • the test area and the alignment area The area is etched at the same time.
  • the etch depth is reduced, the problem of connecting the bottoms of adjacent isolation walls will occur, which increases the probability of subsequent exposure alignment failure, and this method is not feasible.
  • an embodiment of the present application provides a method for fabricating a memory, which comprises removing the remaining second mask layer 500 and the first mask layer 500 after removing part of the second mask layer 500 .
  • a third mask layer 600 is formed on the first isolation layer 200 and part of the second isolation layer 400, and after removing part of the third mask layer 600, the remaining third mask layer 600 is used as mask, remove part of the second isolation layer 400 and part of the first isolation layer 200 to form an isolation layer, in this way, after removing part of the second mask layer 500, the second mask layer 500 and the first mask are directly removed layer 300, and then a third mask layer 600 is formed, and then the third mask layer 600 is used as a mask, and the third mask hardly forms a depression at the trench position, which makes the third mask as a mask When the first isolation layer 200 and the second isolation layer 400 are removed, over-etching will not be caused, so that the structure of the formed isolation wall is complete and the performance of the memory is good.
  • the embodiments of the present application provide a method for preparing a memory, which is used for preparing a memory, for example, a dynamic random access memory.
  • the preparation method includes the following steps:
  • Step S1 providing a substrate 100, the material of the substrate 100 may be silicon, germanium and other materials of the semiconductor substrate 100 well known to those skilled in the art.
  • the substrate 100 includes a first functional area and a second functional area, the first functional area may be, for example, a storage area 101, and the semiconductor structure formed on the storage area 101 is used for storing and releasing charges, and the second functional area may be, for example, a peripheral circuit area , the second functional area includes a test area 102 and an alignment area 103.
  • the semiconductor structure formed on the test area 102 is used for electrical testing of the semiconductor structure formed on the storage area 101 during the preparation process.
  • the semiconductor structure is used to align the semiconductor structures formed on the storage area 101 and the test area 102 during exposure, and the structures formed in this step can be referred to FIG. 5a, FIG. 6a and FIG. 7a.
  • the number of the storage areas 101 formed on the substrate 100 may be multiple, and a cutting area for separating the multiple storage areas 101 is also formed on the substrate 100 .
  • the cutting area is used to cut the substrate 100 after forming the semiconductor structure on the substrate 100 .
  • a plurality of memory cells are formed, and the alignment regions 103 are formed on the cutting regions. In this way, after cutting the substrate 100 , the alignment regions 103 that hardly affect the performance of the memory cells are destroyed, and the performance of the memory is good.
  • Step S2 forming a first isolation layer 200 on the substrate 100 , the material of the first isolation layer 200 includes but not limited to silicon oxide, the formation process of the first isolation layer 200 may be chemical deposition, and the structure formed in this step can refer to FIG. 5a, 6a and 7a, wherein, a metal tungsten layer 201 is arranged on the substrate 100 of the first functional area, an amorphous carbon layer 202 is arranged on the metal tungsten layer 201, and a rotating hard mask is arranged on the amorphous carbon layer 202 Layer 203 (English name is Spin-on ardmasks, English abbreviation is SOH), a silicon oxynitride layer 204 is arranged on the rotating hard mask layer 203, a first isolation layer 200 is arranged on the silicon oxynitride layer 204, and the second functional area is A metal tungsten layer 201 is arranged on the substrate 100 of the metal tungsten, an amorphous carbon layer 202 is arranged on the metal tungsten layer
  • Step S3 forming a first mask layer 300 having a pattern area on the first isolation layer 200, the pattern area includes a first pattern area opposite to the first functional area, and a second pattern area opposite to the second functional area,
  • the first pattern area includes a plurality of first mask walls and first trenches formed between adjacent first mask walls
  • the second pattern area includes a plurality of second mask walls and adjacent second mask walls.
  • the structure formed in this step is shown in FIG. 5b, FIG. 6b and FIG. 7b.
  • the first mask layer 300 has a first pattern area and a second pattern area.
  • the first pattern area is arranged on the first functional area, and the first pattern area is At least a plurality of first mask walls 301 and a first trench 302 between two adjacent first mask walls 301 are included, a second pattern area is disposed on the second functional area, and the second pattern area at least includes a plurality of A second mask wall and a second trench between two adjacent second mask walls.
  • the first mask layer 300 is, for example, a rotating hard mask, and the rotating hard mask is the film quality under the photoresist, which can play an appropriate role as a defense film in the subsequent etching process, helping the circuit to be transcribed onto the target film quality. , for fine-grained accuracy.
  • the second pattern area further includes a test pattern area opposite to the test area 102 and an alignment pattern area opposite to the alignment area 103
  • the test pattern area includes a plurality of Test mask walls 303 and test trenches 304 formed between adjacent test mask walls 303, at least one sub-pattern region 305 is formed in the alignment pattern region, and a plurality of sub-mask regions arranged at intervals are formed in each sub-pattern region 305
  • a film wall 306 and a sub-trench 307 formed by every two adjacent sub-mask walls 306 .
  • the test mask wall 303 and the sub-mask wall 306 together form the second mask wall
  • the test trench 304 and the sub-trench 307 together form the second trench.
  • the groove width of the sub-trench 307 is smaller than that of the test trench 304, and the pattern density of the sub-trench 307 in the sub-pattern region 305 is greater than that of the test trench 304 in the test pattern region.
  • the number of sub-pattern regions 305 may be four, each sub-pattern region 305 is rectangular, the four sub-pattern regions 305 are arranged in a matrix of two rows and two columns, and are rotationally symmetric along the center of the matrix of the four sub-pattern regions 305 .
  • the steps of forming the first mask layer 300 having the pattern area on the first isolation layer 200 include:
  • Step S31 forming a first mask germ layer on the first isolation layer 200 .
  • the first mask germ layer may be a rotating hard mask. Please refer to FIG. 5 a , FIG. 6 a and FIG. 7 a for the structure formed in this step.
  • the membranous layer 308 is disposed on the first isolation layer 200 .
  • Step S32 forming a photoresist layer on the first mask germ layer 308 .
  • the photoresist layer 309 is disposed on the first mask germ layer 308 .
  • Step S33 patterning the photoresist layer 309. Please refer to FIG. 5a, FIG. 6a and FIG. 7a for the structure formed in this step. A plurality of photoresist walls are formed on the photoresist layer 309, two adjacent A gap is formed between the photoresist walls.
  • Step S34 etching a part of the first mask germ layer 308 with the patterned photoresist layer 309 to form a first mask layer 300 having a pattern area.
  • the structure formed in this step is shown in FIG. 5b, FIG. 6b and FIG. 7b.
  • the first mask layer 300 has a first pattern area and a second pattern area.
  • the first pattern area is arranged on the first functional area, and the first pattern area is Including a plurality of first mask walls 301 and a first trench 302 between two adjacent first mask walls 301, the second pattern area further includes a test pattern area opposite to the test area 102, and an alignment area 103 is opposite to the alignment pattern area, the test pattern area includes a plurality of test mask walls 303 and test trenches 304 formed between adjacent test mask walls 303, and at least one sub-pattern area 305 is formed in the alignment pattern area , a plurality of sub-mask walls 306 arranged at intervals and a sub-trench 307 formed by every two adjacent sub-mask walls 306 are formed in each sub-pattern region 305 .
  • the method further includes: forming a dielectric anti-reflection coating on the first mask layer 308 Layer, a dielectric anti-reflection coating is a thin dielectric coating used to reduce the reflectivity of a surface for light in a certain wavelength region.
  • the material of the dielectric anti-reflection coating includes but is not limited to silicon oxynitride.
  • the structure formed in this step is shown in FIG. 5a, FIG. 6a and FIG. 7a.
  • the dielectric anti-reflection coating 310 is disposed on the first mask embryo layer 308, and the photoresist layer 309 is disposed on the dielectric anti-reflection coating 310.
  • Step S4 forming a second isolation layer 400 on the first mask layer 300 and on the first isolation layer 200 exposed in the first trench 302 and in the second trench, and the second isolation layer 400 is in the first trench A third trench is formed in 302, and a fourth trench is formed in the second trench, the material of the second isolation layer 400 can be the same as that of the first isolation layer 200, and the material of the second isolation layer 400 can be silicon oxide , the formation process of the second isolation layer 400 may be an atomic layer deposition method, the deposition thickness of the second isolation layer 400 is less than half of the groove width of the first trench 302 and half of the groove width of the second trench, and then in the first trench A third trench is formed at the position of the trench 302, and a fourth trench is formed at the position of the second trench.
  • the structure formed by this step is shown in FIG. 5c, FIG. 6c and FIG. 7c.
  • the second isolation layer 400 is disposed on the top surface and the side surface of the first mask layer 300, and is disposed on the first trench 302 and the second trench on the exposed first isolation layer 200 .
  • the first isolation layer 200 with a set depth is also etched and removed.
  • the fixed depth is defined as L shown in Figure 5b.
  • the first isolation layer 200 with a set depth is removed by etching, and after the second isolation layer 400 is formed, the first isolation layer directly under the first mask wall 301 can be formed.
  • the top surface of the first isolation layer 200 and the top surface of the second isolation layer 400 at the first trench 302 tend to be flush, so that the top surface of the first isolation layer 200 located directly under the second mask wall is at the position of the second trench
  • the top surface of the second isolation layer 400 tends to be flush, so that the pattern structure of the prepared memory is complete, and the performance of the memory is improved.
  • the depth L is set equal to the thickness D of the second isolation layer 400.
  • the first isolation layer 200 located directly under the first mask wall 301 can be formed.
  • the top surface of the first isolation layer 200 is flush with the top surface of the second isolation layer 400 at the first trench 302, so that the top surface of the first isolation layer 200 located directly under the second mask wall
  • the top surface of the isolation layer 400 is flush, so that the pattern structure of the prepared memory is complete, and the performance of the memory is improved.
  • Step S5 forming a second mask layer 500 on the second isolation layer 400, the second mask layer 500 may be a spin hard mask, the second mask layer 500 fills the third trench and the fourth trench, and The top surface of the second mask layer 500 is higher than the top surface of the second isolation layer 400, the second mask layer 500 has a first recess corresponding to the first pattern area, and a second recess corresponding to the second pattern area The first recessed portion has a smaller recessed depth in the direction of the substrate 100 than the second recessed portion, and can even be ignored.
  • the structure formed by this step is shown in FIG. 5c, FIG. 6c and FIG. 7c, the second mask layer 500 is disposed on the second isolation layer 400, and the second mask layer 500 is filled in the third trench and the fourth trench , the top surface of the second mask layer 500 is higher than the top surface of the second isolation layer 400 .
  • Step S6 removing part of the second mask layer 500 and part of the second isolation layer 400, the top surface of the remaining second isolation layer 400 is flush with the top surface of the first mask layer 300, and the remaining second mask layer 400
  • the top surface of the film layer 500 is equal to or smaller than the top surface of the first mask layer 300 and larger than the top surface of the first isolation layer 200.
  • the structure formed in this step is shown in FIG. 5d, FIG. 6d and FIG.
  • the top surface of the second mask layer 500 is flush with the top surface of the first mask layer 300 , and the remaining second isolation layer 400 , the remaining second mask layer 500 and the first mask layer 300 are strip-shaped structures , and the strip-shaped structure formed by the remaining second isolation layer 400 is disposed between the strip-shaped structure formed by the remaining second mask layer 500 and the strip-shaped structure formed by the first mask layer 300 .
  • Step S7 removing the first mask layer 300 and the remaining second mask layer 500.
  • oxygen plasma can be used to remove the first mask layer 300 and the remaining second mask layer 500.
  • the second isolation layer 400 is etched. The structure formed by this step is shown in FIG. 5e , FIG. 6e and FIG. 7e , and the remaining second isolation layer 400 is disposed on the first isolation layer 200 .
  • Step S8 forming a third mask layer on the first isolation layer 200 and the remaining second isolation layer 400 , and the third mask layer may be, for example, a spin hard mask.
  • the structures formed in this step are shown in FIG. 5f, FIG. 6f and FIG. 7f.
  • the third mask layer 600 fills the gaps between the strip-shaped structures formed by the remaining second isolation layer 400, and covers the remaining second isolation layer 400.
  • the top surface of the third mask layer 600 opposite to the first pattern area and the top surface opposite to the second pattern area are substantially flat.
  • Step S9 removing part of the third mask layer 600, the top surface of the remaining third mask layer 600 is flush with the top surface of the remaining second isolation layer 400, the structure formed in this step is shown in FIG. 5g and FIG. 6g
  • the remaining third mask layer 600 also has a stripe structure, and the stripe structure formed by the remaining third mask layer 600 and the stripe structure formed by the remaining second isolation layer 400 are spaced apart.
  • the top surface of the strip-shaped structure formed by the remaining third mask layer 600 and the top surface of the strip-shaped structure formed by the remaining second isolation layer 400 are flush with each other.
  • Step S10 using the remaining third mask layer 600 as a mask, etching the remaining part of the second isolation layer 400 and the first isolation layer 200 thereunder to form a first functional pattern opposite to the first functional area and a second functional pattern opposite to the second functional area.
  • the remaining third mask layer 600 is used for masking, and the remaining part of the second isolation layer 400 and the first isolation layer below it are etched. 200.
  • Plasma etching may be performed using a mixture of hexafluorobutadiene and oxygen. When plasma etching is performed using a mixture of hexafluorobutadiene and oxygen, the third mask layer 600 will be removed at the same time.
  • the structure formed by this step is shown in FIG. 5h, FIG. 6h and FIG. 7h, and the first isolation layer 200 also has a strip-like structure.
  • the first isolation layer 200 is formed on the substrate 100, the first mask layer 300 having the first trench 302 and the second trench is formed on the first isolation layer 200, and the first mask layer 300 is formed on the first isolation layer 200.
  • a mask layer 300 and the first isolation layer 200 not covered by the first mask layer 300 form a second isolation layer 400.
  • the second isolation layer 400 forms a third trench corresponding to the first trench 302, and a third trench corresponding to the first trench 302.
  • a fourth trench is formed in the two trenches, a second mask layer 500 is formed on the third trench and the second isolation layer 400 in the fourth trench, and then part of the second mask layer 500 and part of the second mask layer 500 are removed first.
  • the second isolation layer 400 is removed, the first mask layer 300 and the remaining second mask layer 500 are removed, and the third mask layer 600 is formed on the first isolation layer 200 and the second isolation layer 400, and then the third mask layer is removed.
  • the partial structure of the mask layer 600 is such that the top surface of the third mask layer 600 is flush with the top surface of the remaining second isolation layer 400, and then the remaining third mask layer 600 is used as a mask, and the remaining
  • the lower second isolation layer 400 and the lower first isolation layer 200 are etched, so that a first functional pattern and a second functional pattern with a complete pattern structure can be formed on the first isolation layer 200, so that the first functional pattern and the second functional pattern are There is no over-etching phenomenon in the functional pattern, and the etching depths of the first functional area and the second functional area are relatively uniform, thereby improving the performance of the memory.
  • the test area 102 , the alignment area 103 and the semiconductor structure on the storage area 101 are all formed in one step. From FIG. 4b and FIG. 4c, it can be seen that the test area 102 A large number of blank areas exist in the periphery of the alignment region 103, which causes structural defects in the semiconductor structure prepared by the memory preparation method of the related art.
  • the memory preparation method of the embodiment of the present application by first forming the second isolation layer 400 The strip-shaped structure is formed, and the third mask layer 600 is used to form a more complete semiconductor structure. This is because, when the second mask layer 500 is formed, there are large-sized test trenches 304 on the test area 102.
  • the top surface of the 600 is more flat, so that when the first isolation layer 200 is etched by using the remaining third mask layer 600, the pattern structure formed on the first isolation layer 200 is more complete, and the pattern is used to further process the tungsten metal.
  • the pattern on the first isolation layer 200 can also be correctly transferred to the metal tungsten layer 201 .

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Abstract

本申请提供一种存储器的制备方法，涉及半导体集成电路制造技术，用于解决存储器的性能差的问题。该存储器的制备方法包括如下步骤：提供基底；在基底上形成第一隔离层；在第一隔离层上形成第一掩膜层；在第一掩膜层上以及部分第一隔离层上形成第二隔离层；在第二隔离层上形成第二掩膜层；去除部分第二掩膜层和部分第二隔离层，保留下的第二隔离层的顶面与第一掩膜层的顶面平齐；去除第一掩膜层和剩余的第二掩膜层；在第一隔离层和保留下的第二隔离层上形成第三掩膜层；去除部分第三掩膜层；以保留下的第三掩膜层为掩膜，刻蚀保留下的部分第二隔离层及其下方的第一隔离层。本申请的存储器的制备方法用于制备性能优越的存储器。

Description

存储器的制备方法
本申请要求于2021年01月29日提交中国专利局、申请号为202110128863.7、申请名称为“存储器的制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体集成电路制造技术，尤其涉及一种存储器的制备方法。
背景技术
动态随机存储器(dynamic random access memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。
动态随机存储器包括基底以及设置在基底上的多个隔离墙，基底以及基底上的多个隔离墙是动态随机存储器内的构成结构。
然而，上述隔离墙存在结构缺陷，会导致存储器的性能差。
发明内容
鉴于上述问题，本申请提供一种存储器的制备方法，用于解决存储器性能差的问题。
为了实现上述目的，本申请实施例提供如下技术方案：
本申请实施例提供一种存储器的制备方法，其包括如下步骤：提供基底，基底包括第一功能区和第二功能区；在基底上形成第一隔离层；在第一隔离层上形成具有图案区的第一掩膜层，图案区包括与第一功能区相对的第一图案区，以及与第二功能区相对的第二图案区，第一图案区包括多个第一掩膜墙和形成在相邻第一掩膜墙之间的第一沟槽，第二图案区包括多个第二掩膜墙和形成在相邻第二掩膜墙之间的第二沟槽；在第一掩膜层 上以及暴露在第一沟槽和第二沟槽内的第一隔离层上形成第二隔离层，第二隔离层在第一沟槽内形成第三沟槽，且在第二沟槽内形成第四沟槽；在第二隔离层上形成第二掩膜层，第二掩膜层填充满第三沟槽和第四沟槽，且覆盖在第二隔离层的顶面，第二掩膜层具有与第一图案区对应的第一凹陷部，以及与第二图案区对应的第二凹陷部；去除部分第二掩膜层和部分第二隔离层，保留下的第二隔离层的顶面与第一掩膜层的顶面平齐，且保留下的第二掩膜层的顶面等于或小于第一掩膜层的顶面且大于第一隔离层的顶面；去除第一掩膜层和剩余的第二掩膜层；在第一隔离层和保留下的第二隔离层上形成第三掩膜层；去除部分第三掩膜层，保留下的第三掩膜层的顶面与保留下的第二隔离层的顶面齐平；以保留下的第三掩膜层为掩膜，刻蚀保留下的部分第二隔离层及其下方的第一隔离层，形成与第一功能区相对的第一功能图案以及与第二功能区相对的第二功能图案。
本申请实施例的存储器的制备方法，在基底上形成第一隔离层，在第一隔离层上形成具有第一沟槽和第二沟槽的第一掩膜层，在第一掩膜层和未被第一掩膜层覆盖的第一隔离层形成第二隔离层，第二隔离层在对应第一沟槽内形成第三沟槽，在对应第二沟槽内形成第四沟槽，在第三沟槽和第四沟槽内的第二隔离层上形成第二掩膜层，之后，先去除部分第二掩膜层和部分第二隔离层，后去除第一掩膜层和保留下的第二掩膜层，并在第一隔离层和第二隔离层上形成第三掩膜层，再去除第三掩膜层的部分结构，使得第三掩膜层的顶面和保留下的第二隔离层的顶面平齐，进而以保留下的第三掩膜层为掩膜，对保留下的第二隔离层以及下方的第一隔离层刻蚀，如此，可以在第一隔离层形成图案结构完整的第一功能图案和第二功能图案，进而提升存储器的性能。
在一些实施方式中，在第一隔离层上形成具有图案区的第一掩膜层的步骤包括：在第一隔离层上形成第一掩膜胚层；在第一掩膜胚层上形成光刻胶层；对光刻胶层进行图形化处理；以图形化处理后的光刻胶层刻蚀部分第一掩膜胚层，形成具有图案区的第一掩膜层。
在一些实施方式中，以图形化处理后的光刻胶层刻蚀部分第一掩膜胚层时，还刻蚀去除设定深度的第一隔离层，设定深度定义为L。
在一些实施方式中，设定深度L等于第二隔离层的厚度D。
在一些实施方式中，在第一隔离层上形成第一掩膜胚层之后，且在第一掩膜胚层上设置光刻胶层之前，还包括：在第一掩膜胚层上形成介电抗反射涂层。
在一些实施方式中，介电抗反射涂层的材质为氮氧化硅。
在一些实施方式中，去除第一掩膜层和剩余的第二掩膜层，采用氧等离子体刻蚀去除。
在一些实施方式中，第一功能区包括存储区，存储区上形成的半导体结构用于电荷的存储和释放。
在一些实施方式中，第二功能区包括测试区，测试区上形成的半导体结构用于在制备过程中对存储区上形成的半导体结构进行电性测试。
在一些实施方式中，第二图案区包括与测试区相对的测试图案区，测试图案区内包括多个测试掩膜墙和形成在相邻测试掩膜墙之间的测试沟槽。
在一些实施方式中，第二功能区还包括对准区，对准区上形成的半导体结构用于在曝光时对存储区和测试区上形成的半导体结构进行对准。
在一些实施方式中，第二图案区还包括与对准区相对的对准图案区，对准图案区内形成至少一个子图案区，每个子图案区内形成间隔排布的多个子掩膜墙和由每相邻两个子掩膜墙形成的子沟槽，子沟槽的槽宽小于测试沟槽的槽宽，且子图案区上的子沟槽的图案密度大于测试图案区上的测试沟槽的图案密度。
在一些实施方式中，子图案区的数量为四个，每个子图案区呈矩形，四个子图案区呈两行两列矩阵排布，且沿以四个子图案区的矩阵中心旋转对称。
在一些实施方式中，基底上形成的存储区的数量为多个；基底上还形成有将多个存储区隔开的切割区，切割区用于在基底上形成半导体结构后，将基底切割成多个存储单元；对准区形成在切割区上。
在一些实施方式中，以保留下的第三掩膜层进行掩膜，刻蚀保留下的部分第二隔离层及其下方的第一隔离层，采用六氟丁二烯和氧气的混合气进行等离子刻蚀。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技 术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请提供的存储器的制备方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a为相关技术中存储区上的光刻胶进行图形化处理后的结构示意图；
图1b为相关技术中存储区上设置具有图案区的第一掩膜层的结构示意图；
图1c为相关技术中存储区上设置第二隔离层和第二掩膜层的结构示意图；
图1d为相关技术中存储区去除部分第二掩膜层的结构示意图；
图1e为相关技术中存储区去除部分第二隔离层、第一掩膜层以及第二掩膜层后的结构示意图；
图2a为相关技术中测试区上的光刻胶进行图形化处理后的结构示意图；
图2b为相关技术中测试区上设置具有图案区的第一掩膜层的结构示意图；
图2c为相关技术中测试区上设置第二隔离层和第二掩膜层的结构示意图；
图2d为相关技术中测试区去除部分第二掩膜层的结构示意图；
图2e为相关技术中测试区去除部分第二隔离层、第一掩膜层以及第二掩膜层后的结构示意图；
图3a为相关技术中对准区上的光刻胶进行图形化处理后的结构示意图；
图3b为相关技术中对准区上设置具有图案区的第一掩膜层的结构示意图；
图3c为相关技术中对准区上设置第二隔离层和第二掩膜层的结构示意图；
图3d为相关技术中对准区去除部分第二掩膜层的结构示意图；
图3e为相关技术中对准区去除部分第二隔离层、第一掩膜层以及第二掩膜层后的结构示意图；
图4a为本申请实施例中存储器的制备方法流程图；
图4b为本申请实施例中对准区的结构示意图；
图4c为本申请实施例中测试区的结构示意图；
图4d为本申请实施例中第一掩膜层的制备方法流程图；
图5a为本申请实施例中存储区上的光刻胶进行图形化处理后的结构示意图；
图5b为本申请实施例中存储区上设置具有图案区的第一掩膜层的结构示意图；
图5c为本申请实施例中存储区上设置第二隔离层和第二掩膜层的结构示意图；
图5d为本申请实施例中存储区去除部分第二掩膜层和第二隔离层的结构示意图；
图5e为本申请实施例中存储区去除保留下的第二掩膜层和第一掩膜层的结构示意图；
图5f为本申请实施例中存储区上设置第三掩膜层的结构示意图；
图5g为本申请实施例中存储区去除部分第三掩膜层的结构示意图；
图5h为本申请实施例中存储区去除保留下第三掩膜层、保留下第二隔离层以及部分第一隔离层的结构示意图；
图6a为本申请实施例中测试区上的光刻胶进行图形化处理后的结构示意图；
图6b为本申请实施例中测试区上设置具有图案区的第一掩膜层的结构示意图；
图6c为本申请实施例中测试区上设置第二隔离层和第二掩膜层的结 构示意图；
图6d为本申请实施例中测试区去除部分第二掩膜层和第二隔离层的结构示意图；
图6e为本申请实施例中测试区去除保留下的第二掩膜层和第一掩膜层的结构示意图；
图6f为本申请实施例中测试区上设置第三掩膜层的结构示意图；
图6g为本申请实施例中测试区去除部分第三掩膜层的结构示意图；
图6h为本申请实施例中测试区去除保留下第三掩膜层、保留下第二隔离层以及部分第一隔离层的结构示意图；
图7a为本申请实施例中对准区上的光刻胶进行图形化处理后的结构示意图；
图7b为本申请实施例中对准区上设置具有图案区的第一掩膜层的结构示意图；
图7c为本申请实施例中对准区上设置第二隔离层和第二掩膜层的结构示意图；
图7d为本申请实施例中对准区去除部分第二掩膜层和第二隔离层的结构示意图；
图7e为本申请实施例中对准区去除保留下的第二掩膜层和第一掩膜层的结构示意图；
图7f为本申请实施例中对准区上设置第三掩膜层的结构示意图；
图7g为本申请实施例中对准区去除部分第三掩膜层的结构示意图；
图7h为本申请实施例中对准区去除保留下第三掩膜层、保留下第二隔离层以及部分第一隔离层的结构示意图。
附图标记：
100：基底；                     101：存储区；
102：测试区；                   103：对准区；
200：第一隔离层；               201：金属钨层；
202：无定型炭层；               203：旋转硬掩膜层；
204：氮氧化硅层；               300：第一掩膜层；
301：第一掩膜墙；               302：第一沟槽；
303：测试掩膜墙；                304：测试沟槽；
305：子图案区；                  306：子掩膜墙；
307：子沟槽；                    308：第一掩膜胚层；
309：光刻胶层；                  310：介电抗反射涂层；
400：第二隔离层；                500：第二掩膜层；
600：第三掩膜层。
具体实施方式
动态随机存储器(dynamic random access memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。动态随机存储器包括基底和设置在基底上的多个隔离墙，基底以及基底上的多个隔离墙是动态随机存储器内的构成结构。
在一些相关技术中，在基底上制备隔离墙的方法为：提供基底，基底包括存储区、测试区以及对准区；在基底上形成第一隔离层，这两个步骤形成的结构如图1a、图2a和图3a所示，基底100包括了存储区、测试区以及对准区，且在基底100上设置了第一隔离层200；在第一隔离层200上形成具有图案区的第一掩膜层300，图案区包括与存储区相对的第一图案区，与测试区相对的第二图案区，以及与对准区相对的第三图案区，第一图案区、第二图案区以及第三图案区均设置有第一掩膜层沟槽，此步骤形成的结构如图1b、图2b和图3b所示，第一掩膜层300上设置有第一掩膜层沟槽；在第一掩膜层300上以及暴露在第一掩膜层沟槽内的第一隔离层200上形成第二隔离层，第二隔离层在第一掩膜层沟槽内形成第二掩膜层沟槽，此步骤形成的结构如图1c、图2c和图3c所示，第二隔离层400设置在第一掩膜层300上以及第一掩膜层沟槽内的第一隔离层200上；在第二隔离层400上形成第二掩膜层，第二掩膜层填充满第二掩膜层沟槽且覆盖在第二隔离层400的顶面，第二掩膜层具有与第一图案区对应的第一凹陷部，与第二图案区对应的第二凹陷部，以及与第三图案区相对的第三凹陷部，此步骤形成的结构如图1c、图2c和图3c所示，第二掩膜层500覆盖在第二隔离层400上，且填充满第二掩膜层沟槽；去除部分第二掩膜层500，保留下的第二掩膜层500的顶面低于第二隔离层400的顶面，此 步骤形成的结构如图1d、图2d和图3d所示，保留下的第二掩膜层500在存储区低于第二隔离层400的顶面，保留下的第二掩膜层500在测试区和对准区低于第二隔离层400的顶面；以保留下的第一掩膜层300和保留下的第二掩膜层500为掩膜，刻蚀第二隔离层400及其下方的第一隔离层200，形成隔离墙，此步骤形成的结构如图1e、图2e和图3e所示，此结构中，存储区形成的隔离墙的结构基本完整，但是，测试区和对准区形成的隔离墙的结构出现过刻蚀的问题，这会导致将该隔离墙形成图案，转移到位于基底和第一隔离层之间的金属层后，金属层的图形结构存在缺陷，存储器的性能较差。
为了解决上述测试区和对准区出现过刻蚀的问题，本申请的发明人曾尝试通过减小刻蚀深度的方式来解决过刻蚀的问题，然而，由于存储区、测试区以及对准区是同时进行刻蚀工艺的，当减小刻蚀深度时，会出现相邻的隔离墙底部连接的问题，这使得后续曝光对准失效的概率增加，该方法不可行。
最后，为了解决上述隔离墙存在结构缺陷的问题，本申请实施例提供一种存储器的制备方法，其通过在去除部分第二掩膜层500之后，去除剩余的第二掩膜层500和第一掩膜层300，再在第一隔离层200和部分第二隔离层400上形成第三掩膜层600，再通过去除部分第三掩膜层600后，以剩余的第三掩膜层600为掩膜，去除部分第二隔离层400和部分第一隔离层200，形成隔离层，如此，由于在去除部分第二掩膜层500之后，直接去除了第二掩膜层500和第一掩膜层300，并再之后形成了第三掩膜层600，进而以第三掩膜层600为掩膜，第三掩膜在沟槽位置几乎不形成凹陷，这使得以第三掩膜为掩膜去除第一隔离层200和第二隔离层400时，不会造成过刻蚀，进而使得形成的隔离墙的结构完整，存储器的性能好。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重 点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
本申请实施例提供了一种存储器的制备方法，用于制备存储器，例如用于制备动态随机存储器。请参阅图4a，该制备方法包括如下步骤：
步骤S1：提供基底100，基底100的材料可以是硅、锗等本领域技术人员熟知的半导体基底100材料。基底100包括第一功能区和第二功能区，第一功能区例如可以是存储区101，存储区101上形成的半导体结构用于电荷的存储和释放，第二功能区例如可以是外围电路区，第二功能区包括测试区102和对准区103，测试区102上形成的半导体结构用于在制备过程中对存储区101上形成的半导体结构进行电性测试，对准区103上形成的半导体结构用于在曝光时对存储区101和测试区102上形成的半导体结构进行对准，此步骤形成的结构可以参阅图5a、图6a和图7a。
基底100上形成的存储区101的数量可以为多个，基底100上还形成有将多个存储区101隔开的切割区，切割区用于在基底100上形成半导体结构后，将基底100切割成多个存储单元，对准区103形成在切割区上，如此，在切割基底100后，破坏的是对存储单元的性能几乎不会造成影响的对准区103，存储器的性能好。
步骤S2：在基底100上形成第一隔离层200，第一隔离层200的材料包括但不限于氧化硅，第一隔离层200的形成工艺可以是化学沉积法，此步骤形成的结构可以参阅图5a、图6a和图7a，其中，第一功能区的基底100上设置有金属钨层201，金属钨层201上设置有无定型炭层202，无定型炭层202上设置有旋转硬掩膜层203(英文名称为Spin-on ardmasks，英文简称为SOH)，旋转硬掩膜层203上设置有氮氧化硅层204，氮氧化硅层204上设置有第一隔离层200，第二功能区的基底100上设置有金属钨层201，金属钨层201上设置有无定型炭层202，无定型炭层202上设置有氮氧化硅层204，氮氧化硅层204上设置有第一隔离层200。
步骤S3：在第一隔离层200上形成具有图案区的第一掩膜层300，图案区包括与第一功能区相对的第一图案区，以及与第二功能区相对的第二图案区，第一图案区包括多个第一掩膜墙和形成在相邻第一掩膜墙之间的第一沟槽，第二图案区包括多个第二掩膜墙和形成在相邻第二掩膜墙之间 的第二沟槽。此步骤形成的结构如图5b、图6b和图7b所示，第一掩膜层300具有第一图案区和第二图案区，第一图案区设置在第一功能区上，第一图案区至少包括多个第一掩膜墙301以及相邻两个第一掩膜墙301之间的第一沟槽302，第二图案区设置在第二功能区上，第二图案区至少包括多个第二掩膜墙以及相邻两个第二掩膜墙之间的第二沟槽。
第一掩膜层300例如是旋转硬掩膜，旋转硬掩膜是光致抗蚀剂下部的膜质，在后续蚀刻工艺中可以起到适当的防御膜作用，帮助电路转录到目标膜质上，以实现微细图形的准确度。
请参阅图6b、图4b、图4c和图7b，第二图案区还包括与测试区102相对的测试图案区，以及与对准区103相对的对准图案区，测试图案区内包括多个测试掩膜墙303和形成在相邻测试掩膜墙303之间的测试沟槽304，对准图案区内形成至少一个子图案区305，每个子图案区305内形成间隔排布的多个子掩膜墙306和由每相邻两个子掩膜墙306形成的子沟槽307。其中，测试掩膜墙303和子掩膜墙306共同组成上述第二掩膜墙，测试沟槽304和子沟槽307共同组成上述第二沟槽。
上述子图案区305中，子沟槽307的槽宽小于测试沟槽304的槽宽，且子图案区305上的子沟槽307的图案密度大于测试图案区上的测试沟槽304的图案密度。子图案区305的数量可以为四个，每个子图案区305呈矩形，四个子图案区305呈两行两列矩阵排布，且沿以四个子图案区305的矩阵中心旋转对称。
请参照图4d，在第一隔离层200上形成具有图案区的第一掩膜层300的步骤包括：
步骤S31：在第一隔离层200上形成第一掩膜胚层，第一掩膜胚层可以是旋转硬掩膜，此步骤形成的结构请参阅图5a、图6a和图7a所示，第一掩膜胚层308设置在第一隔离层200上。
步骤S32：在第一掩膜胚层308上形成光刻胶层，此步骤形成的结构请参阅图5a、图6a和图7a所示，光刻胶层309设置在第一掩膜胚层308上。
步骤S33：对光刻胶层309进行图形化处理，此步骤形成的结构请参阅图5a、图6a和图7a所示，光刻胶层309上形成多个光刻胶墙，相邻两 个光刻胶墙之间形成有间隙。
步骤S34：以图形化处理后的光刻胶层309刻蚀部分第一掩膜胚层308，形成具有图案区的第一掩膜层300。此步骤形成的结构如图5b、图6b和图7b所示，第一掩膜层300具有第一图案区和第二图案区，第一图案区设置在第一功能区上，第一图案区包括多个第一掩膜墙301以及相邻两个第一掩膜墙301之间的第一沟槽302，第二图案区还包括与测试区102相对的测试图案区，以及与对准区103相对的对准图案区，测试图案区内包括多个测试掩膜墙303和形成在相邻测试掩膜墙303之间的测试沟槽304，对准图案区内形成至少一个子图案区305，每个子图案区305内形成间隔排布的多个子掩膜墙306和由每相邻两个子掩膜墙306形成的子沟槽307。
在第一隔离层200上形成第一掩膜胚层308之后，且在第一掩膜胚层308上设置光刻胶层309之前，还包括：在第一掩膜胚层308上形成介电抗反射涂层，介电抗反射涂层是一层薄的电介质涂层，用于减小表面对某一波长区域光的反射率。介电抗反射涂层的材质包括但不限于氮氧化硅。此步骤形成的结构请参阅图5a、图6a和图7a所示，介电抗反射涂层310设置在第一掩膜胚层308上，介电抗反射涂层310上设置光刻胶层309。
步骤S4：在第一掩膜层300上以及暴露在第一沟槽302内和第二沟槽内的第一隔离层200上形成第二隔离层400，第二隔离层400在第一沟槽302内形成第三沟槽，且在第二沟槽内形成第四沟槽，第二隔离层400的材料可以与第一隔离层200的材料一样，第二隔离层400的材料可以是氧化硅，第二隔离层400的形成工艺可以是原子层沉积法,第二隔离层400的沉积厚度小于第一沟槽302的槽宽的一半以及第二沟槽的槽宽的一半，进而在第一沟槽302位置形成第三沟槽，在第二沟槽位置形成第四沟槽。此步骤形成的结构请参阅图5c、图6c和图7c所示，第二隔离层400设置在第一掩膜层300的顶面和侧面，以及设置在第一沟槽302和第二沟槽内暴露的第一隔离层200上。
请参阅图5b、图6b和图7b所示，以图形化处理后的光刻胶层309刻蚀部分第一掩膜胚层308时，还刻蚀去除设定深度的第一隔离层200，设定深度定义为图5b示出的L。在刻蚀部分第一掩膜胚层308时，刻蚀去除设定深度的第一隔离层200，可以在形成第二隔离层400后，使得位 于第一掩膜墙301正下方的第一隔离层200的顶面与第一沟槽302处的第二隔离层400的顶面趋于齐平，使得位于第二掩膜墙正下方的第一隔离层200的顶面与第二沟槽位置处的第二隔离层400的顶面趋于齐平，进而使得制备的存储器的图案结构完整，存储器的性能得到提升。
请参照图5b和图5c，设定深度L等于第二隔离层400的厚度D，如此，可以在形成第二隔离层400后，使得位于第一掩膜墙301正下方的第一隔离层200的顶面与第一沟槽302处的第二隔离层400的顶面齐平，使得位于第二掩膜墙正下方的第一隔离层200的顶面与第二沟槽位置处的第二隔离层400的顶面齐平，进而使得制备的存储器的图案结构完整，存储器的性能得到提升。
步骤S5：在第二隔离层400上形成第二掩膜层500，第二掩膜层500可以是旋转硬掩膜，第二掩膜层500填充满第三沟槽和第四沟槽，且第二掩膜层500的顶面高于第二隔离层400的顶面，第二掩膜层500具有与第一图案区对应的第一凹陷部，以及与第二图案区对应的第二凹陷部，其中，第一凹陷部相比第二凹陷部往基底100方向的凹陷深度很小，甚至可以忽略。此步骤形成的结构如图5c、图6c和图7c所示，第二掩膜层500设置在第二隔离层400上，第二掩膜层500填充在第三沟槽和第四沟槽内，第二掩膜层500的顶面高于第二隔离层400的顶面。
步骤S6：去除部分第二掩膜层500和部分第二隔离层400，保留下的第二隔离层400的顶面与第一掩膜层300的顶面平齐，且保留下的第二掩膜层500的顶面等于或小于第一掩膜层300的顶面且大于第一隔离层200的顶面，此步骤形成的结构如图5d、图6d和图7d所示，保留下的第二掩膜层500的顶面和第一掩膜层300的顶面平齐，保留下的第二隔离层400、保留下的第二掩膜层500以及第一掩膜层300呈条状结构，且保留下的第二隔离层400形成的条形结构设置在保留下的第二掩膜层500形成的条状结构以及第一掩膜层300形成的条状结构之间。
步骤S7：去除第一掩膜层300和剩余的第二掩膜层500，该步骤可以采用氧等离子体去除第一掩膜层300和剩余的第二掩膜层500，该步骤不会对第二隔离层400造成刻蚀，此步骤形成的结构如图5e、图6e和图7e所示，保留下的第二隔离层400设置在第一隔离层200上。
步骤S8：在第一隔离层200和保留下的第二隔离层400上形成第三掩膜层，第三掩膜层例如可以是旋转硬掩膜。此步骤形成的结构如图5f、图6f和图7f所示，第三掩膜层600填充满保留下的第二隔离层400形成的条形结构之间的间隙，并覆盖在保留下的第二隔离层400上，第三掩膜层600与第一图案区相对的顶面以及与第二图案区相对的顶面大致为平面。
步骤S9：去除部分第三掩膜层600，保留下的第三掩膜层600的顶面与保留下的第二隔离层400的顶面齐平，此步骤形成的结构如图5g、图6g和图7g所示，保留下的第三掩膜层600也呈条状结构，保留下的第三掩膜层600形成的条状结构和保留下的第二隔离层400形成的条形结构间隔设置，并同时设置在第一隔离层200上，保留下的第三掩膜层600形成的条状结构的顶面和保留下的第二隔离层400形成的条形结构的顶面齐平。
步骤S10：以保留下的第三掩膜层600为掩膜，刻蚀保留下的部分第二隔离层400及其下方的第一隔离层200，形成与第一功能区相对的第一功能图案以及与第二功能区相对的第二功能图案，此步骤中，以保留下的第三掩膜层600进行掩膜，刻蚀保留下的部分第二隔离层400及其下方的第一隔离层200，可以采用六氟丁二烯和氧气的混合气进行等离子刻蚀，当采用六氟丁二烯和氧气的混合气进行等离子刻蚀时，会同时去除第三掩膜层600。此步骤形成的结构如图5h、图6h和图7h所示，第一隔离层200也呈条状结构。
本申请实施例的存储器的制备方法，在基底100上形成第一隔离层200，在第一隔离层200上形成具有第一沟槽302和第二沟槽的第一掩膜层300，在第一掩膜层300和未被第一掩膜层300覆盖的第一隔离层200形成第二隔离层400，第二隔离层400在对应第一沟槽302内形成第三沟槽，在对应第二沟槽内形成第四沟槽，在第三沟槽和第四沟槽内的第二隔离层400上形成第二掩膜层500，之后，先去除部分第二掩膜层500和部分第二隔离层400，后去除第一掩膜层300和保留下的第二掩膜层500，并在第一隔离层200和第二隔离层400上形成第三掩膜层600，再去除第三掩膜层600的部分结构，使得第三掩膜层600的顶面和保留下的第二隔离层400的顶面平齐，进而以保留下的第三掩膜层600为掩膜，对保留下的第二隔离层400以及下方的第一隔离层200刻蚀，如此，可以在第一隔 离层200形成图案结构完整的第一功能图案和第二功能图案，使得第一功能图案和第二功能图案不会出现过刻蚀现象，且第一功能区和第二功能区的刻蚀深度较均匀，进而提升存储器的性能。
本申请实施例的存储器的制备方法，测试区102、对准区103以及存储区101上的半导体结构都是在一个步骤中形成的，从图4b和图4c中，可以看到，测试区102和对准区103的外围存在大量的空白区，这使得通过相关技术的存储器制备方法制备的半导体结构存在结构缺陷，而采用本申请实施例的存储器的制备方法，通过先形成第二隔离层400的条形结构，再利用第三掩膜层600，形成的半导体结构结构更加完整，这是由于，在形成第二掩膜层500的时候，测试区102上有大尺寸的测试沟槽304，对准区103上有数量较多的小尺寸的子沟槽307，测试区102和对准区103的外围却存在大量的空白区，形成第二掩膜层500时，为了填充测试沟槽304和子沟槽307，容易在测试沟槽304和子沟槽307位置形成凹陷，而去除第二掩膜层500和第一掩膜层300后，在第二隔离层400和第一隔离层200上形成第三掩膜层600的时候，测试区102和对准区103的外围没有了空白区，且第一隔离层200上形成的第二隔离层400的横向尺寸小，形成的第三掩膜层600的顶面更平整，进而使得利用保留下的第三掩膜层600刻蚀第一隔离层200时，在第一隔离层200上形成的图案结构更加完整，后续利用该图案进一步处理金属钨层201时，也可以将第一隔离层200上的图案正确转移到金属钨层201上。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (20)

  1. 一种存储器的制备方法，其中，包括如下步骤：
    提供基底，所述基底包括第一功能区和第二功能区；
    在所述基底上形成第一隔离层；
    在所述第一隔离层上形成具有图案区的第一掩膜层，所述图案区包括与所述第一功能区相对的第一图案区，以及与所述第二功能区相对的第二图案区，所述第一图案区包括多个第一掩膜墙和形成在相邻所述第一掩膜墙之间的第一沟槽，所述第二图案区包括多个第二掩膜墙和形成在相邻所述第二掩膜墙之间的第二沟槽；
    在所述第一掩膜层上以及暴露在所述第一沟槽内和所述第二沟槽内的所述第一隔离层上形成第二隔离层，所述第二隔离层在所述第一沟槽内形成第三沟槽，且在所述第二沟槽内形成第四沟槽；
    在所述第二隔离层上形成第二掩膜层，所述第二掩膜层填充满所述第三沟槽和所述第四沟槽，且覆盖在所述第二隔离层的顶面，所述第二掩膜层具有与所述第一图案区对应的第一凹陷部，以及与所述第二图案区对应的第二凹陷部；
    去除部分所述第二掩膜层和部分所述第二隔离层，保留下的所述第二隔离层的顶面与所述第一掩膜层的顶面平齐，且保留下的所述第二掩膜层的顶面等于或小于所述第一掩膜层的顶面且大于所述第一隔离层的顶面；
    去除所述第一掩膜层和剩余的所述第二掩膜层；
    在所述第一隔离层和保留下的所述第二隔离层上形成第三掩膜层；
    去除部分所述第三掩膜层，保留下的所述第三掩膜层的顶面与保留下的所述第二隔离层的顶面齐平；
    以保留下的所述第三掩膜层为掩膜，刻蚀保留下的部分所述第二隔离层及其下方的所述第一隔离层，形成与所述第一功能区相对的第一功能图案以及与所述第二功能区相对的第二功能图案。
  2. 根据权利要求1所述的存储器的制备方法，其中，在所述第一隔离层上形成具有图案区的第一掩膜层的步骤包括：
    在所述第一隔离层上形成第一掩膜胚层；
    在所述第一掩膜胚层上形成光刻胶层；
    对所述光刻胶层进行图形化处理；
    以图形化处理后的所述光刻胶层刻蚀部分所述第一掩膜胚层，形成具有图案区的所述第一掩膜层。
  3. 根据权利要求2所述的存储器的制备方法，其中，以图形化处理后的所述光刻胶层刻蚀部分所述第一掩膜胚层时，还刻蚀去除设定深度的所述第一隔离层，所述设定深度定义为L。
  4. 根据权利要求3所述的存储器的制备方法，其中，所述设定深度L等于所述第二隔离层的厚度D。
  5. 根据权利要求2所述的存储器的制备方法，其中，在所述第一隔离层上形成第一掩膜胚层之后，且在所述第一掩膜胚层上设置光刻胶层之前，还包括：
    在所述第一掩膜胚层上形成介电抗反射涂层。
  6. 根据权利要求5所述的存储器的制备方法，其中，所述介电抗反射涂层的材质为氮氧化硅。
  7. 根据权利要求1所述的存储器的制备方法，其中，去除所述第一掩膜层和剩余的所述第二掩膜层，采用氧等离子体刻蚀去除。
  8. 根据权利要求1所述的存储器的制备方法，其中，所述第一功能区包括存储区，所述存储区上形成的半导体结构用于电荷的存储和释放。
  9. 根据权利要求8所述的存储器的制备方法，其中，所述第二功能区包括测试区，所述测试区上形成的半导体结构用于在制备过程中对所述存储区上形成的半导体结构进行电性测试。
  10. 根据权利要求9所述的存储器的制备方法，其中，所述第二图案区包括与所述测试区相对的测试图案区，所述测试图案区内包括多个测试掩膜墙和形成在相邻所述测试掩膜墙之间的测试沟槽。
  11. 根据权利要求10所述的存储器的制备方法，其中，所述第二功能区还包括对准区，所述对准区上形成的半导体结构用于在曝光时对所述存储区和所述测试区上形成的半导体结构进行对准。
  12. 根据权利要求11所述的存储器的制备方法，其中，所述第二图案区还包括与所述对准区相对的对准图案区，所述对准图案区内形成至少一个子图案区，每个所述子图案区内形成间隔排布的多个子掩膜墙和由每 相邻两个所述子掩膜墙形成的子沟槽，所述子沟槽的槽宽小于所述测试沟槽的槽宽，且所述子图案区上的所述子沟槽的图案密度大于所述测试图案区上的所述测试沟槽的图案密度。
  13. 根据权利要求12所述的存储器的制备方法，其中，所述子图案区的数量为四个，每个所述子图案区呈矩形，四个所述子图案区呈两行两列矩阵排布，且沿以四个所述子图案区的矩阵中心旋转对称。
  14. 根据权利要求11所述的存储器的制备方法，其中，所述基底上形成的存储区的数量为多个；
    所述基底上还形成有将多个所述存储区隔开的切割区，所述切割区用于在所述基底上形成半导体结构后，将所述基底切割成多个存储单元；
    所述对准区形成在所述切割区上。
  15. 根据权利要求2所述的存储器的制备方法，其中，所述第一功能区包括存储区，所述存储区上形成的半导体结构用于电荷的存储和释放。
  16. 根据权利要求15所述的存储器的制备方法，其中，所述第二功能区包括测试区，所述测试区上形成的半导体结构用于在制备过程中对所述存储区上形成的半导体结构进行电性测试。
  17. 根据权利要求16所述的存储器的制备方法，其中，所述第二图案区包括与所述测试区相对的测试图案区，所述测试图案区内包括多个测试掩膜墙和形成在相邻所述测试掩膜墙之间的测试沟槽。
  18. 根据权利要求17所述的存储器的制备方法，其中，所述第二功能区还包括对准区，所述对准区上形成的半导体结构用于在曝光时对所述存储区和所述测试区上形成的半导体结构进行对准。
  19. 根据权利要求18所述的存储器的制备方法，其中，所述第二图案区还包括与所述对准区相对的对准图案区，所述对准图案区内形成至少一个子图案区，每个所述子图案区内形成间隔排布的多个子掩膜墙和由每相邻两个所述子掩膜墙形成的子沟槽，所述子沟槽的槽宽小于所述测试沟槽的槽宽，且所述子图案区上的所述子沟槽的图案密度大于所述测试图案区上的所述测试沟槽的图案密度。
  20. 根据权利要求1所述的存储器的制备方法，其中，以保留下的所述第三掩膜层进行掩膜，刻蚀保留下的部分所述第二隔离层及其下方的所 述第一隔离层，采用六氟丁二烯和氧气的混合气进行等离子刻蚀。
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