WO2022156010A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2022156010A1
WO2022156010A1 PCT/CN2021/075585 CN2021075585W WO2022156010A1 WO 2022156010 A1 WO2022156010 A1 WO 2022156010A1 CN 2021075585 W CN2021075585 W CN 2021075585W WO 2022156010 A1 WO2022156010 A1 WO 2022156010A1
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Prior art keywords
layer
light shielding
array substrate
thin film
insulating layer
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PCT/CN2021/075585
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English (en)
French (fr)
Inventor
罗成志
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US17/280,913 priority Critical patent/US12107094B2/en
Publication of WO2022156010A1 publication Critical patent/WO2022156010A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si

Definitions

  • the present invention relates to the field of display technology, and in particular, to an array substrate and a display panel.
  • Low temperature polysilicon low temperature polysilicon
  • LTPS temperature poly-silicon
  • LTPO Low temperature polycrystalline oxide
  • LTPO Polycrystalline-si oxide
  • FIG. 1 is a schematic diagram of the film layer structure of an array substrate using low temperature polycrystalline oxide technology in the prior art.
  • the array substrate includes a substrate 101, a buffer layer 102, and a first gate insulating layer that are stacked in sequence. 103, the interlayer dielectric layer 104, the second gate insulating layer 105, the passivation protection layer 106 and the flat layer 107, the array substrate is also provided with a plurality of gate driving thin film transistors 11 and pixel driving thin film transistors 12, the gate
  • the semiconductor layers of the driving thin film transistor 11 and the pixel driving thin film transistor 12 are a polysilicon semiconductor layer 111 and an oxide semiconductor layer 121, respectively.
  • the oxide semiconductor layer 121 is sensitive to light and hydrogen, for the pixel driving thin film transistor 12 of the bottom gate structure, it is necessary to increase the area of the first gate electrode 122 located at the bottom of the oxide semiconductor layer 121 to improve the shading effect.
  • FIG. 2 which is a schematic plan view of the pixel driving thin film transistor 12 in the prior art, the first gate electrode 122 and the scan line 14 are located in the same layer, and the first source electrode 123 and the first drain electrode 124 are connected to the data line. 15 is located on the same layer.
  • the first gate electrode 122 needs to exceed the edge of the oxide semiconductor layer 121 by at least 3 ⁇ m, but this will reduce the aperture ratio of the array substrate.
  • the second gate 112 of the gate driving thin film transistor 11, the second source 113 and the second drain 114 need to be insulated and separated by an interlayer dielectric layer 115, and the interlayer dielectric layer 115 contains hydrogen content.
  • the hydrogen in the interlayer dielectric layer 115 will diffuse into the oxide semiconductor layer 121, resulting in electrical abnormality of the oxide semiconductor layer 121, resulting in the stability of the pixel driving thin film transistor 12. reduce.
  • the existing array substrate has the problem of reducing the aperture ratio caused by improving the shading effect by increasing the area of the gate. Therefore, it is necessary to provide an array substrate and a display panel to improve this defect.
  • Embodiments of the present application provide an array substrate, a method for manufacturing the same, and a display panel, which are used to solve the problem of reducing the aperture ratio caused by increasing the area of the gate to improve the shading effect of the existing array substrate.
  • An embodiment of the present application provides an array substrate, the array substrate includes a plurality of thin film transistors distributed in an array, and at least some of the thin film transistors in the plurality of thin film transistors include an oxide semiconductor layer;
  • the array substrate is provided with a plurality of groove-shaped light-shielding patterns, and the oxide semiconductor layer is correspondingly formed in the grooves of the light-shielding patterns.
  • the array substrate includes a base substrate and a first insulating layer disposed on the base substrate, the first insulating layer is provided with a plurality of via holes, and the light shielding pattern is disposed on in the via hole.
  • the light-shielding pattern includes a bottom-surface light-shielding layer and a side-surface light-shielding layer, the bottom-surface light-shielding layer is laid flat on the bottom of the via hole, and the bottom-surface light-shielding layer faces the first insulating layer away from all One side of the base substrate extends to form the side light shielding layer, and the side light shielding layer and the bottom light shielding layer form a certain angle.
  • the angle formed by the side light shielding layer and the bottom light shielding layer is a right angle or an obtuse angle.
  • the degree of the included angle is greater than 90° and less than or equal to 140°.
  • the distance between the top of the side light shielding layer and the bottom light shielding layer is greater than the distance between the side of the oxide semiconductor layer away from the base substrate and the bottom light shielding layer distance.
  • the orthographic projection area of the light shielding layer on the base substrate covers the orthographic projection area of the oxide semiconductor layer on the base substrate.
  • the plurality of thin film transistors include a first thin film transistor, an active layer of the first thin film transistor is the oxide semiconductor layer, and the light shielding pattern is a gate of the first thin film transistor pole, the first thin film transistor is formed in the via hole.
  • the array substrate includes a second insulating layer, the second insulating layer covers the first insulating layer and the light shielding pattern, and the oxide semiconductor layer is disposed on the second insulating layer on the portion within the via;
  • the first thin film transistor includes a first source electrode and a first drain electrode, and the first source electrode and the first drain electrode are disposed on a side of the second insulating layer away from the first insulating layer, and respectively extend into the via holes to be connected with the oxide semiconductor layer.
  • the plurality of thin film transistors further include a plurality of second thin film transistors, and an active layer of the second thin film transistors is a polysilicon semiconductor layer;
  • the first insulating layer includes a first gate insulating layer and an interlayer dielectric layer stacked on the base substrate, and the polysilicon semiconductor layer is disposed on the first gate insulating layer and the base substrate and the gate of the second thin film transistor is disposed between the first gate insulating layer and the interlayer dielectric layer.
  • a plurality of the via holes are formed on the interlayer dielectric layer, the bottoms of the via holes extend toward the base substrate, and the second insulating layer covers the interlayer dielectric layer and the shading pattern.
  • the second thin film transistor includes a second source electrode and a second drain electrode, and the light shielding pattern and the second source electrode and the second drain electrode are made of the same layer of metal material.
  • the second thin film transistor includes a second source electrode and a second drain electrode, and the second source electrode and the second drain electrode are made of the same layer of metal material as the first source electrode. to make.
  • An embodiment of the present application further provides a display panel, the display panel includes an array substrate, the array substrate includes a plurality of thin film transistors distributed in an array, and at least some of the thin film transistors in the plurality of thin film transistors include an oxide semiconductor layer;
  • the array substrate is provided with a plurality of groove-shaped light-shielding patterns, and the oxide semiconductor layer is correspondingly formed in the grooves of the light-shielding patterns.
  • the array substrate includes a base substrate and a first insulating layer disposed on the base substrate, the first insulating layer is provided with a plurality of via holes, and the light shielding pattern is disposed on in the via hole.
  • the light-shielding pattern includes a bottom-surface light-shielding layer and a side-surface light-shielding layer, the bottom-surface light-shielding layer is laid flat on the bottom of the via hole, and the bottom-surface light-shielding layer faces the first insulating layer away from all One side of the base substrate extends to form the side light shielding layer, and the side light shielding layer and the bottom light shielding layer form a certain angle.
  • the angle formed by the side light shielding layer and the bottom light shielding layer is a right angle or an obtuse angle.
  • the degree of the included angle is greater than 90° and less than or equal to 140°.
  • the distance between the top of the side light shielding layer and the bottom light shielding layer is greater than the distance between the side of the oxide semiconductor layer away from the base substrate and the bottom light shielding layer distance.
  • the orthographic projection area of the light shielding layer on the base substrate covers the orthographic projection area of the oxide semiconductor layer on the base substrate.
  • Embodiments of the present application also provide a method for fabricating an array substrate, including:
  • a second insulating layer is formed on a side of the first insulating layer away from the base substrate, and the second insulating layer covers the light shielding pattern;
  • oxide semiconductor layer in the via hole, the oxide semiconductor layer being located in the groove of the light shielding pattern;
  • a source electrode and a drain electrode are formed on the second insulating layer.
  • the embodiments of the present application provide an array substrate, a manufacturing method thereof, and a display panel, wherein the array substrate includes a plurality of thin film transistors distributed in an array, at least some of the thin film transistors in the plurality of thin film transistors Including an oxide semiconductor layer, the array substrate is provided with a plurality of groove-shaped light-shielding patterns, the oxide semiconductor layer is correspondingly formed in the grooves of the light-shielding pattern, and the bottom surface of the groove-shaped light-shielding pattern can be used to block the array substrate.
  • the light irradiated to the bottom of the oxide semiconductor layer from the light incident side of the array substrate can be shielded from the light incident side of the array substrate to the side of the oxide semiconductor layer by using the side of the groove-shaped light-shielding pattern.
  • the area of the orthographic projection area of the groove-shaped shading pattern on the array substrate is smaller, so that the light-transmitting area on the array substrate is smaller.
  • the area of the area is larger, thereby increasing the aperture ratio of the array substrate.
  • FIG. 1 is a schematic diagram of a film layer structure of an array substrate in the prior art
  • FIG. 2 is a schematic plan view of a pixel driving thin film transistor in the prior art
  • FIG. 3 is a schematic plan view of a display panel according to an embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional structure diagram of the first array substrate along the A-A' direction provided by the embodiment of the present application;
  • FIG. 5 is a schematic cross-sectional structure diagram of the second array substrate along the direction A-A' provided by the embodiment of the present application;
  • FIG. 6 is a schematic cross-sectional structure diagram of a third array substrate along the A-A' direction provided by an embodiment of the present application;
  • FIG. 7 is a schematic cross-sectional structure diagram of a fourth array substrate along the A-A' direction provided by an embodiment of the present application.
  • FIG. 8 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of the present application.
  • FIG. 9A to FIG. 9H are schematic structural diagrams of the array substrate provided in the embodiment of the present application in the manufacturing process.
  • Embodiments of the present application provide an array substrate, which will be described in detail below with reference to FIGS. 3 to 7 .
  • FIG. 3 is a schematic plan view of the structure of an array substrate provided by an embodiment of the present application
  • FIG. 4 is a schematic view of a cross-sectional structure of the first array substrate provided by an embodiment of the present application along the A-A' direction.
  • the array substrate includes a plurality of thin film transistors distributed in an array, at least some of the thin film transistors in the plurality of thin film transistors include an oxide semiconductor layer 231, and a plurality of groove-shaped light-shielding patterns 21 are also arranged in the array substrate.
  • the material semiconductor layer 231 is correspondingly formed in the groove body of the light shielding pattern 21 .
  • the array substrate can form a liquid crystal display panel with a liquid crystal layer, a color filter substrate and a backlight module.
  • the backlight module is located on the light incident side of the array substrate, and the oxide semiconductor layer 231 is located on the light-shielding pattern 21 A side away from the light incident side of the array substrate.
  • the bottom and side surfaces of the groove-shaped light-shielding pattern 21 can block the light irradiating to the bottom and side surfaces of the oxide semiconductor layer 231 respectively. light to ensure the electrical properties of the oxide semiconductor layer 231 .
  • the array substrate includes a base substrate 20 and a first insulating layer 22 disposed on the base substrate.
  • the hole V1 the light-shielding pattern 21 is disposed in the via hole V1.
  • the light-shielding pattern 21 includes a bottom light-shielding layer 211 and a side light-shielding layer 212.
  • the bottom light-shielding layer 211 is laid flat on the bottom of the via hole V1, and the bottom light-shielding layer 211 faces the first insulating layer 22 and is far away from all parts.
  • One side of the base substrate 20 extends to form the side light shielding layer 212 , and the side light shielding layer 212 and the bottom light shielding layer 211 form a certain angle.
  • the base substrate 20 includes a laminated substrate 201 and a buffer layer 202, and the substrate 211 is preferably a glass substrate.
  • the array substrate is provided with a plurality of first thin film transistors 23, the active layer of the first thin film transistors 23 is the oxide semiconductor layer 231, and the first thin film transistors 23 are formed in the via hole V1 , the first thin film transistor 23 further includes a first source electrode 232 and a first drain electrode 233 .
  • the light shielding pattern 21 is made of a metal material, the bottom light shielding layer 211 can prevent light from irradiating the oxide semiconductor layer 231 from the bottom surface of the oxide semiconductor layer 231 , and the side light shielding layer 212 can prevent light from passing through the oxide semiconductor layer 231 .
  • the side surface is irradiated to the oxide semiconductor layer 231 .
  • the light shielding pattern 21 can also be used as the gate of the first thin film transistor 23 to form an oxide thin film transistor with a bottom gate structure.
  • the base substrate 20 is further provided with a second insulating layer 223 , the second insulating layer 223 covers the first insulating layer 22 and the light shielding pattern 21 , and the oxide semiconductor layer 231 is located on the second insulating layer 22 .
  • the layer 223 is located on the part of the via hole V1, the first source electrode 232 and the first drain electrode 233 are both disposed on the side of the second insulating layer 223 away from the base substrate 20, and respectively extend into the via hole V1 to connect with the oxide semiconductor layer 231 to form an ohmic contact.
  • the angle formed by the side light shielding layer 212 and the bottom light shielding layer 211 is an obtuse angle. As shown in FIG. 4 , the size of the via hole V1 gradually increases from the side of the side light shielding layer 212 close to the bottom light shielding layer 211 to the side far from the bottom light shielding layer 211 , so as to facilitate the subsequent second insulating layer 223 , oxide semiconductor Formation of the layer 231 , the first source electrode 232 and the first drain electrode 233 .
  • the embodiment adopts the groove-shaped light-shielding pattern 21. Under the circumstance that the area of the light-shielding pattern 21 is increased by the same area as that of the prior art, the area of the orthographic projection area of the light-shielding pattern 21 on the base substrate 20 in this embodiment is smaller. The shielding of the light penetrating the array substrate is less, so that the array substrate has a larger aperture ratio.
  • the angle formed by the side light shielding layer 212 and the bottom light shielding layer 211 ranges from 90° to 140°.
  • the angle formed by the side light shielding layer 212 and the bottom light shielding layer 211 is 110°.
  • other angle designs can be adopted according to requirements, not limited to the above-mentioned 110°, but also 100°, 130° or 140°, etc.
  • the side light shielding layer 212 and the The included angle formed by the bottom light shielding layer 211 may also be a right angle.
  • the distance between the top of the side light shielding layer 212 and the bottom light shielding layer 211 is greater than the side of the oxide semiconductor layer 231 away from the base substrate 20 The distance between the surface and the bottom light shielding layer 211 . It is conceivable that when the height of the side light shielding layer 212 is greater than the height of the bottom light shielding layer 211, even the light irradiated to the oxide semiconductor layer 231 from the horizontal direction can be blocked by the side light shielding layer 212, thereby further improving the light shielding.
  • the top of the side light shielding layer 212 is flush with the surface of the first insulating layer 22 on the side away from the base substrate 20 .
  • the top of the side light shielding layer 212 may also be lower than the surface of the first insulating layer 22 away from the base substrate 20 , or extend to the first insulating layer 22 away from the base substrate On the surface on one side of 20, it can also obtain the same shading effect as the above-mentioned embodiment, which is not limited here.
  • the orthographic projection area of the light shielding pattern 21 on the base substrate 20 covers the orthographic projection area of the oxide semiconductor layer 231 on the base substrate 20 .
  • the oxide semiconductor layer 231 is located on the side of the light shielding pattern 21 away from the base substrate 20 .
  • the orthographic projection area of the light shielding pattern 21 on the base substrate 20 covers the oxide semiconductor layer 231
  • the orthographic projection area on the base substrate 20 is used, the light irradiated by the backlight module to the oxide semiconductor layer 231 through the base substrate 20 can be effectively blocked.
  • FIG. 5 is a schematic cross-sectional structure diagram of the second type of array substrate provided by the embodiment of the present application along the direction A-A'
  • FIG. 6 is the third embodiment of the present application
  • Figure 7 is a schematic cross-sectional structure diagram of a fourth type of array substrate along the A-A' direction according to an embodiment of the present application.
  • the array substrate further includes a plurality of second thin film transistors 24.
  • the active layer of the second thin film transistors 24 is a polysilicon semiconductor layer 241.
  • the first thin film transistor 23 is disposed in the light-transmitting area A1
  • the second thin-film transistor 24 is disposed in the non-light-transmitting area A2.
  • the light-transmitting area A1 of the array substrate corresponds to the display area of the display panel
  • the non-light-transmitting area A2 corresponds to the non-display area of the display panel.
  • the second thin film transistor 24 is used in the gate driver circuit.
  • the second thin film transistor 24 is a low temperature polysilicon thin film transistor, which has the advantages of high carrier mobility, fast charging, fast switching speed and low power consumption, and is applied in the GOA circuit, which can effectively improve the response speed of the GOA circuit, And reduce the power consumption of the array substrate.
  • the first thin film transistor 23 is disposed in the display area A2, and is used in the sub-pixel driving circuit.
  • the first thin film transistor 23 is an oxide thin film transistor, which has the characteristics of good uniformity and low leakage current, which can further reduce the size of the array. Power consumption of the substrate.
  • the first insulating layer 22 includes a first gate insulating layer 221 and an interlayer dielectric layer 222 stacked on the base substrate 20
  • the second thin film transistor 24 further includes a gate electrode 242 .
  • the polysilicon semiconductor layer 241 is disposed between the first gate insulating layer 221 and the base substrate 20
  • the gate 242 is disposed between the first gate insulating layer 221 and the interlayer dielectric layer 222 between.
  • the plurality of via holes V1 are formed on the interlayer dielectric layer 222 , the bottoms of the via holes V1 extend toward the base substrate 20 , and the second insulating layer 223 covers the interlayer dielectric layer 222 and the base substrate 20 . the shading pattern 21 .
  • the interlayer dielectric layer 222 is a laminated structure formed of silicon nitride and silicon oxide materials, wherein the silicon nitride film layer is located between the silicon oxide film layer and the first gate insulating layer 221, and the The silicon nitride film layer contains more hydrogen, and the silicon oxide film layer is used to separate the silicon nitride film layer from the oxide semiconductor layer 231 to prevent Hydrogen diffuses into the oxide semiconductor layer 231 .
  • the bottom light shielding layer 211 of the light shielding pattern 21 is located on a side surface of the base substrate 20 close to the first gate insulating layer 221 , and the side light shielding layer 212 is formed by the bottom surface.
  • the edge of the light shielding layer 211 is formed to extend along the direction from the base substrate 20 to the interlayer dielectric layer 222 .
  • the side surfaces are flush, and the distance between the oxide semiconductor layer 231 and the bottom light shielding layer 211 is smaller than the distance between the top of the side light shielding layer 212 and the bottom light shielding layer 211 .
  • the groove-shaped light-shielding pattern 21 forms a semi-surrounding of the oxide semiconductor layer 231 , and confines the interlayer dielectric layer 222 to the periphery of the light-shielding pattern 21 .
  • the hydrogen in the interlayer dielectric layer 222 is diffused into the oxide semiconductor layer 231 , so as to ensure the electrical properties of the oxide semiconductor layer 231 , thereby improving the stability of the first thin film transistor 23 .
  • the second thin film transistor 24 includes a second source electrode 243 and a second drain electrode 244, and the light shielding pattern 21 and the second source electrode 243 and the second drain electrode 244 are made of the same layer of metal material to make.
  • the second source electrode 243 and the second drain electrode 244 are disposed on the side of the interlayer dielectric layer 222 away from the first gate insulating layer 221 , and the light-shielding pattern 21 is disposed on the in the via hole V1 on the interlayer dielectric layer 222 .
  • an etching process may be performed to simultaneously form a plurality of through the interlayer dielectric layer 222 and the second drain electrode 244 .
  • the vias V1 of the first gate insulating layer 221, the plurality of vias V1 respectively expose the source contact region and the drain contact region of the polysilicon semiconductor layer 241 and the base substrate 20 close to the first gate insulating layer
  • a groove-shaped light shielding pattern 21 may be formed in the via hole V1 exposing the surface of the base substrate 20 .
  • the gate electrode 241 is formed from the first metal layer M1 through a patterning process, and the light-shielding pattern 21 , the second source electrode 243 and the second drain electrode 244 are formed from the second metal layer M2 through a patterning process prepared, the first source electrode 232 and the first drain electrode 233, the touch signal line 234 and the signal line 235 provided in the same layer as the first source electrode 232 are patterned by the third metal layer M3 prepared by chemical process.
  • the second metal layer M2 is a metal stack wiring structure formed of Mo, Al and Ti, and the materials of the first metal layer M1 , the third metal layer M3 and the second metal layer M2 are and the same structure.
  • the second metal layer M2 may also be a metal wiring structure formed by any one of materials such as Mo, Al, and Ti, or the material of the second metal layer M2 may also be Mo, An alloy formed by two or more of Al and Ti.
  • the materials and structures of the first metal layer M1, the second metal layer M2 and the third metal layer M3 may be the same or different.
  • the materials and structures of the first metal layer M1 , the second metal layer M2 and the third metal layer M3 can be set according to actual conditions, which are not limited here.
  • the first source electrode 232 and the first drain electrode 233 , the second source electrode 243 and the second drain electrode 244 are made of the same layer of metal material production.
  • the gate electrode 242 is formed from the first metal layer M1 through a patterning process
  • the light-shielding pattern 21 is formed from the second metal layer M2 through a patterning process
  • the first source electrode 232 and the first source electrode 232 are formed by a patterning process.
  • the drain electrode 233 , the second source electrode 243 , the second drain electrode 244 , and the touch signal line 234 disposed on the same layer as the first source electrode 232 are prepared from the third metal layer M3 by a patterning process .
  • the depth of the via V1 where the light-shielding pattern 21 is located can be set as required.
  • the bottom of the via hole V1 only penetrates through the interlayer dielectric layer 222 and exposes the side surface of the first gate insulating layer 221 away from the base substrate 20, and the bottom light shielding layer 211 is formed on the surface of the first gate insulating layer 221.
  • the first gate insulating layer 221 is on a surface of one side away from the base substrate 20 , and the side light shielding layer 212 extends from the edge of the bottom light shielding layer 211 to the interlayer dielectric layer 222 away from the base substrate 20 . side surface remains flush.
  • the bottom of the via hole V1 where the light shielding pattern 21 is located may penetrate through the interlayer dielectric layer 222 and the first gate insulating layer 221 as shown in FIG.
  • the bottom of the via hole V1 It can also be located in the interlayer dielectric layer 22 without passing through the interlayer dielectric layer 222; or, the bottom of the via hole V1 can also be located in the first gate insulating layer 221 without passing through the interlayer dielectric layer 222.
  • the first gate insulating layer 221 The depth of the via hole V1 where the light-shielding pattern 21 is located can be set according to actual requirements, which is not limited here.
  • the light-shielding pattern 21 and the second source electrode 243 are made of different layers of metal materials, and the second source electrode 243 and the first source electrode 232 are made of different layers. Layered metal material.
  • the gate electrode 242 is prepared from the first metal layer M1 through a patterning process, and the second source electrode 243 and the second drain electrode 244 are prepared from the second metal layer M2 through a patterning process .
  • the array substrate further includes a third insulating layer 225, the third insulating layer 225 is located on the side of the second insulating layer 223 away from the base substrate 20, a second source electrode 243 and a second drain electrode 244
  • the via hole V1 is formed on the second insulating layer 223 , and the first source electrode 232 and the first drain electrode 233 are arranged on the third insulating layer 225 .
  • a plurality of vias V1 are formed by etching the second insulating layer 223, and then a third metal layer M3 is deposited on the second insulating layer 223, and then a third metal layer M3 is deposited on the second insulating layer 223.
  • the light shielding pattern 21 is formed through a patterning process.
  • the first source electrode 232, the first drain electrode 233 and the touch signal line 234 disposed in the same layer as the first source electrode 232 are prepared by a patterning process of the fourth metal layer M4.
  • the fourth metal layer M4 Formed on the side of the third insulating layer 225 away from the base substrate 20 , the material and structure of the fourth metal layer M4 may be the same as those of the above-mentioned metal layer, which will not be repeated here.
  • the array substrate further includes a passivation protection layer 224 , a flat layer 25 , and a touch electrode stacked on the second insulating layer 223 or the third insulating layer 225 .
  • layer 26 , the second passivation protection layer 27 and the pixel electrode layer 28 , the touch electrodes in the touch electrode layer 26 are connected to the touch signal lines 235 through vias, the sub-layers in the pixel electrode layer 28 are The pixel electrode is connected to the first drain electrode 233 of the first thin film transistor 23 through a via hole.
  • the material of the oxide semiconductor layer 231 is preferably IGZO.
  • the material of the oxide semiconductor layer 231 may also include, but not limited to, oxide semiconductor materials such as indium gallium oxide or indium zinc oxide, and the specific material may be selected according to actual needs. No restrictions.
  • an embodiment of the present application provides an array substrate, the array substrate includes a plurality of thin film transistors distributed in an array, at least some of the thin film transistors in the plurality of thin film transistors include an oxide semiconductor layer, and the array substrate There are a plurality of groove-shaped light-shielding patterns, and the oxide semiconductor layer is correspondingly formed in the grooves of the light-shielding patterns.
  • the bottom surface of the groove-shaped light-shielding patterns can block the light-incident side of the array substrate from irradiating the oxide semiconductor layer.
  • the light at the bottom can be shielded from the light irradiated from the light incident side of the array substrate to the side of the oxide semiconductor layer by using the side of the groove-shaped light-shielding pattern, so that the light-shielding effect of the light-shielding pattern can be improved by setting the light-shielding pattern as a groove.
  • the area of the orthographic projection area of the grooved shading pattern on the array substrate is smaller, so that the area of the light-transmitting area on the array substrate is larger, thereby improving the array substrate. opening rate.
  • An embodiment of the present application further provides a display panel, the display panel includes an array substrate, a color filter substrate, a liquid crystal layer and a backlight module, the array substrate is disposed opposite the color filter substrate, and the liquid crystal layer is disposed on the Between the array substrate and the color filter substrate, the backlight module is disposed on the light incident side of the array substrate.
  • the array substrate in the embodiment of the present application may be the array substrate provided in the above embodiment, and the array substrate is applied to the display panel provided in the embodiment of the present application, and can implement the same technology as the array substrate provided in the above embodiment. The effect will not be repeated here.
  • Embodiments of the present application further provide a method for fabricating an array substrate, which is described in detail below with reference to FIGS. 8 to 9H .
  • FIG. 8 is a schematic flowchart of a method for fabricating an array substrate provided by an embodiment of the present application
  • FIGS. 9A to 9H are A schematic diagram of the structure of the array substrate in the manufacturing process provided by the application embodiment, the manufacturing method of the array substrate includes:
  • Step S10 providing a base substrate 30 on which a first insulating layer 32 is formed.
  • the base substrate 30 is composed of a substrate 301 and a buffer layer 302 arranged in layers, and the substrate 301 is preferably a glass substrate.
  • the first insulating layer 32 includes a first gate insulating layer 321 and an interlayer dielectric layer 322 stacked on the base substrate 30.
  • the step S10 includes:
  • Step S101 providing a base substrate 30 , and forming a polysilicon semiconductor layer 341 on the base substrate 30 ;
  • Step S102 forming a first gate insulating layer 321 on the base substrate 30 , the first gate insulating layer 321 covering the polysilicon semiconductor layer 341 ;
  • Step S103 depositing a first metal layer M1 on the side of the first gate insulating layer 321 away from the base substrate 30 , and performing a patterning process on the first metal layer M1 to form a gate 342 ;
  • Step S104 forming an interlayer dielectric layer 322 on the side of the first gate insulating layer 321 away from the base substrate 30 , and the interlayer dielectric layer 322 covers the gate electrode 342 .
  • the polysilicon semiconductor layer 341 and the gate electrode 342 are both formed in the non-transmissive area A2 of the array substrate, and the non-transparent area A2 of the array substrate corresponds to the non-display area of the display panel.
  • the first metal layer M1 is a metal stack wiring structure formed of Mo, Al and Ti.
  • the first metal layer M1 may also be a metal wiring structure formed by any one of materials such as Mo, Al, and Ti, or the material of the first metal layer M1 may also be Mo, An alloy formed by two or more of Al and Ti.
  • the material and structure of the first metal layer M1 can be set according to actual conditions, which are not limited here.
  • Step S20 forming a plurality of via holes on the first insulating layer 32 .
  • the plurality of via holes include a first via hole V1 and a second via hole V2 , and the first via hole V1 and the second via hole V2 can be formed simultaneously by using the same etching process.
  • the first via V1 penetrates through the interlayer dielectric layer 322 and the first gate insulating layer 321 , and exposes a side surface of the base substrate 30 close to the first gate insulating layer 321 .
  • the second via hole V2 exposes the source contact region and the drain contact region of the polysilicon semiconductor layer 341 .
  • the bottom of the first via hole V1 may only penetrate the interlayer dielectric layer 322; or, the bottom of the first via hole V1 may extend into the interlayer dielectric layer 322 without Through the interlayer dielectric layer 322; or, the bottom of the first via hole V1 may extend into the first gate insulating layer 321, only through the interlayer dielectric layer 322, but not through all The first gate insulating layer 321 is described.
  • Step S30 forming a plurality of groove-shaped light-shielding patterns 31 in the via hole;
  • the step S30 includes:
  • Step S301 depositing a second metal layer M2 on a surface of the first gate insulating layer 321 away from the base substrate 30 , in the first via hole V1 and the first via hole V2 ;
  • Step S302 performing a patterning process on the second metal layer M2 to form a second source electrode 343 , a second drain electrode 344 and a groove-shaped light shielding pattern 31 .
  • the light shielding pattern 31 includes a bottom light shielding layer 311 and a side light shielding layer 312 .
  • the side light shielding layer 312 extends from the edge of the bottom light shielding layer 311 to a distance from the interlayer dielectric layer 322 away from the base substrate 30 .
  • the side surfaces are flush to confine the interlayer dielectric layer 322 to the periphery of the groove-shaped light-shielding pattern 31 .
  • the second source electrode 343, the second drain electrode 344, the gate electrode 342 and the polysilicon semiconductor layer 341 constitute a second thin film transistor 34, and the second thin film transistor 34 is a low temperature polysilicon thin film transistor with a carrier.
  • the advantages of high carrier mobility, fast charging, fast switching and low power consumption can be applied to the GOA circuit in the non-transmissive area A2, which can effectively improve the response speed of the GOA circuit and reduce the power consumption of the array substrate.
  • the second metal layer M2 is a metal stack wiring structure formed of Mo, Al and Ti.
  • the second metal layer M2 may also be a metal wiring structure formed by any one of materials such as Mo, Al, and Ti, or the material of the second metal layer M2 may also be Mo, An alloy formed by two or more of Al and Ti.
  • the material and structure of the second metal layer M2 can be set according to actual conditions, which are not limited here.
  • Step S40 forming a second insulating layer 323 on the side of the first insulating layer 32 away from the base substrate 30 , the second insulating layer 323 covering the light shielding pattern 31 .
  • the second insulating layer 323 may be formed by a vapor deposition method, and the material of the second insulating layer 323 is an inorganic material, preferably a silicon oxide material.
  • the portion of the second insulating layer 323 covering the light-shielding pattern 31 is also recessed into the first via hole V1 , so that the height of the portion of the second insulating layer 323 covering the light-shielding pattern 31 is lower than that of other portions.
  • the step S40 further includes: forming a plurality of third via holes V3 on the second insulating layer 323 through an etching process, the third via holes V3 exposing the second drain electrode 344 .
  • Step S50 forming an oxide semiconductor layer 331 in the via hole, and the oxide semiconductor layer 331 is located in the groove body of the light shielding pattern 31 .
  • step S50 The steps of step S50 include:
  • Step S501 depositing a layer of metal oxide material on the side of the second insulating layer 323 away from the base substrate 30;
  • Step S502 performing a patterning process on the metal oxide material to form an oxide semiconductor layer 331 .
  • the oxide semiconductor layer 331 is located in the first via hole V1 , and the oxide semiconductor layer 331 is located between a side surface of the oxide semiconductor layer 331 away from the base substrate 30 and the bottom light shielding layer 311 .
  • the distance between the top of the side light shielding layer 312 and the bottom light shielding layer 311 is smaller than the distance between the top of the side light shielding layer 312 and the bottom light shielding layer 311 , so that the oxide semiconductor layer 331 is semi-enclosed by the groove-shaped light shielding pattern 31 to form an interlayer dielectric.
  • the layer 322 is separated from the oxide semiconductor layer 331 to prevent the hydrogen in the interlayer dielectric layer 322 from diffusing into the oxide semiconductor layer 331, and also to prevent light from irradiating the oxide semiconductor layer 331 from the bottom and sides of the oxide semiconductor layer 331 to the oxide semiconductor layer 331. in the semiconductor layer 331 .
  • the material of the oxide semiconductor layer 331 is IGZO.
  • the material of the oxide semiconductor layer 331 may also include, but not limited to, oxide semiconductor materials such as indium gallium oxide or indium zinc oxide, and the specific material may be selected according to actual requirements. No restrictions.
  • Step 60 forming a source electrode and a drain electrode on the second insulating layer 323 .
  • the source electrode and the drain electrode in step S50 are the first source electrode 332 and the first drain electrode 333 in FIG. 9E , respectively.
  • the step S50 includes:
  • Step S501 depositing a third metal layer M3 on the side of the second insulating layer 323 away from the base substrate 30 and in the third via hole V3;
  • Step S502 performing a patterning process on the third metal layer M3 to form a first source electrode 332 , a first drain electrode 333 , a touch signal line 334 and a signal line 335 .
  • the first source electrode 332 and the first drain electrode 333 , the oxide semiconductor layer 331 and the light shielding pattern 31 constitute a first thin film transistor 33
  • the light shielding pattern 31 serves as the first thin film transistor 33 .
  • the gate of the thin film transistor 33 is located in the light-transmitting area of the array substrate, and is applied to the sub-pixel driving circuit in the light-transmitting area.
  • the first thin film transistor 33 is an oxide thin film transistor, which has good uniformity and low leakage current. The low characteristic can further reduce the power consumption of the array substrate.
  • the material and structure of the third metal layer M3 and the second metal layer M2 are the same.
  • the third metal layer M3 may also be a metal wiring structure formed by any one of materials such as Mo, Al, and Ti, or the material of the third metal layer M3 may also be Mo, An alloy formed by two or more of Al and Ti.
  • the material and structure of the third metal layer M3 can be set according to the actual situation, which is not limited here.
  • Step S70 forming a first passivation protection layer 324 on the side of the second insulating layer 323 away from the base substrate 30 , and forming a plurality of first passivation protection layers 324 on the first passivation protection layer 324 through an etching process.
  • There are four via holes V4 and a fifth via hole V5 the plurality of fourth via holes V4 expose the touch signal lines 335 , and the plurality of fifth via holes V5 expose the first drain electrode 333 .
  • the first passivation protection layer 324 is formed on the side of the second insulating layer 323 away from the base substrate 30 and covers the touch signal lines 334 and signal traces 335 , a first source electrode 332 , a first drain electrode 333 and the oxide semiconductor layer 331 .
  • the thickness of the first passivation protection layer 324 should be 600 nm.
  • the thickness of the first passivation protection layer 324 may also be 300 nm, 500 nm, 800 nm, or 100 nm.
  • the thickness of the first passivation protection layer 324 can be set according to the actual situation, which is not limited here.
  • Step S80 forming a flat layer 35 on the side of the first passivation protection layer 324 away from the base substrate 30 , and forming a plurality of sixth vias V6 and a plurality of sixth vias V6 and a plurality of sixth vias V6 on the flat layer 35 through an etching process.
  • a seventh via hole V7 , the plurality of sixth via holes V6 expose the touch signal line 334 , and the seventh via hole V7 exposes the first drain electrode 333 .
  • the fourth via V4 communicates with the sixth via V6
  • the fifth via V5 communicates with the seventh via V7 .
  • the material of the flat layer 35 is a common photoresist material, and the first via hole V1 can be filled with its fluidity before being cured.
  • Step S90 forming a touch electrode layer 36 on the side of the flat layer 35 away from the base substrate 30 ; forming a second passivation protection layer on the side of the flat layer away from the base substrate 30 37. Form a plurality of eighth vias V8 on the second passivation protection layer 37 through an etching process; form pixel electrodes on the side of the second passivation protection layer 37 away from the base substrate 30 Layer 38.
  • the touch electrode layer 36 includes a plurality of touch electrodes, and the touch electrodes communicate with the touch signal through the sixth via V6 and the fourth via V4 Line 335 connects.
  • the eighth via hole V8 exposes the first drain electrode 334 , the pixel electrode layer 38 includes a plurality of sub-pixel electrodes, the sub-pixel electrodes pass through the eighth via hole V8 and the first drain electrode 334 connect.
  • the materials of the pixel electrode layer 38 and the touch electrode layer 36 are both ITO. In some other embodiments, the material of the pixel electrode layer 38 and the touch electrode layer 36 may also be other transparent metal oxide materials. The materials of the pixel electrode layer 38 and the touch electrode layer 36 may be the same or different. The materials of the pixel electrode layer 38 and the touch electrode layer 36 can be set according to actual conditions, and are not limited here.
  • an embodiment of the present application provides a method for fabricating an array substrate.
  • the fabricating method includes forming a plurality of via holes on a first insulating layer, forming a groove-shaped light-shielding pattern in the via holes, and forming oxide
  • the semiconductor layer is formed in the groove of the light-shielding pattern, and the bottom surface of the groove-shaped light-shielding pattern can block the light irradiated from the light-incident side of the array substrate to the bottom of the oxide semiconductor layer, and the side of the groove-shaped light-shielding pattern can block the light entering by the array substrate.
  • the light from the light side irradiates the side surface of the oxide semiconductor layer, so that the shading effect of the shading pattern is improved by setting the shading pattern as a groove.
  • the shading effect of the groove is The area of the orthographic projection area of the pattern on the array substrate is smaller, so that the area of the light-transmitting area on the array substrate is larger, thereby increasing the aperture ratio of the array substrate.
  • the semiconductor layers are separated to prevent hydrogen in the interlayer dielectric layer from diffusing into the oxide semiconductor layer, thereby ensuring the electrical properties of the oxide semiconductor layer.

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Abstract

本申请提供一种阵列基板及显示面板，该阵列基板内设有多个槽型的遮光图案，氧化物半导体层对应形成于遮光图案的槽体内，相较于通过增大平面面积来改善遮光图案的遮光效果，槽型的遮光图案在阵列基板上的正投影区域的面积更小，使得阵列基板上可透光的区域的面积更大，从而提高阵列基板的开口率。

Description

阵列基板及显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及显示面板。
 背景技术
随着可穿戴设备技术的发展以及在目前电池领域技术未得到显著突破的背景下，人们对于显示设备的功耗要求越来越高。目前用于驱动薄膜晶体管和开关薄膜晶体管的低温多晶硅（low temperature poly-silicon, LTPS）技术由于其功耗较低的特点，仍为主流技术趋势。但是由于LTPS载流子迁移率较大，存在漏电流较高的问题，因此低温多晶氧化物（low temperature polycrystalline-si oxide, LTPO）技术应运而生，其结合了LTPS和氧化物两者的优点，可在提升显示设备响应速度的同时，降低显示设备的功耗。
 技术问题
如图1所示，图1为现有技术中采用低温多晶氧化物技术的阵列基板的膜层结构示意图，该阵列基板包括依次层叠设置的基底101、缓冲层102、第一栅极绝缘层103、层间介质层104、第二栅极绝缘层105、钝化保护层106和平坦层107，该阵列基板内还设有多个栅极驱动薄膜晶体管11和像素驱动薄膜晶体管12，栅极驱动薄膜晶体管11和像素驱动薄膜晶体管12的半导体层分别为多晶硅半导体层111和氧化物半导体层121。由于氧化物半导体层121对光和氢比较敏感，对于底栅结构的像素驱动薄膜晶体管12，需要通过增大位于氧化物半导体层121底部的第一栅极122的面积来提升遮光的效果。如图2所示，图2为现有技术中像素驱动薄膜晶体管12的平面结构示意图，第一栅极122与扫描线14位于同一层，第一源极123和第一漏极124与数据线15位于同一层，为获得较好的遮光效果，第一栅极122需要超出氧化物半导体层121的边缘至少3μm，但这样会导致阵列基板的开口率降低。另一方面，栅极驱动薄膜晶体管11的第二栅极112与第二源极113和第二漏极114之间需要通过层间介质层115绝缘隔开，层间介质层115中含氢量较高，在制备氧化物半导体层121时，层间介质层115中的氢会扩散至氧化物半导体层121中，造成氧化物半导体层121的电性异常，导致像素驱动薄膜晶体管12的稳定性降低。
综上，现有阵列基板存在通过增大栅极的面积来改善遮光效果导致的开口率降低的问题。故，有必要提供一种阵列基板及显示面板来改善这一缺陷。
 技术解决方案
本申请实施例提供一种阵列基板及其制作方法、显示面板，用于解决现有阵列基板存在通过增大栅极的面积来改善遮光效果导致的开口率降低的问题。
本申请实施例提供一种阵列基板，所述阵列基板包括阵列分布的多个薄膜晶体管，所述多个薄膜晶体管中的至少部分薄膜晶体管包括氧化物半导体层；
其中，所述阵列基板内设有多个槽型的遮光图案，所述氧化物半导体层对应形成于所述遮光图案的槽体内。
根据本申请一实施例，所述阵列基板包括衬底基板和设置于所述衬底基板上的第一绝缘层，所述第一绝缘层上设有多个过孔，所述遮光图案设置于所述过孔内。
根据本申请一实施例，所述遮光图案包括底面遮光层和侧面遮光层，所述底面遮光层平铺设置于所述过孔的底部，所述底面遮光层朝向所述第一绝缘层远离所述衬底基板的一侧延伸形成所述侧面遮光层，所述侧面遮光层与所述底面遮光层形成一定夹角。
根据本申请一实施例，所述侧面遮光层与所述底面遮光层形成的夹角为直角或钝角。
根据本申请一实施例，所述夹角的度数大于90°，小于或等于140°。
根据本申请一实施例，所述侧面遮光层的顶部与所述底面遮光层之间的距离，大于所述氧化物半导体层远离所述衬底基板的一侧与所述底面遮光层之间的距离。
根据本申请一实施例，所述遮光层在所述衬底基板上的正投影区域覆盖所述氧化物半导体层在所述衬底基板上的正投影区域。
根据本申请一实施例，所述多个薄膜晶体管包括第一薄膜晶体管，所述第一薄膜晶体管的有源层为所述氧化物半导体层，所述遮光图案为所述第一薄膜晶体管的栅极，所述第一薄膜晶体管形成于所述过孔内。根据本申请一实施例，所述阵列基板包括第二绝缘层，所述第二绝缘层覆盖所述第一绝缘层和所述遮光图案，所述氧化物半导体层设置于所述第二绝缘层位于所述过孔内的部分上；
所述第一薄膜晶体管包括第一源极和第一漏极，所述第一源极和所述第一漏极设置于所述第二绝缘层远离所述第一绝缘层的一侧上，并分别延伸至所述过孔内与所述氧化物半导体层连接。
根据本申请一实施例，所述多个薄膜晶体管还包括多个第二薄膜晶体管，所述第二薄膜晶体管的有源层为多晶硅半导体层；
所述第一绝缘层包括层叠设置于所述衬底基板上的第一栅极绝缘层和层间介质层，所述多晶硅半导体层设置于所述第一栅极绝缘层与所述衬底基板之间，所述第二薄膜晶体管的栅极设置于所述第一栅极绝缘层与所述层间介质层之间。
根据本申请一实施例，多个所述过孔形成于所述层间介质层上，所述过孔的底部朝向所述衬底基板延伸，所述第二绝缘层覆盖所述层间介质层和所述遮光图案。
根据本申请一实施例，所述第二薄膜晶体管包括第二源极和第二漏极，所述遮光图案与所述第二源极和所述第二漏极由同层金属材料制成。
根据本申请一实施例，所述第二薄膜晶体管包括第二源极和第二漏极，所述第二源极和所述第二漏极与所述第一源极由同层金属材料制成。
本申请实施例还提供一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括阵列分布的多个薄膜晶体管，所述多个薄膜晶体管中的至少部分薄膜晶体管包括氧化物半导体层；
其中，所述阵列基板内设有多个槽型的遮光图案，所述氧化物半导体层对应形成于所述遮光图案的槽体内。
根据本申请一实施例，所述阵列基板包括衬底基板和设置于所述衬底基板上的第一绝缘层，所述第一绝缘层上设有多个过孔，所述遮光图案设置于所述过孔内。
根据本申请一实施例，所述遮光图案包括底面遮光层和侧面遮光层，所述底面遮光层平铺设置于所述过孔的底部，所述底面遮光层朝向所述第一绝缘层远离所述衬底基板的一侧延伸形成所述侧面遮光层，所述侧面遮光层与所述底面遮光层形成一定夹角。
根据本申请一实施例，所述侧面遮光层与所述底面遮光层形成的夹角为直角或钝角。
根据本申请一实施例，所述夹角的度数大于90°，小于或等于140°。
根据本申请一实施例，所述侧面遮光层的顶部与所述底面遮光层之间的距离，大于所述氧化物半导体层远离所述衬底基板的一侧与所述底面遮光层之间的距离。
根据本申请一实施例，所述遮光层在所述衬底基板上的正投影区域覆盖所述氧化物半导体层在所述衬底基板上的正投影区域。
本申请实施例还提供一种阵列基板的制作方法，包括：
提供衬底基板，在所述衬底基板上形成第一绝缘层；
在所述第一绝缘层上形成多个过孔；
在所述过孔内形成多个槽型的遮光图案；
在所述第一绝缘层远离所述衬底基板的一侧形成第二绝缘层，所述第二绝缘层覆盖所述遮光图案；
在所述过孔内形成氧化物半导体层，所述氧化物半导体层位于所述遮光图案的槽体内；以及
在所述第二绝缘层上形成源极和漏极。
 有益效果
本揭示实施例的有益效果：本申请实施例提供一种阵列基板及其制作方法、显示面板，所述阵列基板包括阵列分布的多个薄膜晶体管，所述多个薄膜晶体管中的至少部分薄膜晶体管包括氧化物半导体层，所述阵列基板内设有多个槽型的遮光图案，所述氧化物半导体层对应形成于所述遮光图案的槽体内，利用槽型遮光图案的底面可以遮挡由阵列基板的入光侧照射至氧化物半导体层底部的光线，利用槽型遮光图案的侧面可以遮挡由阵列基板的入光侧照射至氧化物半导体层侧面的光线，以此通过将遮光图案设置为槽型来改善遮光图案的遮光效果，相较于通过增大平面面积来改善遮光图案的遮光效果，槽型的遮光图案在阵列基板上的正投影区域的面积更小，使得阵列基板上可透光的区域的面积更大，从而提高阵列基板的开口率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术的阵列基板的膜层结构示意图；
图2为现有技术的像素驱动薄膜晶体管的平面结构示意图；
图3为本申请实施例提供的显示面板的平面结构示意图；
图4为本申请实施例提供的第一种阵列基板沿A-A`方向的截面结构示意图；
图5为本申请实施例提供的第二种阵列基板沿A-A`方向的截面结构示意图；
图6为本申请实施例提供的第三种阵列基板沿A-A`方向的截面结构示意图；
图7为本申请实施例提供的第四种阵列基板沿A-A`方向的截面结构示意图；
图8为本申请实施例提供的阵列基板的制作方法的流程示意图；
图9A至图9H为本申请实施例提供的阵列基板在制作过程中的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本揭示可用以实施的特定实施例。本揭示所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本揭示做进一步的说明：
本申请实施例提供一种阵列基板，下面结合图3至图7进行详细说明。
如图3和图4所示，图3为本申请实施例提供的阵列基板的平面结构示意图，图4为本申请实施例提供的第一种阵列基板沿A-A`方向的截面结构示意图，所述阵列基板包括阵列分布的多个薄膜晶体管，所述多个薄膜晶体管中的至少部分薄膜晶体管包括氧化物半导体层231，所述阵列基板内还设有多个槽型的遮光图案21，所述氧化物半导体层231对应形成于所述遮光图案21的槽体内。
需要说明的是，所述阵列基板可以与液晶层、彩膜基板以及背光模组构成液晶显示面板，背光模组位于阵列基板的入光侧，所述氧化物半导体层231位于所述遮光图案21远离所述阵列基板的入光侧的一侧。当背光模组发出的光线通过阵列基板的入光侧进入至所述阵列基板的内部时，槽型的遮光图案21的底部和侧面可分别阻挡照射至所述氧化物半导体层231底部和侧面的光线，以此保证所述氧化物半导体层231的电学性能。
在一实施例中，如图4所示，所述阵列基板包括衬底基板20和设置于所述衬底基板上的第一绝缘层22，所述第一绝缘层22上设有多个过孔V1，所述遮光图案21设置于所述过孔V1内。
所述遮光图案21包括底面遮光层211和侧面遮光层212，所述底面遮光层211平铺设置于所述过孔V1的底部，所述底面遮光层211朝向所述第一绝缘层22远离所述衬底基板20的一侧延伸形成所述侧面遮光层212，所述侧面遮光层212与所述底面遮光层211形成一定夹角。
具体地，所述衬底基板20包括层叠设置的基板201和缓冲层202组成，所述基板211优选为玻璃基板。所述阵列基板内设有多个第一薄膜晶体管23，所述第一薄膜晶体管23的有源层为所述氧化物半导体层231，所述第一薄膜晶体管23形成于所述过孔V1内，所述第一薄膜晶体管23还包括第一源极232和第一漏极233。所述遮光图案21由金属材料制成，底面遮光层211可以防止光线从氧化物半导体层231的底面照射至所述氧化物半导体层231，侧面遮光层212可以防止光线从氧化物半导体层231的侧面照射至所述氧化物半导体层231。此外，所述遮光图案21还可以作为所述第一薄膜晶体管23的栅极，以形成底栅结构的氧化物薄膜晶体管。所述衬底基板20上还设有第二绝缘层223，所述第二绝缘层223覆盖所述第一绝缘层22所述遮光图案21，所述氧化物半导体层231位于所述第二绝缘层223位于所述过孔V1内的部分上，所述第一源极232和所述第一漏极233均设置于所述第二绝缘层223远离所述衬底基板20的一侧上，并分别延伸至所述过孔V1内与所述氧化物半导体层231连接，形成欧姆接触。
所述侧面遮光层212与所述底面遮光层211形成的夹角为钝角。如图4所示，过孔V1的尺寸由侧面遮光层212靠近底面遮光层211的一侧至远离底面遮光层211的一侧逐渐增大，以此便于后续第二绝缘层223、氧化物半导体层231、第一源极232以及第一漏极233的形成。本实施例通过增设向外侧倾斜的侧面遮光层212，不仅可以改善遮光图案21对氧化物半导体层231的遮光效果，相较于现有技术通过增大遮光图案的平面面积来改善遮光效果，本实施例采用槽型的遮光图案21，在与现有技术遮光图案增大相同面积的情况下，本实施例中的遮光图案21在衬底基板20上的正投影区域的面积更小，对于需要穿透阵列基板的光线的遮挡就更少，使得阵列基板具有更大的开口率。
所述侧面遮光层212与所述底面遮光层211形成的夹角的度数范围为90°~140°。
具体地，在本申请实施例中，所述侧面遮光层212与所述底面遮光层211形成的夹角的度数为110°。在实际应用中，可以根据需求采用其他的角度设计，而不限于上述的110°，也可以是100°、130°或者140°等，除上述的钝角以外，所述侧面遮光层212与所述底面遮光层211形成的夹角还可以为直角。
在一实施例中，如图4所示，所述侧面遮光层212的顶部与所述底面遮光层211之间的距离，大于所述氧化物半导体层231远离所述衬底基板20的一侧表面与所述底面遮光层211之间的距离。可以想到的是，当侧面遮光层212的高度要大于底面遮光层211的高度时，即使是从水平方向照射至氧化物半导体层231的光线也可以被侧面遮光层212所阻挡，从而进一步提高遮光图案21的遮光效果。在本实施例中，所述侧面遮光层212的顶部与所述第一绝缘层22远离所述衬底基板20的一侧表面齐平。在其他一些实施例中，侧面遮光层212的顶部也可以低于第一绝缘层22远离所述衬底基板20的一侧表面，或者延伸至所述第一绝缘层22远离所述衬底基板20一侧的表面上，其同样也可以获得与上述实施例相同的遮光效果，此处不做限制。
进一步的，所述遮光图案21在所述衬底基板20上的正投影区域覆盖所述氧化物半导体层231在所述衬底基板20上的正投影区域。可以理解的是，氧化物半导体层231位于所述遮光图案21远离衬底基板20的一侧，当所述遮光图案21在衬底基板20上的正投影区域覆盖所述氧化物半导体层231在所述衬底基板20上的正投影区域时，可以有效遮挡背光模组通过衬底基板20照射至氧化物半导体层231的光线。
在一实施例中，如图3至图7所示，其中图5为本申请实施例提供的第二种阵列基板沿A-A`方向的截面结构示意图，图6为本申请实施例提供的第三种阵列基板沿A-A`方向的截面结构示意图，图7为本申请实施例提供的第四种阵列基板沿A-A`方向的截面结构示意图。所述阵列基板还包括多个第二薄膜晶体管24，所述第二薄膜晶体管24的有源层为多晶硅半导体层241，所述阵列基板包括透光区A1和围绕所述透光区A1的非透光区A2，所述第一薄膜晶体管23设置于所述透光区A1内，所述第二薄膜晶体管24设置于所述非透光区A2内。
需要说明的是，所述阵列基板的透光区A1对应显示面板的显示区，非透光区A2对应显示面板的非显示区，位于所述显示区A1的至少一侧非显示区A2内设有栅极驱动电路（gate driver on array, GOA），所述第二薄膜晶体管24应用于所述栅极驱动电路中。所述第二薄膜晶体管24为低温多晶硅薄膜晶体管，具有载流子迁移率高、充电快、开关速度快以及功耗较低的优点，应用于GOA电路中，可以有效提高GOA电路的响应速度，并降低阵列基板的功耗。第一薄膜晶体管23设置于显示区A2内，并被应用于子像素驱动电路中，第一薄膜晶体管23为氧化物薄膜晶体管，具有良好的均一性以及漏电流较低的特点，可进一步降低阵列基板的功耗。
进一步的，所述第一绝缘层22包括层叠设置于所述衬底基板20上的第一栅极绝缘层221和层间介质层222，所述第二薄膜晶体管24还包括栅极242，所述多晶硅半导体层241设置于所述第一栅极绝缘层221与所述衬底基板20之间，所述栅极242设置于所述第一栅极绝缘层221与所述层间介质层222之间。
所述多个过孔V1形成于所述层间介质层222上，所述过孔V1的底部朝向所述衬底基板20延伸，所述第二绝缘层223覆盖所述层间介质层222和所述遮光图案21。
具体地，所述层间介质层222为氮化硅和氧化硅材料形成的叠层结构，其中氮化硅膜层位于氧化硅膜层与所述第一栅极绝缘层221之间，所述氮化硅膜层中含有较多的氢，所述氧化硅膜层则用于将所述氮化硅膜层与所述氧化物半导体层231隔开，防止所述氮化硅膜层中的氢扩散至所述氧化物半导体层231中。
在一实施例中，如图5所示，所述遮光图案21的底面遮光层211位于衬底基板20靠近所述第一栅极绝缘层221的一侧表面，侧面遮光层212由所述底面遮光层211的边缘沿所述衬底基板20至所述层间介质层222的方向延伸形成，所述侧面遮光层212的顶部与所述层间介质层222远离所述衬底基板20的一侧表面齐平，所述氧化物半导体层231与所述底面遮光层211之间的距离小于所述侧面遮光层212的顶部与所述底面遮光层211之间的距离。槽型的遮光图案21对所述氧化物半导体层231构成半包围，将所述层间介质层222限制在所述遮光图案21的外围，在形成所述氧化物半导体层231时，可以避免所述层间介质层222中的氢扩散至所述氧化物半导体层231，以此保证氧化物半导体层231的电学性能，从而提高第一薄膜晶体管23的稳定性。
进一步的，所述第二薄膜晶体管24包括第二源极243和第二漏极244，所述遮光图案21与所述第二源极243和所述第二漏极244由同层金属材料制成。
如图5所示，所述第二源极243和所述第二漏极244设置于层间介质层222远离第一栅极绝缘层221的一侧上，遮光图案21设置在形成于所述层间介质层222上的过孔V1内。
可以理解的是，在形成所述遮光图案21、所述第二源极243和第二漏极244之前，可以通过一次刻蚀制程，同时形成多个贯穿所述层间介质层222和所述第一栅极绝缘层221的过孔V1，该多个过孔V1分别暴露出所述多晶硅半导体层241的源极接触区域和漏极接触区域以及衬底基板20靠近所述第一栅极绝缘层221的一侧表面，槽型的遮光图案21可在暴露出衬底基板20表面的过孔V1内形成。所述栅极241由第一金属层M1通过图案化工艺制备而成，所述遮光图案21与所述第二源极243、所述第二漏极244由第二金属层M2通过图案化工艺制备而成，所述第一源极232与所述第一漏极233、与所述第一源极232同层设置的触控信号线234以及信号走线235由第三金属层M3通过图案化工艺制备而成。
具体地，所述第二金属层M2为Mo、Al和Ti形成的金属叠层走线结构，所述第一金属层M1、所述第三金属层M3与所述第二金属层M2的材料以及结构相同。在其他一些实施例中，所述第二金属层M2还可以为Mo、Al和Ti等材料中的任意一种所形成的金属走线结构，或者第二金属层M2的材料也可以为Mo、Al和Ti中两种或两种以上材料所形成的合金。所述第一金属层M1与所述第二金属层M2和所述第三金属层M3的材料以及结构可以相同，也可以不同。所述第一金属层M1与所述第二金属层M2和所述第三金属层M3的材料以及结构可以根据实际情况进行设定，此处不做限制。
在一实施例中，所述如图6所示，所述第一源极232与所述第一漏极233、所述第二源极243和所述第二漏极244由同层金属材料制成。所述栅极242由第一金属层M1通过图案化工艺制备而成，所述遮光图案21由第二金属层M2通过图案化工艺制备而成，所述第一源极232与所述第一漏极233、所述第二源极243、所述第二漏极244、与所述第一源极232同层设置的触控信号线234由第三金属层M3通过图案化工艺制备而成。
需要说明的是，由于遮光图案21与所述第二源极243和所述第二漏极244由不同层金属材料制备而成，遮光图案21所在的过孔V1的深度则可以根据需求进行设定。如图6所示，过孔V1的底部仅贯穿所述层间介质层222，并暴露出第一栅极绝缘层221远离所述衬底基板20的一侧表面，底面遮光层211形成于所述第一栅极绝缘层221远离所述衬底基板20的一侧表面，侧面遮光层212由所述底面遮光层211的边缘延伸至与所述层间介质层222远离所述衬底基板20的一侧表面保持齐平。在其他一些实施例中，遮光图案21所在的过孔V1的底部可以如图4所示，贯穿所述层间介质层222和所述第一栅极绝缘层221；或者，过孔V1的底部还可以位于所述层间介质层22中，并不贯穿所述层间介质层222；又或者，过孔V1的底部还可以位于所述第一栅极绝缘层221中，并不贯穿所述第一栅极绝缘层221。遮光图案21所在的过孔V1的深度可以根据实际需求进行设定，此处不做限制。
在一实施例中，如图7所述，所述遮光图案21与所述第二源极243由不同层金属材料制成，所述第二源极243与所述第一源极232由不同层金属材料制成。
具体地，所述栅极242由第一金属层M1通过图案化工艺制备而成，所述第二源极243和所述第二漏极244由第二金属层M2通过图案化工艺制备而成。所述阵列基板还包括第三绝缘层225，所述第三绝缘层225位于所述第二绝缘层223远离所述衬底基板20的一侧上，第二源极243和第二漏极244设置于层间介质层222上，过孔V1形成于第二绝缘层223上，第一源极232和第一漏极233设置于第三绝缘层225上。可以理解的是，在形成所述第二绝缘层223后，通过刻蚀所述第二绝缘层223，形成多个过孔V1，然后在第二绝缘层223上沉积第三金属层M3，再通过图案化工艺形成所述遮光图案21。所述第一源极232和第一漏极233以及与所述第一源极232同层设置的触控信号线234由第四金属层M4通过图案化工艺制备而成，第四金属层M4形成于所述第三绝缘层225远离所述衬底基板20的一侧上，所述第四金属层M4的材料和结构可以与上述金属层的材料和结构相同，此处不再赘述。
在一实施例中，如图4至图7所示，所述阵列基板还包括层叠设置于第二绝缘层223或第三绝缘层225上的钝化保护层224、平坦层25、触控电极层26、第二钝化保护层27以及像素电极层28，所述触控电极层26内的触控电极通过过孔与所述触控信号线235连接，所述像素电极层28内的子像素电极通过过孔与所述第一薄膜晶体管23的第一漏极233连接。
在一实施例中，所述氧化物半导体层231的材料优选为IGZO。当然，在其他一些实施例中，所述氧化物半导体层231的材料还可包括但不限于铟镓氧化物或者铟锌氧化物等氧化物半导体材料，具体材料可以根据实际需求进行选择，此处不做限制。
综上所述，本申请实施例提供一种阵列基板，所述阵列基板包括阵列分布的多个薄膜晶体管，所述多个薄膜晶体管中的至少部分薄膜晶体管包括氧化物半导体层，所述阵列基板内设有多个槽型的遮光图案，所述氧化物半导体层对应形成于所述遮光图案的槽体内，利用槽型遮光图案的底面可以遮挡由阵列基板的入光侧照射至氧化物半导体层底部的光线，利用槽型遮光图案的侧面可以遮挡由阵列基板的入光侧照射至氧化物半导体层侧面的光线，以此通过将遮光图案设置为槽型来改善遮光图案的遮光效果，相较于通过增大平面面积来改善遮光图案的遮光效果，槽型的遮光图案在阵列基板上的正投影区域的面积更小，使得阵列基板上可透光的区域的面积更大，从而提高阵列基板的开口率。
本申请实施例还提供一种显示面板，所述显示面板包括阵列基板、彩膜基板、液晶层和背光模组，所述阵列基板与所述彩膜基板相对设置，所述液晶层设置于所述阵列基板与所述彩膜基板之间，所述背光模组设置于所述阵列基板的入光侧。本申请实施例中的阵列基板可以为上述实施例所提供的阵列基板，且该阵列基板应用于本申请实施例所提供的显示面板中，可以实现与上述实施例所提供的阵列基板相同的技术效果，此处不再赘述。
本申请实施例还提供一种阵列基板的制作方法，下面结合图8至图9H进行详细说明，图8为本申请实施例提供的阵列基板的制作方法的流程示意图，图9A至图9H为本申请实施例提供的阵列基板在制作过程中的结构示意图，该阵列基板的制作方法包括：
步骤S10：提供衬底基板30，在所述衬底基板上形成第一绝缘层32。
在一实施例中，如图9A所示，所述衬底基板30由层叠设置的基板301和缓冲层302组成，所述基板301优选为玻璃基板。所述第一绝缘层32包括层叠设置于所述衬底基板30上的第一栅极绝缘层321和层间介质层322，所述步骤S10包括：
步骤S101：提供衬底基板30，在所述衬底基板30上形成多晶硅半导体层341；
步骤S102：在所述衬底基板30上形成第一栅极绝缘层321，所述第一栅极绝缘层321覆盖所述多晶硅半导体层341；
步骤S103：在所述第一栅极绝缘层321远离所述衬底基板30的一侧上沉积第一金属层M1，对所述第一金属层M1进行图案化工艺，形成栅极342；
步骤S104：在所述第一栅极绝缘321层远离所述衬底基板30的一侧上形成层间介质层322，所述层间介质层322覆盖所述栅极342。
在本申请实施例中，所述多晶硅半导体层341和所述栅极342均形成于阵列基板的非透光区A2中，阵列基板的非透光区A2对应于显示面板的非显示区。
具体地，所述步骤S103中，所述第一金属层M1为Mo、Al和Ti形成的金属叠层走线结构。在其他一些实施例中，所述第一金属层M1还可以为Mo、Al和Ti等材料中的任意一种所形成的金属走线结构，或者第一金属层M1的材料也可以为Mo、Al和Ti中两种或两种以上材料所形成的合金。所述第一金属层M1的材料以及结构可以根据实际情况进行设定，此处不做限制。
步骤S20：在所述第一绝缘层32上形成多个过孔。
在一实施例中，如图9B所示，所述多个过孔包括第一过孔V1和第二过孔V2，可以利用同一刻蚀制程，同时形成所述第一过孔V1和第二过孔V2。所述第一过孔V1贯穿所述层间介质层322和所述第一栅极绝缘层321，并暴露出所述衬底基板30靠近所述第一栅极绝缘层321的一侧表面。所述第二过孔V2暴露出所述多晶硅半导体层341的源极接触区域和漏极接触区域。
在其他一些实施例中，第一过孔V1的底部可以仅贯穿所述层间介质层322；或者，所述第一过孔V1的底部可以延伸至所述层间介质层322中，并未贯穿所述层间介质层322；又或者，所述第一过孔V1的底部可以延伸至所述第一栅极绝缘层321中，仅贯穿所述层间介质层322，但并未贯穿所述第一栅极绝缘层321。
步骤S30：在所述过孔内形成多个槽型的遮光图案31；
在一实施例中，所述步骤S30包括：
步骤S301：在第一栅极绝缘层321远离所述衬底基板30的一侧表面、第一过孔V1以及第一过孔V2内沉积第二金属层M2；
步骤S302：对第二金属层M2进行图案化工艺，形成第二源极343、第二漏极344和槽型的遮光图案31。
如图9C所示，所述遮光图案31包括底面遮光层311和侧面遮光层312，侧面遮光层312由底面遮光层311的边缘延伸至与所述层间介质层322远离衬底基板30的一侧表面齐平，以将所述层间介质层322限制在槽型的遮光图案31的外围。
所述第二源极343与所述第二漏极344、所述栅极342和所述多晶硅半导体层341构成第二薄膜晶体管34，所述第二薄膜晶体管34为低温多晶硅薄膜晶体管，具有载流子迁移率高、充电快、开关速度快以及功耗较低的优点，应用于非透光区A2的GOA电路中，可以有效提高GOA电路的响应速度，并降低阵列基板的功耗。
具体地，所述第二金属层M2为Mo、Al和Ti形成的金属叠层走线结构。在其他一些实施例中，所述第二金属层M2还可以为Mo、Al和Ti等材料中的任意一种所形成的金属走线结构，或者第二金属层M2的材料也可以为Mo、Al和Ti中两种或两种以上材料所形成的合金。所述第二金属层M2的材料以及结构可以根据实际情况进行设定，此处不做限制。
步骤S40：在所述第一绝缘层32远离所述衬底基板30的一侧形成第二绝缘层323，所述第二绝缘层323覆盖所述遮光图案31。
如图9D所示，所述步骤S40中，可以通过气相沉积的方法形成所述第二绝缘层323，所述第二绝缘层323的材料为无机材料，优选为氧化硅材料。第二绝缘层323覆盖所述遮光图案31的部分同样凹陷至所述第一过孔V1内，使得第二绝缘层323覆盖所述遮光图案31的部分的高度低于其他部分的高度。
所述步骤S40还包括：通过刻蚀制程，在所述第二绝缘层323上形成多个第三过孔V3，所述第三过孔V3暴露出所述第二漏极344。
步骤S50：在所述过孔内形成氧化物半导体层331，所述氧化物半导体层331位于所述遮光图案31的槽体内。
所述步骤S50的步骤包括：
步骤S501：在所述第二绝缘层323远离所述衬底基板30的一侧沉积一层金属氧化物材料；
步骤S502：对所述金属氧化物材料进行图案化工艺，形成氧化物半导体层331。
如图9D所示，所述氧化物半导体层331位于所述第一过孔V1内，所述氧化物半导体层331远离所述衬底基板30的一侧表面与所述底面遮光层311之间的距离小于所述侧面遮光层312的顶部与所述底面遮光层311之间的距离，以此利用槽型的遮光图案31对所述氧化物半导体层331构成半包围结构，以将层间介质层322与所述氧化物半导体层331隔开，避免层间介质层322中的氢扩散至氧化物半导体层331中，同时还可以避免光线从氧化物半导体层331的底部以及侧面照射至氧化物半导体层331中。
具体地，所述氧化物半导体层331的材料为IGZO。当然，在其他一些实施例中，所述氧化物半导体层331的材料还可包括但不限于铟镓氧化物或者铟锌氧化物等氧化物半导体材料，具体材料可以根据实际需求进行选择，此处不做限制。
步骤60：在所述第二绝缘层323上形成源极和漏极。
如图9E所示，步骤S50中所指的源极和漏极分别为图9E中的第一源极332和第一漏极333，所述步骤S50包括：
步骤S501：在所述第二绝缘层323远离所述衬底基板30的一侧以及所述第三过孔V3内沉积第三金属层M3；
步骤S502：对所述第三金属层M3进行图案化工艺，形成第一源极332、第一漏极333、触控信号线334和信号走线335。
在本实施例中，所述第一源极332与所述第一漏极333、所述氧化物半导体层331以及所述遮光图案31构成第一薄膜晶体管33，所述遮光图案31作为第一薄膜晶体管33的栅极。所述第一薄膜晶体管33位于阵列基板的透光区内，并应用于透光区内的子像素驱动电路中，第一薄膜晶体管33为氧化物薄膜晶体管，具有良好的均一性以及漏电流较低的特点，可进一步降低阵列基板的功耗。
在本实施例中，所述第三金属层M3与第二金属层M2的材料和结构相同。在其他一些实施例中，所述第三金属层M3还可以为Mo、Al和Ti等材料中的任意一种所形成的金属走线结构，或者第三金属层M3的材料也可以为Mo、Al和Ti中两种或两种以上材料所形成的合金。所述第三金属层M3的材料以及结构可以根据实际情况进行设定，此处不做限制。
步骤S70：在所述第二绝缘层323远离所述衬底基板30的一侧上形成第一钝化保护层324，通过刻蚀制程在所述第一钝化保护层324上形成多个第四过孔V4和第五过孔V5，所述多个第四过孔V4暴露出所述触控信号线335，所述多个第五过孔V5暴露出所述第一漏极333。
如图9F所示，所述第一钝化保护层324形成于所述第二绝缘层323远离所述衬底基板30的一侧上，并覆盖所述触控信号线334、信号走线335、第一源极332、第一漏极333以及所述氧化物半导体层331。
在一实施例中，为避免在刻蚀制程中对所述第一钝化保护层324造成侧蚀，所述第一钝化保护层324的厚度应为600nm。当然在其他一些实施例中，所述第一钝化保护层324的厚度也可以为300nm、500nm、800nm或者100nm等。所述第一钝化保护层324的厚度可以根据实际情况进行设定，此处不做限制。
步骤S80：在所述第一钝化保护层324远离所述衬底基板30的一侧上形成平坦层35，通过刻蚀制程在所述平坦层35上形成多个第六过孔V6和多个第七过孔V7，所述多个第六过孔V6暴露出所述触控信号线334，所述第七过孔V7暴露出所述第一漏极333。
如图9G所示，所述第四过孔V4与所述第六过孔V6连通，所述第五过孔V5与所述第七过孔V7连通。
所述平坦层35的材料为常用的光阻材料，在未固化前，利用其流动性可将所述第一过孔V1填充。
步骤S90：在所述平坦层35远离所述衬底基板30的一侧上形成触控电极层36；在所述平坦层远离所述衬底基板30的一侧上形成第二钝化保护层37，通过刻蚀制程在所述第二钝化保护层37上形成多个第八过孔V8；在所述第二钝化保护层37远离所述衬底基板30的一侧上形成像素电极层38。
结合图9G和图9H所示，所述触控电极层36包括多个触控电极，所述触控电极通过所述第六过孔V6和所述第四过孔V4与所述触控信号线335连接。
所述第八过孔V8暴露出所述第一漏极334，所述像素电极层38包括多个子像素电极，所述子像素电极通过所述第八过孔V8与所述第一漏极334连接。
在本申请实施例中，所述像素电极层38和所述触控电极层36的材料均为ITO。在其他一些实施例中，所述像素电极层38和所述触控电极层36的材料也可以为其他透明金属氧化物材料。所述像素电极层38和所述触控电极层36的材料可以相同，也可以不同。所述像素电极层38和所述触控电极层36的材料可以根据实际情况设定，此处不做限制。
综上所述，本申请实施例提供一种阵列基板的制作方法，该制作方法通过在第一绝缘层上形成多个过孔，并在过孔内形成槽型的遮光图案，并将氧化物半导体层形成于遮光图案的槽体内，利用槽型遮光图案的底面可以遮挡由阵列基板的入光侧照射至氧化物半导体层底部的光线，利用槽型遮光图案的侧面可以遮挡由阵列基板的入光侧照射至氧化物半导体层侧面的光线，以此通过将遮光图案设置为槽型来改善遮光图案的遮光效果，相较于通过增大平面面积来改善遮光图案的遮光效果，槽型的遮光图案在阵列基板上的正投影区域的面积更小，使得阵列基板上可透光的区域的面积更大，从而提高阵列基板的开口率，同时还可以利用遮光图案将层间介质层与氧化物半导体层隔开，避免层间介质层中的氢扩散至氧化物半导体层中，从而保证氧化物半导体层的电学性能。
综上所述，虽然本申请以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为基准。

Claims (20)

  1. 一种阵列基板，所述阵列基板包括阵列分布的多个薄膜晶体管，所述多个薄膜晶体管中的至少部分薄膜晶体管包括氧化物半导体层；
    其中，所述阵列基板内设有多个槽型的遮光图案，所述氧化物半导体层对应形成于所述遮光图案的槽体内。
  2. 如权利要求1所述的阵列基板，其中，所述阵列基板包括衬底基板和设置于所述衬底基板上的第一绝缘层，所述第一绝缘层上设有多个过孔，所述遮光图案设置于所述过孔内。
  3. 如权利要求2所述的阵列基板，其中，所述遮光图案包括底面遮光层和侧面遮光层，所述底面遮光层平铺设置于所述过孔的底部，所述底面遮光层朝向所述第一绝缘层远离所述衬底基板的一侧延伸形成所述侧面遮光层，所述侧面遮光层与所述底面遮光层形成一定夹角。
  4. 如权利要求3所述的阵列基板，其中，所述侧面遮光层与所述底面遮光层形成的夹角为直角或钝角。
  5. 如权利要求4所述的阵列基板，其中，所述夹角的度数大于90°，小于或等于140°。
  6. 如权利要求3所述的阵列基板，其中，所述侧面遮光层的顶部与所述底面遮光层之间的距离，大于所述氧化物半导体层远离所述衬底基板的一侧与所述底面遮光层之间的距离。
  7. 如权利要求6所述的阵列基板，其中，所述遮光层在所述衬底基板上的正投影区域覆盖所述氧化物半导体层在所述衬底基板上的正投影区域。
  8. 如权利要求2所述的阵列基板，其中，所述多个薄膜晶体管包括第一薄膜晶体管，所述第一薄膜晶体管的有源层为所述氧化物半导体层，所述遮光图案为所述第一薄膜晶体管的栅极，所述第一薄膜晶体管形成于所述过孔内。
  9. 如权利要求8所述的阵列基板，其中，所述阵列基板包括第二绝缘层，所述第二绝缘层覆盖所述第一绝缘层和所述遮光图案，所述氧化物半导体层设置于所述第二绝缘层位于所述过孔内的部分上；
    所述第一薄膜晶体管包括第一源极和第一漏极，所述第一源极和所述第一漏极设置于所述第二绝缘层远离所述第一绝缘层的一侧上，并分别延伸至所述过孔内与所述氧化物半导体层连接。
  10. 如权利要求9所述的阵列基板，其中，所述多个薄膜晶体管还包括多个第二薄膜晶体管，所述第二薄膜晶体管的有源层为多晶硅半导体层；
    所述第一绝缘层包括层叠设置于所述衬底基板上的第一栅极绝缘层和层间介质层，所述多晶硅半导体层设置于所述第一栅极绝缘层与所述衬底基板之间，所述第二薄膜晶体管的栅极设置于所述第一栅极绝缘层与所述层间介质层之间。
  11. 如权利要求10所述的阵列基板，其中，多个所述过孔形成于所述层间介质层上，所述过孔的底部朝向所述衬底基板延伸，所述第二绝缘层覆盖所述层间介质层和所述遮光图案。
  12. 如权利要求10所述的阵列基板，其中，所述第二薄膜晶体管包括第二源极和第二漏极，所述遮光图案与所述第二源极和所述第二漏极由同层金属材料制成。
  13. 如权利要求10所述的阵列基板，其中，所述第二薄膜晶体管包括第二源极和第二漏极，所述第二源极和所述第二漏极与所述第一源极由同层金属材料制成。
  14. 一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括阵列分布的多个薄膜晶体管，所述多个薄膜晶体管中的至少部分薄膜晶体管包括氧化物半导体层；
    其中，所述阵列基板内设有多个槽型的遮光图案，所述氧化物半导体层对应形成于所述遮光图案的槽体内。
  15. 如权利要求14所述的显示面板，其中，所述阵列基板包括衬底基板和设置于所述衬底基板上的第一绝缘层，所述第一绝缘层上设有多个过孔，所述遮光图案设置于所述过孔内。
  16. 如权利要求15所述的显示面板，其中，所述遮光图案包括底面遮光层和侧面遮光层，所述底面遮光层平铺设置于所述过孔的底部，所述底面遮光层朝向所述第一绝缘层远离所述衬底基板的一侧延伸形成所述侧面遮光层，所述侧面遮光层与所述底面遮光层形成一定夹角。
  17. 如权利要求16所述的显示面板，其中，所述侧面遮光层与所述底面遮光层形成的夹角为直角或钝角。
  18. 如权利要求17所述的显示面板，其中，所述夹角的度数大于90°，小于或等于140°。
  19. 如权利要求16所述的显示面板，其中，所述侧面遮光层的顶部与所述底面遮光层之间的距离，大于所述氧化物半导体层远离所述衬底基板的一侧与所述底面遮光层之间的距离。
  20. 如权利要求19所述的显示面板，其中，所述遮光层在所述衬底基板上的正投影区域覆盖所述氧化物半导体层在所述衬底基板上的正投影区域。
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