WO2020215414A1 - 阵列基板及其制备方法 - Google Patents

阵列基板及其制备方法 Download PDF

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Publication number
WO2020215414A1
WO2020215414A1 PCT/CN2019/087552 CN2019087552W WO2020215414A1 WO 2020215414 A1 WO2020215414 A1 WO 2020215414A1 CN 2019087552 W CN2019087552 W CN 2019087552W WO 2020215414 A1 WO2020215414 A1 WO 2020215414A1
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Prior art keywords
data line
insulating layer
substrate
layer
via hole
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PCT/CN2019/087552
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English (en)
French (fr)
Inventor
聂晓辉
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武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/608,097 priority Critical patent/US11322521B2/en
Publication of WO2020215414A1 publication Critical patent/WO2020215414A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • the present invention relates to the field of display technology, in particular to an array substrate and a preparation method thereof.
  • the resolution and increasing the effective display area are two important directions for the development of small and medium-sized display panels.
  • the load on the driver chip will increase and the drive capability will decrease.
  • the length of the data line responsible for writing pixel signals will increase with the number of pixels and panel size.
  • the data line is generally made of metal material, which will cause a significant increase in metal impedance, resulting in insufficient charging capacity of the remote pixels, and thus resulting in uneven display of the panel.
  • the present invention provides an array substrate to solve the problem of an existing display panel. Due to the increase in the number of pixels to improve the resolution of the panel, the required length of the data line on the array substrate is increased, resulting in an increase in the impedance of the data line, and thus This leads to insufficient charging capacity of the remote pixels, leading to technical problems of uneven display.
  • the present invention provides an array substrate, which includes a substrate, a first data line arranged on the substrate, a first insulating layer arranged on the first data line, and a first insulating layer arranged on the first insulating layer.
  • the second data line on the layer, the first insulating layer is provided with a first via; wherein, the second data line is connected to the first data line through the first via; the first data
  • the orthographic projection of the line on the substrate coincides with the orthographic projection of the second data line on the substrate; the array substrate further includes a buffer layer, an active layer, a gate, and a second insulating layer.
  • the active layer is disposed on the first data line, and the gate is disposed on the active layer.
  • the orthographic projection of the first data line on the substrate covers the orthographic projection of the active layer on the substrate.
  • the buffer layer is disposed between the first data line and the active layer, and the first insulating layer is disposed between the gate and the active layer. In between, the second insulating layer is disposed between the second data line and the gate.
  • a second via hole is provided on the second insulating layer, and a third via hole is provided on the buffer layer.
  • the third via, the second via, and the first via are in communication with each other, and the second data line passes through the third via, the The second via hole and the first via hole are connected to the first data line.
  • the present invention provides another array substrate, including a substrate, a first data line arranged on the substrate, a first insulating layer arranged on the first data line, and a first insulating layer arranged on the first insulating layer On the second data line, a first via is provided on the first insulating layer, wherein the second data line is connected to the first data line through the first via.
  • the orthographic projection of the first data line on the substrate coincides with the orthographic projection of the second data line on the substrate.
  • the array substrate further includes a buffer layer, an active layer, a gate, and a second insulating layer.
  • the active layer is disposed on the first data line, and the gate is disposed on the active layer.
  • the orthographic projection of the first data line on the substrate covers the orthographic projection of the active layer on the substrate.
  • the buffer layer is disposed between the first data line and the active layer, and the first insulating layer is disposed between the gate and the active layer. In between, the second insulating layer is disposed between the second data line and the gate.
  • a second via hole is provided on the second insulating layer, and a third via hole is provided on the buffer layer.
  • the third via, the second via, and the first via are in communication with each other, and the second data line passes through the third via, the The second via hole and the first via hole are connected to the first data line.
  • the present invention also provides a method for preparing the array substrate, including the following steps:
  • a second data line is formed on the first insulating layer, and the second data line is connected to the first data line through the first via hole.
  • the orthographic projection of the first data line on the substrate coincides with the orthographic projection of the second data line on the substrate.
  • the S20 includes:
  • a second insulating layer is formed on the gate, and a second via is formed on the second insulating layer.
  • the second data line sequentially passes through the second via hole, the first via hole, and the third via hole and is electrically connected to the first data line.
  • the beneficial effect of the present invention is that the present invention increases the area of the data line by arranging the double-layer data line, thereby reducing the impedance of the data line, thereby improving the charging ability of the remote pixel and improving the display quality of the panel.
  • FIG. 1 is a schematic diagram of the structure of the array substrate of the present invention.
  • Fig. 2 is a cross-sectional view at A-A' in Fig. 1 of the present invention
  • FIG. 3 is a flow chart of the steps of the manufacturing method of the array substrate of the present invention.
  • 4 to 6 are schematic structural diagrams of the manufacturing process of the array substrate of the present invention.
  • the present invention is aimed at the existing display panel.
  • the resolution of the panel is increased by increasing the number of pixels, the length required for the data line on the array substrate is increased, resulting in an increase in the impedance of the data line, and thus the charging ability of the remote pixel Insufficiency eventually leads to a technical problem of uneven display.
  • This embodiment can solve this defect.
  • the present invention provides an array substrate including a substrate, a first data line, a first insulating layer, and a second data line.
  • the first data line is disposed on the substrate, the first insulating layer is disposed on the first data line, and the second data line is disposed on the first insulating layer.
  • a first via hole is provided on the first insulating layer, and the second data line is electrically connected to the first data line through the first via hole.
  • the orthographic projection of the second data line on the substrate coincides with the orthographic projection of the second data line on the substrate, that is, the second data line and the first data line Overlap in the thickness direction of the substrate.
  • the array substrate further includes an active layer, source and drain electrodes, gates, scan lines, and multiple inorganic film layers, and multiple inorganic film layers may be provided between the first data line and the second data line .
  • the inorganic film layer may be a film layer such as a buffer layer, a gate insulating layer, and an interlayer insulating layer.
  • the present invention also provides a method for preparing an array substrate, including the following steps:
  • a second data line is formed on the second insulating layer, and the second data line is connected to the first data line through the first via hole.
  • the orthographic projection of the first data line on the substrate coincides with the orthographic projection of the second data line on the substrate.
  • the preparation method also includes the preparation of the active layer, the gate electrode, the source and drain electrodes, and the inorganic film layer.
  • the detailed preparation method is described in conjunction with specific embodiments.
  • the present embodiment provides an array substrate 100, which includes a substrate 10, a first data line 20, a second data line 80, and the first data line 20 and the second data line 80.
  • the first data line 20 is provided on the substrate 10
  • the buffer layer 30 is provided on the first data line 20
  • the buffer layer 30 is provided with a third via 301.
  • the active layer 40 is disposed on the first data line 20, and the gate 60 is disposed on the active layer 40.
  • the gate 60 is a top gate structure. In other embodiments, the gate 60 may also be a bottom gate structure.
  • the first insulating layer 50 is disposed between the active layer 40 and the gate 60, the first insulating layer 50 is a gate insulating layer, and a first insulating layer is disposed on the first insulating layer 50. ⁇ 501.
  • the second insulating layer 70 is disposed between the second data line 80 and the gate 60, the second insulating layer 70 is an interlayer insulating layer, and a second insulating layer is disposed on the second insulating layer. ⁇ 701.
  • the third via 301, the first via 501, and the second via 701 communicate with each other to form a through hole, and the through hole passes through the buffer layer 30 and the second via in turn.
  • An insulating layer 50 and the second insulating layer 70 enable the second data line 80 to pass through the through hole to be connected to the first data line 20.
  • the orthographic projection of the first data line 20 on the substrate 10 covers the orthographic projection of the active layer 40 on the substrate 10.
  • the first data line 20 can shield light and avoid the environment Light enters the interior of the array substrate 100 from the direction of the substrate 10, and affects the current and voltage characteristics of the device.
  • the array substrate 100 further includes a source electrode, a drain electrode, and a scan line 90.
  • the source electrode and the drain electrode can be arranged in the same layer as the second data line 80, and the source electrode or the drain electrode can pass through the second data line 80.
  • the insulating layer and the via holes on the first insulating layer are connected to the active layer, the second data line 80 is connected to the source electrode, and the scan line 90 can be arranged in the same layer as the gate electrode 60 .
  • the plurality of scan lines 90 are arranged in parallel along a first direction, and the plurality of second data lines 80 are arranged in parallel along a second direction, and the first direction and the second direction are perpendicular to each other.
  • the substrate 10 is a flexible substrate or a rigid substrate, such as a polyimide substrate or a glass substrate.
  • the first data line 20, the second data line 80, the scan line 90, and the gate 60 are all metal materials.
  • the materials of the buffer layer 30, the first insulating layer 50, and the second insulating layer 70 are all one of silicon nitride and silicon oxide.
  • This embodiment also provides a method for preparing the aforementioned array substrate 100, including:
  • a physical vapor deposition method is used to deposit a metal layer on the substrate 10, and the metal layer is patterned by exposure, development, etching, and other processes to form the first data line 20 ,
  • the substrate 10 is a glass substrate.
  • the S20 includes:
  • a silicon nitride film layer is deposited on the substrate 10 by a chemical vapor deposition method, and the silicon nitride film layer is patterned by processes such as exposure, development, and etching, and the silicon nitride film layer is patterned on the first data line 20 Forming a buffer layer 30, and forming a third via 301 on the buffer layer 30;
  • a polysilicon layer is formed on the buffer layer 30 by a chemical vapor deposition method and an excimer laser annealing process, and a patterned active layer 40 is formed by processes such as exposure, development, and etching;
  • a silicon oxide film layer is deposited on the active layer 40 by chemical vapor deposition, and the patterned first insulating layer 50 is formed by processes such as exposure, development, and etching.
  • a first via 501 is formed above the third via 301, and a via for connecting the source or drain is formed above both ends of the active layer 40;
  • a physical vapor deposition method is used to deposit a metal film layer on the first insulating layer 50, and the metal film layer is patterned by processes such as exposure, development, and etching to form the gate 60 and scan lines;
  • a silicon oxide film layer is deposited on the gate 60 by chemical vapor deposition, and a patterned second insulating layer 70 is formed by processes such as exposure, development, and etching.
  • a second via 701 is formed above the first via 501 of the insulating layer 50, and a via for connecting the source or drain is formed above the two ends of the active layer 40.
  • a physical vapor deposition method is used to deposit a metal film layer on the second insulating layer 70, and the metal film layer is patterned using processes such as exposure, development, and etching to form the second data line 80.
  • a source and a drain are formed, and the second data line 80 sequentially passes through the second via 701, the first via 501, the third via 301 and the first data line 20.
  • the source electrode and the drain electrode pass through the second insulating layer 70 and the via holes on the first insulating layer 50 sequentially to connect to the active layer.
  • the present invention increases the area of the data line by arranging a double-layer data line, thereby reducing the impedance of the data line, thereby improving the charging ability of the remote pixels and improving the display quality of the panel.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种阵列基板，包括衬底、依次设置于所述衬底上的第一数据线、第一绝缘层、以及第二数据线，其中，第一绝缘层上设置有第一过孔，第二数据线通过第一过孔与第一数据线连接。通过设置双层数据线，增大数据线的面积，从而降低数据线的阻抗，进而提高远端像素的充电能力和面板的显示品质。

Description

阵列基板及其制备方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法。
 背景技术
提高分辨率和增大有效显示面积是中小尺寸显示面板发展的两个重要方向。通过增加像素数量来提高显示面板的分辨率，一方面导致驱动芯片的负载增大，驱动能力下降，另一方面负责像素信号写入的数据线的长度会随着像素数量和面板尺寸的增加而增长，而数据线一般为金属材料，会导致金属阻抗的显著增大，从而导致远端像素的充电能力不足，进而导致面板显示不均。
 技术问题
本发明提供一种阵列基板，以解决现有的显示面板，由于采取增加像素数量来提高面板的分辨率，使得阵列基板上的数据线所需的长度增长，导致数据线的阻抗增大，进而导致远端像素充电能力不足，从而导致显示不均的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种阵列基板，其中，包括衬底、设置于所述衬底上的第一数据线、设置于所述第一数据线上的第一绝缘层、以及设置于所述第一绝缘层上第二数据线，所述第一绝缘层上设置有第一过孔；其中，所述第二数据线通过所述第一过孔与所述第一数据线连接；所述第一数据线在所述衬底上的正投影与所述第二数据线在所述衬底上的正投影重合；所述阵列基板还包括缓冲层、有源层、栅极、以及第二绝缘层。
在本发明的一种实施例中，所述有源层设置于所述第一数据线上，所述栅极设置于所述有源层上。
在本发明的一种实施例中，所述第一数据线在所述衬底上的正投影覆盖所述有源层在所述衬底上的正投影。
在本发明的一种实施例中，所述缓冲层设置于所述第一数据线与所述有源层之间，所述第一绝缘层设置于所述栅极与所述有源层之间，所述第二绝缘层设置于所述第二数据线与所述栅极之间。
在本发明的一种实施例中，所述第二绝缘层上设置有第二过孔，所述缓冲层上设置有第三过孔。
在本发明的一种实施例中，所述第三过孔、所述第二过孔、以及所述第一过孔相互连通，所述第二数据线通过所述第三过孔、所述第二过孔、以及所述第一过孔与所述第一数据线连接。
本发明提供另外一种阵列基板，包括衬底、设置于所述衬底上的第一数据线、设置于所述第一数据线上的第一绝缘层、以及设置于所述第一绝缘层上第二数据线，所述第一绝缘层上设置有第一过孔，其中，所述第二数据线通过所述第一过孔与所述第一数据线连接。
在本发明的一种实施例中，所述第一数据线在所述衬底上的正投影与所述第二数据线在所述衬底上的正投影重合。
在本发明的一种实施例中，所述阵列基板还包括缓冲层、有源层、栅极、以及第二绝缘层。
在本发明的一种实施例中，所述有源层设置于所述第一数据线上，所述栅极设置于所述有源层上。
在本发明的一种实施例中，所述第一数据线在所述衬底上的正投影覆盖所述有源层在所述衬底上的正投影。
在本发明的一种实施例中，所述缓冲层设置于所述第一数据线与所述有源层之间，所述第一绝缘层设置于所述栅极与所述有源层之间，所述第二绝缘层设置于所述第二数据线与所述栅极之间。
在本发明的一种实施例中，所述第二绝缘层上设置有第二过孔，所述缓冲层上设置有第三过孔。
在本发明的一种实施例中，所述第三过孔、所述第二过孔、以及所述第一过孔相互连通，所述第二数据线通过所述第三过孔、所述第二过孔、以及所述第一过孔与所述第一数据线连接。
本发明还提供一种阵列基板的制备方法，包括以下步骤：
S10，提供一衬底，在所述衬底上形成第一数据线；
S20，在所述衬底上形成第一绝缘层，所述第一绝缘层设置有第一过孔；
S30，在所述第一绝缘层上形成第二数据线，所述第二数据线通过所述第一过孔与所述第一数据线连接。
在本发明的一种实施例中，所述第一数据线在所述衬底上的正投影与所述第二数据线在所述衬底上的正投影重合。
在本发明的一种实施例中，所述S20包括：
在所述第一数据线上形成缓冲层，所述缓冲层上形成有第三过孔；
在所述缓冲层上形成有源层；
在所述有源层上形成所述第一绝缘层，所述第一绝缘层上形成有所述第一过孔；
在所述第一绝缘层上形成栅极；
在所述栅极上形成第二绝缘层，所述第二绝缘层上形成有第二过孔。
在本发明的一种实施例中，所述第二数据线依次穿过所述第二过孔、所述第一过孔、所述第三过孔与所述第一数据线电性连接。
 有益效果
本发明的有益效果为：本发明通过设置双层数据线，增大数据线的面积，从而降低数据线的阻抗，进而提高远端像素的充电能力和提高面板的显示品质。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明的阵列基板的结构示意图；
图2为本发明图1中的A-A’处的剖视图；
图3为本发明的阵列基板的制备方法的步骤流程图；
图4~6为本发明的阵列基板的制备过程的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的显示面板，由于采用增加像素数量来提高面板的分辨率，使得阵列基板上的数据线所需的长度增长，导致数据线的阻抗增大，进而导致远端像素的充电能力不足，最终导致显示不均的技术问题，本实施例能够解决该缺陷。
本发明提供一种阵列基板，包括衬底、第一数据线、第一绝缘层、以及第二数据线。
其中，所述第一数据线设置于所述衬底上，所述第一绝缘层设置于所述第一数据线上，所述第二数据线设置于所述第一绝缘层上。
所述第一绝缘层上设置有第一过孔，所述第二数据线通过所述第一过孔与所述第一数据线电性连接。通过将数据线分为两层设置，并且两条数据线通过过孔连接，与原有单层数据线的设计相比，能够增加数据线的表面积，从而降低数据线的阻抗，进而提高像素的充电能力和提高面板的显示品质。
进一步地，所述第二数据线在所述衬底上的正投影与所述第二数据线在所述衬底上的正投影重合，即所述第二数据线和所述第一数据线在所述衬底的厚度方向上重叠。
所述阵列基板还包括有源层、源漏极、栅极、扫描线、以及多层无机膜层，所述第一数据线和所述第二数据线之间可设置有多层无机膜层。
所述第二数据线与所述第一数据线之间除设置有所述第一绝缘层外，还可设置有多层无机膜层，但需保证的是，所述多层无机膜层上也设置有过孔，所述过孔能够穿过该多层无机膜层，使得所述第二数据线通过所述过孔实现与所述第一数据线电性连接。所述无机膜层可为缓冲层、栅极绝缘层、层间绝缘层等膜层。
如图3所示，本发明还提供一种阵列基板的制备方法，包括以下步骤：
S10，提供一衬底，在所述衬底上形成第一数据线；
S20，在所述衬底上形成第一绝缘层，所述第一绝缘层设置有第一过孔；
S30，在所述第二绝缘层上形成第二数据线，所述第二数据线通过所述第一过孔与所述第一数据线连接。
其中，所述第一数据线在所述衬底上的正投影与所述第二数据线在所述衬底上的正投影重合。
所述制备方法还包括有源层、栅极、源漏极、以及无机膜层的制备，详细的制备方法结合具体实施例进行说明。
下面结合具体实施例对本发明所述的阵列基板及其制备方法进行详细说明。
如图1和图2所示，本实施例提供一种阵列基板100，包括衬底10、第一数据线20、第二数据线80、以及设置于所述第一数据线20与所述第二数据线80之间的缓冲层30、有源层40、第一绝缘层50、栅极60、第二绝缘层70。
其中，所述第一数据线20设置于所述衬底10上，所述缓冲层30设置于所述第一数据线20上，所述缓冲层30上设置有第三过孔301。
所述有源层40设置于所述第一数据线20上，所述栅极60设置于所述有源层40上。
所述栅极60为顶栅结构，在其他实施例中，所述栅极60还可为底栅结构。
所述第一绝缘层50设置于所述有源层40与所述栅极60之间，所述第一绝缘层50为栅极绝缘层，所述第一绝缘层50上设置有第一过孔501。
所述第二绝缘层70设置于所述第二数据线80与所述栅极60之间，所述第二绝缘层70为层间绝缘层，所述第二绝缘层上设置有第二过孔701。
其中，所述第三过孔301、所述第一过孔501、以及所述第二过孔701相互连通，一起形成一通孔，所述通孔依次穿过所述缓冲层30、所述第一绝缘层50、以及所述第二绝缘层70，使得所述第二数据线80穿过该通孔与所述第一数据线20连接。
所述第一数据线20在所述衬底10上的正投影覆盖所述有源层40在所述衬底10上的正投影，所述第一数据线20能够起到遮光作用，避免环境光从所述衬底10的方向进入所述阵列基板100的内部，对器件的电流电压特性造成影响。
所述阵列基板100还包括源极、漏极以及扫描线90，所述源极和漏极可与所述第二数据线80同层设置，所述源极或漏极可通过所述第二绝缘层和所述第一绝缘层上的过孔与所述有源层连接，所述第二数据线80与所述源极连接，所述扫描线90可与所述栅极60同层设置。
多个所述扫描线90沿第一方向平行设置，多个所述第二数据线80沿第二方向平行设置，所述第一方向和所述第二方向相互垂直。
所述衬底10为柔性基板或刚性基板，例如聚酰亚胺基板或玻璃基板。
所述第一数据线20、所述第二数据线80、所述扫描线90、以及所述栅极60均为金属材料。
所述缓冲层30、所述第一绝缘层50、以及所述第二绝缘层70的材料均为氮化硅、氧化硅中的一种。
本实施例还提供上述阵列基板100的制备方法，包括：
S10，提供一衬底10，在所述衬底10上形成第一数据线20；
如图4所示，在所述衬底10上利用物理气相沉积法在沉积一层金属层，利用曝光、显影、刻蚀、等工艺将所述金属层图案化，以形成第一数据线20，所述衬底10为玻璃基板。
S20，在所述衬底10上形成第一绝缘层50，所述第一绝缘层50上设置有第一过孔501；
具体地，所述S20包括：
首先，利用化学气相沉积法在所述衬底10上沉积氮化硅膜层，利用曝光、显影、刻蚀等工艺将所述氮化硅膜层图案化，在所述第一数据线20上形成缓冲层30，在所述缓冲层30上形成第三过孔301；
然后，利用化学气相沉积法和准分子激光退火工艺在所述缓冲层30上形成多晶硅层，利用曝光、显影、刻蚀等工艺形成图案化的有源层40；
如图5所示，之后，利用化学气相沉积法在所述有源层40上沉积氧化硅膜层，利用曝光、显影、刻蚀等工艺形成图案化的所述第一绝缘层50，在所述第三过孔301上方形成第一过孔501，在所述有源层40两端的上方形成用以连接源极或漏极的过孔；
再利用物理气相沉积法在所述第一绝缘层50上沉积金属膜层，利用曝光、显影、刻蚀等工艺使得该金属膜层图案化，以形成栅极60和扫描线；
如图6所示，最后，利用化学气相沉积法在所述栅极60上沉积氧化硅膜层，利用曝光、显影、刻蚀等工艺形成图案化的第二绝缘层70，在所述第一绝缘层50的第一过孔501的上方形成第二过孔701，在所述有源层40两端的上方形成连接源极或漏极的过孔。
S30，在所述第一绝缘层50上形成第二数据线80，所述第二数据线80通过所述第一过孔501与所述第一数据线20连接；
具体地，利用物理气相沉积法在所述第二绝缘层70上沉积金属膜层，利用曝光、显影、刻蚀等工艺将该金属膜层图案化，形成所述第二数据线80的同时，形成源极和漏极，所述第二数据线80依次穿过所述第二过孔701、所述第一过孔501、所述第三过孔301与所述第一数据线20电性连接，所述源极和漏极依次穿过所述第二绝缘层70和所述第一绝缘层50上的过孔与所述有源层连接。
有益效果：本发明通过设置双层数据线，增大数据线的面积，从而降低数据线的阻抗，进而提高远端像素的充电能力和提高面板的显示品质。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种阵列基板，其中，包括：
    衬底；
    第一数据线，设置于所述衬底上；
    第一绝缘层，设置于所述第一数据线上，所述第一绝缘层上设置有第一过孔；以及
    第二数据线，设置于所述第一绝缘层上；其中，
    所述第二数据线通过所述第一过孔与所述第一数据线连接；
    所述第一数据线在所述衬底上的正投影与所述第二数据线在所述衬底上的正投影重合；
    所述阵列基板还包括缓冲层、有源层、栅极、以及第二绝缘层。
  2. 根据权利要求1所述的阵列基板，其中，所述有源层设置于所述第一数据线上，所述栅极设置于所述有源层上。
  3. 根据权利要求2所述的阵列基板，其中，所述第一数据线在所述衬底上的正投影覆盖所述有源层在所述衬底上的正投影。
  4. 根据权利要求2所述的阵列基板，其中，所述缓冲层设置于所述第一数据线与所述有源层之间，所述第一绝缘层设置于所述栅极与所述有源层之间，所述第二绝缘层设置于所述第二数据线与所述栅极之间。
  5. 根据权利要求3所述的阵列基板，其中，所述第二绝缘层上设置有第二过孔，所述缓冲层上设置有第三过孔。
  6. 根据权利要求5所述的阵列基板，其中，所述第三过孔、所述第二过孔、以及所述第一过孔相互连通，所述第二数据线通过所述第三过孔、所述第二过孔、以及所述第一过孔与所述第一数据线连接。
  7. 一种阵列基板，其中，包括：
    衬底；
    第一数据线，设置于所述衬底上；
    第一绝缘层，设置于所述第一数据线上，所述第一绝缘层上设置有第一过孔；以及
    第二数据线，设置于所述第一绝缘层上；其中，
    所述第二数据线通过所述第一过孔与所述第一数据线连接。
  8. 根据权利要求7所述的阵列基板，其中，所述第一数据线在所述衬底上的正投影与所述第二数据线在所述衬底上的正投影重合。
  9. 根据权利要求7所述的阵列基板，其中，所述阵列基板还包括缓冲层、有源层、栅极、以及第二绝缘层。
  10. 根据权利要求9所述的阵列基板，其中，所述有源层设置于所述第一数据线上，所述栅极设置于所述有源层上。
  11. 根据权利要求10所述的阵列基板，其中，所述第一数据线在所述衬底上的正投影覆盖所述有源层在所述衬底上的正投影。
  12. 根据权利要求10所述的阵列基板，其中，所述缓冲层设置于所述第一数据线与所述有源层之间，所述第一绝缘层设置于所述栅极与所述有源层之间，所述第二绝缘层设置于所述第二数据线与所述栅极之间。
  13. 根据权利要求11所述的阵列基板，其中，所述第二绝缘层上设置有第二过孔，所述缓冲层上设置有第三过孔。
  14. 根据权利要求13所述的阵列基板，其中，所述第三过孔、所述第二过孔、以及所述第一过孔相互连通，所述第二数据线通过所述第三过孔、所述第二过孔、以及所述第一过孔与所述第一数据线连接。
  15. 一种阵列基板的制备方法，其中，包括以下步骤：
    S10，提供一衬底，在所述衬底上形成第一数据线；
    S20，在所述衬底上形成第一绝缘层，所述第一绝缘层上设置有第一过孔；
    S30，在所述第一绝缘层上形成第二数据线，所述第二数据线通过所述第一过孔与所述第一数据线连接。
  16. 根据权利要求15所述的制备方法，其中，所述第一数据线在所述衬底上的正投影与所述第二数据线在所述衬底上的正投影重合。
  17. 根据权利要求15所述的制备方法，其中，所述S20包括：
    在所述第一数据线上形成缓冲层，所述缓冲层上形成有第三过孔；
    在所述缓冲层上形成有源层；
    在所述有源层上形成所述第一绝缘层，所述第一绝缘层上形成有所述第一过孔；
    在所述第一绝缘层上形成栅极；
    在所述栅极上形成第二绝缘层，所述第二绝缘层上形成有第二过孔。
  18. 根据权利要求17所述的制备方法，其中，所述第二数据线依次穿过所述第二过孔、所述第一过孔、所述第三过孔与所述第一数据线电性连接。
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