WO2022118650A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2022118650A1 WO2022118650A1 PCT/JP2021/042046 JP2021042046W WO2022118650A1 WO 2022118650 A1 WO2022118650 A1 WO 2022118650A1 JP 2021042046 W JP2021042046 W JP 2021042046W WO 2022118650 A1 WO2022118650 A1 WO 2022118650A1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
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Definitions
- the present invention relates to a semiconductor device.
- IGBT insulated gate bipolar transistor
- the IGBT is a semiconductor device in which the input unit has a MOSFET structure and the output unit has a bipolar structure.
- the IGBT is provided to compensate for the drawback that the loss during conduction of the MOS transistor is large, but the switching loss tends to be larger than that of the power MOSFET.
- Such an IGBT is known in, for example, Patent Document 1 and Patent Document 2.
- the voltage-driven semiconductor device described in Patent Document 1 in addition to the first transistor, a second transistor having a different polarity is formed in the drain of the first transistor, and the second transistor becomes the drain of the first transistor. Supplying carriers. With such a configuration, the voltage-driven semiconductor device described in Patent Document 1 can cause conductivity modulation in the drain of the first transistor to reduce the loss during conduction and reduce the on-voltage drop.
- the semiconductor device described in Patent Document 2 is a planar gate type IGBT having a main gate electrode on the surface of the semiconductor layer. Further, this semiconductor device is provided with a control gate electrode on the back surface of the semiconductor layer.
- the semiconductor device of Patent Document 2 can suppress the injection of holes into the drift region during the turn-off operation and reduce the turn-off loss (switching loss).
- the present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of reducing switching loss at turn-off while suppressing loss at conduction.
- the semiconductor device of the present invention is provided with a first conductive type emitter layer, a first conductive type collector layer, and a second conductive type provided between the emitter layer and the collector layer.
- the type drift layer, the emitter electrode electrically connected to the emitter layer, the collector electrode electrically connected to the collector layer, and the emitter layer were arranged to face each other via the emitter-side gate insulating film.
- a second conductive type first high-concentration impurity layer provided between the emitter electrode and the emitter layer and having a higher impurity concentration than the emitter layer, and the drift layer.
- a first conductive type impurity layer provided between the collector electrode and the collector electrode, one or more collector-side gate electrodes arranged opposite to the impurity layer via a collector-side gate insulating film, and the collector.
- a second conductive type second high-concentration impurity layer provided between the electrode and the impurity layer and having a higher impurity concentration than the impurity layer is provided, via the emitter layer and the emitter-side gate insulating film.
- the total length in the gate width direction in the first facing region of the emitter-side gate electrodes facing each other is the second of the collector-side gate electrodes facing the impurity layer via the collector-side gate insulating film. It is characterized in that it is longer than the total length in the gate width direction in the facing region.
- the length in the gate width direction in the first facing region of the emitter-side gate electrode, which is arranged to face the emitter layer via the emitter-side gate insulating film, is set to the impurity layer via the collector-side gate insulating film.
- FIG. 1 is a cross-sectional view taken along the line IIa-IIa in FIG.
- B is a cross-sectional view taken along the line IIb-IIb in FIG. It is a schematic diagram for demonstrating the inversion layer formed in an emitter p - layer and the inversion layer formed in a collector p - layer.
- A) is a circuit diagram showing a conventional IGBT evaluation circuit as a comparative example.
- (B) is a circuit diagram showing an evaluation circuit of a semiconductor device according to the first embodiment.
- (A) is a graph showing the simulation result showing the relationship between the gate density ratio and the switching loss.
- (B) is a graph showing the simulation result showing the relationship between the gate density ratio and the on-voltage drop. It is a graph which shows the simulation result which showed the relationship between the gate-on timing deviation of the emitter side and the collector side, and a switching loss.
- (A) to (c) are diagrams for explaining the manufacturing process of the semiconductor device of the first embodiment.
- (D) and (e) are diagrams for explaining the manufacturing process of the semiconductor device of the first embodiment following FIG. 7A. It is sectional drawing for demonstrating the structure of the semiconductor device of the 1st modification.
- (A) is a cross-sectional view taken along the line IXa-IXa of the semiconductor device shown in FIG. 8 as viewed from above to below.
- (B) is a cross-sectional view of the semiconductor device along the line IXb-IXb as viewed from below to above. It is sectional drawing for demonstrating the structure of the semiconductor device of the 2nd modification.
- (A) is a cross-sectional view of the semiconductor device shown in FIG. 10 taken along the line XIa-XIa from above to below.
- (B) is a cross-sectional view of the semiconductor device along the line XIb-XIb as viewed from below to above.
- (A), (b), (c), and (d) are timing charts for explaining a modification of the operation of the semiconductor device of the first embodiment.
- (A), (b), and (c) are timing charts for explaining a modification of the operation of the semiconductor device of the first embodiment at the time of turn-on.
- (A), (b), (c), and (d) are timing charts for explaining a modification of the operation of the semiconductor device of the first embodiment at the time of turn-off.
- (A) is a figure which shows the upper surface of the emitter electrode.
- (B) is a figure which shows the upper surface of a collector electrode.
- the range R shown in FIG. 15 (a) of the semiconductor device shown in FIGS. 15 (a) and 15 (b) is cut by a alternate long and short dash line between the arrow lines XV and XV, and the cross section is cut in the direction of the arrow line XV. It is a cross-sectional view seen in.
- FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device 1 of the first embodiment.
- FIG. 2A is a cross-sectional view of the cross-sectional portion of the semiconductor device 1 shown in FIG. 1 along the lines IIa-IIa as viewed from above to below.
- FIG. 2B is a cross-sectional view of the cross-sectional portion of the semiconductor device 1 along the lines IIb-IIb as viewed from below to above.
- FIG. 1 is a configuration in which the emitter electrode 18 and the collector electrode 28, which will be described later in FIGS. 2 (a) and 2 (b), are provided, from the position of the line I-I shown in FIG. 2 (a).
- the side cross-sectional structure of the seen semiconductor device 1 is shown.
- the Z direction indicates the thickness direction of the semiconductor device 1
- the X direction is the semiconductor substrate of the semiconductor device 1 (hereinafter, simply referred to as “board”) 5.
- the Y direction indicates a direction parallel to the first surface fa and the second surface fb and orthogonal to the Z direction and the X direction.
- the arrow direction in the Z direction which is the thickness direction
- the direction opposite to the arrow in the Z direction is referred to as an upward direction.
- the semiconductor device 1 is an IGBT type semiconductor device, and has, for example, a substrate 5 made of a Si crystal or the like.
- the substrate 5 has an emitter p - layer 11 as an emitter layer, a collector p layer 23 as a collector layer, a drift layer 10 provided between the emitter p - layer 11 and the collector p layer 23, and a first high concentration.
- It has an emitter n layer 12 which is an impurity layer, an emitter p layer 13, a buffer layer 29, a collector p - layer 23a, and a collector n layer 22 which is a second high-concentration impurity layer.
- the term "emitter side” is described in the portion on the emitter electrode 18 side with the drift layer 10 interposed therebetween, and the term “collector side” is described in the portion on the collector electrode 28 side.
- the emitter p layer 13, the emitter p - layer 11 and the collector p layer 23 are impurity layers whose conductive type is p-type (here, the first conductive type), and the emitter n layer 12 and the drift layer 10 are used.
- the buffer layer 29 and the collector n layer 22 are impurity layers whose conductive type is n type (here, the second conductive type).
- the emitter p - layer 11 is formed on the upper surface of the drift layer 10. Above the emitter p - layer 11, an emitter n layer 12 and an emitter p layer 13 are formed. The emitter n layer 12 and the emitter p layer 13 are formed so as to be exposed on the first surface fa of the substrate 5, and are electrically connected to the emitter electrode 18.
- the emitter n layer 12, which is the first high-concentration impurity layer, is provided between the emitter electrode 18 and the emitter p - layer 11. However, a part of the emitter n layer 12 may be arranged between the interlayer insulating layer 16 and the emitter p ⁇ layer 11.
- the emitter p layer 13 is provided between the emitter electrode 18 and the emitter p ⁇ layer 11.
- the emitter n layer 12 and the emitter p layer 13 are contact layers to the emitter p - layer 11 in the semiconductor device 1, and both have a higher impurity concentration than the emitter p - layer 11.
- the emitter n-layer 12 is an n + layer that injects electrons into the lower emitter p - layer 11. Further, the emitter p layer 13 is a p + layer that discharges holes from the lower emitter p ⁇ layer 11. A trench hole 14 (described later) that penetrates the emitter n layer 12 is formed on the first surface fa of the substrate 5.
- the drift layer 10 is an n ⁇ layer, and the impurity concentration is, for example, about 2 ⁇ 10 13 cm -3 .
- the impurity concentrations of the emitter n layer 12 and the emitter p layer 13 are, for example, about 10 18 to 10 21 cm -3 .
- the emitter n layer 12 is arranged adjacent to each trench hole 14 on the first surface fa of the substrate 5, and the emitter p layer is formed between the emitter n layers 12 formed adjacent to each trench hole 14. 13 is arranged.
- the emitter n layer 12 is formed in a band shape in a top view, and is arranged on both sides of the trench hole 14 so as to extend in the Y direction on the first surface fa.
- the emitter p layer 13 is also formed in a band shape in the top view, and is arranged between the emitter n layers 12 so as to extend in the Y direction on the first surface fa.
- the first surface fa of the substrate 5 is provided with a plurality of trench holes 14 extending in the Y direction on the first surface fa.
- the trench holes 14 according to the first embodiment have the same configuration, are arranged in parallel with each other along the Y direction on the first surface fa, and are provided at predetermined intervals in the X direction.
- the trench hole 14 penetrates the emitter n layer 12 and the emitter p - layer 11 from the first surface fa of the substrate 5 and reaches the drift layer 10.
- a gate insulating film 15 which is an emitter-side gate insulating film is formed in each trench hole 14, and a trench-type emitter-side gate electrode 17 is formed in a region surrounded by the gate insulating film 15. There is.
- the gate insulating film 15 is formed of, for example, an oxide film, and insulates the emitter-side gate electrode 17 from the substrate 5 (drift layer 10, emitter p - layer 11 and emitter n layer 12).
- the emitter-side gate electrode 17 is formed of, for example, polycrystalline silicon (polysilicon) or the like, and its upper end is covered with an interlayer insulating layer 16 made of an oxide film or the like.
- An emitter-side gate wiring (not shown) is connected to each emitter-side gate electrode 17, and a predetermined gate voltage Vgg1 is applied via the emitter-side gate wiring.
- the upper end of the emitter-side gate electrode 17 according to the first embodiment is located in the trench hole 14 without protruding from the first surface fa of the substrate 5, and the interlayer insulating layer 16 is located in the trench hole 14. Is also provided and is connected to the gate insulating film 15.
- a predetermined number of emitter-side gate electrodes 17 extending in parallel with each other in the Y direction are predetermined in the X direction. They are arranged at intervals.
- the configuration in the element region R0 is set as one pattern, and the configuration in the element region R0 is formed as a repeating pattern in a predetermined period in the X direction.
- the configuration of the semiconductor device 1 will be described with a focus on the element region R0 defined in the X direction.
- the emitter-side gate electrode 17 has a first facing region (hereinafter, referred to as an emitter-side facing region) which is arranged to face the emitter p - layer 11 via the gate insulating film 15.
- an emitter-side facing region which is arranged to face the emitter p - layer 11 via the gate insulating film 15.
- five emitter-side gate electrodes 17 are shown, and ten emitter-side facing regions Ja0 to Ja8 are shown as emitter-side facing regions Ja.
- the emitter-side facing region Ja0 on the left side of the figure of the emitter-side gate electrode 17 at the leftmost end in the figure is included in the element region R0 which becomes a repeating pattern.
- the emitter-side facing region Ja1 on the right side in the figure is included in the element region R0.
- the emitter-side facing region Ja0 on the right side of the emitter-side gate electrode 17 at the rightmost end in the figure is not included in the element region R0 that becomes a repeating pattern, and the emitter-side facing region Ja8 on the left side in the figure is , Is included in the element region R0.
- a total of eight emitter-side facing regions Ja1 to Ja8 are formed as emitter-side facing regions Ja of the emitter-side gate electrode 17.
- the eight emitter-side facing regions Ja1 to Ja8 are not particularly distinguished, they are simply referred to as the emitter-side facing regions Ja.
- the emitter-side gate electrode 17 according to the first embodiment is formed in a band shape in a top view, and has a length (XY) in the Y direction on the first surface fa of the substrate 5.
- the length in the extending direction of the emitter-side gate electrode 17 in the plane direction) can be defined as W.
- the length W in the Y direction which is the extension direction, is the length in the gate width direction in the emitter-side facing region Ja of the emitter-side gate electrode 17, and in the first embodiment, hereinafter, also referred to as “first facing region length”. I will write it down.
- the lengths of one emitter-side facing region Ja in the gate width direction are all W. Therefore, the total length of the first facing regions of the eight emitter-side facing regions Ja1 to Ja8 in one element region R0, which is a repeating pattern in the first embodiment, can be defined as 8 ⁇ W.
- the emitter-side gate electrode 17 and the collector-side gate electrode 27 are both extended in the Y direction shown in FIG.
- the length L1 of the emitter-side facing region is the channel length of the emitter-side gate electrode 17 extending in the Z direction different from the Y direction.
- the length L2 of the collector-side facing region is the channel length of the collector-side gate electrode 27 extending in the X direction different from the Y direction.
- the first surface fa of the substrate 5 is provided with an emitter electrode 18 formed of, for example, aluminum (Al) or copper (Cu) and covering the surface of the first surface fa and the interlayer insulating layer 16. ing.
- the emitter-side gate electrode 17 in the trench hole 14 is insulated from the emitter electrode 18 by an interlayer insulating layer 16 provided on the substrate 5.
- a contact hole 16a is formed between the adjacent interlayer insulating layers 16, and an emitter electrode 18 provided on the first surface fa of the substrate 5 is also provided in the contact hole 16a.
- the emitter electrode 18 is in contact with the emitter p layer 13, and the emitter electrode 18 is electrically connected to the emitter p - layer 11 via the emitter p layer 13.
- the interlayer insulating layer 16 is provided on the first surface fa of the substrate 5 so as to cover the entire upper surface of the emitter-side gate electrode 17 and also cover a part of the upper surface of the emitter n layer 12 adjacent to the trench hole 14. ..
- the interlayer insulating layer 16 covers not only the upper part of the emitter-side gate electrode 17 but also the emitter n-layer 12 around the emitter-side gate electrode 17, so that the emitter electrode 18 and the emitter-side gate electrode 17 are short-circuited. Is prevented.
- OL1 shown in FIG. 2A shows a region where the interlayer insulating layer 16 is formed on the first surface fa of the substrate 5.
- a buffer layer 29 is formed on the other surface 10b of the drift layer 10.
- a collector p layer 23, a collector p - layer 23a, and a collector n layer 22 serving as a second high-concentration impurity layer are formed below the buffer layer 29, a collector p layer 23, a collector p - layer 23a, and a collector n layer 22 serving as a second high-concentration impurity layer are formed.
- the collector n layer 22 is an n + type impurity layer provided between the collector electrode 28 and the collector p - layer 23a and having a higher impurity concentration than the collector p - layer 23a.
- the collector n layer 22 and the collector p - layer 23a are electrically connected to the collector electrode 28.
- the buffer layer 29 is located between the drift layer 10 and the collector p layer 23, and has a higher impurity concentration than the drift layer 10 to prevent the depletion layer from reaching the collector p layer 23. If the drift layer 10 is sufficiently thick so that the depletion layer does not reach the collector p layer 23, the buffer layer 29 may not be formed.
- the collector p - layer 23a is a p - layer having a lower impurity concentration than the collector p-layer 23.
- the impurity concentration of the collector p layer 23 and the collector n layer 22 is, for example, about 10 18 cm -3 to 10 21 cm -3
- the impurity concentration of the buffer layer 29 is, for example, 10 15 cm -3 to 10 18 cm. It is about -3 .
- the collector p - layer 23a is a p - layer having a lower impurity concentration than the collector p-layer 23 formed by, for example, ion implantation. Further, on the second surface fb, the collector n layer 22 is formed in the collector p layer 23. The collector n layer 22 is formed in a partial region on the second surface fb side of the substrate 5 so as to straddle the collector p - layer 23a and the collector p layer 23.
- the collector p layer 23 on the second surface fb of the substrate 5 is formed in a band shape in the bottom view, and is arranged so as to extend in the Y direction on the second surface fb.
- the collector p - layer 23a and the collector n layer 22 formed in a band shape are sequentially arranged in the bottom view, and these collector p - layer 23a and the collector n layer 22 are second. It is arranged so as to extend in the Y direction on the surface fb.
- a planar type collector-side gate electrode 27 and a collector-side gate insulating film formed on the upper surface of the collector-side gate electrode 27 are formed on the second surface fb of the substrate 5.
- the gate insulating film 25 and the collector electrode 28 are provided.
- the planar type collector-side gate electrode 27 arranged on the surface of the second surface fb (the XY plane of the second surface fb) of the substrate 5 via the gate insulating film 25 is, for example, polycrystalline silicon (polysilicon).
- a collector-side gate wiring (not shown) is connected to the collector-side gate electrode 27, and a predetermined gate voltage Vgg2 is applied via the collector-side gate wiring.
- the collector-side gate electrode 27 has a second facing region (hereinafter referred to as a collector-side facing region) Jb which is arranged to face the collector p - layer 23a of the second surface fb via the gate insulating film 25.
- a collector-side facing region Jb which is arranged to face the collector p - layer 23a of the second surface fb via the gate insulating film 25.
- one collector-side gate electrode 27 is provided in the element region R0 that becomes a repeating pattern, and two collector-side facing regions Jb1 and Jb2 are provided in the element region R0.
- the two collector-side facing regions Jb1 and Jb2 are not particularly distinguished, they are simply referred to as collector-side facing regions Jb.
- the collector-side gate electrode 27 As shown in FIG. 2B, the collector-side gate electrode 27 according to the first embodiment is formed in a band shape in a bottom view, and has a length (X) in the Y direction on the second surface fb of the substrate 5.
- the length in the extension direction of the collector side gate electrode 27 in the Y-plane direction) can be defined as W.
- the length W in the Y direction, which is the extension direction is the length in the gate width direction in the collector-side facing region Jb of the collector-side gate electrode 27, and in the first embodiment, hereinafter, also referred to as “second facing region length”. I will write it down. Therefore, in one element region R0 which is a repeating pattern in the first embodiment, the total of the second opposed region lengths of the two collector-side facing regions Jb1 and Jb2 can be defined as 2 ⁇ W.
- the gate insulating film 25 provided on the second surface fb of the substrate 5 is arranged on the collector-side gate electrode 27, and the interlayer insulating layer 26 is formed below and to the side of the collector-side gate electrode 27.
- the collector-side gate electrode 27 is entirely covered with the gate insulating film 25 and the interlayer insulating layer 26.
- the second surface fb of the substrate 5 is provided with a collector electrode 28 formed of, for example, aluminum (Al) or copper (Cu) and covering the surface of the second surface fb and the interlayer insulating layer 26. ..
- the collector electrode 28 is adjacent to the collector n layer 22 and the collector p layer 23, and is electrically connected to the collector n layer 22 and the collector p layer 23.
- the collector-side gate electrode 27 is insulated from the buffer layer 29 and the collector p - layer 23a by the gate insulating film 25 provided on the second surface fb of the substrate 5.
- the total length of the first opposed regions of the emitter-side opposed regions Ja1 to Ja8 is defined as 8 ⁇ W, and the collector-side opposed regions Jb1 and Jb2 are defined. It is configured to be longer than the total of 2 ⁇ W of the second facing region length of.
- the emitter-side gate electrode 17 on the first surface fa is arranged at a higher density than the collector-side gate electrode 27 on the second surface fb.
- the ratio of the total of the first facing region lengths in the element region R0 and the total of the second facing region lengths when the total of the second facing region lengths in the element region R0 is 1. It is called the gate density ratio.
- the gate density ratio Ja: Jb is 4: 1, that is, the total of the first facing region lengths is four times the total of the second facing region lengths.
- the total length of the first facing region is four times the total length of the second facing region is described, but the present invention is not limited to this, and the first facing region is not limited to this.
- the total of the region lengths may be longer than the total of the second facing region lengths, and the total of the first facing regions may be, for example, twice or more or more than twice the total of the second facing region lengths, and further four times or more. It may be long.
- the gate density ratio Ja: Jb is more than 1 to less than 8: 1. Further, the gate density ratio Ja: Jb is preferably in the range of 2: 1 to 7: 1, more preferably in the range of 3: 1 to 5: 1. It has been confirmed from the simulation results that by setting the gate density ratio Ja: Jb in this way, it is possible to reduce the switching loss at the time of turn-off while suppressing the loss at the time of conduction during the on / off operation of the semiconductor device 1. Details will be described later.
- the total length of the first facing region and the total length of the second facing region in the element region R0 are compared to adjust the conduction loss and the switching loss. ing.
- the driving force of the semiconductor device is proportional to the gate width of the gate electrode, and the driving force is adjusted between the first surface fa (upper surface) and the second surface fb (lower surface) of the semiconductor device 1. It is what is done. Further, the driving force becomes stronger as the gate length becomes shorter, but the influence on the driving force due to the difference in the lengths L1 and L2 with respect to the gate length is sufficiently smaller than the gate width W and can be ignored.
- the length L1 and the length shown in FIGS. 1, 2 (a), and 2 (b) are shown.
- the L2 may be designed to be longer or shorter, and the driving force may be further adjusted between the emitter side and the collector side.
- the emitter n layer 12 and the drift layer 10 are excessive at the timing when the collector n layer 22 and the drift layer 10 conduct with each other, the injection of electrons into the drift layer 10 is stopped and the emitter p from the drift layer 10. -Hole is discharged to layer 11.
- the on operation and the off operation will be described in detail.
- the semiconductor device 1 is formed with an inverted layer (n-channel) La in the emitter p - layer 11 along the emitter-side facing region Ja.
- the emitter n layer 12 and the drift layer 10 are in a conductive state by the inversion layer La, and electrons are injected from the emitter n layer 12 to the drift layer 10 via the inversion layer La.
- the on-voltage applied to the emitter-side gate electrode 17 may be a positive voltage with respect to the emitter electrode 18.
- a gate voltage Vgg2 (off voltage) having a low (for example, 0V) different from the gate voltage Vgg1 is applied to the collector side gate electrode 27, so that the collector p - layer is passed through the gate insulating film 25.
- the inverted layer Lb (n channel) is not formed in the collector p - layer 23a along the collector-side facing region Jb of the collector-side gate electrode 27 facing the 23a. Therefore, in the semiconductor device 1, the collector n layer 22 and the buffer layer 29 are insulated and become non-conducting, and the pn junction formed by the collector p layer 23 and the buffer layer 29 is forward biased.
- holes are injected from the collector p layer 23 into the drift layer 10 via the buffer layer 29 by the forward bias of the pn junction formed by the collector p layer 23 and the buffer layer 29.
- the collector n layer 22 and the drift layer 10 are electrically connected via the buffer layer 29, the conduction and non-conduction between the collector n layer 22 and the buffer layer 29 are the collector n layer 22. It is synonymous with conduction and non-conduction with the drift layer 10.
- the gate voltage Vgg2 different from the above-mentioned gate voltage Vgg1 is not limited to 0V, and may be, for example, a negative voltage, and is positive to the extent that an inversion layer is not formed under the collector-side gate electrode 27. It may be the voltage of. That is, the gate voltage Vgg1 and the gate voltage Vgg2 applied at the same time may be such that an inversion layer is formed in one of the emitter-side and collector-side facing regions and the inversion layer is not formed in the other facing region.
- the on-voltage of the semiconductor device 1 corresponds to the voltage drop between the collector electrode 28 and the emitter electrode 18 at the time of on.
- the low gate voltage Vgg1 is applied to the emitter-side gate electrode 17 as an off voltage
- the high gate voltage Vgg2 is applied to the collector-side gate electrode 27 as an on-voltage to the semiconductor device 1.
- the inverted layer (n channel) La formed in the emitter p - layer 11 along the emitter-side facing region Ja is not formed in the semiconductor device 1, and the emitter n layer 12 and the drift layer 10 are separated from each other. It becomes a non-conducting state.
- the semiconductor device 1 stops injecting electrons from the emitter n layer 12 into the drift layer 10 due to the disappearance of the inversion layer during the off operation.
- the on-voltage applied to the collector-side gate electrode 27 may be a positive voltage with respect to the collector electrode 28.
- the collector side gate electrode 27 when the collector side gate electrode 27 is applied with the high gate voltage Vgg2 during the off operation, the high gate voltage Vgg2 is applied to the collector p - layer 23a along the collector side facing region Jb.
- the inverted layer Lb is formed on the surface.
- the buffer layer 29 and the collector p layer 23 become equipotential through the inversion layer Lb, and the injection of holes from the collector p layer 23 into the drift layer 10 is stopped around the collector side gate electrode 27b.
- the electrons accumulated in the drift layer 10 are discharged from the buffer layer 29 to the collector n layer 22 via the inversion layer Lb, and further discharged from the collector n layer 22 to the collector electrode 28. Further, the holes in the drift layer 10 are discharged to the emitter electrode 18 via the emitter p ⁇ layer 11 and the emitter p layer 13. Further, the pn junction between the emitter p - layer 11 and the drift layer 10 becomes a depletion layer, and the semiconductor device 1 is turned off.
- the inverted layer La formed in the emitter p - layer 11 when the semiconductor device 1 is turned on is formed in the emitter p - layer 11 along the emitter-side facing region Ja. Further, the inverted layer Lb formed in the collector p - layer 23a during the off operation of the semiconductor device 1 is formed in the collector p - layer 23a along the collector-side facing region Jb.
- the total of the first facing regions of the emitter-side facing regions Ja1 to Ja8 in one element region R0 that becomes a repeating pattern is the second facing region of the collector-side facing regions Jb1 and Jb2. It is configured to be longer than the total length. Therefore, in the semiconductor device 1, the total length in the gate width direction of the inverted layer La formed along the emitter-side facing region Ja in the element region R0 during the on operation is combined with the collector p - layer 23a during the off operation. It can be longer than the total length in the gate width direction of the inverted layer Lb formed inside the collector-side facing region Jb.
- the semiconductor device 1 makes the total length of the first facing regions of the emitter-side facing region Ja longer than the total length of the second facing region of the collector-side facing region Jb in the element region R0 (that is, the gate density ratio Ja). : Make the Ja value of Jb larger than the Jb value) to make the total length of the inverted layer La in the emitter p - layer 11 in the gate width direction the sum of the lengths of the inverted layer Lb in the collector p - layer 23a. It is configured to be longer than the total length in the gate width direction, and as a result, the switching loss at the turn-off is reduced while suppressing the loss at the time of conduction.
- FIGS. 4 (a) and 4 (b) show the evaluation circuit used in the simulation.
- the evaluation circuit shown in FIG. 4A is a comparative example, and shows a circuit configuration of a single-sided IGBT in which the emitter-side gate electrode 17 is provided and the collector-side gate electrode 27 is not provided.
- the evaluation circuit shown in FIG. 4B shows the circuit configuration of the semiconductor device 1 according to the first embodiment.
- the inductance L as a load and the diode FWD1 Free Wheeling Diode
- the IGBT unit Tr1 and the diode FWD2 are connected in parallel
- the FWD1 and FWD2 are devices that return the energy stored in the inductance L to the power supply Vdc side when the IGBT unit Tr1 is turned off.
- a power supply Vdc is connected to one end of the inductance L and the diode FWD1.
- the IGBT unit Tr1 has a gate terminal G corresponding to the emitter-side gate electrode 17, a collector terminal C corresponding to the collector electrode 28, and an emitter terminal E corresponding to the emitter electrode 18, and turns the gate on or off.
- the pulse voltage is applied to the gate terminal G via the resistor Rg as the gate voltage Vgg1.
- the inductance L and the other end of the diode FWD1 are connected to the collector terminal C, and one end of the diode FWD1 is connected to the collector terminal C.
- the other end of the diode FWD2 and the ground are connected to the emitter terminal E.
- Vce indicates the voltage between the emitter terminal E and the collector terminal C.
- the evaluation circuit shown in FIG. 4 (b) has a different configuration from the evaluation circuit of FIG. 4 (a) and the IGBT unit Tr2 . Since the other configurations are the same as the evaluation circuit of FIG. 4A, the description thereof will be omitted.
- the IGBT unit Tr2 is provided with an emitter-side gate terminal G1 corresponding to the emitter-side gate electrode 17 and a collector-side gate terminal G2 corresponding to the collector-side gate electrode 27.
- the collector terminal G2 is connected to the collector terminal C via a resistor Rg or the like.
- the gate voltage Vgg1 was applied to the emitter-side gate terminal G1 via the resistance Rg1 and the gate voltage Vgg2 was applied to the collector-side gate terminal G2 via the resistance Rg2 alternately.
- FIG. 5A is a diagram showing simulation results for investigating the relationship between the gate density ratio Ja: Jb and the switching loss.
- the horizontal axis of FIG. 5A shows the gate density ratio, and the vertical axis shows the minimum value (mJ) of the switching loss in FIG.
- the switching loss is energy consumed in one switching, and decreases as the voltage is applied to the semiconductor device 1 due to the steep switching and the time during which the current flows is shortened.
- the switching frequency can be increased by reducing the switching loss.
- FIG. 5B is a diagram showing simulation results for investigating the relationship between the gate density ratio Ja: Jb and the on-voltage drop.
- the horizontal axis of FIG. 5B shows the gate density ratio, and the vertical axis shows the on-voltage drop (V).
- the on-voltage drop is a physical quantity related to the conduction loss of the IGBT, and the smaller the on-voltage drop is, the smaller the conduction loss is.
- S shown in FIGS. 5 (a) and 5 (b) shows the simulation results in the evaluation circuit of FIG. 4 (a) in which the gate electrode is provided only on one side of the substrate 5. Further, D shown in FIGS. 5A and 5B shows a simulation result of an evaluation circuit having gate electrodes on both sides of the substrate 5 shown in FIG. 4B.
- the switching loss was about 185 mJ.
- the switching loss is about 27 mJ when the gate density ratio is 1: 1 and switching when the gate density ratio is 2: 1.
- the loss was about 30mJ.
- the switching loss increases and the gate density ratio increases.
- the switching loss is about 68 mJ
- the gate density ratio is 8: 1
- the switching loss is about 122 mJ. From the results shown in FIG. 5A, it was confirmed that in the evaluation circuit showing the semiconductor device 1 according to the first embodiment, the switching loss is smaller than that in the comparative example regardless of the gate density ratio.
- the above characteristics shorten the value of Ja in the gate density ratio Ja: Jb, that is, the total length of the emitter-side facing region Ja in the gate width direction, in other words, the length of the collector-side facing region Jb in the gate width direction. It is considered that this is because the effect of discharging electrons from the drift layer 10 is enhanced by making the total of the above relatively long, and the loss is reduced by increasing the switching speed.
- the on-voltage drop of the comparative example was about 1.66V.
- the on-voltage drop is about 2.06 V when the gate density ratio is 1: 1 and the on-voltage drop is about about when the gate density ratio is 2: 1. It became 1.86V.
- the above characteristic is to reduce the value of the collector-side facing region Jb with respect to the emitter-side facing region Ja in the gate density ratio Ja: Jb, that is, to make the ratio of the region of the collector p layer 23 contributing to hole emission relatively relative to each other. It is thought to be caused by increasing the size.
- Gate density ratio Ja When the value of Jb in Jb, that is, the total length of the collector side facing region Jb in the gate width direction becomes long, the hole injection area on the collector side decreases and the resistance of the drift layer 10 increases. be.
- the gate density ratio Ja: Jb is set from more than 1 to 1. Less than 8: 1, preferably the gate density ratio Ja: Jb in the range of 2: 1 to 7: 1, more preferably in the range of 3: 1 to 5: 1. Was confirmed.
- the gate density ratio Ja: Jb is changed, and the gate terminal G1 on the emitter side is used when the evaluation circuit of the semiconductor device 1 is switched from the on state to the off state.
- the switching loss when the off voltage was applied and the on voltage was applied to the collector side gate terminal G2 were investigated by simulation. As a result, the simulation result as shown in FIG. 6 was obtained.
- the vertical axis of FIG. 6 shows the switching loss (mJ), and the horizontal axis shows the collector side gate-on timing ( ⁇ s).
- the collector side gate on timing indicates the timing of applying the on voltage to the collector side gate terminal G2 with reference to the timing of applying the off voltage to the emitter side gate terminal G1.
- the negative value on the horizontal axis indicates that the timing of applying the on voltage to the collector side gate terminal G2 is earlier than the timing of applying the off voltage to the emitter side gate terminal G1.
- the positive value on the horizontal axis indicates that the timing of applying the on voltage to the collector side gate terminal G2 is later than the timing of applying the off voltage to the emitter side gate terminal G1.
- the timing of applying the on voltage to the collector side gate terminal G2 is the timing to apply the off voltage to the emitter side gate terminal G1. It was confirmed that the switching loss increased sharply when it was earlier than the timing. It is considered that such a phenomenon occurs because the carriers in the drift layer 10 are rapidly reduced by applying the on voltage to the collector side gate terminal G2, and the semiconductor device 1 is driven in a state of high resistance.
- the gate density ratio Ja: Jb is 4: 1 or 8: 1
- the timing of applying the on voltage to the collector side gate terminal G2 is earlier than the timing of applying the off voltage to the emitter side gate terminal G1.
- the reason for this is that if the total length of the collector-side facing region Jb in the gate width direction is shorter than the total length of the emitter-side facing region Ja in the gate width direction, it is sufficient to stop the conductivity modulation.
- the hole injection suppressing effect cannot be obtained, and even if the gate voltage Vgg2 is turned on earlier than the gate voltage Vgg1, the hole injection into the drift layer 10 does not stop completely, and the resistance of the drift layer 10 increases extremely and is large. This is considered to be because it is possible to avoid the occurrence of switching loss.
- FIG. 7A (a) to 7A (c), FIG. 7B (d), and FIG. 7B (e) are diagrams for explaining an example of a manufacturing method for manufacturing the semiconductor device 1 of the first embodiment.
- impurities are injected into a bare substrate made of single crystal silicon to form a substrate having a drift layer 10, and impurities are sequentially injected into the bare substrate to form a substrate 5 (FIG. 7B (d)).
- the emitter p - layer 11 is a p - layer having a relatively low impurity concentration.
- the emitter n layer 12 is an n + layer having a relatively high concentration with respect to the emitter p ⁇ layer 11.
- the emitter p layer 13 is a p + layer having a relatively high concentration with respect to the emitter p ⁇ layer 11.
- the buffer layer 29 is an n-layer having a relatively high concentration with respect to the drift layer 10.
- the emitter p - layer 11, the emitter n layer 12, the emitter p layer 13, the collector p layer 23 and the buffer layer 29 can be formed by, for example, ion implantation.
- a trench hole 14 is formed from the emitter n layer 12 on the first surface fa, penetrating the emitter p ⁇ layer 11 and reaching the drift layer 10.
- the formation of the trench hole 14 can be performed by photolithography.
- the gate insulating film 15 is formed on the inner surface of the trench hole 14.
- the gate insulating film 15 is formed by forming an insulating film on the entire surface of the wafer in the state shown in FIG. 7A (b).
- polysilicon is filled from above the gate insulating film 15 of the trench hole 14, and the emitter-side gate electrode 17 is formed in the trench hole 14.
- n-type impurities are injected into the collector p layer 23 at a high concentration to form the collector n layer 22 from the collector p layer 23 around the collector side gate electrode 27 to the collector p - layer 23a.
- the substrate 5 is completed by the above steps.
- an interlayer insulating layer 16 is formed on the emitter-side gate electrode 17, a contact hole is formed by photolithography, and a metal is formed on the first surface fa of the substrate 5. Is deposited to form the emitter electrode 18. Similarly, the interlayer insulating layer 26 is formed around the collector side gate electrode 27, a contact hole is formed by photolithography, and metal is deposited on the second surface fb of the substrate 5 to form the collector electrode 28.
- the semiconductor device 1 of the first embodiment can be manufactured.
- the semiconductor device 1 is not manufactured only by the method described above.
- the method and conditions of the manufacturing process are appropriately selected depending on the design of the semiconductor device 1 and the required conditions.
- FIG. 8 is a cross-sectional view showing the configuration of the semiconductor device 2 of the first modification.
- FIG. 9A is a cross-sectional view of the cross-sectional portion of the semiconductor device 2 shown in FIG. 8 along the line IXa-IXa as viewed from above to below.
- FIG. 9B is a cross-sectional view of the cross-sectional portion of the semiconductor device 2 along the line IXb-IXb as viewed from below to above.
- FIG. 8 is a configuration in which the emitter electrode 18 and the collector electrode 28 are provided in FIGS. 9 (a) and 9 (b), and is viewed from the position of the line VIII-VIII shown in FIG. 9 (a).
- the side cross-sectional structure of the semiconductor device 2 is shown.
- five trench holes 14 are formed in the element region R0, and a dummy is formed in the trench holes 14a at the rightmost end and the leftmost end in FIG. 8 via a gate insulating film 15.
- a gate electrode 17a is formed, and an emitter-side gate electrode 17 is formed in the remaining central three trench holes 14 via a gate insulating film 15, and the dummy gate electrode 17a may be short-circuited with the emitter layer 11. preferable.
- the emitter n layer 12 and the emitter p layer 13 are formed on the first surface fa between the three central emitter-side gate electrodes 17, respectively, and between the dummy gate electrode 17a and the emitter-side gate electrode 17.
- the emitter p - layer 11 is covered with the interlayer insulating layer 16 without forming the emitter n layer 12 and the emitter p layer 13 on the first surface fa.
- OL3 in FIG. 9A indicates the length of each interlayer insulating layer 16 in the X direction.
- the emitter-side gate electrode 17 faces the emitter p - layer 11 via the gate insulating film 15 in the element region R0.
- the emitter-side facing regions Ja four emitter-side facing regions Ja11 to Ja14 are provided as emitter-side facing regions Ja that form an inverted layer in the emitter p - layer 11 along the emitter-side facing region Ja. There is.
- the emitter n layer 12 is not formed on the first surface fa of the substrate 5 in the inverted layer formed on the emitter side facing region Ja10 side of the emitter side gate electrode 17 facing the dummy gate electrode 17a. No electrons are injected into the inverted layer.
- the emitter-side facing region Ja here refers to the emitter-side facing regions Ja11 to Ja14 in which the inverted layer is formed and the formed inverted layer is connected to the emitter electrode via the emitter n layer 12.
- the first facing region in the first embodiment does not include those having no emitter n layer 12 for electrically connecting to the emitter electrode 18.
- the length of the emitter-side facing region Ja in the Y direction is W
- the total of the first facing region lengths of the four emitter-side facing regions Ja11 to Ja14 in one element region R0 which is a repeating pattern is It becomes 4W.
- the first modification in the element region R0, only the three emitter-side gate electrodes 17 may be formed without forming the dummy gate electrode 17a. Due to the microloading effect, the etching rate and selection ratio may vary between the center and the periphery of the element region R0. In the first modification, in order to suppress such variation, a dummy gate electrode 17a that does not contribute to the formation of the inversion layer is also formed, and the density of the dummy gate electrode 17a and the emitter-side gate electrode 17 in the element region R0 is uniform. I have to.
- the semiconductor device 2 according to the first modification is realized by changing the mask for injecting the impurity layer to be the emitter n layer 12 and the emitter p layer 13 and the mask for forming the contact hole. can do.
- the semiconductor device 2 according to the first modification is different from the first embodiment in that the trench type collector side gate electrode 27 is provided on the second surface fb of the substrate 5.
- one trench hole 14b is formed in the element region R0 from the second surface fb through the collector n layer 22, the collector p - layer 23a, and the buffer layer 29 to reach the drift layer 10. ..
- a trench-type collector-side gate electrode 27 is provided in the trench hole 14b via a gate insulating film 25. However, the collector-side gate electrode 27 may not penetrate the buffer layer 29.
- a collector p - layer 23a is formed between the collector p layer 23 and the buffer layer 29, and the collector p layer 23 has collector n layers on both side surfaces of the trench hole 14b along the trench hole 14b. 22 is formed.
- the gate insulating film 25 is formed along the two sides of the strip-shaped collector-side gate electrode 27 in the longitudinal direction in the bottom view, and is not adjacent to the collector-side gate electrode 27 of the gate insulating film 25.
- the collector n layer 22 is formed on the opposite side.
- An interlayer insulating layer 26 is provided under the collector side gate electrode 27. Further, collector electrodes 28 are provided on the collector n layer 22, the collector p layer 23, and the interlayer insulating layer 26 arranged on the second surface fb of the substrate 5.
- the structure in which the collector side gate electrode 27 is a trench type is advantageous in increasing the area of the collector p layer 23 into which holes are injected. Further, by lengthening the collector p - layer 23a in the Z direction orthogonal to the second surface fb, the size of the inversion layer formed in the collector p layer 23 can be determined, so that the inversion layer related to electron emission can be determined. It is possible to increase the degree of freedom in designing the collector-side facing region Jb whose size can be specified.
- the length of the collector-side facing region Jb (second facing region length) in the Y direction is W
- the second of the two collector-side facing regions Jb10 and Ja11 in one element region R0 which is a repeating pattern.
- the total length of the facing regions is defined as 2.W.
- the total length of the first facing region is longer than the total length of the second facing region in the element region R0, as in the first embodiment described above.
- the total length of the inverted layer in the emitter p - layer 11 in the gate width direction is longer than the total length of the inverted layer in the collector p - layer 23a in the gate width direction.
- FIG. 10 is a cross-sectional view for explaining the configuration of the semiconductor device 3 of the second modification.
- FIG. 11A is a cross-sectional view of the cross-sectional portion of the semiconductor device 3 shown in FIG. 10 along the line XIa-XIa as viewed from above to below.
- FIG. 11B is a cross-sectional view of the cross-sectional portion of the semiconductor device 3 along the line XIb-XIb as viewed from below to above.
- FIG. 10 is a configuration in which the emitter electrode 18 and the collector electrode 28 are provided in FIGS. 11 (a) and 11 (b), and is viewed from the position of lines XX shown in FIG. 11 (a).
- the side cross-sectional structure of the semiconductor device 3 is shown.
- the semiconductor device 3 is provided with five emitter-side gate electrodes 17 on the first surface fa. A total of 10 emitter-side facing regions are formed in the five emitter-side gate electrodes 17. However, since the element region R0 of the semiconductor device 3 does not include the emitter-side facing regions Ja0 and Ja0 of the emitter-side gate electrodes 17 at the rightmost end and the leftmost end in FIG. 10, the element region R0 includes the element region R0. Has eight emitter-side facing regions Ja21 to Ja28. Assuming that the length of the emitter-side facing region Ja in the Y direction is W, the total of the first facing region lengths of the eight emitter-side facing regions Ja21 to Ja28 in one element region R0 that forms a repeating pattern is 8. It becomes W.
- collector-side facing regions Jb21 and Jb22 are formed on the collector-side gate electrode 27 on the second surface fb of the semiconductor device 3. Therefore, the total of the second facing region lengths of the two collector-side facing regions Jb21 and Jb22 in one element region R0 is 2.W.
- the first facing region Ja of the emitter side facing region Ja in the element region R0 is set to 1.
- the ratio (gate density ratio) Ja: Jb between the total of the region lengths and the total of the second facing region lengths of the collector side facing regions Jb is 4: 1 is described.
- the semiconductor device 3 is provided with a trench-type collector-side gate electrode 27 on the second surface fb.
- the semiconductor device 3 differs from the semiconductor device 2 in that the collector p - layer 23a is formed in the buffer layer 29.
- the semiconductor device 3 is formed with one trench hole 14b that reaches the drift layer 10 from the second surface fb through the collector n layer 22, the collector p - layer 23a, and the buffer layer 29.
- a trench-type collector-side gate electrode 27 is provided in the trench hole 14b via a gate insulating film 25. However, the collector-side gate electrode 27 may not penetrate the buffer layer 29.
- the semiconductor device 3 is a semiconductor device in that the emitter n layer 12 and the emitter p layer 13 are alternately formed in the gate width W direction (Y direction) of the emitter side gate electrode 17. It is different from 1 and 2. According to such a configuration, the pattern of the emitter n layer 12 and the emitter p layer 13 can be widened, and the manufacturing of the semiconductor device 3 can be facilitated.
- the total length of the emitter-side facing region Ja in the gate width direction in the element region R0 is the gate of the collector-side facing region Jb.
- the total length in the gate width direction of the inverted layer in the emitter p - layer 11 is the length in the gate width direction of the inverted layer in the collector p - layer 23a.
- the first embodiment is not limited to the configuration described above.
- the case where the emitter-side gate electrode 17 is a trench-type gate electrode formed in the trench hole 14 formed on the first surface fa of the substrate 5 has been described. Is not limited to this, and the emitter-side gate electrode 17 may be used as a planar type gate electrode.
- the planar type emitter-side gate electrode formed on the emitter side refers to a gate electrode arranged on the surface of the first surface fa via an insulating film serving as a gate insulating film.
- the collector-side gate electrode 27 may be a planar type gate electrode, or may be a trench-type collector-side gate electrode formed in the trench hole of the second surface fb. .. Further, the trench type gate electrode and the planar type gate electrode may be mixedly formed on the first surface fa and the second surface fb of the substrate 5.
- all of the configurations described above include one collector-side gate electrode 27 in the element region R0, but the first embodiment is not limited to one that has one collector-side gate electrode 27, and the element is not limited to one.
- the region R0 may be provided with a plurality of collector-side gate electrodes 27.
- the first embodiment is not limited to the example in which a plurality of emitter-side gate electrodes 17 are provided in the element region R0, and one emitter-side gate electrode 17 may be provided in the element region R0.
- the emitter-side gate electrode 17 and the collector-side gate electrode 27 are not limited to having the same length in the gate width direction (that is, the Y direction), and may have different gate widths from each other. good.
- the element region R0 does not necessarily have to be formed periodically and repeatedly in the entire region of the main region R1 of the element (FIGS. 15A and 15B). Further, the first embodiment may be provided with another impurity layer or other element as appropriate depending on the design and application of the semiconductor device.
- the semiconductor device may have a configuration in which the configuration of the first embodiment, the configuration of the first modification, the configuration of the second modification, and the configuration of the third modification are appropriately combined.
- semiconductor device 1 of the first embodiment the semiconductor device 2 of the first modification, and the semiconductor device 3 of the second modification described above are not limited to those driven by the above operation.
- semiconductor device 1 and the like are diagrams showing the voltage Vce between the emitter electrode 18 and the collector electrode 28 related to the turn-on and turn-off of the semiconductor device 1 and the like, and the collector current Ic flowing through the collector electrode 28, respectively.
- FIG. 12A shows the voltage Vce and the collector current Ic at the time of turn-on of the semiconductor device 1 and the like
- FIG. 12B shows the voltage Vce and the collector current Ic at the time of turn-off of the semiconductor device 1 and the like.
- FIG. 12 (c) is a diagram for explaining the voltage applied to the emitter-side gate electrode 17 and the collector-side gate electrode 27 at the time of turn-on shown in FIG. 12 (a).
- FIG. 12 (d) is a diagram for explaining the gate voltage applied to the emitter-side gate electrode 17 and the collector-side gate electrode 27 at the time of turn-off shown in FIG. 12 (b). Note that FIGS. 12 (c) and 12 (d) are timing charts of what has been described as the operation of the semiconductor device 1 and the like described above.
- the horizontal axis indicates time and the vertical axis indicates voltage or current.
- the solid line in FIGS. 12 (a) and 12 (b) indicates the voltage Vce, and the broken line indicates the collector current Ic.
- the horizontal axis represents time and the vertical axis represents voltage.
- the solid line in FIGS. 12 (c) and 12 (d) shows the gate voltage Vgg1 applied to the emitter-side gate electrode 17, and the broken line shows the gate voltage Vggg2 applied to the collector-side gate electrode 27.
- the semiconductor device 1 and the like are switched from the off state to the on state at the time of turn-on.
- the gate voltage Vgg2 is applied to the collector side gate electrode 27 in the off state, and is constant between the emitter side gate electrode 17 and the collector side gate electrode 27.
- the voltage Vce is applied.
- the gate voltage Vgg2 becomes 0V at the timing Tsw of switching to the ON state, and the gate voltage Vgg1 is applied to the emitter-side gate electrode 17 instead.
- the resistance of the drift layer 10 is lowered by turning on the gate electrode 17 on the emitter side, and the voltage Vce starts falling and takes a constant minimum value near 0V.
- the collector current Ic takes a constant maximum value in the on state of the semiconductor device 1 or the like.
- the semiconductor device 1 and the like are switched from the on state to the off state at the time of turn-off.
- the gate voltage Vgg1 is applied to the emitter-side gate electrode 17 in the ON state, and the voltage Vce takes a constant minimum value.
- the gate voltage Vgg1 becomes 0V at the timing Tsw of switching to the off state, and the gate voltage Vgg2 is applied to the collector side gate electrode 27 instead.
- the drift layer 10 has a high resistance, and the voltage Vce starts to rise and takes a constant maximum value.
- FIGS. 12 (c) and 12 (d) explain the gate voltage Vgg1 applied to the emitter-side gate electrode 17 and the gate voltage Vgg2 applied to the collector-side gate electrode 27 at the time of turn-on. It is a figure to do.
- the gate voltage Vgg1 is applied to the emitter-side gate electrode 17 at the same timing as the gate voltage Vgg1 shown in FIG. 12 (c). .. FIG.
- 13A is a diagram showing an example of an operation in which the gate voltage Vgg2 of the collector side gate electrode 27 is 0V (0 bias) when the semiconductor device 1 or the like is turned off.
- the semiconductor device 1 and the like perform the same operation as the single-type IGBT without the collector-side gate electrode 27.
- the collector-side gate electrode 27 is provided.
- the area of the collector p - layer 23 that contributes to the hole injection is reduced. Therefore, when the gate voltage Vgg1 and the gate voltage Vgg2 shown in FIG. 13A are applied to the semiconductor device 1 or the like, the loss during conduction may be larger than that of the single-type IGBT.
- FIG. 13B shows an example of an operation in which the collector-side gate electrode 27 is set to 0 bias when the semiconductor device 1 or the like is turned off, while a negative gate voltage Vgg2 is applied to the collector-side gate electrode 27 when the semiconductor device 1 or the like is turned on. It is a figure which shows. According to such an operation, the collector p - layer 23a under the collector side gate electrode 27 contributes to the injection of holes into the drift layer 10, and the loss during conduction of the semiconductor device 1 or the like can be reduced. can.
- FIG. 13 (c) shows that the collector-side gate electrode 27 is set to 0 bias when the semiconductor device 1 or the like is turned off, while the negative gate voltage Vgg2 is applied to the collector-side gate electrode 27 when the semiconductor device 1 or the like is turned on in FIG. 13 (b).
- Vgg2 negative gate voltage
- FIG. 14A is a diagram showing an example of an operation in which a positive gate voltage Vgg2 is applied to the collector side gate electrode 27 before the timing at which the gate voltage Vgg1 falls at the time of turn-off of the semiconductor device 1 or the like.
- the gate voltage Vgg1 is applied to the emitter-side gate electrode 17 at the same timing as the gate voltage Vgg1 shown in FIG. 12D.
- the injection of holes from the collector p layer 23 to the drift layer 10 is suppressed before the semiconductor device 1 or the like is turned off, and the gate voltage Vgg1 is turned off until the collector current Ic reaches the minimum value. Time can be shortened, that is, the switching loss can be reduced.
- FIG. 14B is a diagram showing an example of an operation in which the gate voltage Vgg1 applied to the emitter-side gate electrode 17 switches from positive to negative when the semiconductor device 1 or the like is turned off.
- the gate voltage Vgg2 applied to the collector-side gate electrode 27 is applied to the collector-side gate electrode 27 at the same timing as the gate voltage Vgg2 shown in FIG. 12 (d). ..
- the inversion layer La formed in the emitter-side facing region Ja of the collector-side gate electrode 27 disappears at an early stage, and the injection of electrons into the drift layer 10 at the time of turn-off can be suppressed immediately. can. Therefore, in the operation example shown in FIG. 14B, the switching loss of the semiconductor device 1 or the like can be reduced.
- FIG. 14C shows that the gate voltage Vgg1 applied to the emitter-side gate electrode 17 drops to 0V or a negative voltage at the time of turn-off of the semiconductor device 1 or the like (negative voltage in the example shown in FIG. 14C).
- the positive gate voltage Vgg2 rises after the start of application of the gate voltage Vgg1 and falls to 0V at the timing before the gate voltage Vgg1 falls (turns off). According to such an operation, it is possible to suppress the injection of holes into the drift layer 10 before the semiconductor device 1 or the like turns off.
- the emitter n layer 12 and the drift layer are conductive, and the collector n layer 22 and the drift layer are non-conducting, and the emitter n layer. A state in which both the collector n layer 22 and the drift layer are conductive, between the emitter n layer 12 and the drift layer, and between the collector n layer 22 and the drift layer. Both have a non-conducting state.
- FIG. 14D shows an example of the operation in which the positive gate voltage Vgg2 is applied to the collector side gate electrode 27 after the gate voltage Vgg1 drops to 0V or a negative voltage at the time of turn-off of the semiconductor device 1 or the like. It is a figure. According to such an operation, a part of the reflux current generated in the turn-on / turn-off loop of the semiconductor device 1 or the like is passed from the emitter electrode 18 to the collector electrode 28 during the off state to support the reflux operation. Can be done.
- FIG. 15A is a schematic view showing the top surface configuration of the semiconductor chip 60 on which the semiconductor device 6 is formed when viewed from above
- FIG. 15B is a schematic view showing the top surface configuration of the semiconductor chip 60 on which the semiconductor device 6 is formed. It is a schematic diagram which shows the lower surface structure when viewed from the lower side.
- FIG. 15A in the semiconductor device 6 according to the second embodiment, the main region R1 on which the emitter electrode 18 is formed and the peripheral region Re surrounding the periphery of the main region R1 are formed on the semiconductor chip 60. It is formed. In the peripheral region Re, an FLR (Field Limiting Ring) structure or the like for relaxing the electric field in the lateral direction is formed on one surface side on which the emitter electrode 18 is formed.
- FIG. 16 is a cross-sectional view showing a side cross-sectional configuration in a region R of a boundary portion between the main region R1 and the peripheral region Re in the cross-sectional portion of the line XV-XV of the semiconductor chip 60 shown in FIG. 15 (a). ..
- the main region R1 is a region in which the above-mentioned element region R0 is formed as a repeating pattern.
- the electrodes 28 are repeatedly arranged at predetermined intervals.
- the semiconductor device 1 (FIG. 1) according to the first embodiment described above
- the semiconductor device 2 (FIG. 8) according to the first modification
- the semiconductor device 3 according to the second modification (FIG. 1). 10)
- the element region R0 of any of the semiconductor devices 4 according to the third modification is provided.
- FIG. 16 shows, for example, the formation position of the collector side gate electrode 27 is different from the element region R0 (FIG. 1) of the semiconductor device 1 according to the first embodiment
- the semiconductor device 1 according to the first embodiment has a different formation position.
- An example in which the element region R0 is provided is shown, and the description thereof will be omitted below in order to avoid duplication of description.
- an emitter-side gate wiring 18a is provided in the peripheral region Re of the semiconductor device 6, for example, so as to surround the emitter electrode 18.
- the emitter-side gate wiring 18a is electrically connected to each of the emitter-side gate electrodes 17 inside by the emitter-side gate pad 18b, and the gate voltage is applied to the emitter-side gate electrode 17.
- the peripheral region Re is a region in the main region R1 in which the emitter electrode 18 provided on the first surface fa of the substrate 5 and the emitter-side gate electrode 17 formed in the substrate 5 are not formed on the upper surface side. be.
- a collector electrode 28 is provided on the lower surface of the semiconductor chip 60 in the main region R1, and the collector electrode 28 in the main region R1 extends to the peripheral region Re. .. That is, the formation region of the collector electrode 28 provided on the lower surface side of the semiconductor chip 60 is formed larger than the formation region of the emitter electrode 18 provided on the upper surface side of the semiconductor chip 60.
- the main region R1 shown in FIG. 15 (a) is shown by a two-dot chain line.
- a collector side gate wiring 28a is provided so as to surround the collector electrode 28.
- the collector-side gate wiring 28a is electrically connected to each collector-side gate electrode 27 inside by the collector-side gate pad 28b, and a gate voltage is applied to the collector-side gate electrode 27.
- an electrode having the same potential as the collector electrode 28 may be further provided outside the collector side gate wiring 28a on the other surface side where the collector electrode 28 is provided.
- the straight line e1 shown in FIGS. 15 (a) and 15 (b) indicates the positions of one side and the other side of the collector electrode 28, which is provided on the lower surface of the semiconductor chip 60 and has a substantially square shape when viewed from the bottom surface. It shows.
- the straight line e2 shown in FIG. 15A is the position of one side and the other side facing each other in the emitter electrode 18 having a substantially square shape in the top view provided on the upper surface of the semiconductor chip 60, that is, one side of the main region R1. And the position of the other side.
- the straight line e1 along one side and the other side of the collector electrode 28 is located outside the straight line e2 along one side and the other side of the emitter electrode 18, and the collector electrode 28 formed in the main region R1 is the periphery. It extends to the region Re, and the collector electrode 28 is formed larger than the emitter electrode 18.
- the collector electrode 28 is formed large by the difference Y1 between the straight line e1 along one side of the collector electrode 28 and the straight line e2 along one side of the emitter electrode 18.
- each side constituting the four sides of the collector electrode 28 is separated by a difference Y1 from each side constituting the four sides of the emitter electrode 18, so that the collector electrode 28 is larger than the emitter electrode 18 as a whole. It is formed.
- the collector electrode 28 is formed to be larger than the emitter electrode 18 as a whole, but the present invention is not limited to this, and at least one of the four sides of the collector electrode 28 is one.
- the collector electrode 28 may be made larger than the emitter electrode 18 by separating one side from the side of the emitter electrode 18 by a difference Y1.
- the peripheral region Re is provided with the substrate 5 provided in the main region R1, and the drift layer 10 of the substrate 5 is extended. Further, the emitter p-layer 11 formed in the main region R1 is extended on the first surface fa of the substrate 5 in the peripheral region Re, and the emitter p- layer 11 is provided on the drift layer 10. There is.
- the peripheral region Re is not provided with the emitter-side gate electrode 17 on the first surface fa of the substrate 5, and is provided with a p-type impurity layer 131 having a polarity different from that of the drift layer 10.
- An insulating film 132 is formed on the first surface fa of the substrate 5 on which the emitter p - layer 11 and the p-type impurity layer 131 are formed.
- the emitter-side gate wiring 18a is arranged at a predetermined position of the insulating film 132 formed on the p-type impurity layer 131.
- the second surface fb of the substrate 5 in the peripheral region Re has the same configuration as the second surface fb of the substrate 5 in the main region R1, and has a buffer layer 29, a collector p layer 23, and a collector p - layer 23a.
- the collector n layer 22, the collector side gate electrode 27, and the like are provided.
- a plurality of collector-side gate electrodes 27 are provided in the peripheral region Re, but the collector-side gate electrodes 27 and their surrounding configurations all have the same configuration.
- the second surface fb of the substrate 5 in the peripheral region Re has the same configuration as the second surface fb of the substrate of the semiconductor device 1 according to the first embodiment described above.
- the buffer layer 29 and the collector p layer 23 provided in the main region R1 are extended in the peripheral region Re, and the collector n layer 22 and the collector p - layer 23a are formed in the collector p layer 23. Has been done.
- a part of the buffer layer 29 is exposed on the second surface fb of the substrate, and collector p - layers 23a are formed on both sides of the buffer layer 29. Further, a collector n layer 22 is formed on the second surface fb of the substrate at the boundary between the collector p - layer 23a and the collector p layer 23, and the buffer layer 29 and the collector exposed on the second surface fb of these substrates.
- a collector-side gate electrode 27 is provided below the p - layer 23a via the gate insulating film 25.
- An interlayer insulating layer 26 is provided around the collector-side gate electrode 27.
- the interlayer insulating layer 26 and the collector electrode 28 are arranged under the collector n layer 22 exposed on the second surface fb.
- the collector electrode 28 in the peripheral region Re is provided on the second surface fb so as to cover the second surface fb of the substrate and the interlayer insulating layer 26, similarly to the collector electrode 28 in the main region R1.
- the main region R1 having the element region R0 and the peripheral region Re adjacent to the main region R1 are provided.
- the emitter-side gate electrode 17 formed in the main region R1 is not formed in the peripheral region Re, and the buffer layer 29, the collector p layer 23, the collector p - layer 23a, and the collector n provided in the main region R1 are not formed.
- the layer 22, the collector-side gate electrode 27, and the collector electrode 28 are formed.
- the semiconductor device 6 when the semiconductor device 6 is on, not only in the main region R1 but also in the peripheral region Re, a forward bias is applied between the collector p layer 23 and the buffer layer 29 due to the positive voltage. And holes can be injected into the drift layer 10. At this time, in the semiconductor device 6, holes can be injected into the drift layer 10 not only from the main region R1 but also from the peripheral region Re, so that the holes are injected into the drift layer 10 only from the main region R1. More holes can be injected into the drift layer 10.
- the difference Y1 between the side of the collector electrode 28 and the side of the emitter electrode 18 is preferably about the thickness of the substrate 5 or more.
- the reason is that the conductivity modulation region formed by the collector electrode 27 extends from the end of the emitter electrode 18 toward the substrate surface by about the thickness of the substrate 5, so that the second of the range in which the conductivity modulation region expands. This is because it is desirable to provide the collector electrode 27 on the surface fb in order to prevent an increase in conduction loss.
- the second embodiment it is possible to efficiently stop the injection of holes from the peripheral region Re to the drift layer of the main region R1 and reduce the switching loss at the time of turn-off of the semiconductor device 6.
- the p-type is the first conductive type and the n-type is the second conductive type, but the present invention is not limited to this, and the p-type is the second conductive type and the n-type is the second conductive type. It may be a conductive type.
- the collector p - layer 23a having a lower impurity concentration than the collector p layer 23 is separately provided as the impurity layer
- the present invention is not limited to this, and for example, the collector p.
- a part of the collector p layer 23 may be simply used as the collector p - layer 23a (impurity layer) without changing the impurity concentration between the layer 23 and the collector p - layer 23a.
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Abstract
Description
以下、本発明の第一実施形態を説明する。
(半導体装置の構成)
図1は、第一実施形態の半導体装置1の構成を示す断面図である。図2(a)は、図1に示す半導体装置1の線IIa―IIaに沿う断面部分を上方から下方に向けて見た断面図である。図2(b)は、半導体装置1の線IIb―IIbに沿う断面部分を下方から上方に向けて見た断面図である。なお、図1は、図2(a)及び図2(b)に後述するエミッタ電極18やコレクタ電極28等が設けられている構成において、図2(a)に示す線I―Iの位置から見た半導体装置1の側断面構成を示している。
次に、以上説明した半導体装置1のオンオフ動作について説明する。なお、半導体装置1には、エミッタ電極18及びコレクタ電極28間に正の電圧Vceが印加されているものとする。半導体装置1は、エミッタ側ゲート電極17に印加される第一ゲート電圧であるゲート電圧Vgg1と、コレクタ側ゲート電極27に印加される第二ゲート電圧であるゲート電圧Vgg2と、の印加状態により制御される。半導体装置1のオン状態にあっては、エミッタn層12とドリフト層10との間が導通し、かつ、コレクタn層22とドリフト層10との間が非導通となる。このとき、エミッタp-層11内に形成された反転層を介してエミッタ電極18からドリフト層10に電子が注入され、かつ、コレクタp層23からドリフト層10に正孔が注入される。また、半導体装置1をオフ状態に切り替えるターンオフ時にあっては、少なくともコレクタn層22とドリフト層10とが導通する。このとき、コレクタp-層23a内に形成された反転層及びコレクタn層22を介してドリフト層10からコレクタ電極28に電子が排出される。コレクタn層22とドリフト層10とが導通するタイミングにおいて、エミッタn層12とドリフト層10との間を非道通とすると、ドリフト層10への電子の注入が停止し、ドリフト層10からエミッタp-層11に正孔が排出される。以下、このオン動作、オフ動作について詳細に説明する。
次に、上記のような半導体装置1において、ゲート密度比率Ja:Jbを変えたときの導通時損失とスイッチング損失との関係についてシミュレーションにより調べた。ここで、図4(a)及び図4(b)は、シミュレーションに用いた評価回路を示す。図4(a)に示した評価回路は、比較例であり、エミッタ側ゲート電極17が設けられ、コレクタ側ゲート電極27が設けられていない片面のIGBTの回路構成を示したものである。図4(b)に示した評価回路は、第一実施形態に係る半導体装置1の回路構成を示したものである。
次に、第一実施形態の半導体装置1の製造方法を説明する。
図7A(a)から図7A(c)、図7B(d)図7B(e)は、第一実施形態の半導体装置1を製造する製造方法の一例を説明するための図である。第一実施形態では、単結晶シリコン製のベア基板に不純物を注入し、ドリフト層10を有する基板を形成し、これに順次不純物を注入して基板5(図7B(d))を形成する。図7A(a)に示す不純物層のうち、エミッタp-層11は、比較的不純物濃度の低いp-層である。また、エミッタn層12は、エミッタp-層11に対して相対的に高濃度のn+層である。エミッタp層13は、エミッタp-層11に対して相対的に高濃度のp+層である。バッファ層29は、ドリフト層10に対して相対的に高濃度のn層である。エミッタp-層11、エミッタn層12、エミッタp層13、コレクタp層23及びバッファ層29の形成は、例えばイオン注入によって行うことができる。
次に、第一実施形態では、図7A(c)に示すように、トレンチ孔14のゲート絶縁膜15の上からポリシリコンを充填し、トレンチ孔14内にエミッタ側ゲート電極17を形成する。
次に、以上説明した第一実施形態の変形例を説明する。
(第一変形例)
図8は、第一変形例の半導体装置2の構成を示す断面図である。図9(a)は、図8に示す半導体装置2の線IXa―IXaに沿う断面部分を上方から下方に向けて見た断面図である。図9(b)は、半導体装置2の線IXb―IXbに沿う断面部分を下方から上方に向けて見た断面図である。なお、図8は、図9(a)及び図9(b)にエミッタ電極18やコレクタ電極28等が設けられている構成において、図9(a)に示す線VIII―VIIIの位置から見た半導体装置2の側断面構成を示している。
図10は、第二変形例の半導体装置3の構成を説明するための断面図である。図11(a)は、図10に示す半導体装置3の線XIa―XIaに沿う断面部分を上方から下方に向けて見た断面図である。図11(b)は、半導体装置3の線XIb―XIbに沿う断面部分を下方から上方に向けて見た断面図である。なお、図10は、図11(a)及び図11(b)にエミッタ電極18やコレクタ電極28等が設けられている構成において、図11(a)に示す線X―Xの位置から見た半導体装置3の側断面構成を示している。
なお、第一実施形態は、以上説明した構成に限定されるものではない。以上説明した第一実施形態では、エミッタ側ゲート電極17を、基板5の第一面faに形成されたトレンチ孔14内に形成されたトレンチ型のゲート電極とした場合について説明したが、本発明はこれに限らず、エミッタ側ゲート電極17をプレーナ型のゲート電極としても良い。なお、エミッタの側に形成されるプレーナ型のエミッタ側ゲート電極は、第一面faの表面にゲート絶縁膜となる絶縁膜を介して配置されるゲート電極をいう。さらに、第一実施形態は、コレクタ側ゲート電極27がプレーナ型のゲート電極であっても良いし、第二面fbのトレンチ孔内に形成されたトレンチ型のコレクタ側ゲート電極であってもよい。また、基板5の第一面fa及び第二面fbに、トレンチ型のゲート電極とプレーナ型のゲート電極とを混在して形成するようにしてもよい。
図12(a)、図12(b)は、それぞれ半導体装置1等のターンオン時、ターンオフ時に係るエミッタ電極18、コレクタ電極28間の電圧Vceと、コレクタ電極28を流れるコレクタ電流Icを示す図である。図12(a)は半導体装置1等のターンオン時の電圧Vceとコレクタ電流Icとを示し、図12(b)は半導体装置1等のターンオフ時の電圧Vceとコレクタ電流Icとを示している。
次に、本発明の第二実施形態を説明する。図15(a)及び図15(b)は、第二実施形態の半導体装置6を説明するものである。図15(a)は半導体装置6が形成されている半導体チップ60を上方から見たときの上面構成を示す概略図であり、図15(b)は半導体装置6が形成されている半導体チップ60を下方から見たときの下面構成を示す概略図である。
5 基板
10 ドリフト層(ドリフト層)
11 エミッタp-層(エミッタ層)
12 エミッタn層(第一高濃度不純物層)
13 エミッタp層
14、14a、14b トレンチ孔
15 ゲート絶縁膜(エミッタ側ゲート絶縁膜)
17 エミッタ側ゲート電極
18 エミッタ電極(エミッタ電極)
22 コレクタn層(第二高濃度不純物層)
23 コレクタp層(コレクタ層)
23a コレクタp-層(不純物層)
25 ゲート絶縁膜(コレクタ側ゲート絶縁膜)
27 コレクタ側ゲート電極
28 コレクタ電極(コレクタ電極)
29 バッファ層
Ja エミッタ側対向領域(第一対向領域)
Jb コレクタ側対向領域(第二対向領域)
R0 素子領域
R1 主領域
Claims (7)
- 第一導電型のエミッタ層と、
第一導電型のコレクタ層と、
前記エミッタ層と前記コレクタ層との間に設けられた、第二導電型のドリフト層と、
前記エミッタ層と電気的に接続されたエミッタ電極と、
前記コレクタ層と電気的に接続されたコレクタ電極と、
前記エミッタ層にエミッタ側ゲート絶縁膜を介して対向配置された、一又は複数のエミッタ側ゲート電極と、
前記エミッタ電極と前記エミッタ層との間に設けられ、前記エミッタ層よりも不純物濃度が高い第二導電型の第一高濃度不純物層と、
前記ドリフト層と前記コレクタ電極との間に設けられた、第一導電型の不純物層と、
前記不純物層にコレクタ側ゲート絶縁膜を介して対向配置された、一又は複数のコレクタ側ゲート電極と、
前記コレクタ電極と前記不純物層との間に設けられ、前記不純物層よりも不純物濃度が高い第二導電型の第二高濃度不純物層と、を備え、
前記エミッタ層と前記エミッタ側ゲート絶縁膜を介して対向している、前記エミッタ側ゲート電極の第一対向領域におけるゲート幅方向の長さの合計が、前記不純物層と前記コレクタ側ゲート絶縁膜を介して対向している、前記コレクタ側ゲート電極の第二対向領域におけるゲート幅方向の長さの合計よりも長い、半導体装置。 - 前記第一高濃度不純物層と前記ドリフト層との間が導通し、かつ、前記第二高濃度不純物層と前記ドリフト層との間が非導通となるオン状態と、
少なくとも前記第二高濃度不純物層と前記ドリフト層とが導通する状態と、を有する、
請求項1に記載の半導体装置。 - 前記第一対向領域のゲート幅方向における長さの合計が、前記第二対向領域のゲート幅方向における長さの合計の2倍以上長い、
請求項1または2に記載の半導体装置。 - 前記第一対向領域のゲート幅方向における長さの合計が、前記第二対向領域のゲート幅方向における長さの合計の4倍以上長い、
請求項1または2に記載の半導体装置。 - 前記エミッタ側ゲート電極は、前記エミッタ層の表面に絶縁膜を介して配置されるプレーナ型のエミッタ側ゲート電極、又は、前記エミッタ層のトレンチ孔内に形成されるトレンチ型のエミッタ側ゲート電極のいずれかであり、
前記コレクタ側ゲート電極は、前記不純物層の表面に配置されるプレーナ型のコレクタ側ゲート電極、又は、前記不純物層のトレンチ孔内に形成されるトレンチ型のコレクタ側ゲート電極のいずれかである、
請求項1から4のいずれか1項に記載の半導体装置。 - 所定方向に向けて前記エミッタ側ゲート電極及び前記コレクタ側ゲート電極が所定間隔で配置されている素子領域の構成を1つのパターンとし、前記素子領域の構成が繰り返しパターンとして所定方向に所定周期で形成されており、
1つの前記素子領域において、前記第一対向領域のゲート幅方向における長さの合計が、前記第二対向領域のゲート幅方向における長さの合計よりも長い、
請求項1から5のいずれか1項に記載の半導体装置。 - 前記素子領域を有する主領域と、前記主領域と隣接した周辺領域と、が設けられており、
前記周辺領域には、前記主領域に形成されている前記エミッタ側ゲート電極が形成されておらず、前記コレクタ層と、前記コレクタ電極と、前記不純物層と、前記コレクタ側ゲート電極と、が形成されている、
請求項6に記載の半導体装置。
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JP2001320049A (ja) * | 2000-05-09 | 2001-11-16 | Fuji Electric Co Ltd | 半導体装置およびその製造方法 |
JP2010123667A (ja) * | 2008-11-18 | 2010-06-03 | Denso Corp | 半導体装置 |
JP2020061429A (ja) * | 2018-10-09 | 2020-04-16 | 三菱電機株式会社 | 半導体装置 |
JP2020155581A (ja) * | 2019-03-20 | 2020-09-24 | 株式会社東芝 | 半導体装置 |
JP2021150544A (ja) * | 2020-03-19 | 2021-09-27 | 株式会社東芝 | 半導体装置及び半導体回路 |
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JP2001320049A (ja) * | 2000-05-09 | 2001-11-16 | Fuji Electric Co Ltd | 半導体装置およびその製造方法 |
JP2010123667A (ja) * | 2008-11-18 | 2010-06-03 | Denso Corp | 半導体装置 |
JP2020061429A (ja) * | 2018-10-09 | 2020-04-16 | 三菱電機株式会社 | 半導体装置 |
JP2020155581A (ja) * | 2019-03-20 | 2020-09-24 | 株式会社東芝 | 半導体装置 |
JP2021150544A (ja) * | 2020-03-19 | 2021-09-27 | 株式会社東芝 | 半導体装置及び半導体回路 |
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