WO2022116286A1 - 阵列基板及测量阵列基板电容的方法 - Google Patents

阵列基板及测量阵列基板电容的方法 Download PDF

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Publication number
WO2022116286A1
WO2022116286A1 PCT/CN2020/137506 CN2020137506W WO2022116286A1 WO 2022116286 A1 WO2022116286 A1 WO 2022116286A1 CN 2020137506 W CN2020137506 W CN 2020137506W WO 2022116286 A1 WO2022116286 A1 WO 2022116286A1
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Prior art keywords
thin film
pixel electrode
film transistor
electrode
data line
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PCT/CN2020/137506
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English (en)
French (fr)
Inventor
刘梦阳
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Tcl华星光电技术有限公司
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Publication of WO2022116286A1 publication Critical patent/WO2022116286A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a method for measuring the capacitance of the array substrate.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the mechanism of the TFT-LCD display image is: applying a voltage to generate an electric field between the two substrates to deflect the liquid crystal molecules in the liquid crystal layer, and the deflected liquid crystal molecules refract the light of the backlight module to generate a picture.
  • the overlapping capacitance between the data line and the common electrode line in the thin film transistor array substrate capacitance is likely to cause a crosstalk phenomenon, which will affect the actual voltage difference between the two substrates, thereby affecting the display of the screen.
  • the overlap capacitance in the thin film transistor array substrate is usually measured and analyzed.
  • the current method of measuring the overlap capacitance of the thin film transistor array substrate in order to match the probe size of the measuring instrument for measuring the capacitance, it is necessary to set the non-display area of the thin film transistor array substrate respectively extending from the data line and the common electrode line with a ratio of Larger area terminals for data lines and common electrode lines.
  • the measurement of the overlap capacitance is carried out by placing the two probes of the instrument on the two terminals extending from the data line and the common electrode line, respectively.
  • the current measurement method cannot directly measure and analyze the overlapping capacitance of the data line and the common electrode line in the display area of the thin film transistor array substrate. Therefore, it is necessary to develop an array substrate and a method for measuring the capacitance of the array substrate.
  • the present disclosure provides the following solutions.
  • the present disclosure provides a method for measuring the capacitance of an array substrate, which includes the following steps.
  • An array substrate is provided, wherein the array substrate includes a plurality of pixel units on a base substrate.
  • Each pixel unit includes a master pixel electrode, a slave pixel electrode, a data line, a common electrode line, a shared thin film transistor and a first thin film transistor.
  • the data line is disposed on the side of the slave pixel electrode close to the master pixel electrode and is electrically connected to the slave pixel electrode.
  • Common electrode lines are disposed on three sides of the main pixel electrode close to the slave pixel electrode, and are disposed on three sides of the slave pixel electrode close to the main pixel electrode.
  • the drains of the shared thin film transistors are connected to the data lines.
  • the drain of the first thin film transistor is connected to the data line.
  • the connection between the drain of the shared thin film transistor and the data line and the connection between the drain of the first thin film transistor and the data line are cut off, so that all
  • the slave pixel electrode is only electrically connected to the data line.
  • the main pixel electrode and the common electrode line are cut along a cutting line extending in a direction parallel to the data line, so that the main pixel electrode and the common electrode line are cut off.
  • the electrodes are separated into a first area close to the data line and a second area away from the data line, and the common electrode line is separated into a first section close to the data line and a second area at the main pixel electrode
  • the second section and the third section on opposite sides.
  • the master pixel electrode of the adjacent pixel unit is adjacent to the slave pixel electrode of the pixel unit to be tested.
  • the second section and the third section of the common electrode lines of the adjacent pixel units are respectively connected with the common electrode lines on opposite sides of the pixel electrode of the pixel unit to be tested.
  • At least one conduction hole is provided in the second area of the main pixel electrode, so that the second area of the main pixel electrode is only connected to the second section of the common electrode line and at least one of the third segments is electrically connected.
  • each pixel unit further includes a second thin film transistor.
  • the drain electrode of the second thin film transistor is electrically connected to the main pixel electrode.
  • each pixel unit further includes a gate line, disposed between the master pixel electrode and the slave pixel electrode, and forming a gate of the shared thin film transistor, the first thin film transistor and the second thin film transistor.
  • the array substrate further includes a first insulating layer and a second insulating layer.
  • the common electrode line and the gate line are disposed on the base substrate.
  • the first insulating layer covers the common electrode line and the gate line.
  • the data line, the drain of the shared thin film transistor, the drain of the first thin film transistor and the drain of the second thin film transistor are disposed on the first insulating layer.
  • the second insulating layer covers the data line, the drain of the shared thin film transistor, the drain of the first thin film transistor and the drain of the second thin film transistor.
  • the master pixel electrode and the slave pixel electrode are disposed on the second insulating layer.
  • the data line is electrically connected to the slave pixel electrode through a first via penetrating the second insulating layer, and the drain of the second thin film transistor is penetrating the second insulating layer.
  • the second via hole of the layer is electrically connected to the main pixel electrode.
  • the second region of the main pixel electrode is electrically connected to the common electrode line through the via hole penetrating the first insulating layer and the second insulating layer.
  • each pixel unit the drain of the shared thin film transistor, the drain of the first thin film transistor and the data line are integrally formed.
  • connection between the drain electrode of the shared thin film transistor and the data line and the connection between the drain electrode of the first thin film transistor and the data line are cut off in the pixel unit to be tested.
  • the connection between, the cutting off the main pixel electrode and the common electrode line in the adjacent pixel unit, and the disposing at least one conduction hole in the main pixel electrode in the adjacent pixel unit is all carried out by laser.
  • the main pixel electrode and the pixel electrode in each pixel unit have a four-domain structure, so that the pixel unit has an eight-domain structure.
  • the present disclosure also provides an array substrate including a plurality of pixel units on a base substrate.
  • Each pixel unit includes a master pixel electrode, a slave pixel electrode, a data line, a common electrode line, a shared thin film transistor and a first thin film transistor.
  • the data line is disposed on the side of the slave pixel electrode close to the master pixel electrode and is electrically connected to the slave pixel electrode.
  • Common electrode lines are disposed on three sides of the main pixel electrode close to the slave pixel electrode, and are disposed on three sides of the slave pixel electrode close to the main pixel electrode.
  • the drains of the shared thin film transistors are connected to the data lines.
  • the drain of the first thin film transistor is connected to the data line.
  • a first trench for separating the drain of the shared thin film transistor and the data line is provided, and a first trench for separating the drain of the first thin film transistor and the data line is provided.
  • a third groove extending in a direction parallel to the data line is provided, and is constructed to separate the main pixel electrode into a groove close to the data line. a first area and a second area away from the data line, and constructed to separate the common electrode line into a first section close to the data line and a second section on opposite sides of the main pixel electrode and the third section.
  • the master pixel electrode of the adjacent pixel unit is adjacent to the slave pixel electrode of the pixel unit to be tested, and the second section and the third section of the common electrode line of the adjacent pixel unit are respectively connected to the Common electrode lines on opposite sides of the pixel electrode of the pixel unit to be tested are connected.
  • the second area is provided with at least one via hole, and is constructed so that the second area of the main pixel electrode is only electrically connected to at least one of the second section and the third section of the common electrode line.
  • each pixel unit further includes a second thin film transistor.
  • the drain electrode of the second thin film transistor is electrically connected to the main pixel electrode.
  • each pixel unit further includes a gate line, disposed between the master pixel electrode and the slave pixel electrode, and forming a gate of the shared thin film transistor, the first thin film transistor and the second thin film transistor.
  • the array substrate further includes a first insulating layer and a second insulating layer.
  • the common electrode line and the gate line are disposed on the base substrate.
  • the first insulating layer covers the common electrode line and the gate line.
  • the data line, the drain of the shared thin film transistor and the drain of the first thin film transistor are disposed on the first insulating layer.
  • the second insulating layer covers the data line, the drain electrode of the shared thin film transistor and the drain electrode of the first thin film transistor.
  • the master pixel electrode and the slave pixel electrode are disposed on the second insulating layer.
  • the data line is electrically connected to the slave pixel electrode through a first via hole penetrating the second insulating layer.
  • the drain electrode of the second thin film transistor is electrically connected to the main pixel electrode through a second via hole penetrating the second insulating layer.
  • the second region of the main pixel electrode is electrically connected to the common electrode line through the via hole penetrating the first insulating layer and the second insulating layer.
  • each pixel unit the drain of the shared thin film transistor, the drain of the first thin film transistor and the data line are integrally formed.
  • the main pixel electrode and the pixel electrode in each pixel unit have a four-domain structure, so that the pixel unit has an eight-domain structure.
  • the slave pixel electrode of the pixel unit to be tested is only electrically connected to the data line
  • the main pixel electrode of the adjacent pixel unit is only electrically connected to the common electrode line
  • the main pixel electrode of the adjacent pixel unit is electrically connected to the data line.
  • the slave pixel electrodes of the pixel unit to be tested are adjacent to each other, and the common electrode lines on the opposite sides of the main pixel electrode of the adjacent pixel unit and the common electrode lines on the opposite sides of the slave pixel electrode of the pixel unit to be tested are mutually connected.
  • the capacitance between the data line and the common electrode line in the pixel unit to be tested can be obtained by measuring the capacitance between the secondary pixel electrode of the pixel unit to be tested and the primary pixel electrode of the adjacent pixel unit. Accordingly, the array substrate provided by the present disclosure is convenient for measuring and analyzing the overlapping capacitances of the data lines and the common electrode lines in the display area of the array substrate, without the need to provide separate data lines and common electrode lines in the non-display area of the tube array substrate. extended terminals. Furthermore, the method for measuring the capacitance of the array substrate provided by the present disclosure can directly measure and analyze the overlapping capacitance of the data line and the common electrode line in the display area of the array substrate.
  • FIG. 1 is a schematic diagram of an array substrate according to an disclosed embodiment.
  • FIG. 2 is a schematic diagram of the pixel unit of FIG. 1 .
  • Fig. 3 is a schematic cross-sectional view of the pixel unit of Fig. 2 along the line A-A'.
  • FIG. 4 is a schematic cross-sectional view of the pixel unit of FIG. 2 along the line B-B'.
  • FIG. 5 is a schematic diagram of a pixel unit to be tested and adjacent pixel units according to an embodiment of the disclosure.
  • FIG. 6 is an enlarged schematic view of region B of FIG. 5 .
  • FIG. 7 is a schematic cross-sectional view of the pixel unit to be tested and the adjacent pixel units in the area B of FIG. 6 along the line C-C'.
  • FIG. 8 is a schematic cross-sectional view of the pixel unit to be tested and the adjacent pixel units in the area B of FIG. 6 along the line D-D'.
  • FIG. 9 is a schematic cross-sectional view of the pixel unit to be tested and the adjacent pixel units in the area B of FIG. 6 along the line E-E'.
  • orientations or positional relationships indicated by the terms “upper”, “lower”, “perpendicular”, “parallel”, “inner”, “outer”, “center” and “side” are based on The orientation or positional relationship shown in the drawings is only for the convenience of describing the present disclosure and simplifying the description. Furthermore, terms such as “first” and “second” are used for descriptive purposes only and should not be construed to indicate or imply relative importance. Features defined by terms such as “first” and “second” may expressly or implicitly include one or more of the stated features.
  • the present disclosure provides a method for measuring the capacitance of an array substrate, which includes the following steps.
  • Step 1 Provide the array substrate.
  • the array substrate 1 includes a display area 2 and a non-display area 3 surrounding the display area 2 .
  • the display area 2 of the array substrate 1 is provided with a plurality of pixel units 4 .
  • each pixel unit 4 is disposed on the base substrate 5 of the array substrate 1 .
  • Each pixel unit 4 includes a master pixel electrode 10 , a slave pixel electrode 20 , a data line 30 , a common electrode line 40 , a gate line 50 , a shared thin film transistor 60 , a first thin film transistor 70 and a second thin film transistor 80 .
  • both the main pixel electrode 10 and the pixel electrode 20 have a four-domain structure, so that the pixel unit 4 has an eight-domain structure.
  • the data line 30 is disposed on the side of the slave pixel electrode 20 close to the master pixel electrode 10 , and is electrically connected to the slave pixel electrode 20 through the first via hole 91 .
  • the protruding portion 21 is provided from the pixel electrode 20 .
  • the projection of the protrusion 21 on the base substrate 5 at least partially overlaps the projection of the data line 30 on the base substrate 5 .
  • the projection of the first via hole 91 on the base substrate 5 falls within the projection of the protrusion 21 overlapping the data line 30 .
  • the data line 30 is directly electrically connected to the protruding portion 21 from the pixel electrode 20 through the first via hole 91 .
  • the common electrode lines 40 are disposed on three sides of the main pixel electrode 10 close to the slave pixel electrode 20 , and are disposed on three sides of the slave pixel electrode 20 close to the main pixel electrode 10 .
  • the gate line 50 is disposed between the master pixel electrode 10 and the slave pixel electrode 20 , and forms a gate of the shared thin film transistor 60 , the first thin film transistor 70 and the second thin film transistor 80 .
  • the shared thin film transistor 60 , the first thin film transistor 70 and the second thin film transistor 80 are disposed between the master pixel electrode 10 and the slave pixel electrode 20 .
  • the shared thin film transistor 60 further includes a drain electrode 61 and a source electrode 62 .
  • the drain 61 of the shared thin film transistor 60 is connected to the data line 30 .
  • the drain 61 and the data line 30 have an integrally formed structure.
  • the source electrode 62 of the shared thin film transistor 60 is electrically connected to the main pixel electrode 10 through the third via hole 93 .
  • the main pixel electrode 10 has the first protruding portion 11
  • the source electrode 62 has the source electrode extension portion 63 .
  • the projection of the first protrusion 11 on the base substrate 5 at least partially overlaps the projection of the source extension 63 on the base substrate 5 .
  • the projection of the third via hole 93 on the base substrate 5 falls within the overlapping projection of the first protrusion 11 and the source extension portion 63 .
  • the source extension portion 63 of the shared thin film transistor 60 is directly electrically connected to the first protruding portion 11 of the main pixel electrode 10 through the third via hole 93 .
  • the first thin film transistor 70 further includes a drain electrode 71 and a source electrode 72 .
  • the drain electrode 71 is connected to the data line 30 .
  • the drain electrode 71 and the data line 30 have an integrally formed structure.
  • the second thin film transistor 80 further includes a drain electrode 81 and a source electrode 82 .
  • the drain electrode 81 of the second thin film transistor 80 is electrically connected to the main pixel electrode 10 through the second via hole 92 .
  • the main pixel electrode 10 also has a second protrusion 12
  • the drain electrode 81 has a drain extension portion 83 .
  • the projection of the second protrusion 12 on the base substrate 5 at least partially overlaps the projection of the drain extension 83 on the base substrate 5 .
  • the projection of the second via hole 92 on the base substrate 5 falls within the overlapping projection of the second protruding portion 12 and the drain extension portion 83 .
  • the drain extension portion 83 of the second thin film transistor 80 is directly electrically connected to the second protrusion portion 12 of the main pixel electrode 10 through the second via hole 92 .
  • the source electrode 72 of the first thin film transistor 70 is connected to the source electrode 82 of the second thin film transistor 80 to form a source electrode line 88 .
  • the source electrode 72 of the first thin film transistor 70 and the source electrode 82 of the second thin film transistor 80 have an integrally formed structure.
  • the array substrate 1 further includes a first insulating layer 6 and a second insulating layer 7 .
  • the common electrode line 40 and the gate line 50 are disposed on the base substrate 5 and can be made of the same metal layer.
  • the first insulating layer 6 covers the common electrode line 40 and the gate line 50 .
  • the drain electrode 61 and the source electrode 62 of the shared thin film transistor 60 , the drain electrode 71 of the first thin film transistor 70 , the drain electrode 81 of the second thin film transistor 80 , the source electrode 72 of the first thin film transistor 70 and the source electrode 72 of the second thin film transistor 80 are shared
  • the source line 88 of the source electrode 82 and the data line 30 are disposed on the first insulating layer 6 and can be made of the same metal layer.
  • source 62 has source extension 63 and drain 81 has drain extension 83 . Therefore, the source extension 63 and the drain extension 83 are also disposed on the first insulating layer 6 .
  • the second insulating layer 7 covers the drain 61 , the source 62 , the source extension 63 , the drain 71 , the drain 81 , the drain extension 83 , the source line 88 and the data line 30 .
  • the master pixel electrode 10 and the slave pixel electrode 20 are disposed on the second insulating layer 7 and may be made of the same metal layer. As described above, the slave pixel electrode 20 has the protruding portion 21 , and the main pixel electrode 10 has the first protruding portion 11 and the second protruding portion 12 .
  • the protruding portion 21 of the secondary pixel electrode 20 and the first protruding portion 11 and the second protruding portion 12 of the main pixel electrode 10 are also disposed on the second insulating layer 7 . Therefore, the data line 30 is electrically connected to the slave pixel electrode 20 through the first via hole 91 penetrating the second insulating layer 7 .
  • the drain electrode 71 of the second thin film transistor 70 is electrically connected to the main pixel electrode 10 through the second via hole 92 penetrating the second insulating layer 7 .
  • the source electrode 62 of the shared thin film transistor 60 is electrically connected to the main pixel electrode 10 through the third via hole 93 penetrating the second insulating layer 7 .
  • the plurality of pixel units 4 include a pixel unit 100 to be tested and an adjacent pixel unit 200 .
  • the pixel unit 100 to be tested and the adjacent pixel unit 200 have the same structure as the pixel unit 4 .
  • the same elements as the pixel unit 4 in the pixel unit 100 to be tested and the adjacent pixel unit 200 are denoted by different reference numerals.
  • the pixel unit 100 to be tested includes a master pixel electrode 110 , a slave pixel electrode 120 , a data line 130 , a common electrode line 140 , a gate line 150 , a shared thin film transistor 160 , a first thin film transistor 170 and a second thin film transistor 170 .
  • Two thin film transistors 180 .
  • the data line 130 is electrically connected to the slave pixel electrode 120 through the first via hole 191 penetrating the second insulating layer 7 .
  • the protruding portion 121 is provided from the pixel electrode 120 .
  • the projection of the protrusion 121 on the base substrate 5 at least partially overlaps the projection of the data line 130 on the base substrate 5 .
  • the projection of the first via hole 191 on the base substrate 5 falls within the projection of the protrusion 121 overlapping the data line 130 .
  • the data line 130 is directly electrically connected to the protruding portion 121 from the pixel electrode 120 through the first via hole 191 .
  • the shared thin film transistor 160 includes a drain electrode 161 and a source electrode 162 .
  • the source electrode 162 of the shared thin film transistor 160 is electrically connected to the main pixel electrode 110 through the third via hole 193 penetrating the second insulating layer 7 .
  • the main pixel electrode 110 has a first protruding portion 111
  • the source electrode 162 has a source electrode extension portion 163 .
  • the projection of the first protrusion 111 on the base substrate 5 at least partially overlaps the projection of the source extension 163 on the base substrate 5 .
  • the projection of the third via hole 193 on the base substrate 5 falls within the overlapping projection of the first protrusion 111 and the source extension portion 163 .
  • the source extension portion 163 of the shared thin film transistor 160 is directly electrically connected to the first protrusion portion 111 of the main pixel electrode 110 through the third via hole 193 .
  • the first thin film transistor 170 further includes a drain electrode 171 and a source electrode 172 .
  • the second thin film transistor 180 further includes a drain electrode 181 and a source electrode 182 .
  • the drain electrode 181 of the second thin film transistor 180 is electrically connected to the main pixel electrode 110 through the second via hole 192 penetrating the second insulating layer 7 .
  • the main pixel electrode 110 further has a second protrusion 112
  • the drain electrode 181 has a drain extension portion 183 .
  • the projection of the second protrusion 112 on the base substrate 5 at least partially overlaps the projection of the drain extension 183 on the base substrate 5 .
  • the projection of the second via hole 192 on the base substrate 5 falls within the overlapping projection of the second protrusion 112 and the drain extension portion 183 .
  • the drain extension portion 183 of the second thin film transistor 180 is directly electrically connected to the second protrusion portion 112 of the main pixel electrode 110 through the second via hole 192 .
  • the source electrode 172 of the first thin film transistor 170 is connected to the source electrode 182 of the second thin film transistor 180 to form a source electrode line 188 .
  • the relative positions and relationships of the elements in the pixel unit 100 to be tested are the same as the relative positions and relationships of the elements in the pixel unit 4 , and will not be described in detail here.
  • the adjacent pixel units 200 include a master pixel electrode 210 , a slave pixel electrode 220 , a data line 230 , a common electrode line 240 , a gate line 250 , a shared thin film transistor 260 , a first thin film transistor 270 and a second thin film transistor 270 .
  • Two thin film transistors 280 are used to control the adjacent pixel units 200 .
  • the data line 230 is electrically connected to the slave pixel electrode 220 through the first via hole 291 penetrating the second insulating layer 7 .
  • the protruding portion 221 is provided from the pixel electrode 220 .
  • the projection of the protrusion 221 on the base substrate 5 at least partially overlaps the projection of the data line 230 on the base substrate 5 .
  • the projection of the first via hole 291 on the base substrate 5 falls within the projection of the protrusion 221 overlapping the data line 230 .
  • the data line 230 is directly electrically connected to the protruding portion 221 from the pixel electrode 220 through the first via hole 291 .
  • the shared thin film transistor 260 includes a drain electrode 261 and a source electrode 262 .
  • the source electrode 262 of the shared thin film transistor 260 is electrically connected to the main pixel electrode 210 through the third via hole 293 penetrating the second insulating layer 7 .
  • the main pixel electrode 210 has a first protruding portion 211
  • the source electrode 262 has a source electrode extension portion 263 .
  • the projection of the first protrusion 211 on the base substrate 5 at least partially overlaps the projection of the source extension 263 on the base substrate 5 .
  • the projection of the third via hole 293 on the base substrate 5 falls within the projection of the first protruding portion 211 overlapping the source extension portion 263 .
  • the source extension portion 263 of the shared thin film transistor 260 is directly electrically connected to the first protrusion portion 111 of the main pixel electrode 210 through the third via hole 293 .
  • the first thin film transistor 270 further includes a drain electrode 271 and a source electrode 272 .
  • the second thin film transistor 280 further includes a drain electrode 281 and a source electrode 282 .
  • the drain electrode 281 of the second thin film transistor 280 is electrically connected to the main pixel electrode 210 through the second via hole 292 penetrating the second insulating layer 7 .
  • the main pixel electrode 210 further has a second protrusion 212
  • the drain electrode 281 has a drain extension portion 283 .
  • the projection of the second protrusion 212 on the base substrate 5 at least partially overlaps the projection of the drain extension 283 on the base substrate 5 .
  • the projection of the second via hole 292 on the base substrate 5 falls within the overlapping projection of the second protrusion 212 and the drain extension portion 283 .
  • the drain extension portion 283 of the second thin film transistor 280 is directly electrically connected to the second protrusion portion 212 of the main pixel electrode 210 through the second via hole 292 .
  • the source electrode 272 of the first thin film transistor 270 is connected to the source electrode 282 of the second thin film transistor 280 to form a source electrode line 288 .
  • the relative positions and relationships of the elements in the adjacent pixel unit 200 are the same as the relative positions and relationships of the elements in the pixel unit 4 , and will not be described in detail here.
  • the master pixel electrode 210 of the adjacent pixel unit 200 is adjacent to the slave pixel electrode 120 of the pixel unit 100 under test.
  • the common electrode lines 240 on opposite sides of the main pixel electrodes 210 of adjacent pixel units 200 are respectively connected to the common electrode lines 140 on opposite sides of the secondary pixel electrodes 120 of the pixel unit 100 to be tested.
  • Step 2 Referring to FIGS. 5 to 8, in the pixel unit 100 to be tested, cut off the connection between the drain 161 of the shared thin film transistor 160 and the data line 130, and the drain 171 of the first thin film transistor 170 and the data line 130, so that the slave pixel electrode 120 is only electrically connected to the data line 130.
  • the connection between the drain 161 of the shared thin film transistor 160 and the data line 130 can be cut off along the cutting line 301 by using a laser. After this dicing, first trenches 3011 are formed. The depth of laser cutting can be adjusted according to actual needs. In this embodiment, the first trench 3011 penetrates through the second insulating layer 7 and the drain 161 of the shared thin film transistor 160 .
  • the depth of the laser cutting can also be adjusted so that the first trench 3011 penetrates through the second insulating layer 7 , the drain 161 of the shared thin film transistor 160 and a part of the first insulating layer 6 .
  • the connection between the drain electrode 171 of the first thin film transistor 170 and the data line 130 can also be cut off along the cutting line 302 by using a laser. After this dicing, second trenches 3021 are formed. In this embodiment, the second trench 3021 penetrates the second insulating layer 7 and the drain electrode 171 of the first thin film transistor 170 .
  • the depth of laser cutting can also be adjusted so that the first trench 3011 penetrates through the second insulating layer 7 , the drain electrode 171 of the first thin film transistor 170 and a part of the first insulating layer 6 .
  • the data line 130 is electrically connected to the slave pixel electrode 120 only through the first via hole 191 penetrating the second insulating layer 7 .
  • the data line 130 is directly electrically connected to the protruding portion 121 from the pixel electrode 120 only through the first via hole 191 .
  • Step 3 Referring to FIG. 5, FIG. 6 and FIG. 9, in the adjacent pixel units 200, the main pixel electrode 210 and the common electrode line 240 are cut along the cutting line 303 extending in the direction parallel to the data line 230 to cut off the main pixel electrode 210 and the common electrode line 240.
  • the main pixel electrode 210 is separated into a first region 211 close to the data line 230 and a second region 212 away from the data line 230
  • the common electrode line 240 is separated into a first section 241 close to the data line 230 and a second region 212 away from the data line 230
  • the second section 242 and the third section 243 on opposite sides of the 210 .
  • the second section 242 and the third section 243 of the common electrode line 240 are respectively connected to the common electrode line 140 on opposite sides of the pixel electrode 120 of the pixel unit 100 under test.
  • the main pixel electrode 210 and the common electrode line 240 can be cut along the cutting line 303 by using a laser. After this cutting, third trenches 3031 are formed.
  • the third trench 3031 penetrates through the main pixel electrode 210 , the second insulating layer 7 , the second insulating layer 6 , and the common electrode line 240 .
  • the cutting lines 303 and the third trenches 3031 are straight lines parallel to the data lines 230, but not limited thereto.
  • the cutting lines 303 and the third trenches 3031 may also be any non-straight lines extending in a direction parallel to the data lines 230 , such as curved lines.
  • Step 4 Referring to FIGS. 5 , 6 and 9 , in adjacent pixel units 200 , at least one via hole 304 is arranged in the second area 212 of the main pixel electrode 210 , so that the second area 212 of the main pixel electrode 210 The region 212 is only electrically connected to at least one of the second section 242 and the third section 243 of the common electrode line 240 .
  • a via hole 304 which penetrates the first insulating layer 6 and the second insulating layer 7 and electrically connects the second region 212 of the main pixel electrode 210 and the common electrode line 240 , can be formed by laser.
  • the projection of the via hole 304 on the base substrate 5 falls within the overlapping projection of the second region 212 of the main pixel electrode 210 and the common electrode line 240 on the base substrate 5 .
  • the projected area of the via hole 304 is equal to the overlapping projected area of the second region 212 of the main pixel electrode 210 and the common electrode line 240 .
  • the projection of the via hole 304 may also overlap with the overlapping projection portion of the second region 212 of the main pixel electrode 210 and the common electrode line 240 .
  • the projected area of the via hole 304 may also be larger or smaller than the overlapping projected area of the second region 212 of the main pixel electrode 210 and the common electrode line 240 .
  • the number and relative positions of the via holes 304 can be adjusted according to actual needs. Increasing the number of vias 304 can ensure that the second region 212 of the main pixel electrode 210 is electrically connected to the common electrode line 240 . In this embodiment, two vias 304 are respectively provided on the second section 242 and the third section 243 of the common electrode line 240 , but not limited thereto.
  • the sequence of the foregoing steps 1 to 4 can be arbitrarily adjusted as required.
  • Step 5 Referring to FIG. 5 and FIG. 6 , measure the capacitance between the secondary pixel electrode 120 of the pixel unit 100 to be tested and the second area 212 of the primary pixel electrode 210 of the adjacent pixel unit 200 to obtain the pixel unit 100 to be tested capacitance between the data line 130 and the common electrode line 140 in .
  • the master pixel electrode 210 of the adjacent pixel unit 200 is adjacent to the slave pixel electrode 110 of the pixel unit 100 to be tested.
  • the slave pixel electrode 120 of the pixel unit 100 to be tested is only electrically connected to the data line 130 .
  • the second region 212 of the main pixel electrode 210 of the adjacent pixel unit 200 is electrically connected only to at least one of the second section 242 and the third section 243 of the common electrode line 240 .
  • the second section 242 and the third section 243 of the common electrode line 240 are respectively connected with the common electrode line 130 on opposite sides of the pixel electrode 120 of the pixel unit 100 to be tested. Therefore, in the method provided by the present disclosure, the pixel unit 100 to be tested can be obtained by measuring the capacitance between the secondary pixel electrode 120 of the pixel unit 100 to be tested and the second area 212 of the primary pixel electrode 210 of the adjacent pixel unit 200 Capacitance between the data line 130 and the common electrode line 140 in the X region.
  • the method provided by the present disclosure can directly measure the overlapping capacitances of the data lines and the common electrode lines of the pixel units in the display area of the analysis array substrate, without the need to provide separate data lines and common electrode lines in the non-display area of the tube array substrate extended terminals.
  • the present disclosure also provides an array substrate, which is an array substrate obtained by performing steps 1-4 of the foregoing method.
  • the array substrate 1 includes a display area 2 and a non-display area 3 surrounding the display area 2 .
  • the display area 2 of the array substrate 1 is provided with a plurality of pixel units 4 .
  • each pixel unit 4 is disposed on the base substrate 5 of the array substrate 1 .
  • Each pixel unit 4 includes a master pixel electrode 10 , a slave pixel electrode 20 , a data line 30 , a common electrode line 40 , a gate line 50 , a shared thin film transistor 60 , a first thin film transistor 70 and a second thin film transistor 80 .
  • the data line 30 is disposed on the side of the slave pixel electrode 20 close to the master pixel electrode 10 , and is electrically connected to the slave pixel electrode 20 through the first via hole 91 .
  • the protruding portion 21 is provided from the pixel electrode 20 .
  • the data line 30 is directly electrically connected to the protruding portion 21 from the pixel electrode 20 through the first via hole 91 .
  • the common electrode lines 40 are disposed on three sides of the main pixel electrode 10 close to the slave pixel electrode 20 , and are disposed on three sides of the slave pixel electrode 20 close to the main pixel electrode 10 .
  • the gate line 50 is disposed between the master pixel electrode 10 and the slave pixel electrode 20 , and forms a gate of the shared thin film transistor 60 , the first thin film transistor 70 and the second thin film transistor 80 .
  • the shared thin film transistor 60 , the first thin film transistor 70 and the second thin film transistor 80 are disposed between the master pixel electrode 10 and the slave pixel electrode 20 .
  • the shared thin film transistor 60 further includes a drain electrode 61 and a source electrode 62 .
  • the drain 61 of the shared thin film transistor 60 is connected to the data line 30 .
  • the drain 61 and the data line 30 have an integrally formed structure.
  • the source electrode 62 of the shared thin film transistor 60 is electrically connected to the main pixel electrode 10 through the third via hole 93 .
  • the main pixel electrode 10 has the first protruding portion 11
  • the source electrode 62 has the source electrode extension portion 63 .
  • the source extension portion 63 of the shared thin film transistor 60 is directly electrically connected to the first protruding portion 11 of the main pixel electrode 10 through the third via hole 93 .
  • the first thin film transistor 70 further includes a drain electrode 71 and a source electrode 72 .
  • the drain electrode 71 is connected to the data line 30 .
  • the drain electrode 71 and the data line 30 have an integrally formed structure.
  • the second thin film transistor 80 further includes a drain electrode 81 and a source electrode 82 .
  • the drain electrode 81 of the second thin film transistor 80 is electrically connected to the main pixel electrode 10 through the second via hole 92 .
  • the main pixel electrode 10 also has a second protrusion 12
  • the drain electrode 81 has a drain extension portion 83 .
  • the drain extension portion 83 of the second thin film transistor 80 is directly electrically connected to the second protrusion portion 12 of the main pixel electrode 10 through the second via hole 92 .
  • the source electrode 72 of the first thin film transistor 70 is connected to the source electrode 82 of the second thin film transistor 80 to form a source electrode line 88 .
  • the source electrode 72 of the first thin film transistor 70 and the source electrode 82 of the second thin film transistor 80 have an integrally formed structure.
  • the array substrate 1 further includes a first insulating layer 6 and a second insulating layer 7 .
  • the common electrode line 40 and the gate line 50 are provided on the base substrate 5 .
  • the first insulating layer 6 covers the common electrode line 40 and the gate line 50 .
  • the drain electrode 61 and the source electrode 62 of the shared thin film transistor 60 , the drain electrode 71 of the first thin film transistor 70 , the drain electrode 81 of the second thin film transistor 80 , the source electrode 72 of the first thin film transistor 70 and the source electrode 72 of the second thin film transistor 80 are shared
  • the source line 88 of the source electrode 82 and the data line 30 are disposed on the first insulating layer 6 .
  • source 62 has source extension 63 and drain 81 has drain extension 83 . Therefore, the source extension 63 and the drain extension 83 are also disposed on the first insulating layer 6 .
  • the second insulating layer 7 covers the drain 61 , the source 62 , the source extension 63 , the drain 71 , the drain 81 , the drain extension 83 , the source line 88 and the data line 30 .
  • the master pixel electrode 10 and the slave pixel electrode 20 are disposed on the second insulating layer 7 . As described above, the slave pixel electrode 20 has the protruding portion 21 , and the main pixel electrode 10 has the first protruding portion 11 and the second protruding portion 12 .
  • the protruding portion 21 of the secondary pixel electrode 20 and the first protruding portion 11 and the second protruding portion 12 of the main pixel electrode 10 are also disposed on the second insulating layer 7 .
  • the data line 30 is electrically connected to the slave pixel electrode 20 through the first via hole 91 penetrating the second insulating layer 7 .
  • the drain electrode 71 of the second thin film transistor 70 is electrically connected to the main pixel electrode 10 through the second via hole 92 penetrating the second insulating layer 7 .
  • the source electrode 62 of the shared thin film transistor 60 is electrically connected to the main pixel electrode 10 through the third via hole 93 penetrating the second insulating layer 7 .
  • the plurality of pixel units 4 include a pixel unit 100 to be tested and an adjacent pixel unit 200 .
  • the pixel unit 100 to be tested and the adjacent pixel unit 200 have the same structure as the pixel unit 4 .
  • the same elements as the pixel unit 4 in the pixel unit 100 to be tested and the adjacent pixel unit 200 are denoted by different reference numerals.
  • the pixel unit 100 to be tested includes a master pixel electrode 110 , a slave pixel electrode 120 , a data line 130 , a common electrode line 140 , a gate line 150 , a shared thin film transistor 160 , a first thin film transistor 170 and a second thin film transistor 170 .
  • Two thin film transistors 180 .
  • the data line 130 is electrically connected to the slave pixel electrode 120 through the first via hole 191 penetrating the second insulating layer 7 .
  • the protruding portion 121 is provided from the pixel electrode 120 .
  • the data line 130 is directly electrically connected to the protruding portion 121 from the pixel electrode 120 through the first via hole 191 .
  • the shared thin film transistor 160 includes a drain electrode 161 and a source electrode 162 .
  • the source electrode 162 of the shared thin film transistor 160 is electrically connected to the main pixel electrode 110 through the third via hole 193 penetrating the second insulating layer 7 .
  • the main pixel electrode 110 has a first protruding portion 111
  • the source electrode 162 has a source electrode extension portion 163 .
  • the source extension portion 163 of the shared thin film transistor 160 is directly electrically connected to the first protrusion portion 111 of the main pixel electrode 110 through the third via hole 193 .
  • the first thin film transistor 170 further includes a drain electrode 171 and a source electrode 172 .
  • the second thin film transistor 180 further includes a drain electrode 181 and a source electrode 182 .
  • the drain electrode 181 of the second thin film transistor 180 is electrically connected to the main pixel electrode 110 through the second via hole 192 penetrating the second insulating layer 7 .
  • the main pixel electrode 110 further has a second protrusion 112
  • the drain electrode 181 has a drain extension portion 183 .
  • the drain extension portion 183 of the second thin film transistor 180 is directly electrically connected to the second protrusion portion 112 of the main pixel electrode 110 through the second via hole 192 .
  • the source electrode 172 of the first thin film transistor 170 is connected to the source electrode 182 of the second thin film transistor 180 to form a source electrode line 188 .
  • the relative positions and relationships of the elements in the pixel unit 100 to be tested are the same as the relative positions and relationships of the elements in the pixel unit 4 , and will not be described in detail here.
  • the adjacent pixel units 200 include a master pixel electrode 210 , a slave pixel electrode 220 , a data line 230 , a common electrode line 240 , a gate line 250 , a shared thin film transistor 260 , a first thin film transistor 270 and a second thin film transistor 270 .
  • Two thin film transistors 280 are used to control the adjacent pixel units 200 .
  • the data line 230 is electrically connected to the slave pixel electrode 220 through the first via hole 291 penetrating the second insulating layer 7 .
  • the protruding portion 221 is provided from the pixel electrode 220 .
  • the data line 230 is directly electrically connected to the protruding portion 221 from the pixel electrode 220 through the first via hole 291 .
  • the shared thin film transistor 260 includes a drain electrode 261 and a source electrode 262 .
  • the source electrode 262 of the shared thin film transistor 260 is electrically connected to the main pixel electrode 210 through the third via hole 293 penetrating the second insulating layer 7 .
  • the main pixel electrode 210 has a first protruding portion 211
  • the source electrode 262 has a source electrode extension portion 263 .
  • the source extension portion 263 of the shared thin film transistor 260 is directly electrically connected to the first protrusion portion 111 of the main pixel electrode 210 through the third via hole 293 .
  • the first thin film transistor 270 further includes a drain electrode 271 and a source electrode 272 .
  • the second thin film transistor 280 further includes a drain electrode 281 and a source electrode 282 .
  • the drain electrode 281 of the second thin film transistor 280 is electrically connected to the main pixel electrode 210 through the second via hole 292 penetrating the second insulating layer 7 .
  • the main pixel electrode 210 further has a second protrusion 212
  • the drain electrode 281 has a drain extension portion 283 .
  • the drain extension portion 283 of the second thin film transistor 280 is directly electrically connected to the second protrusion portion 212 of the main pixel electrode 210 through the second via hole 292 .
  • the source electrode 272 of the first thin film transistor 270 is connected to the source electrode 282 of the second thin film transistor 280 to form a source electrode line 288 .
  • the relative positions and relationships of the elements in the adjacent pixel unit 200 are the same as the relative positions and relationships of the elements in the pixel unit 4 , and will not be described in detail here.
  • the master pixel electrode 210 of the adjacent pixel unit 200 is adjacent to the slave pixel electrode 120 of the pixel unit 100 under test.
  • the common electrode lines 240 on opposite sides of the main pixel electrodes 210 of adjacent pixel units 200 are respectively connected to the common electrode lines 140 on opposite sides of the secondary pixel electrodes 120 of the pixel unit 100 to be tested.
  • a first trench 3011 for separating the drain 161 of the shared thin film transistor 160 and the data line 130 is provided, and a drain for separating the first thin film transistor 170
  • the electrode 171 is connected to the second trench 3021 of the data line 130 , so that the slave pixel electrode 120 is only electrically connected to the data line 130 .
  • the data line 130 is electrically connected to the slave pixel electrode 120 only through the first via hole 191 penetrating the second insulating layer 7 . More specifically, the data line 130 is directly electrically connected to the protruding portion 121 from the pixel electrode 120 only through the first via hole 191 .
  • the connection between the drain 161 of the shared thin film transistor 160 and the data line 130 can be cut off along the cutting line 301 by a laser to form the first trench 3011 .
  • the connection between the drain electrode 171 of the first thin film transistor 170 and the data line 130 can also be cut off along the cutting line 302 by a laser to form the second trench 3021 .
  • the depth of laser cutting can be adjusted according to actual needs.
  • the first trench 3011 penetrates the second insulating layer 7 and the drain electrode 161 of the shared thin film transistor 160
  • the second trench 3021 penetrates the second insulating layer 7 and the drain electrode 171 of the first thin film transistor 170 .
  • adjacent pixel units 200 are provided with third trenches 3031 extending in a direction parallel to the data lines 230 , and are constructed to separate the main pixel electrodes 210 into areas close to the data lines.
  • the first area 211 of the 230 and the second area 212 away from the data line 230 are constructed to separate the common electrode line 240 into a first section 241 close to the data line 230 and a second area on opposite sides of the main pixel electrode 210 segment 242 and third segment 243 .
  • the second section 242 and the third section 243 of the common electrode line 240 are respectively connected to the common electrode line 140 on opposite sides of the pixel electrode 120 of the pixel unit 100 under test.
  • the main pixel electrode 210 and the common electrode line 240 may be cut by laser along the cutting line 303 extending in a direction parallel to the data line 230 to form the third trench 3031 .
  • the third trench 3031 penetrates through the main pixel electrode 210 , the second insulating layer 7 , the second insulating layer 6 , and the common electrode line 240 .
  • the cutting lines 303 and the third trenches 3031 are straight lines parallel to the data lines 230, but not limited thereto.
  • the cutting lines 303 and the third trenches 3031 may also be any non-straight lines extending in a direction parallel to the data lines 230 , such as curved lines.
  • Increasing the number of vias 304 can ensure that the second region 212 of the main pixel electrode 210 is electrically connected to the common electrode line 240 .
  • two vias 304 are respectively provided on the second section 242 and the third section 243 of the common electrode line 240 , but not limited thereto.
  • the master pixel electrode 210 of the adjacent pixel unit 200 is adjacent to the slave pixel electrode 110 of the pixel unit 100 to be tested.
  • the slave pixel electrode 120 of the pixel unit 100 to be tested is only electrically connected to the data line 130 .
  • the second region 212 of the main pixel electrode 210 of the adjacent pixel unit 200 is electrically connected only to at least one of the second section 242 and the third section 243 of the common electrode line 240 .
  • the second section 242 and the third section 243 of the common electrode line 240 are respectively connected with the common electrode line 130 on opposite sides of the pixel electrode 120 of the pixel unit 100 to be tested.
  • the pixel unit to be tested can be obtained by measuring the capacitance between the secondary pixel electrode 120 of the pixel unit 100 to be tested and the second area 212 of the primary pixel electrode 210 of the adjacent pixel unit 200 Capacitance between the data line 130 and the common electrode line 140 in 100 .
  • the two probes of the instrument for measuring capacitance are respectively placed on the second area 212 of the secondary pixel electrode 120 of the pixel unit 100 to be tested and the second area 212 of the primary pixel electrode 210 of the adjacent pixel unit 200 and measured, it can be obtained.
  • the distance between the data line and the common electrode line in the pixel unit to be tested can be obtained by directly measuring the capacitance between the slave pixel electrode of the pixel unit to be tested and the main pixel electrode of the adjacent pixel unit capacitor.
  • the array substrate provided by the present disclosure facilitates direct measurement and analysis of the overlapping capacitances of data lines and common electrode lines of pixel units in the display area of the array substrate, without the need to provide separate data lines and common electrodes in the non-display area of the tube array substrate The terminal from which the wire extends.

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Abstract

本揭示公开一种阵列基板及测量所述阵列基板电容的方法。所述方法包含：在待测像素单元中，切断第一薄膜晶体管及共享薄膜晶体管与数据线之间的连接，使从像素电极仅与数据线电连接；在相邻像素单元中，切割主像素电极及公共电极线，并设置至少一个导通孔，以使主像素电极仅与公共电极线电连接；及测量待测像素单元的从像素电极与相邻像素单元的主像素电极之间的电容，以获得待测像素单元中的数据线与公共电极线之间的电容。

Description

阵列基板及测量阵列基板电容的方法 技术领域
本揭示涉及显示技术领域，特别是涉及一种阵列基板及测量阵列基板电容的方法。
 背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)是由薄膜晶体管阵列基板、彩色滤光片基板及设置在前述两基板之间的液晶层所构成。TFT-LCD显示影像的机制为：施加电压使前述两基板之间产生电场，来偏转液晶层中的液晶分子，被偏转后的液晶分子折射背光模组的光线进而产生画面。然而，薄膜晶体管阵列基板中的数据线和公共电极线之间的重叠电容(overlap capacitance)易引起串扰(crosstalk)现象，其会影响所述两基板之间的实际电压差值，进而影响画面的显示。为避免此问题，通常会对薄膜晶体管阵列基板中的重叠电容进行测量分析。
在现今测量薄膜晶体管阵列基板的重叠电容的方法中，为配合测量电容的仪器的探针尺寸，必须在薄膜晶体管阵列基板的非显示区中设置分别从数据线和公共电极线延伸出且具有比数据线和公共电极线更大的面积的端子。通过将仪器的两探针置于分别从数据线和公共电极线延伸出的两端子上来进行重叠电容的测量。
 技术问题
现今的测量方法无法直接测量分析薄膜晶体管阵列基板的显示区中的数据线和公共电极线的重叠电容，因此有需要研发一种阵列基板及测量阵列基板电容的方法。
 技术解决方案
为了解决现今测量方法无法直接测量分析阵列基板显示区中的重叠电容的技术问题，本揭示提供了下列解决方案。
本揭示提供了一种测量阵列基板电容的方法，其包含下列步骤。提供阵列基板，其中所述阵列基板包含位于衬底基板上的多个像素单元。每一像素单元包含主像素电极、从像素电极、数据线、公共电极线、共享薄膜晶体管及第一薄膜晶体管。数据线设置在所述从像素电极靠近所述主像素电极的一侧且与所述从像素电极电连接。公共电极线设置在所述主像素电极靠近所述从像素电极的三侧边，以及设置在所述从像素电极靠近所述主像素电极的三侧边。共享薄膜晶体管的漏极与所述数据线相连接。第一薄膜晶体管的漏极与所述数据线相连接。在待测的像素单元中，切断所述共享薄膜晶体管的漏极与所述数据线之间的连接，以及所述第一薄膜晶体管的漏极与所述数据线之间的连接，以使所述从像素电极仅与所述数据线电连接。在与所述待测像素单元相邻的像素单元中，沿着在平行于所述数据线的方向上延伸的切割线切断所述主像素电极及所述公共电极线，以使所述主像素电极分离成靠近所述数据线的第一区域及远离所述数据线的第二区域，以及使所述公共电极线被分离成靠近所述数据线的第一区段与在所述主像素电极相对两侧的第二区段及第三区段。所述相邻像素单元的主像素电极与所述待测像素单元的从像素电极相邻。所述相邻像素单元的公共电极线的第二区段及第三区段分别与在所述待测像素单元的从像素电极的相对两侧边的公共电极线相连接。在所述相邻像素单元中，设置至少一个导通孔在所述主像素电极的第二区域中，以使所述主像素电极的第二区域仅与所述公共电极线的第二区段及第三区段中的至少一者电连接。测量所述待测像素单元的从像素电极与所述相邻像素单元的主像素电极的第二区域之间的电容，以获得所述待测像素单元中的数据线与公共电极线之间的电容。
在一实施例中，每一像素单元还包含第二薄膜晶体管。第二薄膜晶体管的漏极与所述主像素电极电连接。
在一实施例中，每一像素单元还包含栅极线，设置于主像素电极与从像素电极之间，且形成共享薄膜晶体管、第一薄膜晶体管及第二薄膜晶体管的栅级。
在一实施例中，所述阵列基板还包含第一绝缘层及第二绝缘层。所述公共电极线及所述栅极线设置在所述衬底基板上。第一绝缘层覆盖所述公共电极线及所述栅极线。所述数据线、所述共享薄膜晶体管的漏极、第一薄膜晶体管的漏极及第二薄膜晶体管的漏极设置在第一绝缘层上。第二绝缘层覆盖所述数据线、所述共享薄膜晶体管的漏极、第一薄膜晶体管的漏极及第二薄膜晶体管的漏极。所述主像素电极及所述从像素电极设置在第二绝缘层上。
在一实施例中，在每一像素单元中，数据线是通过贯穿第二绝缘层的第一过孔与所述从像素电极电连接，且第二薄膜晶体管的漏极是通过贯穿第二绝缘层的第二过孔与所述主像素电极电连接。在所述相邻像素单元中，所述主像素电极的第二区域是通过贯穿第一绝缘层及第二绝缘层的所述导通孔与所述公共电极线电连接。
在一实施例中，在每一像素单元中，共享薄膜晶体管的漏极、第一薄膜晶体管的漏极与所述数据线为一体成形的结构。
在一实施例中，所述在所述待测像素单元中切断所述共享薄膜晶体管的漏极与所述数据线之间的连接及所述第一薄膜晶体管的漏极与所述数据线之间的连接、所述在所述相邻像素单元中切断所述主像素电极及所述公共电极线，以及所述在所述相邻像素单元中设置至少一个导通孔在所述主像素电极的第二区域中，均是通过激光进行。
在一实施例中，每一像素单元中的主像素电极及像素电极均具有四畴结构，以使像素单元具有八畴结构。
本揭示还提供了一种阵列基板，其包含位于衬底基板上的多个像素单元。每一像素单元包含主像素电极、从像素电极、数据线、公共电极线、共享薄膜晶体管及第一薄膜晶体管。数据线设置在所述从像素电极靠近所述主像素电极的一侧且与所述从像素电极电连接。公共电极线设置在所述主像素电极靠近所述从像素电极的三侧边，以及设置在所述从像素电极靠近所述主像素电极的三侧边。共享薄膜晶体管的漏极与所述数据线相连接。第一薄膜晶体管的漏极与所述数据线相连接。在待测像素单元中，设置有用以分离所述共享薄膜晶体管的漏极与所述数据线的第一沟槽，以及用以分离所述第一薄膜晶体管的漏极与所述数据线的第二沟槽，使得从像素电极仅与数据线电连接。在与所述待测像素单元相邻的像素单元中，设置有在平行于所述数据线的方向上延伸的第三沟槽，建构成将所述主像素电极分离成靠近所述数据线的第一区域及远离所述数据线的第二区域，以及建构成将所述公共电极线分离成靠近所述数据线的第一区段及在所述主像素电极相对两侧的第二区段及第三区段。所述相邻像素单元的主像素电极与所述待测像素单元的从像素电极相邻，且所述相邻像素单元的公共电极线的第二区段及第三区段分别与在所述待测像素单元的从像素电极的相对两侧边的公共电极线相连接。所述第二区域设有至少一个导通孔，建构成使所述主像素电极的第二区域仅与所述公共电极线的第二区段及第三区段中的至少一者电连接。
在一实施例中，每一像素单元还包含第二薄膜晶体管。第二薄膜晶体管的漏极与所述主像素电极电连接。
在一实施例中，每一像素单元还包含栅极线，设置于主像素电极与从像素电极之间，且形成共享薄膜晶体管、第一薄膜晶体管及第二薄膜晶体管的栅级。
在一实施例中，所述阵列基板还包含第一绝缘层及第二绝缘层。所述公共电极线及所述栅极线设置在所述衬底基板上。第一绝缘层覆盖所述公共电极线及所述栅极线。所述数据线、所述共享薄膜晶体管的漏极及第一薄膜晶体管的漏极设置在第一绝缘层上。第二绝缘层覆盖所述数据线、所述共享薄膜晶体管的漏极及第一薄膜晶体管的漏极。所述主像素电极及所述从像素电极设置在第二绝缘层上。
在一实施例中，在每一像素单元中，数据线是通过贯穿第二绝缘层的第一过孔与所述从像素电极电连接。第二薄膜晶体管的漏极是通过贯穿第二绝缘层的第二过孔与所述主像素电极电连接。在所述相邻像素单元中，所述主像素电极的第二区域是通过贯穿第一绝缘层及第二绝缘层的所述导通孔与所述公共电极线电连接。
在一实施例中，在每一像素单元中，共享薄膜晶体管的漏极、第一薄膜晶体管的漏极与所述数据线为一体成形的结构。
在一实施例中，每一像素单元中的主像素电极及像素电极均具有四畴结构，以使像素单元具有八畴结构。
 有益效果
在本揭示所提供的阵列基板中，待测像素单元的从像素电极仅与数据线电连接，相邻像素单元的主像素电极仅与公共电极线电连接，相邻像素单元的主像素电极与待测像素单元的从像素电极相邻，在相邻像素单元的主像素电极的相对两侧边的公共电极线分别与在待测像素单元的从像素电极的相对两侧边的公共电极线彼此相连。因此，可通过测量待测像素单元的从像素电极与相邻像素单元的主像素电极之间的电容，来获得待测像素单元中的数据线与公共电极线之间的电容。据此，本揭示所提供的阵列基板便于测量分析阵列基板的显示区中的数据线和公共电极线的重叠电容，而无需在管阵列基板的非显示区中设置分别从数据线和公共电极线延伸出的的端子。再者，本揭示所提供的测量阵列基板电容的方法可直接测量分析阵列基板的显示区中的数据线和公共电极线的重叠电容。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本揭示实施例的阵列基板的示意图。
图2为图1的像素单元的示意图。
图3为图2的像素单元沿A-A’线的剖面示意图。
图4为图2的像素单元沿B-B’线的剖面示意图。
图5为本揭示实施例的待测像素单元及相邻像素单元的示意图。
图6为图5的B区域的放大示意图。
图7为图6的B区域中的待测像素单元及相邻像素单元沿C-C’线的剖面示意图。
图8为图6的B区域中的待测像素单元及相邻像素单元沿D-D’线的剖面示意图。
图9为图6的B区域中的待测像素单元及相邻像素单元沿E-E’线的剖面示意图。
 本发明的实施方式
下面将结合附图，对本揭示实施例中的技术方案进行清楚、完整地描述。所描述的实施例仅仅是本揭示一部分实施例，而非全部的实施例。基于本揭示中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本揭示保护的范围。
在本揭示的描述中，术语“上”、“下”、“垂直”、“平行”、“内”、“外”、“中心”及“侧边”等所指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本揭示和简化描述。再者，“第一”及“第二”等术语仅用于描述目的，而不能理解为指示或暗示相对重要性。以“第一”及“第二”等术语限定的特征可明示或者隐含地包括一个或者更多个所述特征。
本揭示提供了一种测量阵列基板电容的方法，其包含下列步骤。
步骤1：提供阵列基板。请参阅图1，阵列基板1包含显示区2及围绕显示区2的非显示区3。阵列基板1的显示区2设有多个像素单元4。请参阅图2，每一像素单元4设置在阵列基板1的衬底基板5上。每一像素单元4包含主像素电极10、从像素电极20、数据线30、公共电极线40、栅极线50、共享薄膜晶体管60、第一薄膜晶体管70及第二薄膜晶体管80。
请参阅图2，主像素电极10及像素电极20均具有四畴结构，以使像素单元4具有八畴结构。数据线30设置在从像素电极20靠近主像素电极10的一侧，且通过第一过孔91与从像素电极20电连接。具体地，从像素电极20具有突出部21。突出部21在衬底基板5上的投影与数据线30在衬底基板5上的投影至少部分重叠。第一过孔91在衬底基板5上的投影落于突出部21与数据线30重叠的投影内。数据线30通过第一过孔91直接与从像素电极20的突出部21电连接。
请参阅图2，公共电极线40设置在主像素电极10靠近从像素电极20的三侧边，以及设置在从像素电极20靠近主像素电极10的三侧边。栅极线50设置于主像素电极10与从像素电极20之间，且形成共享薄膜晶体管60、第一薄膜晶体管70及第二薄膜晶体管80的栅级。共享薄膜晶体管60、第一薄膜晶体管70及第二薄膜晶体管80设置在主像素电极10及从像素电极20之间。
请参阅图2，共享薄膜晶体管60还包含漏极61及源极62。共享薄膜晶体管60的漏极61与数据线30相连接。具体地，漏极61与数据线30具有一体成形的结构。共享薄膜晶体管60的源极62通过第三过孔93与主像素电极10电连接。具体地，主像素电极10具有第一突出部11，且源极62具有源极延伸部63。第一突出部11在衬底基板5上的投影与源极延伸部63在衬底基板5上的投影至少部分重叠。第三过孔93在衬底基板5上的投影落于第一突出部11与源极延伸部63重叠的投影内。共享薄膜晶体管60的源极延伸部63通过第三过孔93直接与主像素电极10的第一突出部11电连接。
请参阅图2，第一薄膜晶体管70还包含漏极71及源极72。在第一薄膜晶体管70中，漏极71与数据线30相连接。具体地，漏极71与数据线30具有一体成形的结构。第二薄膜晶体管80还包含漏极81及源极82。第二薄膜晶体管80的漏极81通过第二过孔92与主像素电极10电连接。具体地，主像素电极10还具有第二突出部12，且漏极81具有漏极延伸部83。第二突出部12在衬底基板5上的投影与漏极延伸部83在衬底基板5上的投影至少部分重叠。第二过孔92在衬底基板5上的投影落于第二突出部12与漏极延伸部83重叠的投影内。第二薄膜晶体管80的漏极延伸部83通过第二过孔92直接与主像素电极10的第二突出部12电连接。第一薄膜晶体管70的源极72与第二薄膜晶体管80的源极82相连接，形成源极线88。具体地，第一薄膜晶体管70的源极72与第二薄膜晶体管80的源极82具有一体成形的结构。
请参阅图2至图4，阵列基板1还包含第一绝缘层6及第二绝缘层7。公共电极线40及栅极线50设置在衬底基板5上，且可由同一金属层制成。第一绝缘层6覆盖公共电极线40及栅极线50。共享薄膜晶体管60的漏极61及源极62、第一薄膜晶体管70的漏极71、第二薄膜晶体管80的漏极81、包含第一薄膜晶体管70的源极72与第二薄膜晶体管80的源极82的源极线88，以及数据线30设置在第一绝缘层6上，且可由同一金属层制成。如前所述，源极62具有源极延伸部63，以及漏极81具有漏极延伸部83。因此，源极延伸部63及漏极延伸部83亦设置在第一绝缘层6上。第二绝缘层7覆盖漏极61、源极62、源极延伸部63、漏极71、漏极81、漏极延伸部83、源极线88及数据线30。主像素电极10及从像素电极20设置在第二绝缘层7上，且可由同一金属层制成。如前所述，从像素电极20具有突出部21，以及主像素电极10具有第一突出部11及第二突出部12。因此，从像素电极20的突出部21，以及主像素电极10的第一突出部11及第二突出部12亦设置在第二绝缘层7上。因此，数据线30通过贯穿第二绝缘层7的第一过孔91与从像素电极20电连接。第二薄膜晶体管70的漏极71是通过贯穿第二绝缘层7的第二过孔92与主像素电极10电连接。共享薄膜晶体管60的源极62通过贯穿第二绝缘层7的第三过孔93与主像素电极10电连接。
请参阅图5，多个像素单元4包含待测像素单元100及相邻像素单元200。待测像素单元100及相邻像素单元200具有与像素单元4相同的结构。为清楚说明，以不同的标号表示在待测像素单元100及相邻像素单元200中与像素单元4相同的元件。
请参阅图5及图6，待测像素单元100包含主像素电极110、从像素电极120、数据线130、公共电极线140、栅极线150、共享薄膜晶体管160、第一薄膜晶体管170及第二薄膜晶体管180。数据线130通过贯穿第二绝缘层7的第一过孔191与从像素电极120电连接。具体地，从像素电极120具有突出部121。突出部121在衬底基板5上的投影与数据线130在衬底基板5上的投影至少部分重叠。第一过孔191在衬底基板5上的投影落于突出部121与数据线130重叠的投影内。数据线130通过第一过孔191直接与从像素电极120的突出部121电连接。共享薄膜晶体管160包含漏极161及源极162。共享薄膜晶体管160的源极162通过贯穿第二绝缘层7的第三过孔193与主像素电极110电连接。具体地，主像素电极110具有第一突出部111，且源极162具有源极延伸部163。第一突出部111在衬底基板5上的投影与源极延伸部163在衬底基板5上的投影至少部分重叠。第三过孔193在衬底基板5上的投影落于第一突出部111与源极延伸部163重叠的投影内。共享薄膜晶体管160的源极延伸部163通过第三过孔193直接与主像素电极110的第一突出部111电连接。第一薄膜晶体管170还包含漏极171及源极172。第二薄膜晶体管180还包含漏极181及源极182。第二薄膜晶体管180的漏极181通过贯穿第二绝缘层7的第二过孔192与主像素电极110电连接。具体地，主像素电极110还具有第二突出部112，且漏极181具有漏极延伸部183。第二突出部112在衬底基板5上的投影与漏极延伸部183在衬底基板5上的投影至少部分重叠。第二过孔192在衬底基板5上的投影落于第二突出部112与漏极延伸部183重叠的投影内。第二薄膜晶体管180的漏极延伸部183通过第二过孔192直接与主像素电极110的第二突出部112电连接。第一薄膜晶体管170的源极172与第二薄膜晶体管180的源极182相连接，形成源极线188。待测像素单元100中各元件的相对位置及关系，与像素单元4各元件的相对位置及关系相同，在此不再详细描述。
请参阅图5及图6，相邻像素单元200包含主像素电极210、从像素电极220、数据线230、公共电极线240、栅极线250、共享薄膜晶体管260、第一薄膜晶体管270及第二薄膜晶体管280。数据线230通过贯穿第二绝缘层7的第一过孔291与从像素电极220电连接。具体地，从像素电极220具有突出部221。突出部221在衬底基板5上的投影与数据线230在衬底基板5上的投影至少部分重叠。第一过孔291在衬底基板5上的投影落于突出部221与数据线230重叠的投影内。数据线230通过第一过孔291直接与从像素电极220的突出部221电连接。共享薄膜晶体管260包含漏极261及源极262。共享薄膜晶体管260的源极262通过贯穿第二绝缘层7的第三过孔293与主像素电极210电连接。具体地，主像素电极210具有第一突出部211，且源极262具有源极延伸部263。第一突出部211在衬底基板5上的投影与源极延伸部263在衬底基板5上的投影至少部分重叠。第三过孔293在衬底基板5上的投影落于第一突出部211与源极延伸部263重叠的投影内。共享薄膜晶体管260的源极延伸部263通过第三过孔293直接与主像素电极210的第一突出部111电连接。第一薄膜晶体管270还包含漏极271及源极272。第二薄膜晶体管280还包含漏极281及源极282。第二薄膜晶体管280的漏极281通过贯穿第二绝缘层7的第二过孔292与主像素电极210电连接。具体地，主像素电极210还具有第二突出部212，且漏极281具有漏极延伸部283。第二突出部212在衬底基板5上的投影与漏极延伸部283在衬底基板5上的投影至少部分重叠。第二过孔292在衬底基板5上的投影落于第二突出部212与漏极延伸部283重叠的投影内。第二薄膜晶体管280的漏极延伸部283通过第二过孔292直接与主像素电极210的第二突出部212电连接。第一薄膜晶体管270的源极272与第二薄膜晶体管280的源极282相连接，形成源极线288。相邻像素单元200中各元件的相对位置及关系，与像素单元4各元件的相对位置及关系相同，在此不再详细描述。
请参阅图5及图6，相邻像素单元200的主像素电极210与待测像素单元100的从像素电极120相邻。在相邻像素单元200的主像素电极210的相对两侧边的公共电极线240分别与在待测像素单元100的从像素电极120的相对两侧边的公共电极线140彼此相连。
步骤2：请参阅图5至图8，在待测像素单元100中，切断共享薄膜晶体管160的漏极161与数据线130之间的连接，以及第一薄膜晶体管170的漏极171与数据线130之间的连接，以使从像素电极120仅与数据线130电连接。在一实施例中，可利用激光沿切割线301切断共享薄膜晶体管160的漏极161与数据线130之间的连接。在此切割后，形成第一沟槽3011。激光切割的深度可依实际需要调整。在此实施例中，第一沟槽3011贯穿第二绝缘层7及共享薄膜晶体管160的漏极161。在一实施例中，亦可将激光切割的深度调整成使第一沟槽3011贯穿第二绝缘层7、共享薄膜晶体管160的漏极161及第一绝缘层6的一部分。再者，亦可利用激光沿切割线302切断第一薄膜晶体管170的漏极171与数据线130之间的连接。在此切割后，形成第二沟槽3021。在此实施例中，第二沟槽3021贯穿第二绝缘层7及第一薄膜晶体管170的漏极171。在一实施例中，亦可将激光切割的深度调整成使第一沟槽3011贯穿第二绝缘层7、第一薄膜晶体管170的漏极171及第一绝缘层6的一部分。在步骤2后，数据线130仅通过贯穿第二绝缘层7的第一过孔191与从像素电极120电连接。具体地，数据线130仅通过第一过孔191直接与从像素电极120的突出部121电连接。
步骤3：请参阅图5、图6及图9，在相邻像素单元200中，沿着在平行于数据线230的方向上延伸的切割线303切断主像素电极210及公共电极线240，以使主像素电极210分离成靠近数据线230的第一区域211及远离数据线230的第二区域212，以及使公共电极线240分离成靠近数据线230的第一区段241及在主像素电极210相对两侧的第二区段242及第三区段243。公共电极线240的第二区段242及第三区段243分别与在待测像素单元100的从像素电极120的相对两侧边的公共电极线140相连接。可利用激光沿切割线303切割主像素电极210及公共电极线240。在此切割后，形成第三沟槽3031。第三沟槽3031贯穿主像素电极210、第二绝缘层7、第二绝缘层6、及公共电极线240。在此实施例中，切割线303及第三沟槽3031为平行于数据线230的直线，但不限于此。切割线303及第三沟槽3031亦可为沿着在平行于数据线230的方向上延伸的任何非直线，例如曲线。
步骤4：请参阅图5、图6及图9，在相邻像素单元200中，设置至少一个导通孔304在主像素电极210的第二区域212中，以使主像素电极210的第二区域212仅与公共电极线240的第二区段242及第三区段243中的至少一者电连接。在一实施例中，可利用激光形成贯穿第一绝缘层6及第二绝缘层7并电连接主像素电极210的第二区域212与公共电极线240的导通孔304。在此实施例中，导通孔304在衬底基板5上的投影，落入主像素电极210的第二区域212与公共电极线240在衬底基板5上的重叠投影内。导通孔304的投影面积等于主像素电极210的第二区域212与公共电极线240的重叠投影面积。在一实施例中，导通孔304的投影，亦可与主像素电极210的第二区域212与公共电极线240的重叠投影部分重叠。导通孔304的投影面积亦可大于或小于主像素电极210的第二区域212与公共电极线240的重叠投影面积。导通孔304的数量和相对位置可依实际需求调整。增加导通孔304的数量，可确保主像素电极210的第二区域212与公共电极线240电连接。在此实施例中，在公共电极线240的第二区段242及第三区段243上各设置两个导通孔304，但不限于此。
在一实施例中，可根据需要，任意调整前述步骤1至步骤4的顺序。
步骤5：请参阅图5及图6，测量待测像素单元100的从像素电极120与相邻像素单元200的主像素电极210的第二区域212之间的电容，以获得待测像素单元100中的数据线130与公共电极线140之间的电容。如前所述，相邻像素单元200的主像素电极210与待测像素单元100的从像素电极110相邻。在步骤2后，待测像素单元100的从像素电极120仅与数据线130电连接。在步骤4后，相邻像素单元200的主像素电极210的第二区域212仅与公共电极线240的第二区段242及第三区段243中的至少一者电连接。公共电极线240的第二区段242及第三区段243分别与在待测像素单元100的从像素电极120的相对两侧边的公共电极线130彼此相连。因此，本揭示所提供的方法，可通过测量待测像素单元100的从像素电极120与相邻像素单元200的主像素电极210的第二区域212之间的电容，来获得待测像素单元100在X区中的数据线130与公共电极线140之间的电容。具体地，只要将测量电容的仪器的两探针分别置于待测像素单元100的从像素电极120与相邻像素单元200的主像素电极210的第二区域212上并进行测量，即可获得待测像素单元100中的数据线130与公共电极线140之间的电容。
本揭示所提供的方法可直接测量分析阵列基板的显示区中的像素单元的数据线和公共电极线的重叠电容，而无需在管阵列基板的非显示区中设置分别从数据线和公共电极线延伸出的端子。
本揭示还提供了一种阵列基板，其为进行前述方法步骤1-4后所获得的阵列基板。请参阅图1，阵列基板1包含显示区2及围绕显示区2的非显示区3。阵列基板1的显示区2设有多个像素单元4。请参阅图2，每一像素单元4设置在阵列基板1的衬底基板5上。每一像素单元4包含主像素电极10、从像素电极20、数据线30、公共电极线40、栅极线50、共享薄膜晶体管60、第一薄膜晶体管70及第二薄膜晶体管80。数据线30设置在从像素电极20靠近主像素电极10的一侧，且通过第一过孔91与从像素电极20电连接。具体地，从像素电极20具有突出部21。数据线30通过第一过孔91直接与从像素电极20的突出部21电连接。公共电极线40设置在主像素电极10靠近从像素电极20的三侧边，以及设置在从像素电极20靠近主像素电极10的三侧边。栅极线50设置于主像素电极10与从像素电极20之间，且形成共享薄膜晶体管60、第一薄膜晶体管70及第二薄膜晶体管80的栅级。共享薄膜晶体管60、第一薄膜晶体管70及第二薄膜晶体管80设置在主像素电极10及从像素电极20之间。
请参阅图2，共享薄膜晶体管60还包含漏极61及源极62。共享薄膜晶体管60的漏极61与数据线30相连接。具体地，漏极61与数据线30具有一体成形的结构。共享薄膜晶体管60的源极62通过第三过孔93与主像素电极10电连接。具体地，主像素电极10具有第一突出部11，且源极62具有源极延伸部63。共享薄膜晶体管60的源极延伸部63通过第三过孔93直接与主像素电极10的第一突出部11电连接。第一薄膜晶体管70还包含漏极71及源极72。在第一薄膜晶体管70中，漏极71与数据线30相连接。具体地，漏极71与数据线30具有一体成形的结构。第二薄膜晶体管80还包含漏极81及源极82。第二薄膜晶体管80的漏极81通过第二过孔92与主像素电极10电连接。具体地，主像素电极10还具有第二突出部12，且漏极81具有漏极延伸部83。第二薄膜晶体管80的漏极延伸部83通过第二过孔92直接与主像素电极10的第二突出部12电连接。第一薄膜晶体管70的源极72与第二薄膜晶体管80的源极82相连接，形成源极线88。具体地，第一薄膜晶体管70的源极72与第二薄膜晶体管80的源极82具有一体成形的结构。
请参阅图2至图4，阵列基板1还包含第一绝缘层6及第二绝缘层7。公共电极线40及栅极线50设置在衬底基板5上。第一绝缘层6覆盖公共电极线40及栅极线50。共享薄膜晶体管60的漏极61及源极62、第一薄膜晶体管70的漏极71、第二薄膜晶体管80的漏极81、包含第一薄膜晶体管70的源极72与第二薄膜晶体管80的源极82的源极线88，以及数据线30设置在第一绝缘层6上。如前所述，源极62具有源极延伸部63，以及漏极81具有漏极延伸部83。因此，源极延伸部63及漏极延伸部83亦设置在第一绝缘层6上。第二绝缘层7覆盖漏极61、源极62、源极延伸部63、漏极71、漏极81、漏极延伸部83、源极线88及数据线30。主像素电极10及从像素电极20设置在第二绝缘层7上。如前所述，从像素电极20具有突出部21，以及主像素电极10具有第一突出部11及第二突出部12。因此，从像素电极20的突出部21，以及主像素电极10的第一突出部11及第二突出部12亦设置在第二绝缘层7上。数据线30通过贯穿第二绝缘层7的第一过孔91与从像素电极20电连接。第二薄膜晶体管70的漏极71是通过贯穿第二绝缘层7的第二过孔92与主像素电极10电连接。共享薄膜晶体管60的源极62通过贯穿第二绝缘层7的第三过孔93与主像素电极10电连接。
请参阅图5，多个像素单元4包含待测像素单元100及相邻像素单元200。待测像素单元100及相邻像素单元200具有与像素单元4相同的结构。为清楚说明，以不同的标号表示在待测像素单元100及相邻像素单元200中与像素单元4相同的元件。
请参阅图5及图6，待测像素单元100包含主像素电极110、从像素电极120、数据线130、公共电极线140、栅极线150、共享薄膜晶体管160、第一薄膜晶体管170及第二薄膜晶体管180。数据线130通过贯穿第二绝缘层7的第一过孔191与从像素电极120电连接。具体地，从像素电极120具有突出部121。数据线130通过第一过孔191直接与从像素电极120的突出部121电连接。共享薄膜晶体管160包含漏极161及源极162。共享薄膜晶体管160的源极162通过贯穿第二绝缘层7的第三过孔193与主像素电极110电连接。具体地，主像素电极110具有第一突出部111，且源极162具有源极延伸部163。共享薄膜晶体管160的源极延伸部163通过第三过孔193直接与主像素电极110的第一突出部111电连接。第一薄膜晶体管170还包含漏极171及源极172。第二薄膜晶体管180还包含漏极181及源极182。第二薄膜晶体管180的漏极181通过贯穿第二绝缘层7的第二过孔192与主像素电极110电连接。具体地，主像素电极110还具有第二突出部112，且漏极181具有漏极延伸部183。第二薄膜晶体管180的漏极延伸部183通过第二过孔192直接与主像素电极110的第二突出部112电连接。第一薄膜晶体管170的源极172与第二薄膜晶体管180的源极182相连接，形成源极线188。待测像素单元100中各元件的相对位置及关系，与像素单元4各元件的相对位置及关系相同，在此不再详细描述。
请参阅图5及图6，相邻像素单元200包含主像素电极210、从像素电极220、数据线230、公共电极线240、栅极线250、共享薄膜晶体管260、第一薄膜晶体管270及第二薄膜晶体管280。数据线230通过贯穿第二绝缘层7的第一过孔291与从像素电极220电连接。具体地，从像素电极220具有突出部221。数据线230通过第一过孔291直接与从像素电极220的突出部221电连接。共享薄膜晶体管260包含漏极261及源极262。共享薄膜晶体管260的源极262通过贯穿第二绝缘层7的第三过孔293与主像素电极210电连接。具体地，主像素电极210具有第一突出部211，且源极262具有源极延伸部263。共享薄膜晶体管260的源极延伸部263通过第三过孔293直接与主像素电极210的第一突出部111电连接。第一薄膜晶体管270还包含漏极271及源极272。第二薄膜晶体管280还包含漏极281及源极282。第二薄膜晶体管280的漏极281通过贯穿第二绝缘层7的第二过孔292与主像素电极210电连接。具体地，主像素电极210还具有第二突出部212，且漏极281具有漏极延伸部283。第二薄膜晶体管280的漏极延伸部283通过第二过孔292直接与主像素电极210的第二突出部212电连接。第一薄膜晶体管270的源极272与第二薄膜晶体管280的源极282相连接，形成源极线288。相邻像素单元200中各元件的相对位置及关系，与像素单元4各元件的相对位置及关系相同，在此不再详细描述。
请参阅图5及图6，相邻像素单元200的主像素电极210与待测像素单元100的从像素电极120相邻。在相邻像素单元200的主像素电极210的相对两侧边的公共电极线240分别与在待测像素单元100的从像素电极120的相对两侧边的公共电极线140彼此相连。
请参阅图5至图8，在待测像素单元100中，设置有用以分离共享薄膜晶体管160的漏极161与数据线130的第一沟槽3011，以及用以分离第一薄膜晶体管170的漏极171与数据线130的第二沟槽3021，使得从像素电极120仅与数据线130电连接。具体地，数据线130仅通过贯穿第二绝缘层7的第一过孔191与从像素电极120电连接。更具体地，数据线130仅通过第一过孔191直接与从像素电极120的突出部121电连接。在一实施例中，可利用激光沿切割线301切断共享薄膜晶体管160的漏极161与数据线130之间的连接，以形成第一沟槽3011。再者，亦可利用激光沿切割线302切断第一薄膜晶体管170的漏极171与数据线130之间的连接，以形成第二沟槽3021。激光切割的深度可依实际需要调整。在此实施例中，第一沟槽3011贯穿第二绝缘层7及共享薄膜晶体管160的漏极161，且第二沟槽3021贯穿第二绝缘层7及第一薄膜晶体管170的漏极171。
请参阅图5、图6及图9，在相邻像素单元200中，设置有在平行于数据线230的方向上延伸的第三沟槽3031，建构成将主像素电极210分离成靠近数据线230的第一区域211及远离数据线230的第二区域212，以及建构成将公共电极线240分离成靠近数据线230的第一区段241及在主像素电极210相对两侧的第二区段242及第三区段243。公共电极线240的第二区段242及第三区段243分别与在待测像素单元100的从像素电极120的相对两侧边的公共电极线140相连接。在一实施例中，可利用激光沿着在平行于数据线230的方向上延伸的的切割线303切割主像素电极210及公共电极线240，以形成第三沟槽3031。第三沟槽3031贯穿主像素电极210、第二绝缘层7、第二绝缘层6、及公共电极线240。在此实施例中，切割线303及第三沟槽3031为平行于数据线230的直线，但不限于此。切割线303及第三沟槽3031亦可为沿着在平行于数据线230的方向上延伸的任何非直线，例如曲线。
请参阅图5、图6及图9，主像素电极210的第二区域212设置有至少一个导通孔304，建构成使主像素电极210的第二区域212仅与公共电极线240的第二区段242及第三区段243中的至少一者电连接。在一实施例中，可利用激光形成贯穿第一绝缘层6及第二绝缘层7并电连接主像素电极210的第二区域212与公共电极线240的导通孔304。导通孔304的数量和相对位置可依实际需求调整。增加导通孔304的数量，可确保主像素电极210的第二区域212与公共电极线240电连接。在此实施例中，在公共电极线240的第二区段242及第三区段243上各设置两个导通孔304，但不限于此。
阵列基板1中各元件的其它相对位置及关系，请参考前面对于本揭示所提供的方法的描述，在此不再详细描述。
如前所述，相邻像素单元200的主像素电极210与待测像素单元100的从像素电极110相邻。待测像素单元100的从像素电极120仅与数据线130电连接。相邻像素单元200的主像素电极210的第二区域212仅与公共电极线240的第二区段242及第三区段243中的至少一者电连接。公共电极线240的第二区段242及第三区段243分别与在待测像素单元100的从像素电极120的相对两侧边的公共电极线130彼此相连。因此，本揭示所提供的阵列基板，可通过测量待测像素单元100的从像素电极120与相邻像素单元200的主像素电极210的第二区域212之间的电容，来获得待测像素单元100中的数据线130与公共电极线140之间的电容。具体地，只要将测量电容的仪器的两探针分别置于待测像素单元100的从像素电极120与相邻像素单元200的主像素电极210的第二区域212上并进行测量，即可获得待测像素单元100在X区中的数据线130与公共电极线140之间的电容。
本揭示所提供的阵列基板，可通过直接测量待测像素单元的从像素电极与相邻像素单元的主像素电极之间的电容，来获得待测像素单元中的数据线与公共电极线之间的电容。本揭示所提供的阵列基板便于直接测量分析阵列基板的显示区中的像素单元的数据线和公共电极线的重叠电容，而无需在管阵列基板的非显示区中设置分别从数据线和公共电极线延伸出的的端子。
虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本发明的保护范围以权利要求界定的范围为准。本领域的普通技术人员，在不脱离本发明的保护范围内，均可作各种更动与润饰。例如，上述实施例是以具有八畴结构的像素单元作为例示，然而本领域的普通技术人员可将本发明的概念应用于具有多畴结构的像素单元中。

Claims (15)

  1. 一种测量阵列基板电容的方法，其包含：
    提供阵列基板，其中所述阵列基板包含位于衬底基板上的多个像素单元，且每一像素单元包含：
    主像素电极；
    从像素电极；
    数据线，设置在所述从像素电极靠近所述主像素电极的一侧，与所述从像素电极电连接；
    公共电极线，设置在所述主像素电极靠近所述从像素电极的三侧边，以及设置在所述从像素电极靠近所述主像素电极的三侧边；
    共享薄膜晶体管，其中共享薄膜晶体管的漏极与所述数据线相连接；及
    第一薄膜晶体管，其中第一薄膜晶体管的漏极与所述数据线相连接；
    在待测的像素单元中，切断所述共享薄膜晶体管的漏极与所述数据线之间的连接，以及所述第一薄膜晶体管的漏极与所述数据线之间的连接，以使所述从像素电极仅与所述数据线电连接；
    在与所述待测像素单元相邻的像素单元中，沿着在平行于所述数据线的方向上延伸的切割线切断所述主像素电极及所述公共电极线，以使所述主像素电极分离成靠近所述数据线的第一区域及远离所述数据线的第二区域，以及使所述公共电极线被分离成靠近所述数据线的第一区段与在所述主像素电极相对两侧的第二区段及第三区段，其中所述相邻像素单元的主像素电极与所述待测像素单元的从像素电极相邻，且所述相邻像素单元的公共电极线的第二区段及第三区段分别与在所述待测像素单元的从像素电极的相对两侧边的公共电极线相连接；
    在所述相邻像素单元中，设置至少一个导通孔在所述主像素电极的第二区域中，以使所述主像素电极的第二区域仅与所述公共电极线的第二区段及第三区段中的至少一者电连接；及
    测量所述待测像素单元的从像素电极与所述相邻像素单元的主像素电极的第二区域之间的电容，以获得所述待测像素单元中的数据线与公共电极线之间的电容。
  2. 根据权利要求1所述的测量阵列基板电容的方法，其中每一像素单元还包含第二薄膜晶体管，且第二薄膜晶体管的漏极与所述主像素电极电连接。
  3. 根据权利要求2所述的测量阵列基板电容的方法，其中每一像素单元还包含栅极线，设置于主像素电极与从像素电极之间，且形成共享薄膜晶体管、第一薄膜晶体管及第二薄膜晶体管的栅级。
  4. 根据权利要求3所述的测量阵列基板电容的方法，其中：
    所述阵列基板还包含第一绝缘层及第二绝缘层；
    所述公共电极线及所述栅极线设置在所述衬底基板上；
    第一绝缘层覆盖所述公共电极线及所述栅极线；
    所述数据线、所述共享薄膜晶体管的漏极、第一薄膜晶体管的漏极及第二薄膜晶体管的漏极设置在第一绝缘层上；
    第二绝缘层覆盖所述数据线、所述共享薄膜晶体管的漏极、第一薄膜晶体管的漏极及第二薄膜晶体管的漏极；及
    所述主像素电极及所述从像素电极设置在第二绝缘层上。
  5. 根据权利要求4所述的测量阵列基板电容的方法，其中：
    在每一像素单元中，数据线是通过贯穿第二绝缘层的第一过孔与所述从像素电极电连接，且第二薄膜晶体管的漏极是通过贯穿第二绝缘层的第二过孔与所述主像素电极电连接；及
    在所述相邻像素单元中，所述主像素电极的第二区域是通过贯穿第一绝缘层及第二绝缘层的所述导通孔与所述公共电极线电连接。
  6. 根据权利要求1所述的测量阵列基板电容的方法，其中在每一像素单元中，共享薄膜晶体管的漏极、第一薄膜晶体管的漏极与所述数据线为一体成形的结构。
  7. 根据权利要求1所述的测量阵列基板电容的方法，其中所述在所述待测像素单元中切断所述共享薄膜晶体管的漏极与所述数据线之间的连接及所述第一薄膜晶体管的漏极与所述数据线之间的连接、所述在所述相邻像素单元中切断所述主像素电极及所述公共电极线，以及所述在所述相邻像素单元中设置至少一个导通孔在所述主像素电极的第二区域中，均是通过激光进行。
  8. 根据权利要求1所述的测量阵列基板电容的方法，其中每一像素单元中的主像素电极及像素电极均具有四畴结构，以使像素单元具有八畴结构。
  9. 一种阵列基板，其包含位于衬底基板上的多个像素单元，其中每一像素单元包含：
    主像素电极；
    从像素电极；
    数据线，设置在所述从像素电极靠近所述主像素电极的一侧，与所述从像素电极电连接；
    公共电极线，设置在所述主像素电极靠近所述从像素电极的三侧边，以及设置在所述从像素电极靠近所述主像素电极的三侧边；
    共享薄膜晶体管，其中共享薄膜晶体管的漏极与所述数据线相连接；及
    第一薄膜晶体管，其中第一薄膜晶体管的漏极与所述数据线相连接；
    在待测像素单元中，设置有用以分离所述共享薄膜晶体管的漏极与所述数据线的第一沟槽，以及用以分离所述第一薄膜晶体管的漏极与所述数据线的第二沟槽，使得从像素电极仅与数据线电连接；
    在与所述待测像素单元相邻的像素单元中，设置有在平行于所述数据线的方向上延伸的第三沟槽，建构成将所述主像素电极分离成靠近所述数据线的第一区域及远离所述数据线的第二区域，以及建构成将所述公共电极线分离成靠近所述数据线的第一区段及在所述主像素电极相对两侧的第二区段及第三区段；
    所述相邻像素单元的主像素电极与所述待测像素单元的从像素电极相邻，且所述相邻像素单元的公共电极线的第二区段及第三区段分别与在所述待测像素单元的从像素电极的相对两侧边的公共电极线相连接；以及
    所述第二区域设有至少一个导通孔，建构成使所述主像素电极的第二区域仅与所述公共电极线的第二区段及第三区段中的至少一者电连接。
  10. 根据权利要求9所述的阵列基板，其中每一像素单元还包含第二薄膜晶体管，且第二薄膜晶体管的漏极与所述主像素电极电连接。
  11. 根据权利要求10所述的阵列基板，其中每一像素单元还包含栅极线，设置于主像素电极与从像素电极之间，且形成共享薄膜晶体管、第一薄膜晶体管及第二薄膜晶体管的栅级。
  12. 根据权利要求11所述的阵列基板，其中：
    所述阵列基板还包含第一绝缘层及第二绝缘层；
    所述公共电极线及所述栅极线设置在所述衬底基板上；
    第一绝缘层覆盖所述公共电极线及所述栅极线；
    所述数据线、所述共享薄膜晶体管的漏极及第一薄膜晶体管的漏极设置在第一绝缘层上；
    第二绝缘层覆盖所述数据线、所述共享薄膜晶体管的漏极及第一薄膜晶体管的漏极；
    所述主像素电极及所述从像素电极设置在第二绝缘层上。
  13. 根据权利要求12所述的阵列基板，其中：
    在每一像素单元中，数据线是通过贯穿第二绝缘层的第一过孔与所述从像素电极电连接，且第二薄膜晶体管的漏极是通过贯穿第二绝缘层的第二过孔与所述主像素电极电连接；及
    在所述相邻像素单元中，所述主像素电极的第二区域是通过贯穿第一绝缘层及第二绝缘层的所述导通孔与所述公共电极线电连接。
  14. 根据权利要求9所述的阵列基板，其中在每一像素单元中，共享薄膜晶体管的漏极、第一薄膜晶体管的漏极与所述数据线为一体成形的结构。
  15. 根据权利要求9所述的阵列基板，其中每一像素单元中的主像素电极及像素电极均具有四畴结构，以使像素单元具有八畴结构。
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